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https://github.com/openmv/openmv.git
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517 lines
17 KiB
C
517 lines
17 KiB
C
/**********************************************************************************************************************
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* Copyright (c) Prophesee S.A. *
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* *
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* Licensed under the Apache License, Version 2.0 (the "License"); *
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* you may not use this file except in compliance with the License. *
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* You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 *
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* Unless required by applicable law or agreed to in writing, software distributed under the License is distributed *
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* on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
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* See the License for the specific language governing permissions and limitations under the License. *
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**********************************************************************************************************************/
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#ifndef __GENX320_H
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#define __GENX320_H
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/* Standard Includes */
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#include <math.h>
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#include <stdint.h>
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#include <stdio.h>
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/* User Includes*/
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#include "genx320_all_pub_registers.h"
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#include "psee_issd.h"
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#include "omv_csi.h"
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/* Sensor I2C Address */
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#define I2C_ADDRESS 0x3C
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/* Sensor Chip ID */
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#define SAPHIR_CHIP_ID 0x0014
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#define SAPHIR_ES_ID 0x30501C01
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#define SAPHIR_MP_ID 0xB0602003
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/* Memory Bank Defines */
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#define IMEM_START 0x00200000UL
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#define DMEM_START 0x00300000UL
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#define MEM_BANK_SELECT 0x0000F800UL
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#define MEM_BANK_MEM0 0x0000F900UL
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#define GENX_MEM_BANK_IMEM 0b10
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#define GENX_MEM_BANK_DMEM 0b11
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/* RISC-V Defines */
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#define RISC_BOOT_DONE 0x0ABCDEF
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/**
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* @brief GenX320 Histomode pin structure definition
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*/
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typedef enum {
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HM_EVT = 0U,
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HM_HISTO = 1U,
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} GenX320_Histomode;
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/**
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* @brief GenX320 Mipimode pin structure definition
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*/
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typedef enum {
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MM_CPI = 0U,
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MM_MIPI = 1U,
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} GenX320_Mipimode;
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/**
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* @brief GenX320 Rommode pin structure definition
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*/
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typedef enum {
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RM_IMEM = 0U,
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RM_ROM = 1U,
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} GenX320_Rommode;
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/**
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* @brief GenX320 Modules structures definition
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*/
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typedef enum {
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EHC = 0U,
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AFK = 1U,
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STC = 2U,
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ERC = 3U,
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ERC_DFIFO = 4U,
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ERC_ILG = 5U,
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ERC_TDROP = 6U,
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MIPI = 7U,
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CPI = 8U,
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CPU = 9U,
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} GenX320_ModulesTypeDef;
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/**
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* @brief RISCV FW status structures definition
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*/
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typedef enum {
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fw_OK = 0U,
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fw_Error_InvalidSize = 1U,
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fw_Error_InvalidPointer = 2U,
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fw_Flash_Error = 3U,
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fw_Start_Error = 4U,
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fw_Flashed_Already = 5U
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} FW_StatusTypeDef;
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/**
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* @brief Shadow register status structures definition
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*/
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typedef enum {
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shadow_valid = 0U,
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shadow_not_valid = 01
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} Shadow_StatusTypeDef;
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/**
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* @brief Structure to hold the parameters for the bias
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*/
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typedef struct {
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uint8_t pr;
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uint8_t fo;
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uint8_t fes;
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uint8_t hpf;
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uint8_t diff_on;
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uint8_t diff;
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uint8_t diff_off;
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uint8_t inv;
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uint8_t refr;
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uint8_t invp;
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uint8_t req_pu;
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uint8_t sm_pdy;
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} BIAS_Params_t;
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/**
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* @brief Structure to hold the border value for the Activity Map
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*/
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typedef struct {
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uint16_t x0;
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uint16_t x1;
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uint16_t x2;
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uint16_t x3;
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uint16_t x4;
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uint16_t y0;
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uint16_t y1;
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uint16_t y2;
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uint16_t y3;
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uint16_t y4;
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} AM_Borders_t;
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/**
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* @brief Structure to hold the risc-v firmware
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*/
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typedef struct {
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uint32_t address;
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uint32_t value;
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} Firmware;
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/**
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* @brief Structure to hold the sensor clock frequencies
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*/
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typedef struct {
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uint32_t in_freq;
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uint32_t sys_freq;
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uint32_t evt_icn_freq;
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uint32_t cpu_ss_freq;
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uint32_t pll_in_freq;
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uint32_t pll_vco_freq;
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uint32_t phy_freq;
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uint32_t mipi_freq;
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uint32_t esc_freq;
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} clk_freq_dict;
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/**
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* @brief Enum to hold the parameters for the bias
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*/
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typedef enum {
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PR,
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FO,
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FES,
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HPF,
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DIFF_ON,
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DIFF,
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DIFF_OFF,
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INV,
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REFR,
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INVP,
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REQ_PU,
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SM_PDY,
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} BIAS_Name_t;
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/**
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* @brief Structure to hold AFK Invalidation
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*/
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typedef struct {
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uint32_t dt_fifo_wait_time;
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uint32_t dt_fifo_timeout;
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} AFK_InvalidationTypeDef;
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/**
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* @brief AFK Init structures definition
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*/
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typedef enum {
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AFK_INIT_NOT_DONE = 0x00U,
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AFK_INIT_DONE = 0x01U,
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} AFK_InitTypeDef;
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/**
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* @brief AFK Status structures definition
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*/
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typedef enum {
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AFK_OK = 0x00U,
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AFK_BUSY = 0x01U,
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AFK_ERROR = 0x02U,
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AFK_STATE_ERROR = 0x03U,
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AFK_STATS_ERROR = 0x04U,
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AFK_FREQ_ERROR = 0x05U,
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AFK_CLK_ERROR = 0x06U,
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} AFK_StatusTypeDef;
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/**
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* @brief AFK State structures definition
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*/
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typedef enum {
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AFK_STATE_RESET = 0x00U,
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AFK_STATE_READY = 0x01U,
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AFK_STATE_BUSY = 0x02U,
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} AFK_StateTypeDef;
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/**
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* @brief AFK Statistics structures definition
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*/
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typedef enum {
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AFK_STATS_RESET = 0x00U,
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AFK_STATS_READY = 0x01U,
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} AFK_StatisticsTypeDef;
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/**
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* @brief AFK Handle Structure definition
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*/
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typedef struct
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{
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omv_csi_t *csi;
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AFK_InitTypeDef Init; /*!< AFK Init */
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AFK_StateTypeDef State; /*!< AFK State */
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AFK_StatisticsTypeDef Stats; /*!< AFK Statistics */
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uint16_t f_min; /*!< AFK Minimum frequency */
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uint16_t f_max; /*!< AFK Maximum frequency */
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uint32_t stats_acc; /*!< AFK Statistics Accumulation time */
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} AFK_HandleTypeDef;
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/**
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* @brief EHC Init structures definition
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*/
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typedef enum {
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EHC_INIT_NOT_DONE = 0x00U,
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EHC_INIT_DONE = 0x01U,
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} EHC_InitTypeDef;
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/**
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* @brief EHC Status structures definition
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*/
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typedef enum {
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EHC_OK = 0x00U,
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EHC_BUSY = 0x01U,
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EHC_ERROR = 0x02U,
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EHC_STATE_ERROR = 0x03U,
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EHC_PARAM_ERROR = 0x04U,
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} EHC_StatusTypeDef;
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/**
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* @brief EHC State structures definition
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*/
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typedef enum {
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EHC_STATE_RESET = 0x00U,
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EHC_STATE_READY = 0x01U,
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EHC_STATE_BUSY = 0x02U,
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} EHC_StateTypeDef;
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/**
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* @brief EHC Algo structures definition
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*/
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typedef enum {
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EHC_ALGO_DIFF3D = 0x00U,
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EHC_ALGO_HISTO3D = 0x01U,
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EHC_ALGO_RESET = 0x02U,
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} EHC_AlgoTypeDef;
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/**
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* @brief EHC Trigger structures definition
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*/
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typedef enum {
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EHC_TRIGGER_EVENT_RATE = 0x00U,
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EHC_TRIGGER_INTEGRATION_PERIOD = 0x01U,
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EHC_TRIGGER_RESET = 0x02U,
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} EHC_TriggerTypeDef;
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/**
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* @brief EHC Padding structures definition
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*/
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typedef enum {
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EHC_WITHOUT_PADDING = 0x00U,
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EHC_WITH_PADDING = 0x01U,
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EHC_PADDING_RESET = 0x02U,
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} EHC_PaddingTypeDef;
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/**
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* @brief EHC Override structures definition
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*/
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typedef enum {
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EHC_NO_OVERRIDE = 0x00U,
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EHC_OVERRIDE = 0x01U,
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EHC_OVERRIDE_RESET = 0x02U,
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} EHC_OverrideTypeDef;
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/**
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* @brief EHC Handle Structure definition
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*/
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typedef struct
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{
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omv_csi_t *csi;
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EHC_InitTypeDef Init; /*!< EHC Init */
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EHC_StateTypeDef State; /*!< EHC State */
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EHC_AlgoTypeDef Algo; /*!< EHC Algo */
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EHC_TriggerTypeDef Trigger; /*!< EHC Trigger */
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EHC_PaddingTypeDef Padding; /*!< EHC Padding */
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EHC_OverrideTypeDef Override; /*!< EHC Override */
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uint32_t accumulation_period; /*!< EHC Accumulation Period */
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uint8_t p_bits_size; /*!< EHC Positive bits size */
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uint8_t n_bits_size; /*!< EHC Negative bits size */
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} EHC_HandleTypeDef;
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/**
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* @brief STC Params structures definition
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*/
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typedef struct {
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uint16_t Presc;
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uint16_t Mult;
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uint16_t Timeout;
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} STC_ParamsTypeDef;
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/**
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* @brief STC Init structures definition
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*/
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typedef enum {
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STC_INIT_NOT_DONE = 0x00U,
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STC_INIT_DONE = 0x01U,
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} STC_InitTypeDef;
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/**
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* @brief STC Status structures definition
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*/
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typedef enum {
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STC_OK = 0x00U,
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STC_BUSY = 0x01U,
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STC_ERROR = 0x02U,
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STC_STATE_ERROR = 0x03U,
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STC_THRESHOLD_ERROR = 0x04U,
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STC_CLK_ERROR = 0x05U,
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} STC_StatusTypeDef;
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/**
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* @brief STC State structures definition
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*/
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typedef enum {
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STC_STATE_RESET = 0x00U,
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STC_STATE_READY = 0x01U,
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STC_STATE_BUSY = 0x02U,
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} STC_StateTypeDef;
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/**
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* @brief STC Mode structures definition
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*/
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typedef enum {
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STC_MODE_RESET = 0x00U,
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STC_MODE_STC = 0x01U,
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STC_MODE_TRAIL = 0x02U,
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STC_MODE_STC_TRAIL = 0x03U,
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} STC_ModeTypeDef;
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/**
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* @brief STC Handle Structure definition
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*/
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typedef struct
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{
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omv_csi_t *csi;
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STC_InitTypeDef Init; /*!< STC block Init */
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STC_StateTypeDef State; /*!< STC block State */
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STC_ModeTypeDef Mode; /*!< STC Mode */
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STC_ParamsTypeDef Params; /*!< STC Params */
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} STC_HandleTypeDef;
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/* Constants/Variables to hold default bias */
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extern const BIAS_Params_t genx320es_default_biases;
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extern const BIAS_Params_t genx320mp_default_biases;
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extern BIAS_Params_t genx320_default_biases;
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/* Variable to hold default borders for Activity map */
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extern AM_Borders_t genx320mp_default_am_borders;
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/* ISSD sequences. */
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extern const struct issd dcmi_evt;
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extern const struct issd dcmi_histo;
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extern const struct issd *current_issd;
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/* Variable to hold the current boot mode */
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extern GenX320_Rommode genx320_boot_mode;
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/* Sensor Register Manipulation Functions */
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extern void psee_sensor_read(omv_csi_t *csi, uint16_t register_address, uint32_t *buf);
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extern void psee_sensor_write(omv_csi_t *csi, uint16_t register_address, uint32_t register_data);
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/* Sensor Bring Up Functions */
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extern void psee_sensor_init(omv_csi_t *csi, const struct issd *);
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extern void psee_sensor_start(omv_csi_t *csi, const struct issd *);
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extern void psee_sensor_stop(omv_csi_t *csi, const struct issd *);
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extern const struct issd *psee_open_evt(omv_csi_t *csi);
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extern void psee_sensor_set_bias(omv_csi_t *csi, BIAS_Name_t bias, uint32_t val);
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extern void psee_sensor_set_biases(omv_csi_t *csi, const BIAS_Params_t *bias);
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extern void psee_sensor_set_CPI_EVT20(omv_csi_t *csi);
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extern void psee_sensor_set_CPI_HISTO(omv_csi_t *csi);
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extern void psee_sensor_set_flip(omv_csi_t *csi, uint32_t flip_x, uint32_t flip_y);
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extern void psee_sensor_destroy(omv_csi_t *csi);
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/* Operating Mode Control Functions */
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extern void psee_PM3C_config(omv_csi_t *csi);
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extern void psee_PM3C_Histo_config(omv_csi_t *csi);
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extern void psee_PM2_config(omv_csi_t *csi);
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extern void psee_PM2_Histo_config(omv_csi_t *csi);
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/* Firmware flashing functions */
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extern FW_StatusTypeDef psee_write_firmware_single(omv_csi_t *csi, const Firmware *firmwareArray, uint32_t n_bytes);
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extern FW_StatusTypeDef psee_test_firmware_single(omv_csi_t *csi, const Firmware *firmwareArray, uint32_t n_bytes);
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extern uint32_t psee_read_firmware_register(omv_csi_t *csi, uint32_t reg_address);
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extern FW_StatusTypeDef psee_write_firmware_burst(omv_csi_t *csi, const Firmware *firmwareArray, uint32_t n_bytes);
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extern FW_StatusTypeDef psee_start_firmware(omv_csi_t *csi, GenX320_Rommode boot_mode, uint32_t jump_add);
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extern FW_StatusTypeDef psee_reset_firmware(omv_csi_t *csi, GenX320_Rommode boot_mode);
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/* Mailbox Communication Functions */
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extern uint32_t psee_get_mbx_cmd_ptr(omv_csi_t *csi);
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extern uint32_t psee_get_mbx_misc(omv_csi_t *csi);
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extern uint32_t psee_get_mbx_status_ptr(omv_csi_t *csi);
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extern void psee_set_mbx_cmd_ptr(omv_csi_t *csi, uint32_t val);
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extern void psee_set_mbx_misc(omv_csi_t *csi, uint32_t val);
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extern void psee_set_mbx_status_ptr(omv_csi_t *csi, uint32_t val);
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/* ROI Access Functions */
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extern void psee_write_ROI_X(omv_csi_t *csi, uint32_t offset, uint32_t val);
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extern void psee_write_ROI_Y(omv_csi_t *csi, uint32_t offset, uint32_t val);
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extern void psee_write_ROI_CTRL(omv_csi_t *csi, uint32_t val);
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/* RISC-V Debugger Functions */
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extern uint32_t psee_mbx_read_uint32(omv_csi_t *csi);
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extern void psee_decode_debugger(omv_csi_t *csi);
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extern uint32_t psee_sensor_read_dmem(omv_csi_t *csi, uint32_t address);
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extern uint32_t psee_sensor_read_imem(omv_csi_t *csi, uint32_t address);
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/* Statistics Register Read Functions */
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extern void psee_read_ro_lp_evt_cnt(omv_csi_t *csi, uint32_t *p_data);
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extern uint32_t psee_read_ro_evt_cd_cnt(omv_csi_t *csi);
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/* Activity Map Configuration Functions */
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extern void psee_configure_activity_map(omv_csi_t *csi);
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extern void psee_set_default_XY_borders(omv_csi_t *csi, AM_Borders_t *border);
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/* AFK Configuration Functions */
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extern AFK_StatusTypeDef psee_afk_init(omv_csi_t *csi, AFK_HandleTypeDef *afk);
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extern AFK_StatusTypeDef psee_afk_activate(AFK_HandleTypeDef *afk,
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uint16_t f_min,
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uint16_t f_max,
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uint16_t evt_clk_freq);
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extern AFK_StatusTypeDef psee_afk_deactivate(AFK_HandleTypeDef *afk);
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extern AFK_StatusTypeDef psee_afk_start_statistics(AFK_HandleTypeDef *afk,
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uint32_t acc_time);
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extern AFK_StatusTypeDef psee_afk_stop_statistics(AFK_HandleTypeDef *afk);
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extern uint32_t psee_afk_read_total_evt_cnt(AFK_HandleTypeDef *afk);
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extern uint32_t psee_afk_read_flicker_evt_cnt(AFK_HandleTypeDef *afk);
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extern uint16_t psee_afk_get_f_min(AFK_HandleTypeDef *afk);
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extern uint16_t psee_afk_get_f_max(AFK_HandleTypeDef *afk);
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extern AFK_StateTypeDef psee_afk_get_state(AFK_HandleTypeDef *afk);
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extern AFK_StatisticsTypeDef psee_afk_get_stats(AFK_HandleTypeDef *afk);
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extern uint32_t psee_afk_get_stats_acc_time(AFK_HandleTypeDef *afk);
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/* EHC Configuration Functions */
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extern const struct issd *psee_open_ehc(omv_csi_t *csi);
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extern EHC_StatusTypeDef psee_ehc_init(omv_csi_t *csi, EHC_HandleTypeDef *ehc);
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extern EHC_StatusTypeDef psee_ehc_activate(EHC_HandleTypeDef *ehc,
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EHC_AlgoTypeDef sel_algo,
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uint8_t p_bits_size,
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uint8_t n_bits_size,
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uint32_t integration_period,
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EHC_PaddingTypeDef bits_padding);
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extern EHC_StatusTypeDef psee_ehc_deactivate(EHC_HandleTypeDef *ehc);
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extern EHC_AlgoTypeDef psee_ehc_get_algo(EHC_HandleTypeDef *ehc);
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extern uint8_t psee_ehc_get_p_bits_size(EHC_HandleTypeDef *ehc);
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extern uint8_t psee_ehc_get_n_bits_size(EHC_HandleTypeDef *ehc);
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extern uint32_t psee_ehc_get_accumulation_period(EHC_HandleTypeDef *ehc);
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extern EHC_PaddingTypeDef psee_ehc_get_bits_padding(EHC_HandleTypeDef *ehc);
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extern EHC_StatusTypeDef psee_ehc_activate_override(EHC_HandleTypeDef *ehc,
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EHC_AlgoTypeDef sel_algo,
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uint8_t p_bits_size,
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uint8_t n_bits_size,
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uint32_t integration_period,
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EHC_PaddingTypeDef bits_padding,
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EHC_OverrideTypeDef override);
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extern EHC_StatusTypeDef psee_ehc_start_histo_acc(EHC_HandleTypeDef *ehc);
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extern EHC_StatusTypeDef psee_ehc_drain_histo(EHC_HandleTypeDef *ehc);
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extern void psee_close_ehc(omv_csi_t *csi, const struct issd *issd);
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/* STC Configuration Functions */
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extern STC_StatusTypeDef psee_stc_init(omv_csi_t *csi, STC_HandleTypeDef *stc);
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extern STC_StatusTypeDef psee_stc_only_activate(STC_HandleTypeDef *stc,
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uint32_t stc_threshold,
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uint8_t evt_clk_freq);
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extern STC_StatusTypeDef psee_trail_only_activate(STC_HandleTypeDef *stc,
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uint32_t trail_threshold,
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uint8_t evt_clk_freq);
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extern STC_StatusTypeDef psee_stc_trail_activate(STC_HandleTypeDef *stc,
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uint32_t stc_threshold,
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uint32_t trail_threshold,
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uint8_t evt_clk_freq);
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extern STC_StatusTypeDef psee_stc_trail_deactivate(STC_HandleTypeDef *stc);
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extern STC_StateTypeDef psee_stc_get_state(STC_HandleTypeDef *stc);
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extern STC_ModeTypeDef psee_stc_get_mode(STC_HandleTypeDef *stc);
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extern uint16_t psee_stc_get_params_mult(STC_HandleTypeDef *stc);
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extern uint16_t psee_stc_get_params_presc(STC_HandleTypeDef *stc);
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extern uint16_t psee_stc_get_params_timeout(STC_HandleTypeDef *stc);
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#endif
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