mirror of
https://github.com/openmv/openmv.git
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325 lines
8.4 KiB
C
325 lines
8.4 KiB
C
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/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**
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* @file mhu_driver.h
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* @brief Header file for MHU driver module
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* @par
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* @defgroup host_services host_services
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*/
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#ifndef __MHU_DRIVER_H__
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#define __MHU_DRIVER_H__
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/******************************************************************************
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* I N C L U D E F I L E S
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*****************************************************************************/
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#include <stdint.h>
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#include <stdbool.h>
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#include "mhu.h"
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/*******************************************************************************
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* M A C R O D E F I N E S
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******************************************************************************/
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/*
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* Register bit definitions. The name are as in the SSE700 TRM
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*/
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// Response configuration (RESP_CFG)
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#define MHU_NR_RESP 0x1
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// Access request (ACCESS_REQUEST)
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#define MHU_ACC_REQ 0x1
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// Access ready (ACCESS_READY)
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#define MHU_ACC_RDY 0x1
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// Channel interrupt status
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#define MHU_CH_INT_ST 0x1
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// Channel interrupt status (CH_INT_ST)
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// Channel interrupt clear (CH_INT_CLR)
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// Channel interrupt clear (CH_INT_EN)
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#define MHU_CH_CLR 0x1
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// Interrupt enable (INT_EN)
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#define MHU_CHCOMB 0x4
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#define MHU_R2NR 0x2
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#define MHU_NR2R 0x1
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#define MHU_NUMBER_MAX 10
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#define MHU_CHANNELS 2
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/*******************************************************************************
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* T Y P E D E F S
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******************************************************************************/
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typedef struct
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{
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volatile const uint32_t CH_ST; //0x00
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uint32_t Reserved0; //0x04
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uint32_t Reserved1; //0x08
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volatile uint32_t CH_SET; //0x0C
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volatile const uint32_t CH_INT_ST; //0x10
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volatile uint32_t CH_INT_CLR; //0x14
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volatile uint32_t CH_INT_EN; //0x18
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uint32_t Reserved2; //0x1C
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} MHU_sender_channel_window_t;
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typedef struct
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{
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MHU_sender_channel_window_t CHANNEL[MHU_NUMBER_OF_CHANNELS_MAX]; //0x0-0xF7C
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volatile const uint32_t MHU_CFG;
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volatile uint32_t RESP_CFG;
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volatile uint32_t ACCESS_REQUEST;
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volatile const uint32_t ACCESS_READY;
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volatile const uint32_t INT_ST;
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volatile uint32_t INT_CLR;
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volatile uint32_t INT_EN;
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uint32_t Reserved0;
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volatile const uint32_t CH_INT_ST0;
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volatile const uint32_t CH_INT_ST1;
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volatile const uint32_t CH_INT_ST2;
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volatile const uint32_t CH_INT_ST3;
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uint32_t Reserved1[6];
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volatile const uint32_t IIDR;
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volatile const uint32_t AIDR;
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volatile const uint32_t PID4;
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volatile const uint32_t Reserved2[3];
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volatile const uint32_t PID0;
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volatile const uint32_t PID1;
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volatile const uint32_t PID2;
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volatile const uint32_t PID3;
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volatile const uint32_t CID0;
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volatile const uint32_t CID1;
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volatile const uint32_t CID2;
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volatile const uint32_t CID3;
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} MHU_sender_frame_register_t;
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typedef struct {
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volatile const uint32_t CH_ST; //0x00
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volatile const uint32_t CH_ST_MASKED; //0x04
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volatile uint32_t CH_CLR; //0x08
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uint32_t Reserved0; //0x0C
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volatile const uint32_t CH_MASK_ST; //0x10
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volatile uint32_t CH_MSK_SET; //0x14
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volatile uint32_t CH_MSK_CLR; //0x18
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uint32_t Reserved1; //0x1C
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} MHU_receiver_channel_window_t;
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typedef struct {
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MHU_receiver_channel_window_t CHANNEL[MHU_NUMBER_OF_CHANNELS_MAX];
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volatile const uint32_t MHU_CFG;
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uint32_t Reserved0[3];
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volatile const uint32_t INT_ST;
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volatile uint32_t INT_CLR;
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volatile uint32_t INT_EN;
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uint32_t Reserved1;
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volatile const uint32_t CH_INT_ST0;
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volatile const uint32_t CH_INT_ST1;
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volatile const uint32_t CH_INT_ST2;
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volatile const uint32_t CH_INT_ST3;
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volatile const uint32_t Reserved2[6];
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volatile const uint32_t IIDR;
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volatile const uint32_t AIDR;
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volatile const uint32_t PID4;
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volatile const uint32_t Reserved3[3];
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volatile const uint32_t PID0;
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volatile const uint32_t PID1;
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volatile const uint32_t PID2;
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volatile const uint32_t PID3;
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volatile const uint32_t CID0;
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volatile const uint32_t CID1;
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volatile const uint32_t CID2;
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volatile const uint32_t CID3;
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} MHU_receiver_frame_register_t;
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typedef enum
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{
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MHU_SENDER_INTR_NR2R = 0,
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MHU_SENDER_INTR_R2NR,
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MHU_SENDER_INTR_CHCOMB,
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} MHU_sender_intr_source_t;
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typedef enum
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{
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MHU_CHANNEL_0,
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MHU_CHANNEL_1,
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MHU_CHANNEL_2,
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MHU_CHANNEL_3,
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MHU_CHANNEL_4,
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MHU_CHANNEL_5,
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MHU_CHANNEL_6,
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MHU_CHANNEL_7,
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MHU_CHANNEL_8,
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MHU_CHANNEL_9,
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MHU_CHANNEL_10,
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MHU_CHANNEL_11,
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MHU_CHANNEL_12,
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MHU_CHANNEL_13,
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MHU_CHANNEL_14,
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MHU_CHANNEL_15,
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MHU_CHANNEL_16,
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MHU_CHANNEL_17,
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MHU_CHANNEL_18,
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MHU_CHANNEL_19,
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MHU_CHANNEL_20,
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MHU_CHANNEL_21,
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MHU_CHANNEL_22,
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MHU_CHANNEL_23,
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MHU_CHANNEL_24,
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MHU_CHANNEL_25,
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MHU_CHANNEL_26,
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MHU_CHANNEL_27,
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MHU_CHANNEL_28,
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MHU_CHANNEL_29,
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MHU_CHANNEL_30,
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MHU_CHANNEL_31,
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MHU_CHANNEL_32,
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MHU_CHANNEL_33,
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MHU_CHANNEL_34,
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MHU_CHANNEL_35,
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MHU_CHANNEL_36,
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MHU_CHANNEL_37,
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MHU_CHANNEL_38,
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MHU_CHANNEL_39,
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MHU_CHANNEL_40,
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MHU_CHANNEL_41,
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MHU_CHANNEL_42,
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MHU_CHANNEL_43,
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MHU_CHANNEL_44,
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MHU_CHANNEL_45,
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MHU_CHANNEL_46,
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MHU_CHANNEL_47,
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MHU_CHANNEL_48,
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MHU_CHANNEL_49,
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MHU_CHANNEL_50,
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MHU_CHANNEL_51,
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MHU_CHANNEL_52,
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MHU_CHANNEL_53,
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MHU_CHANNEL_54,
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MHU_CHANNEL_55,
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MHU_CHANNEL_56,
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MHU_CHANNEL_57,
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MHU_CHANNEL_58,
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MHU_CHANNEL_59,
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MHU_CHANNEL_60,
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MHU_CHANNEL_61,
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MHU_CHANNEL_62,
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MHU_CHANNEL_63,
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MHU_CHANNEL_64,
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MHU_CHANNEL_65,
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MHU_CHANNEL_66,
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MHU_CHANNEL_67,
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MHU_CHANNEL_68,
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MHU_CHANNEL_69,
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MHU_CHANNEL_70,
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MHU_CHANNEL_71,
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MHU_CHANNEL_72,
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MHU_CHANNEL_73,
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MHU_CHANNEL_74,
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MHU_CHANNEL_75,
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MHU_CHANNEL_76,
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MHU_CHANNEL_77,
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MHU_CHANNEL_78,
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MHU_CHANNEL_79,
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MHU_CHANNEL_80,
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MHU_CHANNEL_81,
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MHU_CHANNEL_82,
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MHU_CHANNEL_83,
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MHU_CHANNEL_84,
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MHU_CHANNEL_85,
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MHU_CHANNEL_86,
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MHU_CHANNEL_87,
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MHU_CHANNEL_88,
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MHU_CHANNEL_89,
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MHU_CHANNEL_90,
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MHU_CHANNEL_91,
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MHU_CHANNEL_92,
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MHU_CHANNEL_93,
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MHU_CHANNEL_94,
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MHU_CHANNEL_95,
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MHU_CHANNEL_96,
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MHU_CHANNEL_97,
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MHU_CHANNEL_98,
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MHU_CHANNEL_99,
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MHU_CHANNEL_100,
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MHU_CHANNEL_101,
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MHU_CHANNEL_102,
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MHU_CHANNEL_103,
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MHU_CHANNEL_104,
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MHU_CHANNEL_105,
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MHU_CHANNEL_106,
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MHU_CHANNEL_107,
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MHU_CHANNEL_108,
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MHU_CHANNEL_109,
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MHU_CHANNEL_110,
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MHU_CHANNEL_111,
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MHU_CHANNEL_112,
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MHU_CHANNEL_113,
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MHU_CHANNEL_114,
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MHU_CHANNEL_115,
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MHU_CHANNEL_116,
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MHU_CHANNEL_117,
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MHU_CHANNEL_118,
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MHU_CHANNEL_119,
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MHU_CHANNEL_120,
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MHU_CHANNEL_121,
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MHU_CHANNEL_122,
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MHU_CHANNEL_123,
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MHU_CHANNEL_MAX,
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} mhu_channel_number_t;
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typedef enum
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{
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MHU_CHANNEL_COMBINED_CH0_31,
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MHU_CHANNEL_COMBINED_CH32_63,
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MHU_CHANNEL_COMBINED_CH64_95,
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MHU_CHANNEL_COMBINED_CH96_123,
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} mhu_channel_combined_group_t;
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/*******************************************************************************
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* F U N C T I O N P R O T O T Y P E S
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******************************************************************************/
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typedef void (*MHU_sender_callback) (void);
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void MHU_sender_initialize(uint32_t sender_frame_base_address_list[],
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uint32_t sender_frame_count,
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MHU_send_msg_acked_callback_t msg_acked_callback);
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void MHU_send_message_irq_handler(uint32_t sender_id);
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mhu_send_status_t MHU_send_message(uint32_t sender_id,
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uint32_t channel_number,
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uint32_t message_data);
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void MHU_receiver_initialize(
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uint32_t receiver_frame_base_address_list[],
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uint32_t receiver_frame_count,
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MHU_rx_msg_callback_t callback);
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void MHU_receive_message_irq_handler(uint32_t receiver_id);
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#endif /* __MHU_DRIVER_H__ */
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