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715 lines
22 KiB
C
715 lines
22 KiB
C
/*
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* Copyright (C) 2023-2024 OpenMV, LLC.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Any redistribution, use, or modification in source or binary form
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* is done solely for personal benefit and not for any commercial
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* purpose or for monetary gain. For commercial licensing options,
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* please contact openmv@openmv.io
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*
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* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
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* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Alif DMA driver.
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <string.h>
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#include "irq.h"
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#include CMSIS_MCU_H
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#include "evtrtr.h"
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#include "dma_op.h"
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#include "dma_ctrl.h"
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#include "dma_config.h"
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#include "dma_opcode.h"
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#include "dma_mapping.h"
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#include "sys_ctrl_i2s.h"
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#include "sys_ctrl_dma.h"
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#include "py/mphal.h"
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#include "runtime.h"
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#include "alif_hal.h"
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#include "alif_dma.h"
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#define DMA_SHARED_INDEX (0)
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#define DMA_LOCAL_INDEX (1)
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#define DMA_SHARED_FILTER (0)
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#define DMA_LOCAL_FILTER (0)
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#define DMA_IS_LOCAL(dma) ((dma == ((DMA_Type *) DMALOCAL_SEC_BASE)) || (dma == ((DMA_Type *) DMALOCAL_NS_BASE)))
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#define DMA_IS_SECURE(dma) ((dma == ((DMA_Type *) DMALOCAL_SEC_BASE)) || (dma == ((DMA_Type *) DMA0_SEC_BASE)))
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#define DMA_DESCR_INDEX(dma) (DMA_IS_LOCAL(dma) ? DMA_LOCAL_INDEX : DMA_SHARED_INDEX)
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#define IRQ_PRI_DMA NVIC_EncodePriority(NVIC_PRIORITYGROUP_7, 2, 0)
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typedef struct {
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DMA_Type *dma_inst;
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bool is_local;
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bool is_secure;
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bool initialized;
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IRQn_Type irqn;
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uint32_t channels;
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dma_callback_t callback[DMA_MAX_CHANNELS];
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dma_config_info_t config;
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} dma_descr_t;
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typedef dma_channel_info_t chn_descr_t;
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static dma_descr_t dma_descr_all[2] __attribute__((section(".bss.sram0")));
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// DMA helper functions.
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static dma_descr_t *dma_get_dma_descr(DMA_Type *inst) {
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return &dma_descr_all[DMA_DESCR_INDEX(inst)];
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}
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static chn_descr_t *dma_get_chn_descr(DMA_Type *inst, int8_t index) {
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dma_descr_t *dma_descr = dma_get_dma_descr(inst);
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return &dma_descr->config.channel_thread[index].channel_info;
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}
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static bool dma_thread_stopped(DMA_Type *inst, uint8_t index) {
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return (dma_get_channel_status(inst, index) == DMA_THREAD_STATUS_STOPPED);
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}
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static bool dma_thread_allocated(DMA_Type *inst, uint8_t index) {
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dma_descr_t *dma_descr = dma_get_dma_descr(inst);
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return dma_descr->config.channel_thread[index].in_use;
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}
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static void dma_event_handler(dma_descr_t *dma_descr, uint8_t event) {
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uint8_t index = dma_descr->config.event_map[event];
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dma_clear_interrupt(dma_descr->dma_inst, event);
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// Call event callback if set.
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if (dma_descr->callback[index]) {
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dma_descr->callback[index](DMA_EVENT_COMPLETE);
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}
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}
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static void dma_fault_handler(dma_descr_t *dma_descr) {
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if (dma_manager_is_faulting(dma_descr->dma_inst)) {
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// Requires a software reset.
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}
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for (uint8_t index = 0; index < DMA_MAX_CHANNELS; index++) {
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if (dma_get_channel_fault_status(dma_descr->dma_inst, index)) {
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dma_channel_t channel = {
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.index = index,
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.inst = dma_descr->dma_inst
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};
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// Abort channel.
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dma_abort(&channel, true);
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// Call event callback if set.
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if (dma_descr->callback[index]) {
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dma_descr->callback[index](DMA_EVENT_ABORTED);
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}
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}
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}
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}
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static int dma_execute_opcode(DMA_Type *dma, const dma_opcode_buf *opcode, uint8_t channel, uint8_t dthread) {
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uint8_t *opcode_buf = opcode->buf;
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uint8_t opcode_len = opcode->buf_size;
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dma_dbginst0_t dma_dbginst0 = { .dbginst0 = 0 };
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dma_dbginst0.dbginst0_b.chn_num = channel;
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dma_dbginst0.dbginst0_b.dbg_thrd = dthread;
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dma_dbginst0.dbginst0_b.ins_byte0 = opcode_buf[0];
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if (opcode_len > DMA_OP_1BYTE_LEN) {
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dma_dbginst0.dbginst0_b.ins_byte1 = opcode_buf[1];
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}
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dma_dbginst1_t dma_dbginst1 = { .dbginst1 = 0 };
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if (opcode_len > DMA_OP_2BYTE_LEN) {
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dma_dbginst1.dbginst1_b.ins_byte2 = opcode_buf[2];
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}
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if (opcode_len > DMA_OP_3BYTE_LEN) {
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dma_dbginst1.dbginst1_b.ins_byte3 = opcode_buf[3];
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}
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if (opcode_len == DMA_OP_6BYTE_LEN) {
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dma_dbginst1.dbginst1_b.ins_byte4 = opcode_buf[4];
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dma_dbginst1.dbginst1_b.ins_byte5 = opcode_buf[5];
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}
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dma_execute(dma, dma_dbginst0.dbginst0, dma_dbginst1.dbginst1);
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return 0;
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}
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static int dma_init(dma_descr_t *dma_descr, DMA_Type *inst) {
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bool is_local = DMA_IS_LOCAL(inst);
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bool is_secure = DMA_IS_SECURE(inst);
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uint32_t ns_mask = is_secure ? 0 : 0xFFFFFFFF;
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// Reset events and chans_descr.
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dma_reset_all_events(&dma_descr->config);
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dma_reset_all_channels(&dma_descr->config);
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// Initialize DMA
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if (is_local) {
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dmalocal_set_glitch_filter(DMA_LOCAL_FILTER);
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dmalocal_enable_periph_clk();
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evtrtrlocal_enable_dma_req();
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if (is_secure) {
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dmalocal_set_boot_manager_secure();
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} else {
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dmalocal_set_boot_manager_nonsecure();
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}
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dmalocal_set_boot_irq_ns_mask(ns_mask);
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dmalocal_set_boot_periph_ns_mask(ns_mask);
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dmalocal_reset();
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} else {
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dma0_set_glitch_filter(DMA_SHARED_FILTER);
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dma0_enable_periph_clk();
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evtrtr0_enable_dma_req();
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if (is_secure) {
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dma0_set_boot_manager_secure();
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} else {
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dma0_set_boot_manager_nonsecure();
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}
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dma0_set_boot_irq_ns_mask(ns_mask);
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dma0_set_boot_periph_ns_mask(ns_mask);
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dma0_reset();
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}
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dma_descr->dma_inst = inst;
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dma_descr->is_local = is_local;
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dma_descr->is_secure = is_secure;
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dma_descr->irqn = (IRQn_Type) (is_local ? DMALOCAL_IRQ0_IRQn : DMA0_IRQ0_IRQn);
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dma_descr->initialized = true;
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// Configure DMA abort IRQ
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NVIC_ClearPendingIRQ(dma_descr->irqn + DMA_IRQ_ABORT_OFFSET);
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NVIC_SetPriority(dma_descr->irqn + DMA_IRQ_ABORT_OFFSET, IRQ_PRI_DMA);
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NVIC_EnableIRQ(dma_descr->irqn + DMA_IRQ_ABORT_OFFSET);
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return 0;
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}
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static int dma_deinit(dma_descr_t *dma_descr) {
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if (!dma_descr->initialized) {
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return 0;
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}
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// Deinitialize DMA
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if (dma_descr->is_local) {
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dmalocal_reset();
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evtrtrlocal_disable_dma_req();
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dmalocal_disable_periph_clk();
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} else {
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dma0_reset();
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evtrtr0_disable_dma_req();
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dma0_disable_periph_clk();
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}
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// Disable DMA abort IRQ
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NVIC_DisableIRQ(dma_descr->irqn + DMA_IRQ_ABORT_OFFSET);
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NVIC_ClearPendingIRQ(dma_descr->irqn + DMA_IRQ_ABORT_OFFSET);
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// Clear DMA descriptor.
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memset(dma_descr, 0, sizeof(dma_descr_t));
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return 0;
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}
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int dma_deinit_all() {
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dma_deinit(&dma_descr_all[0]);
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dma_deinit(&dma_descr_all[1]);
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return 0;
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}
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int dma_alloc(dma_channel_t *channel, dma_config_t *config) {
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dma_descr_t *dma_descr = dma_get_dma_descr(config->inst);
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chn_descr_t *chn_descr = dma_get_chn_descr(config->inst, channel->index);
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// Set DMA instance.
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channel->inst = config->inst;
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// Initialize DMA descriptor (if not initialized yet).
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if (!dma_descr->initialized) {
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dma_init(dma_descr, channel->inst);
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}
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// Check if DMA instance is configured in a different mode.
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if (dma_descr->dma_inst != channel->inst) {
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return -1;
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}
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// Allocate a DMA channel.
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if ((channel->index = dma_allocate_channel(&dma_descr->config)) < 0) {
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;
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return -1;
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}
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// Allocate a DMA event.
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int8_t event;
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if ((event = dma_allocate_event(&dma_descr->config, channel->index)) < 0) {
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;
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dma_release_channel(&dma_descr->config, channel->index);
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return -1;
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}
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#if CORE_M55_HP
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// Select DMA0 for LP peripherals on HP core.
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// The HE core uses local DMA to access these.
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if (!dma_descr->is_local) {
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switch (config->request & 0xFF) {
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case LPPDM_DMA_PERIPH_REQ:
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lppdm_select_dma0();
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break;
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case LPI2S_DMA_TX_PERIPH_REQ:
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case LPI2S_DMA_RX_PERIPH_REQ:
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lpi2s_select_dma0();
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break;
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case LPUART_DMA_TX_PERIPH_REQ:
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case LPUART_DMA_RX_PERIPH_REQ:
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lpuart_select_dma0();
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break;
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case LPSPI_DMA_TX_PERIPH_REQ:
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case LPSPI_DMA_RX_PERIPH_REQ:
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lpspi_select_dma0(RTE_LPSPI_SELECT_DMA0_GROUP);
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break;
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}
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}
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#endif
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// Configure event router.
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if (dma_descr->is_local) {
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evtrtrlocal_enable_dma_channel(config->request & 0xFF, DMA_ACK_COMPLETION_PERIPHERAL);
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} else {
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evtrtr0_enable_dma_channel(config->request & 0xFF, config->request >> 8, DMA_ACK_COMPLETION_PERIPHERAL);
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evtrtr0_enable_dma_handshake(config->request & 0xFF, config->request >> 8);
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}
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// Update active channels count.
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dma_descr->channels++;
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// Copy channel config to internal channel descriptor.
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chn_descr->flags |= config->flags;
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chn_descr->desc_info.direction = config->direction;
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chn_descr->desc_info.periph_num = config->request & 0xFF;
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chn_descr->desc_info.src_bsize = config->burst_size;
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chn_descr->desc_info.dst_bsize = config->burst_size;
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chn_descr->desc_info.src_blen = config->burst_blen;
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chn_descr->desc_info.dst_blen = config->burst_blen;
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chn_descr->desc_info.sec_state = dma_descr->is_secure == false;
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chn_descr->desc_info.dst_prot_ctrl = dma_descr->is_secure ? 0x00 : 0x02;
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chn_descr->desc_info.src_prot_ctrl = dma_descr->is_secure ? 0x00 : 0x02;
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chn_descr->desc_info.src_cache_ctrl = (config->direction == DMA_TRANSFER_DEV_TO_MEM) ? 0x0 : 0x02;
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chn_descr->desc_info.dst_cache_ctrl = (config->direction == DMA_TRANSFER_MEM_TO_DEV) ? 0x0 : 0x02;
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chn_descr->desc_info.endian_swap_size = config->byte_swap;
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// Configure the DMA channel's IRQ priority.
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NVIC_SetPriority(dma_descr->irqn + chn_descr->event_index, config->priority);
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return 0;
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}
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int dma_start(dma_channel_t *channel, void *src, void *dst0, void *dst1, uint32_t size, dma_callback_t callback) {
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dma_descr_t *dma_descr = dma_get_dma_descr(channel->inst);
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chn_descr_t *chn_descr = dma_get_chn_descr(channel->inst, channel->index);
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uint8_t go_opcode_buf[DMA_OP_6BYTE_LEN] = {0};
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dma_opcode_buf go_opcode = { .off = 0, .buf = go_opcode_buf, .buf_size = DMA_OP_6BYTE_LEN };
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if (dma_debug_is_busy(dma_descr->dma_inst)) {
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mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("DMA debug is busy"));
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}
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if (!dma_thread_stopped(dma_descr->dma_inst, channel->index)) {
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mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("DMA channel is busy"));
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}
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if (!dma_thread_allocated(dma_descr->dma_inst, channel->index)) {
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mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("DMA channel not allocated"));
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}
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if (((uint32_t) src | (uint32_t) dst0 | size)
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& ((1 << (uint32_t) chn_descr->desc_info.dst_bsize) - 1)) {
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mp_raise_msg(&mp_type_ValueError, MP_ERROR_TEXT("Unaligned DMA transfer"));
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}
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// Set transfer source, destination and and total size.
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chn_descr->desc_info.src_addr = LocalToGlobal(src);
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chn_descr->desc_info.dst_addr0 = LocalToGlobal(dst0);
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chn_descr->desc_info.dst_addr1 = LocalToGlobal(dst1);
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chn_descr->desc_info.total_len = size;
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if (!dma_generate_opcode(&dma_descr->config, channel->index)) {
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mp_raise_msg(&mp_type_RuntimeError, MP_ERROR_TEXT("Generate OP code failed"));
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}
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// Flush opcode buffer.
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uint8_t *opcode_buf = dma_get_opcode_buf(&dma_descr->config, channel->index);
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RTSS_CleanDCache_by_Addr(opcode_buf, DMA_MICROCODE_SIZE);
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// Construct go microcode.
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dma_construct_go(!dma_descr->is_secure, channel->index, LocalToGlobal(opcode_buf), &go_opcode);
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dma_execute_opcode(dma_descr->dma_inst, &go_opcode, channel->index, DMA_THREAD_MANAGER);
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// Set channel callback
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dma_descr->callback[channel->index] = callback;
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// Configure and enable DMA channel IRQ
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IRQn_Type irqn = (IRQn_Type) (dma_descr->irqn + chn_descr->event_index);
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NVIC_DisableIRQ(irqn);
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NVIC_ClearPendingIRQ(irqn);
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NVIC_EnableIRQ(irqn);
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dma_clear_interrupt(dma_descr->dma_inst, chn_descr->event_index);
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dma_enable_interrupt(dma_descr->dma_inst, chn_descr->event_index);
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return 0;
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}
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int dma_abort(dma_channel_t *channel, bool dealloc) {
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dma_descr_t *dma_descr = dma_get_dma_descr(channel->inst);
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chn_descr_t *chn_descr = dma_get_chn_descr(channel->inst, channel->index);
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uint8_t opcode_buf[DMA_OP_1BYTE_LEN] = { 0 };
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dma_opcode_buf kill_opcode = { .off = 0, .buf = opcode_buf, .buf_size = DMA_OP_1BYTE_LEN };
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if (!dma_descr->initialized ||
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!dma_descr->channels ||
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dma_debug_is_busy(dma_descr->dma_inst) ||
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dma_thread_stopped(dma_descr->dma_inst, channel->index) ||
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!dma_thread_allocated(dma_descr->dma_inst, channel->index)) {
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return -1;
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}
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// Construct kill microcode.
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dma_construct_kill(&kill_opcode);
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dma_execute_opcode(dma_descr->dma_inst, &kill_opcode, channel->index, DMA_THREAD_CHANNEL);
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for (size_t i = 0, max_retry = 1000; i < max_retry; i++) {
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if (dma_thread_stopped(dma_descr->dma_inst, channel->index)) {
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break;
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}
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if ((i + 1) == max_retry) {
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return -1;
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}
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}
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// Disable and clear DMA channel IRQ
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IRQn_Type irqn = (IRQn_Type) (dma_descr->irqn + chn_descr->event_index);
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NVIC_DisableIRQ(irqn);
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NVIC_ClearPendingIRQ(irqn);
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dma_disable_interrupt(dma_descr->dma_inst, chn_descr->event_index);
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dma_clear_interrupt(dma_descr->dma_inst, chn_descr->event_index);
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printf("DMA channel: %d event: %d stopped\n", channel->index, chn_descr->event_index);
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// Deallocate channel
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if (dealloc) {
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dma_descr->channels--;
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dma_release_event(&dma_descr->config, chn_descr->event_index);
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dma_release_channel(&dma_descr->config, channel->index);
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}
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|
// Deinit DMA if last channel.
|
|
if (dma_descr->channels == 0) {
|
|
dma_deinit(dma_descr);
|
|
}
|
|
|
|
// Clear callback
|
|
dma_descr->callback[channel->index] = NULL;
|
|
return 0;
|
|
}
|
|
|
|
void *dma_target_address(dma_channel_t *channel) {
|
|
chn_descr_t *chn_descr = dma_get_chn_descr(channel->inst, channel->index);
|
|
uint32_t target = dma_get_channel_dest_addr(channel->inst, channel->index);
|
|
if (chn_descr->desc_info.dst_addr1 == 0) {
|
|
// Single buffer mode.
|
|
return GlobalToLocal(target);
|
|
} else if (target == chn_descr->desc_info.dst_addr0) {
|
|
return GlobalToLocal(chn_descr->desc_info.dst_addr1);
|
|
} else {
|
|
return GlobalToLocal(chn_descr->desc_info.dst_addr0);
|
|
}
|
|
}
|
|
|
|
// DMA0 Handlers
|
|
void DMA0_IRQ0Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 0);
|
|
}
|
|
|
|
void DMA0_IRQ1Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 1);
|
|
}
|
|
|
|
void DMA0_IRQ2Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 2);
|
|
}
|
|
|
|
void DMA0_IRQ3Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 3);
|
|
}
|
|
|
|
void DMA0_IRQ4Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 4);
|
|
}
|
|
|
|
void DMA0_IRQ5Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 5);
|
|
}
|
|
|
|
void DMA0_IRQ6Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 6);
|
|
}
|
|
|
|
void DMA0_IRQ7Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 7);
|
|
}
|
|
|
|
void DMA0_IRQ8Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 8);
|
|
}
|
|
|
|
void DMA0_IRQ9Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 9);
|
|
}
|
|
|
|
void DMA0_IRQ10Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 10);
|
|
}
|
|
|
|
void DMA0_IRQ11Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 11);
|
|
}
|
|
|
|
void DMA0_IRQ12Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 12);
|
|
}
|
|
|
|
void DMA0_IRQ13Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 13);
|
|
}
|
|
|
|
void DMA0_IRQ14Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 14);
|
|
}
|
|
|
|
void DMA0_IRQ15Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 15);
|
|
}
|
|
|
|
void DMA0_IRQ16Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 16);
|
|
}
|
|
|
|
void DMA0_IRQ17Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 17);
|
|
}
|
|
|
|
void DMA0_IRQ18Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 18);
|
|
}
|
|
|
|
void DMA0_IRQ19Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 19);
|
|
}
|
|
|
|
void DMA0_IRQ20Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 20);
|
|
}
|
|
|
|
void DMA0_IRQ21Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 21);
|
|
}
|
|
|
|
void DMA0_IRQ22Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 22);
|
|
}
|
|
|
|
void DMA0_IRQ23Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 23);
|
|
}
|
|
|
|
void DMA0_IRQ24Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 24);
|
|
}
|
|
|
|
void DMA0_IRQ25Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 25);
|
|
}
|
|
|
|
void DMA0_IRQ26Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 26);
|
|
}
|
|
|
|
void DMA0_IRQ27Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 27);
|
|
}
|
|
|
|
void DMA0_IRQ28Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 28);
|
|
}
|
|
|
|
void DMA0_IRQ29Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 29);
|
|
}
|
|
|
|
void DMA0_IRQ30Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 30);
|
|
}
|
|
|
|
void DMA0_IRQ31Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_SHARED_INDEX], 31);
|
|
}
|
|
|
|
void DMA0_IRQ_ABORT_Handler(void) {
|
|
dma_fault_handler(&dma_descr_all[DMA_SHARED_INDEX]);
|
|
}
|
|
|
|
// DMALOCAL Handlers
|
|
void DMALOCAL_IRQ0Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 0);
|
|
}
|
|
|
|
void DMALOCAL_IRQ1Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 1);
|
|
}
|
|
|
|
void DMALOCAL_IRQ2Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 2);
|
|
}
|
|
|
|
void DMALOCAL_IRQ3Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 3);
|
|
}
|
|
|
|
void DMALOCAL_IRQ4Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 4);
|
|
}
|
|
|
|
void DMALOCAL_IRQ5Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 5);
|
|
}
|
|
|
|
void DMALOCAL_IRQ6Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 6);
|
|
}
|
|
|
|
void DMALOCAL_IRQ7Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 7);
|
|
}
|
|
|
|
void DMALOCAL_IRQ8Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 8);
|
|
}
|
|
|
|
void DMALOCAL_IRQ9Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 9);
|
|
}
|
|
|
|
void DMALOCAL_IRQ10Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 10);
|
|
}
|
|
|
|
void DMALOCAL_IRQ11Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 11);
|
|
}
|
|
|
|
void DMALOCAL_IRQ12Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 12);
|
|
}
|
|
|
|
void DMALOCAL_IRQ13Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 13);
|
|
}
|
|
|
|
void DMALOCAL_IRQ14Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 14);
|
|
}
|
|
|
|
void DMALOCAL_IRQ15Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 15);
|
|
}
|
|
|
|
void DMALOCAL_IRQ16Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 16);
|
|
}
|
|
|
|
void DMALOCAL_IRQ17Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 17);
|
|
}
|
|
|
|
void DMALOCAL_IRQ18Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 18);
|
|
}
|
|
|
|
void DMALOCAL_IRQ19Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 19);
|
|
}
|
|
|
|
void DMALOCAL_IRQ20Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 20);
|
|
}
|
|
|
|
void DMALOCAL_IRQ21Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 21);
|
|
}
|
|
|
|
void DMALOCAL_IRQ22Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 22);
|
|
}
|
|
|
|
void DMALOCAL_IRQ23Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 23);
|
|
}
|
|
|
|
void DMALOCAL_IRQ24Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 24);
|
|
}
|
|
|
|
void DMALOCAL_IRQ25Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 25);
|
|
}
|
|
|
|
void DMALOCAL_IRQ26Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 26);
|
|
}
|
|
|
|
void DMALOCAL_IRQ27Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 27);
|
|
}
|
|
|
|
void DMALOCAL_IRQ28Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 28);
|
|
}
|
|
|
|
void DMALOCAL_IRQ29Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 29);
|
|
}
|
|
|
|
void DMALOCAL_IRQ30Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 30);
|
|
}
|
|
|
|
void DMALOCAL_IRQ31Handler(void) {
|
|
dma_event_handler(&dma_descr_all[DMA_LOCAL_INDEX], 31);
|
|
}
|
|
|
|
void DMALOCAL_IRQ_ABORT_Handler(void) {
|
|
dma_fault_handler(&dma_descr_all[DMA_LOCAL_INDEX]);
|
|
}
|