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353 lines
15 KiB
C
353 lines
15 KiB
C
/**
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******************************************************************************
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* @file stm32n6xx_hal_cacheaxi.h
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* @author MCD Application Team
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* @brief Header file of CACHEAXI HAL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion ------------------------------------*/
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#ifndef STM32N6xx_HAL_CACHEAXI_H
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#define STM32N6xx_HAL_CACHEAXI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes -----------------------------------------------------------------*/
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#include "stm32n6xx_hal_def.h"
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/** @addtogroup STM32N6xx_HAL_Driver
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* @{
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*/
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#if defined (CACHEAXI)
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/** @addtogroup CACHEAXI
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup CACHEAXI_Exported_Types CACHEAXI Exported Types
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* @{
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*/
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/**
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* @brief HAL State structures definition
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*/
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typedef enum
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{
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HAL_CACHEAXI_STATE_RESET = 0x00U, /*!< CACHEAXI not yet initialized or disabled */
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HAL_CACHEAXI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
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HAL_CACHEAXI_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
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HAL_CACHEAXI_STATE_TIMEOUT = 0x05U, /*!< Timeout state */
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HAL_CACHEAXI_STATE_ERROR = 0x06U, /*!< CACHEAXI state error */
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} HAL_CACHEAXI_StateTypeDef;
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/** @defgroup CACHEAXI_Configuration_Structure_definition CACHEAXI Configuration Structure definition
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* @brief CACHEAXI Configuration Structure definition
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* @{
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*/
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#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
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typedef struct __CACHEAXI_HandleTypeDef
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#else
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typedef struct
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#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
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{
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CACHEAXI_TypeDef *Instance; /*!< CACHEAXI register base address. */
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__IO HAL_CACHEAXI_StateTypeDef State;
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__IO uint32_t ErrorCode;
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#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
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void (* ErrorCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
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void (* CleanByAddrCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
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void (* InvalidateCompleteCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
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void (* CleanAndInvalidateByAddrCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
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void (* MspInitCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
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void (* MspDeInitCallback)(struct __CACHEAXI_HandleTypeDef *hcacheaxi);
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#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
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} CACHEAXI_HandleTypeDef;
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#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
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/**
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* @brief HAL CACHEAXI Callback ID enumeration definition
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*/
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typedef enum
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{
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HAL_CACHEAXI_CLEAN_BY_ADDRESS_CB_ID = 0x00U, /*!< CACHEAXI Clean By Address callback ID */
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HAL_CACHEAXI_CLEAN_AND_INVALIDATE_BY_ADDRESS_CB_ID = 0x01U, /*!< CACHEAXI Clean And Invalidate By Address callback ID */
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HAL_CACHEAXI_INVALIDATE_COMPLETE_CB_ID = 0x02U, /*!< CACHEAXI Invalidate Complete ID */
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HAL_CACHEAXI_ERROR_CB_ID = 0x03U, /*!< CACHEAXI Error callback ID */
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HAL_CACHEAXI_MSPINIT_CB_ID = 0x04U, /*!< CACHEAXI Msp Init callback ID */
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HAL_CACHEAXI_MSPDEINIT_CB_ID = 0x05U /*!< CACHEAXI Msp DeInit callback ID */
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} HAL_CACHEAXI_CallbackIDTypeDef;
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/**
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* @brief HAL CACHEAXI Callback pointer definition
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*/
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/*!< Pointer to a CACHEAXI common callback function */
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typedef void (*pCACHEAXI_CallbackTypeDef)(CACHEAXI_HandleTypeDef *hcacheaxi);
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#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported constants -------------------------------------------------------*/
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/** @defgroup CACHEAXI_Exported_Constants CACHEAXI Exported Constants
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* @{
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*/
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/** @defgroup CACHEAXI_Error_Code CACHEAXI Error Code
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* @{
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*/
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#define HAL_CACHEAXI_ERROR_NONE 0x00000000U /*!< No error */
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#define HAL_CACHEAXI_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
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#define HAL_CACHEAXI_ERROR_EVICTION_CLEAN 0x00000020U /*!< Eviction or clean operation write-back error */
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#define HAL_CACHEAXI_ERROR_INVALID_OPERATION 0x00000040U /*!< Invalid operation */
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#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
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#define HAL_CACHEAXI_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid callback error */
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#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_Monitor_Type Monitor type
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* @{
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*/
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#define CACHEAXI_MONITOR_READ_HIT CACHEAXI_CR1_RHITMEN /*!< Read Hit monitoring */
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#define CACHEAXI_MONITOR_READ_MISS CACHEAXI_CR1_RMISSMEN /*!< Read Miss monitoring */
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#define CACHEAXI_MONITOR_WRITE_HIT CACHEAXI_CR1_WHITMEN /*!< Write Hit monitoring */
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#define CACHEAXI_MONITOR_WRITE_MISS CACHEAXI_CR1_WMISSMEN /*!< Write Miss monitoring */
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#define CACHEAXI_MONITOR_READALLOC_MISS CACHEAXI_CR1_RAMMEN /*!< Read-allocate Miss monitoring */
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#define CACHEAXI_MONITOR_WRITEALLOC_MISS CACHEAXI_CR1_WAMMEN /*!< Write-allocate Miss monitoring */
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#define CACHEAXI_MONITOR_WRITETHROUGH CACHEAXI_CR1_WTMEN /*!< Write-through monitoring */
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#define CACHEAXI_MONITOR_EVICTION CACHEAXI_CR1_EVIMEN /*!< Eviction monitoring */
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#define CACHEAXI_MONITOR_ALL (CACHEAXI_CR1_RHITMEN | CACHEAXI_CR1_RMISSMEN | \
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CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_WMISSMEN | \
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CACHEAXI_CR1_RAMMEN | CACHEAXI_CR1_WAMMEN | \
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CACHEAXI_CR1_WTMEN | CACHEAXI_CR1_EVIMEN )
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_Interrupts Interrupts
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* @{
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*/
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#define CACHEAXI_IT_BUSYEND CACHEAXI_IER_BSYENDIE /*!< Busy end interrupt */
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#define CACHEAXI_IT_ERROR CACHEAXI_IER_ERRIE /*!< Cache error interrupt */
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#define CACHEAXI_IT_CMDEND CACHEAXI_IER_CMDENDIE /*!< Command end interrupt */
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_Flags Flags
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* @{
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*/
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#define CACHEAXI_FLAG_BUSY CACHEAXI_SR_BUSYF /*!< Busy flag */
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#define CACHEAXI_FLAG_BUSYEND CACHEAXI_SR_BSYENDF /*!< Busy end flag */
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#define CACHEAXI_FLAG_ERROR CACHEAXI_SR_ERRF /*!< Cache error flag */
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#define CACHEAXI_FLAG_BUSYCMD CACHEAXI_SR_BUSYCMDF /*!< Busy command flag */
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#define CACHEAXI_FLAG_CMDEND CACHEAXI_SR_CMDENDF /*!< Command end flag */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros ----------------------------------------------------------*/
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/** @defgroup CACHEAXI_Exported_Macros CACHEAXI Exported Macros
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* @{
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*/
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/** @brief Enable CACHEAXI interrupts.
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* @param __HANDLE__ specifies the CACHEAXI handle.
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* @param __INTERRUPT__ specifies the CACHEAXI interrupt sources to be enabled.
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* This parameter can be any combination of the following values:
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* @arg @ref CACHEAXI_IT_BUSYEND Busy end interrupt
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* @arg @ref CACHEAXI_IT_ERROR Cache error interrupt
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* @arg @ref CACHEAXI_IT_CMDEND Cache Command end interrupt
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* @retval None
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*/
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#define __HAL_CACHEAXI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
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/** @brief Disable CACHEAXI interrupts.
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* @param __HANDLE__ specifies the CACHEAXI handle.
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* @param __INTERRUPT__ specifies the CACHEAXI interrupt sources to be disabled.
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* This parameter can be any combination of the following values:
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* @arg @ref CACHEAXI_IT_BUSYEND Busy end interrupt
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* @arg @ref CACHEAXI_IT_ERROR Cache error interrupt
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* @arg @ref CACHEAXI_IT_CMDEND Cache Command end interrupt
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* @retval None
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*/
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#define __HAL_CACHEAXI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
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/** @brief Check whether the specified CACHEAXI interrupt source is enabled or not.
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* @param __HANDLE__ specifies the CACHEAXI handle.
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* @param __INTERRUPT__ specifies the CACHEAXI interrupt source to check.
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* This parameter can be any combination of the following values:
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* @arg @ref CACHEAXI_IT_BUSYEND Busy end interrupt
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* @arg @ref CACHEAXI_IT_ERROR Cache error interrupt
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* @arg @ref CACHEAXI_IT_CMDEND Cache Command end interrupt
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*
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* @retval The state of __INTERRUPT__ (SET or RESET).
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*/
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#define __HAL_CACHEAXI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
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((READ_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
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/** @brief Check whether the selected CACHEAXI flag is set or not.
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* @param __HANDLE__ specifies the CACHEAXI handle.
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* @param __FLAG__ specifies the flag to check.
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* This parameter can be one of the following values:
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* @arg @ref CACHEAXI_FLAG_BUSY Busy flag
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* @arg @ref CACHEAXI_FLAG_BUSYEND Busy end flag
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* @arg @ref CACHEAXI_FLAG_ERROR Cache error flag
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* @arg @ref CACHEAXI_FLAG_BUSYCMD Cache Busy command flag
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* @arg @ref CACHEAXI_FLAG_CMDEND Cache command end flag
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* @retval The state of __FLAG__ (0 or 1).
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*/
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#define __HAL_CACHEAXI_GET_FLAG(__HANDLE__, __FLAG__) \
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((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? 1U : 0U)
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/** @brief Clear the selected CACHEAXI flags.
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* @param __HANDLE__ specifies the CACHEAXI handle.
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* @param __FLAG__ specifies the CACHEAXI flags to clear.
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* This parameter can be any combination of the following values:
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* @arg @ref CACHEAXI_FLAG_BUSYEND Busy end flag
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* @arg @ref CACHEAXI_FLAG_ERROR Cache error flag
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* @arg @ref CACHEAXI_FLAG_CMDEND Cache command end flag
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*/
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#define __HAL_CACHEAXI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
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/**
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* @}
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*/
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/* Exported functions -------------------------------------------------------*/
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/** @defgroup CACHEAXI_Exported_Functions CACHEAXI Exported Functions
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* @brief CACHEAXI Exported functions
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* @{
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*/
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/** @defgroup CACHEAXI_Exported_Functions_Group1 Initialization and De-Initialization Functions
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* @brief Initialization and De-Initialization Functions
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* @{
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*/
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HAL_StatusTypeDef HAL_CACHEAXI_Init(CACHEAXI_HandleTypeDef *hcacheaxi);
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HAL_StatusTypeDef HAL_CACHEAXI_DeInit(CACHEAXI_HandleTypeDef *hcacheaxi);
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void HAL_CACHEAXI_MspInit(CACHEAXI_HandleTypeDef *hcacheaxi);
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void HAL_CACHEAXI_MspDeInit(CACHEAXI_HandleTypeDef *hcacheaxi);
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_Exported_Functions_Group2 I/O Operation Functions
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* @brief I/O Operation Functions
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* @{
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*/
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/* Peripheral Control functions ***/
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HAL_StatusTypeDef HAL_CACHEAXI_Enable(CACHEAXI_HandleTypeDef *hcacheaxi);
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HAL_StatusTypeDef HAL_CACHEAXI_Disable(CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_IsEnabled(const CACHEAXI_HandleTypeDef *hcacheaxi);
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/*** Cache maintenance in blocking mode (Polling) ***/
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HAL_StatusTypeDef HAL_CACHEAXI_Invalidate(CACHEAXI_HandleTypeDef *hcacheaxi);
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HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
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uint32_t dSize);
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HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
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uint32_t dSize);
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/*** Cache maintenance in non-blocking mode (Interrupt) ***/
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HAL_StatusTypeDef HAL_CACHEAXI_Invalidate_IT(CACHEAXI_HandleTypeDef *hcacheaxi);
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HAL_StatusTypeDef HAL_CACHEAXI_CleanByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
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uint32_t dSize);
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HAL_StatusTypeDef HAL_CACHEAXI_CleanInvalidByAddr_IT(CACHEAXI_HandleTypeDef *hcacheaxi, const uint32_t *const pAddr,
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uint32_t dSize);
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/*** IRQHandler and Callbacks ***/
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void HAL_CACHEAXI_IRQHandler(CACHEAXI_HandleTypeDef *hcacheaxi);
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void HAL_CACHEAXI_ErrorCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
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void HAL_CACHEAXI_CleanByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
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void HAL_CACHEAXI_InvalidateCompleteCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
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void HAL_CACHEAXI_CleanAndInvalidateByAddrCallback(CACHEAXI_HandleTypeDef *hcacheaxi);
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#if (USE_HAL_CACHEAXI_REGISTER_CALLBACKS == 1)
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/* Callbacks Register/UnRegister functions ***/
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HAL_StatusTypeDef HAL_CACHEAXI_RegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi,
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HAL_CACHEAXI_CallbackIDTypeDef CallbackID,
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pCACHEAXI_CallbackTypeDef pCallback);
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HAL_StatusTypeDef HAL_CACHEAXI_UnRegisterCallback(CACHEAXI_HandleTypeDef *hcacheaxi,
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HAL_CACHEAXI_CallbackIDTypeDef CallbackID);
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#endif /* USE_HAL_CACHEAXI_REGISTER_CALLBACKS */
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/*** Performance instruction cache monitoring functions ***/
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uint32_t HAL_CACHEAXI_Monitor_GetReadHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_Monitor_GetReadMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_Monitor_GetWriteHitValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_Monitor_GetWriteMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_Monitor_GetReadAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_Monitor_GetWriteAllocMissValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_Monitor_GetWriteThroughValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_Monitor_GetEvictionValue(const CACHEAXI_HandleTypeDef *hcacheaxi);
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HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Reset(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType);
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HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Start(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType);
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HAL_StatusTypeDef HAL_CACHEAXI_Monitor_Stop(CACHEAXI_HandleTypeDef *hcacheaxi, uint32_t MonitorType);
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_Exported_Functions_Group3 State and Error Functions
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* @brief State and Error Functions
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* @{
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*/
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HAL_CACHEAXI_StateTypeDef HAL_CACHEAXI_GetState(const CACHEAXI_HandleTypeDef *hcacheaxi);
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uint32_t HAL_CACHEAXI_GetError(const CACHEAXI_HandleTypeDef *hcacheaxi);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/**
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* @}
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*/
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#endif /* CACHEAXI */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32N6xx_HAL_CACHEAXI_H */
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