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373 lines
13 KiB
C
373 lines
13 KiB
C
/**
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******************************************************************************
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* @file stm32n6xx_ll_utils.h
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* @author MCD Application Team
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* @brief Header file of UTILS LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL UTILS driver contains a set of generic APIs that can be
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used by user:
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(+) Device electronic signature
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(+) Timing functions
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(+) PLL configuration functions
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@endverbatim
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32N6xx_LL_UTILS_H
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#define STM32N6xx_LL_UTILS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32n6xx.h"
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#include "stm32n6xx_ll_system.h"
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#include "stm32n6xx_ll_bus.h"
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#include "stm32n6xx_ll_rcc.h"
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/** @addtogroup STM32N6xx_LL_Driver
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* @{
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*/
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/** @defgroup UTILS_LL UTILS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
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* @{
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*/
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/* Max delay can be used in LL_mDelay */
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#define LL_MAX_DELAY 0xFFFFFFFFUL
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/**
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* @brief Unique device ID register base address
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* Available from BSEC_OTP_DATA5...BSEC_OTP_DATA7
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*/
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#define UID_BASE_ADDRESS (BSEC_BASE + 0x14U)
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/**
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* @brief Device RPN register base address
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* Available from BSEC_OTP_DATA9
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*/
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#define RPN_BASE_ADDRESS (BSEC_BASE + 0x24U)
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/**
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* @brief Package data register base address
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* Available from BSEC_OTP_DATA122
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*/
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#define PACKAGE_BASE_ADDRESS (BSEC_BASE + 0x1E8U)
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
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* @{
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*/
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/**
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* @brief UTILS PLL structure definition
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*/
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typedef struct
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{
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uint32_t PLLM; /*!< Division factor M for PLL VCO input clock.
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This parameter must be a number between Min_Data = 1 and Max_Data = 63
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and shall ensure that VCO input is below 50 MHz.
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetM(). */
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uint32_t PLLN; /*!< Multiplication factor N for PLL VCO output clock.
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This parameter must be a number between Min_Data = 16 and Max_Data = 640
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in integer mode and between Min_Data = 20 and Max_Data = 320 in fractional mode
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetN(). */
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uint32_t PLLP1; /*!< Division factor level 1 for PLL VCO output clock.
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This parameter must be a number between Min_Data = 1 and Max_Data = 7
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetP1(). */
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uint32_t PLLP2; /*!< Division factor level 2 for PLL VCO output clock.
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This parameter must be a number between Min_Data = 1 and Max_Data = 7
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetP2(). */
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uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO.
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This parameter can be a value between 0 and (2^24)-1
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_PLL1_SetFRACN(). */
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} LL_UTILS_PLLInitTypeDef;
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/**
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* @brief UTILS IC structure definition
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*/
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typedef struct
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{
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uint32_t IC1Source; /*!< The IC1 clock source for sysa_ck(cpu_ck) */
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uint32_t IC1Divider; /*!< The IC1 clock divider for sysa_ck(cpu_ck) */
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uint32_t IC2Source; /*!< The IC2 clock source for sysb_ck */
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uint32_t IC2Divider; /*!< The IC2 clock divider for sysb_ck */
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uint32_t IC6Source; /*!< The IC6 clock source for sysc_ck */
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uint32_t IC6Divider; /*!< The IC6 clock divider for sysc_ck */
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uint32_t IC11Source; /*!< The IC11 clock source for sysd_ck */
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uint32_t IC11Divider; /*!< The IC11 clock divider for sysd_ck */
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} LL_UTILS_ICInitTypeDef;
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/**
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* @brief UTILS System, AHB and APB buses clock configuration structure definition
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*/
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typedef struct
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{
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uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
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This parameter can be a value of @ref RCC_LL_EC_AHB_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAHBPrescaler(). */
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uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB1Prescaler(). */
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uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB2Prescaler(). */
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uint32_t APB4CLKDivider; /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB4_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB4Prescaler(). */
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uint32_t APB5CLKDivider; /*!< The APB5 clock (PCLK5) divider. This clock is derived from the AHB clock (HCLK).
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This parameter can be a value of @ref RCC_LL_EC_APB5_DIV
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This feature can be modified afterwards using unitary function
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@ref LL_RCC_SetAPB5Prescaler(). */
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} LL_UTILS_ClkInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
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* @{
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*/
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/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
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* @{
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*/
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#define LL_UTILS_HSEBYPASS_OFF 0U /*!< HSE Bypass is not enabled */
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#define LL_UTILS_HSEBYPASS_ON 1U /*!< HSE Bypass is enabled */
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/**
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* @}
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*/
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/** @defgroup UTILS_EC_DEVICE_RPN DEVICE RPN
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* @{
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*/
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#define LL_UTILS_DEVICE_STM32N657 0x2000U /*!< STM32N657 */
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#define LL_UTILS_DEVICE_STM32N647 0x2200U /*!< STM32N647 */
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#define LL_UTILS_DEVICE_STM32N655 0x6000U /*!< STM32N655 */
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#define LL_UTILS_DEVICE_STM32N645 0x6200U /*!< STM32N645 */
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/**
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* @}
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*/
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/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
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* @{
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*/
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#define LL_UTILS_PACKAGETYPE_BGA142 2U /*!< BGA142 package type */
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#define LL_UTILS_PACKAGETYPE_BGA169 4U /*!< BGA169 package type */
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#define LL_UTILS_PACKAGETYPE_BGA178 6U /*!< BGA178 package type */
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#define LL_UTILS_PACKAGETYPE_BGA198 8U /*!< BGA198 package type */
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#define LL_UTILS_PACKAGETYPE_BGA223 10U /*!< BGA223 package type */
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#define LL_UTILS_PACKAGETYPE_BGA264 12U /*!< BGA264 package type */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
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* @{
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*/
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/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
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* @{
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*/
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/**
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* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
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* @note The application must ensures that SYSCFG clock is enabled.
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* @retval UID[31:0]
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
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{
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return (uint32_t)(READ_REG(*((__IO uint32_t *)UID_BASE_ADDRESS)));
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}
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/**
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* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
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* @note The application must ensures that SYSCFG clock is enabled.
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* @retval UID[63:32]
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
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{
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return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 4U))));
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}
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/**
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* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
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* @note The application must ensures that SYSCFG clock is enabled.
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* @retval UID[95:64]
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*/
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__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
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{
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return (uint32_t)(READ_REG(*((__IO uint32_t *)(UID_BASE_ADDRESS + 8U))));
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}
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/**
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* @brief Get Package type
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* @note The application must ensures that SYSCFG clock is enabled.
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA142
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA169
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA178
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA198
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA223
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* @arg @ref LL_UTILS_PACKAGETYPE_BGA264
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*/
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__STATIC_INLINE uint32_t LL_GetPackageType(void)
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{
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return (uint32_t)(READ_REG(*((__IO uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0FUL);
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}
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/**
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* @brief Get Device Part Number (RPN)
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* @note The application must ensures that SYSCFG clock is enabled.
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_UTILS_DEVICE_STM32N657
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* @arg @ref LL_UTILS_DEVICE_STM32N647
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* @arg @ref LL_UTILS_DEVICE_STM32N645
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*/
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__STATIC_INLINE uint32_t LL_GetDevicePartNumber(void)
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{
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return (uint32_t)(READ_REG(*((__IO uint32_t *)RPN_BASE_ADDRESS)));
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}
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/**
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* @}
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*/
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/** @defgroup UTILS_LL_EF_DELAY DELAY
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* @{
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*/
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/**
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* @brief This function configures the Cortex-M SysTick source of the time base.
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* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
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* @note When a RTOS is used, it is recommended to avoid changing the SysTick
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* configuration by calling this function, for a delay use rather osDelay RTOS service.
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* @param Ticks Number of ticks
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* @retval None
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*/
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__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
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{
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if (Ticks > 0U)
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{
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/* Configure the SysTick to have interrupt in 1ms time base */
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SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
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SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
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SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
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SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
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}
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}
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void LL_Init1msTick(uint32_t CPU_Frequency);
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void LL_mDelay(uint32_t Delay);
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/**
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* @}
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*/
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/** @defgroup UTILS_EF_SYSTEM SYSTEM
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* @{
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*/
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void LL_SetSystemCoreClock(uint32_t CPU_Frequency);
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ErrorStatus LL_PLL_ConfigSystemClock_HSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
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const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct,
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const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct);
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ErrorStatus LL_PLL_ConfigSystemClock_MSI(const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
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const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct,
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const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct);
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ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
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uint32_t HSEBypass,
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const LL_UTILS_PLLInitTypeDef *pUTILS_PLLInitStruct,
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const LL_UTILS_ICInitTypeDef *pUTILS_ICInitStruct,
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const LL_UTILS_ClkInitTypeDef *pUTILS_ClkInitStruct);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* STM32N6xx_LL_UTILS_H */
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