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https://github.com/openmv/openmv.git
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426 lines
14 KiB
C
426 lines
14 KiB
C
/**
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**********************************************************************************************************************
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* @file stm32n6xx_util_i3c.c
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* @author MCD Application Team
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* @brief This utility help to calculate the different I3C Timing.
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**********************************************************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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**********************************************************************************************************************
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*/
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/* Includes ----------------------------------------------------------------------------------------------------------*/
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#include "stm32n6xx_util_i3c.h"
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/** @addtogroup STM32N6xx_UTIL_Driver
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* @{
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*/
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/** @addtogroup UTILITY_I3C
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* @{
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*/
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#if (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER)
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/* Private typedef ---------------------------------------------------------------------------------------------------*/
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/* Private define ----------------------------------------------------------------------------------------------------*/
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/** @defgroup I3C_UTIL_Private_Define I3C Utility Private Define
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* @{
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*/
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#define SEC210PSEC (uint64_t)100000000000 /*!< 10ps, to take two decimal float of ns calculation */
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#define TI3CH_MIN 3200U /*!< Open drain & push pull SCL high min, 32ns */
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#define TI3CH_OD_MAX 4100U /*!< Open drain SCL high max, 41 ns */
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#define TI3CL_OD_MIN 20000U /*!< Open drain SCL low min, 200 ns */
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#define TFMPL_OD_MIN 50000U /*!< Fast Mode Plus Open drain SCL low min, 500 ns */
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#define TFML_OD_MIN 130000U /*!< Fast Mode Open drain SCL low min, 1300 ns */
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#define TFM_MIN 250000U /*!< Fast Mode, period min for ti3cclk, 2.5us */
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#define TSM_MIN 1000000U /*!< Standard Mode, period min for ti3cclk, 10us */
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#define TI3C_CAS_MIN 3840U /*!< Time SCL after START min, 38.4 ns */
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#define TCAPA 35000U /*!< Capacitor effect Value measure on Nucleo around 350ns */
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#define I3C_FREQUENCY_MAX 257000000U /*!< Maximum I3C frequency */
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/**
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* @}
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*/
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/* Private macro -----------------------------------------------------------------------------------------------------*/
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/** @defgroup I3C_UTIL_Private_Macro I3C Utility Private Macro
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* @{
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*/
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#define DIV_ROUND_CLOSEST(x, d) (((x) + ((d) / 2U)) / (d))
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/**
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* @}
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*/
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/* Private function prototypes ---------------------------------------------------------------------------------------*/
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/* Exported functions ------------------------------------------------------------------------------------------------*/
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/** @defgroup I3C_UTIL_Exported_Functions I3C Utility Exported Functions
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* @{
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*/
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/** @defgroup I3C_UTIL_EF_Computation Computation
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* @{
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*/
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/**
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* @brief Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock.
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* @param pInputTiming : [IN] Pointer to an I3C_CtrlTimingTypeDef structure that contains
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* the required parameter for I3C timing computation.
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* @param pOutputConfig : [OUT] Pointer to an LL_I3C_CtrlBusConfTypeDef structure that contains
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* the configuration information for the specified I3C.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: Timing calculation successfully
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* - ERROR: Parameters or timing calculation error
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*/
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ErrorStatus I3C_CtrlTimingComputation(const I3C_CtrlTimingTypeDef *pInputTiming,
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LL_I3C_CtrlBusConfTypeDef *pOutputConfig)
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{
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ErrorStatus status = SUCCESS;
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/* MIPI Standard constants */
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/* I3C: Open drain & push pull SCL high min, tDIG_H & tDIG_H_MIXED: 32 ns */
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uint32_t ti3ch_min = TI3CH_MIN;
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/* I3C: Open drain SCL high max, t_HIGH: 41 ns */
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uint32_t ti3ch_od_max = TI3CH_OD_MAX;
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/* I3C: Open drain SCL high max, tHIGH: 41 ns (Ti3ch_od_max= 410)
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I3C (pure bus): Open drain SCL low min, tLOW_OD: 200 ns */
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uint32_t ti3cl_od_min = TI3CL_OD_MIN;
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/* I3C (mixed bus): Open drain SCL low min,
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tLOW: 500 ns (FM+ I2C on the bus)
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tLOW: 1300 ns (FM I2C on the bus) */
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uint32_t tfmpl_od_min = TFMPL_OD_MIN;
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uint32_t tfml_od_min = TFML_OD_MIN;
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/* I2C: min ti3cclk
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fSCL: 1 MHz (FM+)
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fSCL: 100 kHz (SM) */
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uint32_t tfm_min = TFM_MIN;
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uint32_t tsm_min = TSM_MIN;
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/* I3C: time SCL after START min, Tcas: 38,4 ns */
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uint32_t ti3c_cas_min = TI3C_CAS_MIN;
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/* Period Clock source */
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uint32_t ti3cclk = 0U;
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/* I3C: Push pull period */
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uint32_t ti3c_pp_min = 0U;
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/* I2C: Open drain period */
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uint32_t ti2c_od_min = 0U;
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/* Time for SDA rise to 70% VDD from GND, capacitor effect */
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/* Value measure on Nucleo around 350ns */
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uint32_t tcapa = TCAPA;
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/* Compute variable */
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uint32_t sclhi3c;
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uint32_t scllpp;
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uint32_t scllod;
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uint32_t sclhi2c;
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uint32_t oneus;
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uint32_t free;
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uint32_t sdahold;
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/* Verify Parameters */
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if (pInputTiming->clockSrcFreq > I3C_FREQUENCY_MAX)
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{
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/* Above this frequency, some timing register parameters are over than field value */
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status = ERROR;
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}
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if ((pInputTiming->busType != I3C_PURE_I3C_BUS) && (pInputTiming->busType != I3C_MIXED_BUS))
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{
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status = ERROR;
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}
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if (((pInputTiming->clockSrcFreq == 0U) || (pInputTiming->i3cPPFreq == 0U)) &&
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(pInputTiming->busType == I3C_PURE_I3C_BUS))
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{
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status = ERROR;
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}
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if (((pInputTiming->clockSrcFreq == 0U) || (pInputTiming->i3cPPFreq == 0U) || (pInputTiming->i2cODFreq == 0U)) &&
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(pInputTiming->busType == I3C_MIXED_BUS))
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{
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status = ERROR;
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}
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if (status == SUCCESS)
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{
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/* Period Clock source */
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ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->clockSrcFreq / (uint64_t)2)) /
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(uint64_t)pInputTiming->clockSrcFreq);
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if ((pInputTiming->dutyCycle > 50U) || (ti3cclk == 0U))
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{
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status = ERROR;
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}
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}
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if ((status == SUCCESS) && (ti3cclk != 0U))
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{
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/* I3C: Push pull period */
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ti3c_pp_min = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->i3cPPFreq / (uint64_t)2)) /
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(uint64_t)pInputTiming->i3cPPFreq);
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/* I2C: Open drain period */
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ti2c_od_min = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->i2cODFreq / (uint64_t)2)) /
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(uint64_t)pInputTiming->i2cODFreq);
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if ((pInputTiming->busType != I3C_PURE_I3C_BUS) && (ti2c_od_min > tsm_min))
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{
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status = ERROR;
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}
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}
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/* SCL Computation */
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if ((status == SUCCESS) && (ti3cclk != 0U))
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{
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/* I3C SCL high level (push-pull & open drain) */
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if (pInputTiming->busType == I3C_PURE_I3C_BUS)
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{
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sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * pInputTiming->dutyCycle, ti3cclk), 100U) - 1U;
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/* Check if sclhi3c < ti3ch_min, in that case calculate sclhi3c based on ti3ch_min */
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if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
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{
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sclhi3c = DIV_ROUND_CLOSEST(ti3ch_min, ti3cclk) - 1U;
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/* Check if sclhi3c < ti3ch_min */
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if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
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{
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sclhi3c += 1U;
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}
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scllpp = DIV_ROUND_CLOSEST(ti3c_pp_min, ti3cclk) - (sclhi3c + 1U) - 1U;
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}
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else
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{
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sclhi3c = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti3c_pp_min * pInputTiming->dutyCycle, ti3cclk), 100U) - 1U;
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/* Check if sclhi3c < ti3ch_min */
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if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
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{
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sclhi3c += 1U;
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}
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scllpp = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk) + (ti3cclk / 2U)), ti3cclk) - 1U;
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}
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}
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else
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{
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/* Warning: (sclhi3c + 1) * ti3cclk > Ti3ch_od_max expected */
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sclhi3c = DIV_ROUND_CLOSEST(ti3ch_od_max, ti3cclk) - 1U;
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if (((sclhi3c + 1U) * ti3cclk) < ti3ch_min)
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{
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sclhi3c += 1U;
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}
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else if (((sclhi3c + 1U) * ti3cclk) > ti3ch_od_max)
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{
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sclhi3c = (ti3ch_od_max / ti3cclk);
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}
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else
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{
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/* Do nothing, keep sclhi3c as previously calculated */
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}
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/* I3C SCL low level (push-pull) */
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/* tscllpp = (scllpp + 1) x ti3cclk */
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scllpp = DIV_ROUND_CLOSEST((ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk)), ti3cclk) - 1U;
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}
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/* Check if scllpp is superior at (ti3c_pp_min + 1/2 clock source cycle) */
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/* Goal is to choice the scllpp approach lowest, to have a value frequency highest approach as possible */
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uint32_t ideal_scllpp = (ti3c_pp_min - ((sclhi3c + 1U) * ti3cclk));
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if (((scllpp + 1U) * ti3cclk) >= (ideal_scllpp + (ti3cclk / 2U) + 1U))
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{
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scllpp -= 1U;
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}
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/* Check if scllpp + sclhi3c is inferior at (ti3c_pp_min + 1/2 clock source cycle) */
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/* Goal is to increase the scllpp, to have a value frequency not out of the clock request */
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if (((scllpp + sclhi3c + 1U + 1U) * ti3cclk) < (ideal_scllpp + (ti3cclk / 2U) + 1U))
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{
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scllpp += 1U;
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}
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/* I3C SCL low level (pure I3C bus) */
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if (pInputTiming->busType == I3C_PURE_I3C_BUS)
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{
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if (ti3c_pp_min < ti3cl_od_min)
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{
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scllod = DIV_ROUND_CLOSEST(ti3cl_od_min, ti3cclk) - 1U;
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if (((scllod + 1U) * ti3cclk) < ti3cl_od_min)
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{
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scllod += 1U;
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}
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}
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else
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{
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scllod = scllpp;
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}
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/* Verify that SCL Open drain Low duration is superior as SDA rise time 70% */
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if (((scllod + 1U) * ti3cclk) < tcapa)
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{
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scllod = DIV_ROUND_CLOSEST(tcapa, ti3cclk) + 1U;
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}
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sclhi2c = 0U; /* I2C SCL not used in pure I3C bus */
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}
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/* SCL low level on mixed bus (open-drain) */
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/* I2C SCL high level (mixed bus with I2C) */
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else
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{
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scllod = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(ti2c_od_min * (100U - pInputTiming->dutyCycle),
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ti3cclk), 100U) - 1U;
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/* Mix Bus Fast Mode plus */
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if (ti2c_od_min < tfm_min)
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{
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if (((scllod + 1U) * ti3cclk) < tfmpl_od_min)
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{
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scllod = DIV_ROUND_CLOSEST(tfmpl_od_min, ti3cclk) - 1U;
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}
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}
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/* Mix Bus Fast Mode */
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else
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{
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if (((scllod + 1U) * ti3cclk) < tfml_od_min)
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{
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scllod = DIV_ROUND_CLOSEST(tfml_od_min, ti3cclk) - 1U;
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}
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}
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sclhi2c = DIV_ROUND_CLOSEST((ti2c_od_min - ((scllod + 1U) * ti3cclk)), ti3cclk) - 1U;
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}
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/* Clock After Start computation */
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/* I3C pure bus: (Tcas + tcapa)/2 */
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if (pInputTiming->busType == I3C_PURE_I3C_BUS)
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{
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free = DIV_ROUND_CLOSEST((ti3c_cas_min + tcapa), (2U * ti3cclk)) + 1U;
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}
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/* I3C, I2C mixed: (scllod + tcapa)/2 */
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else
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{
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free = DIV_ROUND_CLOSEST((((scllod + 1U) * ti3cclk) + tcapa), (2U * ti3cclk));
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}
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/* One cycle hold time addition */
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/* By default 1/2 cycle: must be > 3 ns */
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if (ti3cclk > 600U)
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{
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sdahold = 0U;
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}
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else
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{
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sdahold = 1U;
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}
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/* 1 microsecond reference */
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oneus = DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U;
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if ((scllpp > 0xFFU) || (sclhi3c > 0xFFU) || (scllod > 0xFFU) || (sclhi2c > 0xFFU) ||
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(free > 0xFFU) || (oneus > 0xFFU))
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{
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/* Case of value is over 8bits, issue may be due to clocksource have a rate too high for bus clock request */
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/* Update the return status */
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status = ERROR;
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}
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else
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{
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/* SCL configuration */
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pOutputConfig->SCLPPLowDuration = (uint8_t)scllpp;
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pOutputConfig->SCLI3CHighDuration = (uint8_t)sclhi3c;
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pOutputConfig->SCLODLowDuration = (uint8_t)scllod;
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pOutputConfig->SCLI2CHighDuration = (uint8_t)sclhi2c;
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/* Free, Idle and SDA hold time configuration */
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pOutputConfig->BusFreeDuration = (uint8_t)free;
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pOutputConfig->BusIdleDuration = (uint8_t)oneus;
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pOutputConfig->SDAHoldTime = (uint32_t)(sdahold << I3C_TIMINGR1_SDA_HD_Pos);
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}
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}
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return status;
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}
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/**
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* @brief Calculate the I3C Controller timing according current I3C clock source and required I3C bus clock.
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* @param pInputTiming : [IN] Pointer to an I3C_TgtTimingTypeDef structure that contains
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* the required parameter for I3C timing computation.
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* @param pOutputConfig : [OUT] Pointer to an LL_I3C_TgtBusConfTypeDef structure that contains
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* the configuration information for the specified I3C.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: Timing calculation successfully
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* - ERROR: Parameters or timing calculation error
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*/
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ErrorStatus I3C_TgtTimingComputation(const I3C_TgtTimingTypeDef *pInputTiming,
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LL_I3C_TgtBusConfTypeDef *pOutputConfig)
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{
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ErrorStatus status = SUCCESS;
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uint32_t oneus;
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uint32_t ti3cclk = 0U;
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/* Verify Parameters */
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if (pInputTiming->clockSrcFreq == 0U)
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{
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status = ERROR;
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}
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if (status == SUCCESS)
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{
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/* Period Clock source */
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ti3cclk = (uint32_t)((SEC210PSEC + ((uint64_t)pInputTiming->clockSrcFreq / (uint64_t)2)) /
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(uint64_t)pInputTiming->clockSrcFreq);
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/* Verify Parameters */
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if (ti3cclk == 0U)
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{
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status = ERROR;
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}
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}
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if ((status == SUCCESS) && (ti3cclk != 0U))
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{
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/* 1 microsecond reference */
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oneus = DIV_ROUND_CLOSEST(100000U, ti3cclk) - 2U;
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/* Bus available time configuration */
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pOutputConfig->BusAvailableDuration = (uint8_t)oneus;
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}
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return status;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private functions ---------------------------------------------------------*/
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#endif /* (defined(USE_HAL_DRIVER) && defined(HAL_I3C_MODULE_ENABLED)) || defined(USE_FULL_LL_DRIVER) */
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/**
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* @}
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*/
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/**
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* @}
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*/
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