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195 lines
7.4 KiB
C
195 lines
7.4 KiB
C
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file mpu_M55.c
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* @author Sudhir Sreedharan
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* @email sudhir@alifsemi.com
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* @version V1.0.0
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* @date 14-December-2021
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* @brief MPU Configuration Source
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*
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* This file load the MPU regions from the table and provides the function to enable it.
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* @bug None.
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******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#if defined (M55_HP)
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#include "M55_HP.h"
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#elif defined (M55_HE)
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#include "M55_HE.h"
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#else
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#error device not specified!
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#endif
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#include <stdint.h>
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/* Public functions ----------------------------------------------------------*/
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/**
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* @brief Load the MPU regions from the given table
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* @note This function loads the region and also sets the
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* attributes for the regions.
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* Set this function as weak, so that User can
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* override from application.
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* @note This function will be invoked much early in the boot process
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* and before the scatterload. User must ensure that this function
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* is included in the primary load region.
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* region.
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* @param None
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* @retval None
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*/
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__attribute__ ((weak))
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void MPU_Load_Regions(void)
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{
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/* Define the memory attribute index with the below properties */
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#define MEMATTRIDX_NORMAL_WT_RA_TRANSIENT 0
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#define MEMATTRIDX_DEVICE_nGnRE 1
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#define MEMATTRIDX_NORMAL_WB_RA_WA 2
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#define MEMATTRIDX_NORMAL_WT_RA 3
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static const ARM_MPU_Region_t mpu_table[] __STARTUP_RO_DATA_ATTRIBUTE =
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{
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{ /* SRAM0 - 4MB : RO-0, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0x02000000, ARM_MPU_SH_NON, 0, 1, 0),
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.RLAR = ARM_MPU_RLAR(0x023FFFFF, MEMATTRIDX_NORMAL_WT_RA_TRANSIENT)
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},
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{ /* SRAM1 - 2.5MB : RO-0, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0x08000000, ARM_MPU_SH_NON, 0, 1, 0),
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.RLAR = ARM_MPU_RLAR(0x0827FFFF, MEMATTRIDX_NORMAL_WB_RA_WA)
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},
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{ /* Host Peripherals - 16MB : RO-0, NP-1, XN-1 */
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.RBAR = ARM_MPU_RBAR(0x1A000000, ARM_MPU_SH_NON, 0, 1, 1),
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.RLAR = ARM_MPU_RLAR(0x1AFFFFFF, MEMATTRIDX_DEVICE_nGnRE)
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},
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#if defined (M55_HP)
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{ /* RTSS HE ITCM - 256K(SRAM4) : RO-0, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0x58000000, ARM_MPU_SH_OUTER, 0, 1, 0),
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.RLAR = ARM_MPU_RLAR(0x5803FFFF, MEMATTRIDX_NORMAL_WB_RA_WA)
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},
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{ /* RTSS HE DTCM - 256K(SRAM5) : RO-0, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0x58800000, ARM_MPU_SH_OUTER, 0, 1, 0),
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.RLAR = ARM_MPU_RLAR(0x5883FFFF, MEMATTRIDX_NORMAL_WB_RA_WA)
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},
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#elif defined (M55_HE)
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{ /* RTSS HP ITCM - 256K(SRAM2) : RO-0, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0x50000000, ARM_MPU_SH_OUTER, 0, 1, 0),
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.RLAR = ARM_MPU_RLAR(0x5003FFFF, MEMATTRIDX_NORMAL_WB_RA_WA)
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},
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{ /* RTSS HP DTCM - 1MB(SRAM3) : RO-0, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0x50800000, ARM_MPU_SH_OUTER, 0, 1, 0),
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.RLAR = ARM_MPU_RLAR(0x508FFFFF, MEMATTRIDX_NORMAL_WB_RA_WA)
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},
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#endif
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{ /* MRAM - 5.5MB : RO-1, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0x80000000, ARM_MPU_SH_NON, 1, 1, 0),
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.RLAR = ARM_MPU_RLAR(0x8057FFFF, MEMATTRIDX_NORMAL_WT_RA)
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},
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{ /* OSPI Regs - 16MB : RO-0, NP-1, XN-1 */
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.RBAR = ARM_MPU_RBAR(0x83000000, ARM_MPU_SH_NON, 0, 1, 1),
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.RLAR = ARM_MPU_RLAR(0x83FFFFFF, MEMATTRIDX_DEVICE_nGnRE)
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},
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{ /* OSPI0 XIP(eg:hyperram) - 512MB : RO-0, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0xA0000000, ARM_MPU_SH_NON, 0, 1, 0),
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.RLAR = ARM_MPU_RLAR(0xBFFFFFFF, MEMATTRIDX_NORMAL_WB_RA_WA)
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},
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{ /* OSPI1 XIP(eg:flash) - 512MB : RO-1, NP-1, XN-0 */
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.RBAR = ARM_MPU_RBAR(0xC0000000, ARM_MPU_SH_NON, 1, 1, 0),
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.RLAR = ARM_MPU_RLAR(0xDFFFFFFF, MEMATTRIDX_NORMAL_WT_RA)
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},
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};
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/* Mem Attribute for 0th index */
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ARM_MPU_SetMemAttr(MEMATTRIDX_NORMAL_WT_RA_TRANSIENT, ARM_MPU_ATTR(
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/* NT=0, WB=0, RA=1, WA=0 */
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ARM_MPU_ATTR_MEMORY_(0,0,1,0),
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ARM_MPU_ATTR_MEMORY_(0,0,1,0)));
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/* Mem Attribute for 1st index */
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ARM_MPU_SetMemAttr(MEMATTRIDX_DEVICE_nGnRE, ARM_MPU_ATTR(
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/* Device Memory */
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ARM_MPU_ATTR_DEVICE,
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ARM_MPU_ATTR_DEVICE_nGnRE));
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/* Mem Attribute for 2nd index */
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ARM_MPU_SetMemAttr(MEMATTRIDX_NORMAL_WB_RA_WA, ARM_MPU_ATTR(
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/* NT=1, WB=1, RA=1, WA=1 */
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ARM_MPU_ATTR_MEMORY_(1,1,1,1),
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ARM_MPU_ATTR_MEMORY_(1,1,1,1)));
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/* Mem Attribute for 3th index */
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ARM_MPU_SetMemAttr(MEMATTRIDX_NORMAL_WT_RA, ARM_MPU_ATTR(
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/* NT=1, WB=0, RA=1, WA=0 */
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ARM_MPU_ATTR_MEMORY_(1,0,1,0),
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ARM_MPU_ATTR_MEMORY_(1,0,1,0)));
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/* Load the regions from the table */
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ARM_MPU_Load(0, mpu_table, sizeof(mpu_table)/sizeof(ARM_MPU_Region_t));
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}
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/**
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* @brief Clear all the MPU registers
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* @note This function disables the MPU and clear
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* all the existing regions.
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* @param None
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* @retval None
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*/
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void MPU_Clear_All_Regions(void)
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{
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MPU_Type* mpu = MPU;
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/* Retrieve the number of regions */
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uint32_t num_regions = (mpu->TYPE >> 8);
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uint32_t cnt;
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for(cnt = 0U; cnt < num_regions; cnt++)
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ARM_MPU_ClrRegion(cnt);
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}
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/**
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* @brief Configure the MPU.
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* @note This function disables the MPU and loads the regions
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* from the table. Once it is loaded, MPU is enabled.
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* Set this function as weak, so that User can
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* override from application.
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* @note This function will be invoked much early in the boot process
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* and before the scatterload. User must ensure that this function
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* is included in the primary load region.
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* @param None
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* @retval None
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*/
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__attribute__ ((weak))
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void MPU_Setup(void)
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{
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#define MPU_CONTROL (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk)
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/*
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* Make this conditional to avoid an unnecessary DSB -
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* If this call is made from the booting sequence, it is very
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* likely that cache auto-invalidation is ongoing (as we prepare
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* the table), and DSB would wait for it to finish.
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*/
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if (MPU->CTRL & MPU_CTRL_ENABLE_Msk)
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{
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/* Disable the MPU before operating on the table */
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ARM_MPU_Disable();
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}
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/* Clear all the regions */
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MPU_Clear_All_Regions();
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/* Load the new table: mpu_table */
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MPU_Load_Regions();
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/* Enable the MPU now */
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ARM_MPU_Enable(MPU_CONTROL);
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}
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/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
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