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169 lines
3.9 KiB
C
169 lines
3.9 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file Driver_I2S_Private.h
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* @author Sudhir Sreedharan
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* @email sudhir@alifsemi.com
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* @version V3.0.0
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* @date 06-Jun-2023
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* @brief I2S Private header file.
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* @bug None.
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* @Note None
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******************************************************************************/
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#ifndef DRIVER_I2S_PRIVATE_H
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#define DRIVER_I2S_PRIVATE_H
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/* Includes ------------------------------------------------------------------*/
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#include <Driver_SAI.h>
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#include "RTE_Device.h"
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#include "RTE_Components.h"
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#include CMSIS_device_header
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#include <stdbool.h>
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#include "sys_ctrl_i2s.h"
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#include "i2s.h"
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#if (RTE_I2S0_DMA_ENABLE || RTE_I2S1_DMA_ENABLE || RTE_I2S2_DMA_ENABLE || \
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RTE_I2S3_DMA_ENABLE || RTE_LPI2S_DMA_ENABLE)
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#define I2S_DMA_ENABLE 1
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#else
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#define I2S_DMA_ENABLE 0
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#endif
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#if I2S_DMA_ENABLE
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#include <DMA_Common.h>
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#endif
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#if ( RTE_I2S0_BLOCKING_MODE_ENABLE || RTE_I2S1_BLOCKING_MODE_ENABLE || \
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RTE_I2S2_BLOCKING_MODE_ENABLE || RTE_I2S3_BLOCKING_MODE_ENABLE || \
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RTE_LPI2S_BLOCKING_MODE_ENABLE )
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#define I2S_BLOCKING_MODE_ENABLE 1
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#else
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#define I2S_BLOCKING_MODE_ENABLE 0
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#endif
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/** \brief I2S Driver states. */
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typedef struct _I2S_DRIVER_STATE {
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uint32_t initialized : 1; /* Driver Initialized*/
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uint32_t powered : 1; /* Device powered */
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uint32_t reserved : 30;/* Reserved */
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} I2S_DRIVER_STATE;
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typedef enum _I2S_FLAG {
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I2S_FLAG_DRV_MONO_MODE = (1U << 0), /*!< I2S Driver in Mono Mode */
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} I2S_FLAG;
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typedef union _I2S_DRV_STATUS {
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uint32_t status;
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volatile ARM_SAI_STATUS status_b;
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} I2S_DRV_STATUS;
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typedef struct _I2S_CONFIG_INFO {
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/*!< I2S Word Select Size */
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I2S_WSS wss_len;
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/*!< I2S SCLK Gating */
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I2S_SCLKG sclkg;
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/*!< I2S word length */
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I2S_WLEN wlen;
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/*!< I2S Rx FIFO Trigger Level */
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const uint8_t rx_fifo_trg_lvl;
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/*!< I2S Tx FIFO Trigger Level */
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const uint8_t tx_fifo_trg_lvl;
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/*!< I2S clock source in Hz */
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const uint32_t clk_source;
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#if I2S_BLOCKING_MODE_ENABLE
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/*!< I2S instance blocking mode transfer enable */
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const bool blocking_mode;
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#endif
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#if I2S_DMA_ENABLE
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/*!< I2S dma enable */
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const bool dma_enable;
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/*!< DMA IRQ priority number */
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const uint32_t dma_irq_priority;
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#endif
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/*!< I2S irq priority number */
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const uint32_t irq_priority;
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} I2S_CONFIG_INFO;
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#if I2S_DMA_ENABLE
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typedef struct _I2S_DMA_HW_CONFIG {
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/*!< Tx interface */
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DMA_PERIPHERAL_CONFIG dma_tx;
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/*!< Rx interface */
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DMA_PERIPHERAL_CONFIG dma_rx;
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} I2S_DMA_HW_CONFIG;
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#endif
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/** \brief Resources for a I2S instance */
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typedef struct _I2S_RESOURCES {
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/*!< I2S Application Event Callback */
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ARM_SAI_SignalEvent_t cb_event;
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#if I2S_DMA_ENABLE
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/*!< I2S DMA Callback */
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ARM_DMA_SignalEvent_t dma_cb;
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/*!< DMA Controller configuration */
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I2S_DMA_HW_CONFIG *dma_cfg;
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#endif
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/*!< I2S ARM I2S Status */
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I2S_DRV_STATUS drv_status;
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/*!< I2S Driver state */
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I2S_DRIVER_STATE state;
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/*!< I2S Audio Sample Rate */
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uint32_t sample_rate;
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/*!< I2S Controller configuration */
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I2S_CONFIG_INFO *cfg;
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/*!< I2S physical address */
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I2S_Type *regs;
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/*!< I2S Instance number */
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const I2S_INSTANCE instance;
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/*!< I2S irq number */
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const IRQn_Type irq;
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/* I2S transfer buffer information */
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i2s_transfer_t transfer;
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/*!< I2S Driver Flags */
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uint8_t flags;
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} I2S_RESOURCES;
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#ifdef __cplusplus
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}
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#endif
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#endif // DRIVER_I2S_PRIVATE_H
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