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123 lines
6.1 KiB
C
123 lines
6.1 KiB
C
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file dphy.h
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* @author Prasanna Ravi
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* @email prasanna.ravi@alifsemi.com
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* @version V1.0.0
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* @date 24-Feb-2022
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* @brief Device Specific Header file for DPHY Driver.
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******************************************************************************/
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#ifndef DPHY_H_
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#define DPHY_H_
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/*DPHY TX register index*/
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#define dphy4txtester_DIG_RDWR_TX_SYS_3 (0x004U)
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#define dphy4txtester_DIG_RD_TX_SYS_0 (0x01EU)
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#define dphy4txtester_DIG_RD_TX_SYS_1 (0x01FU)
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#define dphy4txtester_DIG_RDWR_TX_CB_0 (0x1AAU)
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#define dphy4txtester_DIG_RDWR_TX_CB_1 (0x1ABU)
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#define dphy4txtester_DIG_RDWR_TX_CB_2 (0x1ACU)
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#define dphy4txtester_DIG_RDWR_TX_CB_3 (0x1ADU)
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#define dphy4txtester_DIG_RDWR_TX_DAC_0 (0x1DAU)
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#define dphy4txtester_DIG_RD_TX_DAC_0 (0x1F2U)
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#define dphy4txtester_DIG_RDWR_TX_SLEW_5 (0x270U)
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#define dphy4txtester_DIG_RDWR_TX_SLEW_6 (0x271U)
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#define dphy4txtester_DIG_RDWR_TX_SLEW_7 (0x272U)
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#define dphy4txtester_DIG_RDWR_TX_CLK_TERMLOWCAP (0x402U)
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#define dphy4txtester_DIG_RDWR_TX_LANE0_LANE_0 (0x501U)
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#define dphy4txtester_DIG_RDWR_TX_LANE1_LANE_0 (0x701U)
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#define dphy4txtester_DIG_RDWR_TX_LANE1_SLEWRATE_0 (0x70BU)
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#define dphy4txtester_DIG_RDWR_TX_LANE2_SLEWRATE_0 (0x90BU)
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#define dphy4txtester_DIG_RDWR_TX_LANE3_SLEWRATE_0 (0xB0BU)
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/*TX PLL register index*/
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#define dphy4txtester_DIG_RDWR_TX_PLL_0 (0x15DU)
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#define dphy4txtester_DIG_RDWR_TX_PLL_1 (0x15EU)
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#define dphy4txtester_DIG_RDWR_TX_PLL_5 (0x162U)
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#define dphy4txtester_DIG_RDWR_TX_PLL_9 (0x166U)
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#define dphy4txtester_DIG_RDWR_TX_PLL_10 (0x167U)
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#define dphy4txtester_DIG_RDWR_TX_PLL_13 (0x16AU)
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#define dphy4txtester_DIG_RDWR_TX_PLL_17 (0x16EU)
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#define dphy4txtester_DIG_RDWR_TX_PLL_27 (0x178U)
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#define dphy4txtester_DIG_RDWR_TX_PLL_28 (0x179U)
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#define dphy4txtester_DIG_RDWR_TX_PLL_29 (0x17AU)
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#define dphy4txtester_DIG_RDWR_TX_PLL_30 (0x17BU)
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#define dphy4txtester_DIG_RD_TX_PLL_0 (0x191U)
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/*DPHY RX register index*/
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#define dphy4rxtester_DIG_RD_RX_SYS_1 (0x01FU)
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#define dphy4rxtester_DIG_RDWR_RX_RX_STARTUP_OVR_2 (0x0E2U)
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#define dphy4rxtester_DIG_RDWR_RX_RX_STARTUP_OVR_3 (0x0E3U)
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#define dphy4rxtester_DIG_RDWR_RX_RX_STARTUP_OVR_4 (0x0E4U)
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#define dphy4rxtester_DIG_RDWR_RX_RX_STARTUP_OVR_17 (0x0F1U)
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#define dphy4rxtester_DIG_RDWR_RX_BIST_3 (0x10AU)
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#define dphy4rxtester_DIG_RDWR_RX_CLKLANE_LANE_6 (0x307U)
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#define dphy4rxtester_DIG_RD_RX_CLKLANE_OFFSET_CAL_3 (0x39CU)
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#define dphy2rxtester_DIG_RD_RX_CLKLANE_OFFSET_CAL_0 (0x39DU)
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#define dphy4rxtester_DIG_RDWR_RX_LANE0_LANE_9 (0x50AU)
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#define dphy4rxtester_DIG_RDWR_RX_LANE0_LANE_12 (0x50DU)
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#define dphy4rxtester_DIG_RD_RX_LANE0_LANE_7 (0x532U)
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#define dphy4rxtester_DIG_RD_RX_LANE0_LANE_8 (0x533U)
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#define dphy2rxtester_DIG_RD_RX_LANE0_OFFSET_CAL_0 (0x58DU)
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#define dphy2rxtester_DIG_RD_RX_LANE0_OFFSET_CAL_2 (0x5A1U)
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#define dphy2rxtester_DIG_RD_RX_LANE0_DDL_0 (0x5E0U)
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#define dphy2rxtester_DIG_RD_RX_LANE0_DDL_5 (0x5E5U)
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#define dphy4rxtester_DIG_RDWR_RX_LANE1_LANE_9 (0x70AU)
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#define dphy4rxtester_DIG_RDWR_RX_LANE1_LANE_12 (0x70DU)
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#define dphy4rxtester_DIG_RD_RX_LANE1_LANE_7 (0x732U)
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#define dphy4rxtester_DIG_RD_RX_LANE1_LANE_8 (0x733U)
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#define dphy2rxtester_DIG_RD_RX_LANE1_OFFSET_CAL_0 (0x79FU)
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#define dphy2rxtester_DIG_RD_RX_LANE1_OFFSET_CAL_2 (0x7A1U)
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#define dphy4rxtester_DIG_RD_RX_LANE1_DDL_0 (0x7E0U)
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#define dphy2rxtester_DIG_RD_RX_LANE1_DDL_5 (0x7E5U)
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/*PHY_TEST_CTRL0 register bits parameters*/
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#define PHY_TESTCLR_Pos 0U
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#define PHY_TESTCLR_Msk (1U << PHY_TESTCLR_Pos)
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#define PHY_TESTCLK_Pos 1U
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#define PHY_TESTCLK_Msk (1U << PHY_TESTCLK_Pos)
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/*PHY_TEST_CTRL1 register bits parameters*/
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#define PHY_TESTDIN_Pos 0U
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#define PHY_TESTDIN_Msk MASK(7,0)
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#define PHY_TESTDOUT_Pos 8U
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#define PHY_TESTDOUT_Msk MASK(15,8)
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#define PHY_TESTEN_Pos 16U
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#define PHY_TESTEN_Msk (1U << PHY_TESTEN_Pos)
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/*DPHY Test control base*/
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#define PHY_CSI_TEST_CTRL0_BASE (CSI_BASE + 0x50)
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#define PHY_CSI_TEST_CTRL1_BASE (CSI_BASE + 0x54)
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#define PHY_DSI_TEST_CTRL0_BASE (DSI_BASE + 0xB4)
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#define PHY_DSI_TEST_CTRL1_BASE (DSI_BASE + 0xB8)
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/*CFG_CLK frequency*/
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#define DPHY_FCFG_CLOCK_MHZ 25
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/*Input Reference Clock Frequency*/
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#define DPHY_FCLKIN_MHZ 38.4f
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/*Charge-pump Programmability*/
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#define DPHY_CPBIAS_CNTRL 0x00
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#define DPHY_GMP_CNTRL 0x01
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#define DPHY_INT_CNTRL 0x04
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#define DPHY_PROP_CNTRL 0x10
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#define DPHY_CB_VREF_MPLL_REG_REL_RW 0x02
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/*Oscillation target for slew rate calibration*/
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#define DPHY_LESS_THEN_1GBPS_SR_OSC_FREQ_TARGET 657
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#define DPHY_MORE_THEN_1GBPS_SR_OSC_FREQ_TARGET 920
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/*PLL input division factor*/
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#define DPHY_DEFAULT_PLL_INPUT_DIV_FACTOR_N 3
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/*Minimum DPHY clock frequency*/
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#define DPHY_MINIMUM_FREQUENCY 40000000
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#endif /* DPHY_H_ */
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