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500 lines
20 KiB
C
500 lines
20 KiB
C
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file driver_mac.h
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* @author Silesh C V
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* @email silesh@alifsemi.com
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* @version V1.0.0
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* @date 22-Mar-2022
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* @brief CMSIS driver for ETH MAC.
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* @bug None.
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* @Note None
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******************************************************************************/
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#ifndef _DRIVER_MAC_H_
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#define _DRIVER_MAC_H_
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#include <Driver_ETH_MAC.h>
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#include "RTE_Device.h"
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#include "RTE_Components.h"
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#include CMSIS_device_header
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#if defined(RTE_CMSIS_RTOS2)
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#include <cmsis_os2.h>
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#elif defined(RTE_CMSIS_RTOS)
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#include <cmsis_os.h>
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#else
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#error "Driver needs CMSIS-RTOS or CMSIS-RTOS2."
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#endif
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#include "system_utils.h"
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#define RX_DESC_COUNT 8 /**< Rx DMA descriptor count */
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#define TX_DESC_COUNT 8 /**< Tx DMA descriptor count */
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/* Each descriptor is 16 bytes */
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#define DESCS_AREA_SIZE ((RX_DESC_COUNT + TX_DESC_COUNT) * 16) /**< Total memory area needed for descs */
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#define ETH_BUF_SIZE 1536 /**< Ethernet buffer size */
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/** \brief Rx/Tx Dma Descriptor. */
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typedef struct {
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uint32_t des0;
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uint32_t des1;
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uint32_t des2;
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uint32_t des3;
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} DMA_DESC;
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/** \brief MAC register map. */
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typedef struct {
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uint32_t MAC_CONFIG;
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uint32_t MAC_EXT_CONFIG;
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uint32_t MAC_PACKET_FILTER;
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uint32_t RESERVED_0;
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uint32_t MAC_HASH_TAB_0;
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uint32_t MAC_HASH_TAB_1;
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uint32_t RESERVED_1[22];
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uint32_t MAC_Q0_TX_FLOW_CTRL;
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uint32_t RESERVED[7];
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uint32_t MAC_RX_FLOW_CTRL;
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uint32_t RESERVED_2[3];
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uint32_t MAC_RXQ_CTRL_0;
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uint32_t MAC_RXQ_CTRL_1;
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uint32_t MAC_RXQ_CTRL_2;
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uint32_t MAC_RXQ_CTRL_3;
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uint32_t MAC_INT_STATUS;
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uint32_t MAC_INT_ENABLE;
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uint32_t RESERVED_3[2];
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uint32_t MAC_PMT_CTRL_STS;
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uint32_t RESERVED_4[22];
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uint32_t MAC_HW_FEATURE_0;
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uint32_t MAC_HW_FEATURE_1;
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uint32_t MAC_HW_FEATURE_2;
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uint32_t MAC_HW_FEATURE_3;
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uint32_t RESERVED_5[53];
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uint32_t MAC_MDIO_ADDR;
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uint32_t MAC_MDIO_DATA;
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uint32_t RESERVED_6[62];
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uint32_t MAC_ADDR_HIGH_0;
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uint32_t MAC_ADDR_LOW_0;
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uint32_t RESERVED_7[510];
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uint32_t MAC_TIMESTAMP_CONTROL;
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uint32_t MAC_SUB_SEC_INCR;
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uint32_t MAC_SYS_TIME_SEC;
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uint32_t MAC_SYS_TIME_NANOSEC;
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uint32_t MAC_SYS_TIME_SEC_UPD;
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uint32_t MAC_SYS_TIME_NANOSEC_UPD;
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uint32_t MAC_TIMESTAMP_ADDEND;
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uint32_t RESERVED_8[25];
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uint32_t MAC_PPS_TARGET_SEC;
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uint32_t MAC_PPS_TARGET_NANOSEC;
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uint32_t RESERVED_9[94];
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uint32_t MTL_TXQ0_OP_MODE;
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uint32_t RESERVED_10[11];
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uint32_t MTL_RXQ0_OP_MODE;
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uint32_t RESERVED_11[179];
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uint32_t DMA_BUS_MODE;
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uint32_t DMA_SYS_BUS_MODE;
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uint32_t DMA_STATUS;
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uint32_t RESERVED_12[61];
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uint32_t DMA_CH0_CTRL;
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uint32_t DMA_CH0_TX_CTRL;
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uint32_t DMA_CH0_RX_CTRL;
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uint32_t RESERVED_13;
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uint32_t DMA_CH0_TX_BASE_ADDR_HIGH;
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uint32_t DMA_CH0_TX_BASE_ADDR;
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uint32_t DMA_CH0_RX_BASE_ADDR_HIGH;
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uint32_t DMA_CH0_RX_BASE_ADDR;
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uint32_t DMA_CH0_TX_END_ADDR;
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uint32_t RESERVED_14;
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uint32_t DMA_CH0_RX_END_ADDR;
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uint32_t DMA_CHO_TX_RING_LEN;
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uint32_t DMA_CH0_RX_RING_LEN;
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uint32_t DMA_CH0_INT_ENABLE;
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uint32_t RESERVED_15[10];
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uint32_t DMA_CH0_STATUS;
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} MAC_REGS;
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/** \brief Representation of MAC device. */
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typedef struct {
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volatile MAC_REGS *regs; /**< IOMEM base address of the Ethernet MAC instance */
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void *descs; /**< Pointer to the DMA descriptor area */
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DMA_DESC *rx_descs; /**< Array of Rx DMA descriptors */
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DMA_DESC *tx_descs; /**< Array of Tx DMA descriptors */
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ARM_ETH_MAC_SignalEvent_t cb_event;/**< Registered callback function */
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uint32_t rx_desc_id; /**< Index of the current Rx DMA descriptor */
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uint32_t tx_desc_id; /**< Index of the current Tx DMA descriptor */
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IRQn_Type irq; /**< IRQ number of the Ethernet MAC instance */
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uint8_t irq_priority; /**< priority of the ETH MAC IRQ */
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uint8_t flags; /**< MAC driver flags */
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uint8_t *frame_end; /**< Current frame address, to support fragments */
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} MAC_DEV;
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/** \brief Driver state flags */
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#define ETH_INIT 0x01 /**< Driver initialized */
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#define ETH_POWER 0x02 /**< Driver power on */
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/* MAC register fields */
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/* RX Queues Routing */
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#define MAC_RXQCTRL_AVCPQ_MASK MASK(2, 0)
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#define MAC_RXQCTRL_AVCPQ_SHIFT 0
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#define MAC_RXQCTRL_PTPQ_MASK MASK(6, 4)
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#define MAC_RXQCTRL_PTPQ_SHIFT 4
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#define MAC_RXQCTRL_DCBCPQ_MASK MASK(10, 8)
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#define MAC_RXQCTRL_DCBCPQ_SHIFT 8
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#define MAC_RXQCTRL_UPQ_MASK MASK(14, 12)
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#define MAC_RXQCTRL_UPQ_SHIFT 12
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#define MAC_RXQCTRL_MCBCQ_MASK MASK(18, 16)
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#define MAC_RXQCTRL_MCBCQ_SHIFT 16
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#define MAC_RXQCTRL_MCBCQEN BIT(20)
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#define MAC_RXQCTRL_MCBCQEN_SHIFT 20
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#define MAC_RXQCTRL_TACPQE BIT(21)
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#define MAC_RXQCTRL_TACPQE_SHIFT 21
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#define MAC_RXQCTRL_FPRQ MASK(26, 24)
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#define MAC_RXQCTRL_FPRQ_SHIFT 24
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#define MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
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#define MAC_RXQ_CTRL0_RXQ0EN_MASK 3
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#define MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
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#define MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
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#define MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
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#define MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
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#define MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
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#define MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
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#define DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
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#define DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
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#define DMA_CH0_TX_CONTROL_OSP BIT(4)
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#define DMA_CH0_TX_CONTROL_ST BIT(0)
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#define DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
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#define DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
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#define DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
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#define DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
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#define DMA_CH0_RX_CONTROL_SR BIT(0)
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#define DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
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#define DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
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#define DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT 24
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#define DMA_SYSBUS_MODE_EAME BIT(11)
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#define DMA_SYSBUS_MODE_ONEKBBE BIT(13)
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#define DMA_SYSBUS_MODE_BLEN16 BIT(3)
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#define DMA_SYSBUS_MODE_BLEN8 BIT(2)
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#define DMA_SYSBUS_MODE_BLEN4 BIT(1)
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/* MAC Packet Filtering */
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#define MAC_PACKET_FILTER_PR BIT(0)
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#define MAC_PACKET_FILTER_HMC BIT(2)
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#define MAC_PACKET_FILTER_PM BIT(4)
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#define MAC_PACKET_FILTER_DBF BIT(5)
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#define MAC_PACKET_FILTER_PCF BIT(7)
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#define MAC_PACKET_FILTER_HPF BIT(10)
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#define MAC_PACKET_FILTER_VTFE BIT(16)
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#define MAC_PACKET_FILTER_IPFE BIT(20)
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#define MAC_PACKET_FILTER_RA BIT(31)
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#define MAC_MAX_PERFECT_ADDRESSES 128
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/* MAC PMT Control Status */
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#define MAC_PMT_CTRL_STS_MGKPKTEN BIT(1)
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#define MAC_PMT_CTRL_STS_PWRDWN BIT(0)
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/* MAC Flow Control RX */
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#define MAC_RX_FLOW_CTRL_RFE BIT(0)
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/* MAC Flow Control TX */
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#define MAC_TX_FLOW_CTRL_TFE BIT(1)
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#define MAC_TX_FLOW_CTRL_PT_SHIFT 16
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/* MAC config */
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#define MAC_CONFIG_ARPEN BIT(31)
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#define MAC_CONFIG_SARC MASK(30, 28)
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#define MAC_CONFIG_SARC_SHIFT 28
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#define MAC_CONFIG_IPC BIT(27)
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#define MAC_CONFIG_IPG MASK(26, 24)
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#define MAC_CONFIG_IPG_SHIFT 24
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#define MAC_CONFIG_2K BIT(22)
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#define MAC_CONFIG_CST BIT(21)
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#define MAC_CONFIG_ACS BIT(20)
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#define MAC_CONFIG_WD BIT(19)
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#define MAC_CONFIG_BE BIT(18)
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#define MAC_CONFIG_JD BIT(17)
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#define MAC_CONFIG_JE BIT(16)
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#define MAC_CONFIG_PS BIT(15)
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#define MAC_CONFIG_FES BIT(14)
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#define MAC_CONFIG_FES_SHIFT 14
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#define MAC_CONFIG_DM BIT(13)
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#define MAC_CONFIG_LM BIT(12)
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#define MAC_CONFIG_DCRS BIT(9)
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#define MAC_CONFIG_TE BIT(1)
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#define MAC_CONFIG_RE BIT(0)
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#define MAC_MDIO_ADDR_PA_SHIFT 21
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#define MAC_MDIO_ADDR_RDA_SHIFT 16
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#define MAC_MDIO_ADDR_CR_SHIFT 8
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/* MDC clock divisors for different CSR clk values */
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#define MAC_MDIO_ADDR_CR_60_100 0
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#define MAC_MDIO_ADDR_CR_100_150 1
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#define MAC_MDIO_ADDR_CR_20_35 2
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#define MAC_MDIO_ADDR_CR_35_60 3
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#define MAC_MDIO_ADDR_CR_150_250 4
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#define MAC_MDIO_ADDR_CR_250_300 5
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#define MAC_MDIO_ADDR_CR_300_500 6
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#define MAC_MDIO_ADDR_CR_500_800 7
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#define MAC_MDIO_ADDR_SKAP BIT(4)
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#define MAC_MDIO_ADDR_GOC_SHIFT 2
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#define MAC_MDIO_ADDR_GOC_READ 3
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#define MAC_MDIO_ADDR_GOC_WRITE 1
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#define MAC_MDIO_ADDR_C45E BIT(1)
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#define MAC_MDIO_ADDR_GB BIT(0)
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#define MAC_MDIO_DATA_GD_MASK 0xffff
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#define MAC_ADDR_HIGH_AE BIT(31)
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#define MAC_INT_EN_TSIE BIT(12)
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#define MAC_INT_EN_PMTIE BIT(4)
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#define MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
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#define MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
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#define MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
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#define MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
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/* MTL registers */
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#define MTL_FRPE BIT(15)
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#define MTL_OPERATION_SCHALG_MASK MASK(6, 5)
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#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
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#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
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#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
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#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
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#define MTL_OPERATION_RAA BIT(2)
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#define MTL_OPERATION_RAA_SP (0x0 << 2)
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#define MTL_OPERATION_RAA_WSP (0x1 << 2)
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#define MTL_OP_MODE_RSF BIT(5)
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#define MTL_OP_MODE_FEP BIT(4)
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#define MTL_OP_MODE_FUP BIT(3)
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#define MTL_OP_MODE_TXQEN_MASK MASK(3, 2)
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#define MTL_OP_MODE_TXQEN_AV BIT(2)
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#define MTL_OP_MODE_TXQEN BIT(3)
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#define MTL_OP_MODE_TSF BIT(1)
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#define MTL_OP_MODE_TTC_64B (1 << 4)
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#define MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
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#define MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
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#define MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
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#define MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
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/* DMA Bus Mode bitmap */
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#define DMA_BUS_MODE_SFT_RESET BIT(0)
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/* DMA SYS Bus Mode bitmap */
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#define DMA_BUS_MODE_SPH BIT(24)
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#define DMA_BUS_MODE_PBL BIT(16)
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#define DMA_BUS_MODE_PBL_SHIFT 16
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#define DMA_BUS_MODE_RPBL_SHIFT 16
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#define DMA_BUS_MODE_MB BIT(14)
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#define DMA_BUS_MODE_FB BIT(0)
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/* DMA Interrupt top status */
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#define DMA_STATUS_MAC BIT(17)
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#define DMA_STATUS_MTL BIT(16)
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#define DMA_STATUS_CHAN7 BIT(7)
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#define DMA_STATUS_CHAN6 BIT(6)
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#define DMA_STATUS_CHAN5 BIT(5)
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#define DMA_STATUS_CHAN4 BIT(4)
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#define DMA_STATUS_CHAN3 BIT(3)
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#define DMA_STATUS_CHAN2 BIT(2)
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#define DMA_STATUS_CHAN1 BIT(1)
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#define DMA_STATUS_CHAN0 BIT(0)
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/* definitions for DMA channels */
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/* DMA Control X */
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#define DMA_CONTROL_SPH BIT(24)
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#define DMA_CONTROL_MSS_MASK MASK(13, 0)
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#define DMA_CHAN_CONTROL_PBLX8 BIT(16)
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/* DMA Tx Channel X Control register defines */
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#define DMA_CONTROL_EDSE BIT(28)
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#define DMA_CONTROL_TSE BIT(12)
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#define DMA_CONTROL_OSP BIT(4)
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#define DMA_CONTROL_ST BIT(0)
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/* DMA Rx Channel X Control register defines */
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#define DMA_CONTROL_SR BIT(0)
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#define DMA_RBSZ_MASK MASK(14, 1)
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#define DMA_RBSZ_SHIFT 1
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/* Interrupt status per channel */
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#define DMA_CHAN_STATUS_REB MASK(21, 19)
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#define DMA_CHAN_STATUS_REB_SHIFT 19
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#define DMA_CHAN_STATUS_TEB MASK(18, 16)
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#define DMA_CHAN_STATUS_TEB_SHIFT 16
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#define DMA_CHAN_STATUS_NIS BIT(15)
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#define DMA_CHAN_STATUS_AIS BIT(14)
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#define DMA_CHAN_STATUS_CDE BIT(13)
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#define DMA_CHAN_STATUS_FBE BIT(12)
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#define DMA_CHAN_STATUS_ERI BIT(11)
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#define DMA_CHAN_STATUS_ETI BIT(10)
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#define DMA_CHAN_STATUS_RWT BIT(9)
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#define DMA_CHAN_STATUS_RPS BIT(8)
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#define DMA_CHAN_STATUS_RBU BIT(7)
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#define DMA_CHAN_STATUS_RI BIT(6)
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#define DMA_CHAN_STATUS_TBU BIT(2)
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#define DMA_CHAN_STATUS_TPS BIT(1)
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#define DMA_CHAN_STATUS_TI BIT(0)
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/* Interrupt enable bits per channel */
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#define DMA_CHAN_INTR_ENA_NIE BIT(15)
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#define DMA_CHAN_INTR_ENA_AIE BIT(14)
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#define DMA_CHAN_INTR_ENA_CDE BIT(13)
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#define DMA_CHAN_INTR_ENA_FBE BIT(12)
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#define DMA_CHAN_INTR_ENA_ERE BIT(11)
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#define DMA_CHAN_INTR_ENA_ETE BIT(10)
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#define DMA_CHAN_INTR_ENA_RWE BIT(9)
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#define DMA_CHAN_INTR_ENA_RSE BIT(8)
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#define DMA_CHAN_INTR_ENA_RBUE BIT(7)
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#define DMA_CHAN_INTR_ENA_RIE BIT(6)
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#define DMA_CHAN_INTR_ENA_TBUE BIT(2)
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#define DMA_CHAN_INTR_ENA_TSE BIT(1)
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#define DMA_CHAN_INTR_ENA_TIE BIT(0)
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/* Descriptor definitions */
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/* TDES2 (read format) */
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#define TDES2_BUFFER1_SIZE_MASK MASK(13, 0)
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#define TDES2_VLAN_TAG_MASK MASK(15, 14)
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#define TDES2_VLAN_TAG_SHIFT 14
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#define TDES2_BUFFER2_SIZE_MASK MASK(29, 16)
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#define TDES2_BUFFER2_SIZE_MASK_SHIFT 16
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#define TDES3_IVTIR_MASK MASK(19, 18)
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#define TDES3_IVTIR_SHIFT 18
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#define TDES3_IVLTV BIT(17)
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#define TDES2_TIMESTAMP_ENABLE BIT(30)
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#define TDES2_IVT_MASK MASK(31, 16)
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#define TDES2_IVT_SHIFT 16
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#define TDES2_INTERRUPT_ON_COMPLETION BIT(31)
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/* TDES3 (read format) */
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#define TDES3_PACKET_SIZE_MASK MASK(14, 0)
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#define TDES3_VLAN_TAG MASK(15, 0)
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#define TDES3_VLTV BIT(16)
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#define TDES3_CHECKSUM_INSERTION_MASK MASK(17, 16)
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#define TDES3_CHECKSUM_INSERTION_SHIFT 16
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#define TDES3_TCP_PKT_PAYLOAD_MASK MASK(17, 0)
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#define TDES3_TCP_SEGMENTATION_ENABLE BIT(18)
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#define TDES3_HDR_LEN_SHIFT 19
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#define TDES3_SLOT_NUMBER_MASK MASK(22, 19)
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#define TDES3_SA_INSERT_CTRL_MASK MASK(25, 23)
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#define TDES3_SA_INSERT_CTRL_SHIFT 23
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#define TDES3_CRC_PAD_CTRL_MASK MASK(27, 26)
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/* TDES3 (write back format) */
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#define TDES3_IP_HDR_ERROR BIT(0)
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#define TDES3_DEFERRED BIT(1)
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#define TDES3_UNDERFLOW_ERROR BIT(2)
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#define TDES3_EXCESSIVE_DEFERRAL BIT(3)
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#define TDES3_COLLISION_COUNT_MASK MASK(7, 4)
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#define TDES3_COLLISION_COUNT_SHIFT 4
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#define TDES3_EXCESSIVE_COLLISION BIT(8)
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#define TDES3_LATE_COLLISION BIT(9)
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#define TDES3_NO_CARRIER BIT(10)
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#define TDES3_LOSS_CARRIER BIT(11)
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#define TDES3_PAYLOAD_ERROR BIT(12)
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#define TDES3_PACKET_FLUSHED BIT(13)
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#define TDES3_JABBER_TIMEOUT BIT(14)
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#define TDES3_ERROR_SUMMARY BIT(15)
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#define TDES3_TIMESTAMP_STATUS BIT(17)
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#define TDES3_TIMESTAMP_STATUS_SHIFT 17
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/* TDES3 context */
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#define TDES3_CTXT_TCMSSV BIT(26)
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/* TDES3 Common */
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#define TDES3_RS1V BIT(26)
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#define TDES3_RS1V_SHIFT 26
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#define TDES3_LAST_DESCRIPTOR BIT(28)
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#define TDES3_LAST_DESCRIPTOR_SHIFT 28
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#define TDES3_FIRST_DESCRIPTOR BIT(29)
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#define TDES3_CONTEXT_TYPE BIT(30)
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#define TDES3_CONTEXT_TYPE_SHIFT 30
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/* TDES4 */
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#define TDES4_LTV BIT(31)
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#define TDES4_LT MASK(7, 0)
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/* TDS3 use for both format (read and write back) */
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#define TDES3_OWN BIT(31)
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#define TDES3_OWN_SHIFT 31
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/* RDES0 (write back format) */
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#define RDES0_VLAN_TAG_MASK MASK(15, 0)
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/* RDES1 (write back format) */
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#define RDES1_IP_PAYLOAD_TYPE_MASK MASK(2, 0)
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#define RDES1_IP_HDR_ERROR BIT(3)
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#define RDES1_IPV4_HEADER BIT(4)
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#define RDES1_IPV6_HEADER BIT(5)
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#define RDES1_IP_CSUM_BYPASSED BIT(6)
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#define RDES1_IP_CSUM_ERROR BIT(7)
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#define RDES1_PTP_MSG_TYPE_MASK MASK(11, 8)
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#define RDES1_PTP_PACKET_TYPE BIT(12)
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#define RDES1_PTP_VER BIT(13)
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#define RDES1_TIMESTAMP_AVAILABLE BIT(14)
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#define RDES1_TIMESTAMP_AVAILABLE_SHIFT 14
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#define RDES1_TIMESTAMP_DROPPED BIT(15)
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#define RDES1_IP_TYPE1_CSUM_MASK MASK(31, 16)
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/* RDES2 (write back format) */
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#define RDES2_L3_L4_HEADER_SIZE_MASK MASK(9, 0)
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#define RDES2_VLAN_FILTER_STATUS BIT(15)
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#define RDES2_SA_FILTER_FAIL BIT(16)
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#define RDES2_DA_FILTER_FAIL BIT(17)
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#define RDES2_HASH_FILTER_STATUS BIT(18)
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#define RDES2_MAC_ADDR_MATCH_MASK MASK(26, 19)
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#define RDES2_HASH_VALUE_MATCH_MASK MASK(26, 19)
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#define RDES2_L3_FILTER_MATCH BIT(27)
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#define RDES2_L4_FILTER_MATCH BIT(28)
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#define RDES2_L3_L4_FILT_NB_MATCH_MASK MASK(27, 26)
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#define RDES2_L3_L4_FILT_NB_MATCH_SHIFT 26
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#define RDES2_HL MASK(9, 0)
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/* RDES3 (write back format) */
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#define RDES3_PACKET_SIZE_MASK MASK(14, 0)
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#define RDES3_ERROR_SUMMARY BIT(15)
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#define RDES3_PACKET_LEN_TYPE_MASK MASK(18, 16)
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#define RDES3_DRIBBLE_ERROR BIT(19)
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#define RDES3_RECEIVE_ERROR BIT(20)
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#define RDES3_OVERFLOW_ERROR BIT(21)
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#define RDES3_RECEIVE_WATCHDOG BIT(22)
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#define RDES3_GIANT_PACKET BIT(23)
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#define RDES3_CRC_ERROR BIT(24)
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#define RDES3_RDES0_VALID BIT(25)
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#define RDES3_RDES1_VALID BIT(26)
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#define RDES3_RDES2_VALID BIT(27)
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#define RDES3_LAST_DESCRIPTOR BIT(28)
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#define RDES3_FIRST_DESCRIPTOR BIT(29)
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#define RDES3_CONTEXT_DESCRIPTOR BIT(30)
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#define RDES3_CONTEXT_DESCRIPTOR_SHIFT 30
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/* RDES3 (read format) */
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#define RDES3_BUFFER1_VALID_ADDR BIT(24)
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#define RDES3_BUFFER2_VALID_ADDR BIT(25)
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#define RDES3_INT_ON_COMPLETION_EN BIT(30)
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#define RDES3_OWN BIT(31)
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#endif /* _DRIVER_MAC_H_ */
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