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Old header files are no longer needed. Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
161 lines
7.7 KiB
C
161 lines
7.7 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2013-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* MT9M114 driver.
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*/
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#ifndef __REG_REGS_H__
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#define __REG_REGS_H__
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#define MT9M114_REG_PAD_SLEW (0x001E)
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#define MT9M114_REG_SYSCTL (0x001A)
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#define MT9M114_SYSCTL_SOFT_RESET (1 << 0)
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#define MT9M114_REG_HOST_COMMAND (0x0080)
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#define MT9M114_HC_APPLY_PATCH (0x0001)
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#define MT9M114_HC_SET_STATE (0x0002)
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#define MT9M114_HC_REFRESH (0x0004)
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#define MT9M114_HC_WAIT_FOR_EVENT (0x0008)
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#define MT9M114_HC_OK (0x8000)
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#define MT9M114_HC_DELAY (1)
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#define MT9M114_HC_TIMEOUT (100)
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#define MT9M114_SS_ENTER_CONFIG_CHANGE (0x28)
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#define MT9M114_SS_STREAMING (0x31)
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#define MT9M114_SS_START_STREAMING (0x34)
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#define MT9M114_SS_ENTER_SUSPEND (0x40)
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#define MT9M114_SS_SUSPENDED (0x41)
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#define MT9M114_SS_ENTER_STANDBY (0x50)
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#define MT9M114_SS_STANDBY (0x52)
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#define MT9M114_SS_LEAVE_STANDBY (0x54)
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#define MT9M114_REG_XMDA_ACCESS_CTL_STAT (0x0982)
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#define MT9M114_REG_XMDA_PHYSICAL_ADDRESS_ACCESS (0x098A)
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#define MT9M114_REG_XMDA_LOGIC_ADDRESS_ACCESS (0x098E)
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#define MT9M114_REG_SEQ_ERROR_CODE (0x8406)
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#define MT9M114_REG_CAM_OUTPUT_FORMAT (0xC86C)
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#define MT9M114_OUTPUT_FORMAT_SWAP_RB (1 << 0)
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#define MT9M114_OUTPUT_FORMAT_SWAP_BYTES (1 << 1)
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#define MT9M114_OUTPUT_FORMAT_MONO (1 << 2)
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#define MT9M114_OUTPUT_FORMAT_BT656 (1 << 3)
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#define MT9M114_OUTPUT_FORMAT_BT656_FIXED (1 << 4)
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#define MT9M114_OUTPUT_FORMAT_YUV (0 << 8)
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#define MT9M114_OUTPUT_FORMAT_RGB (1 << 8)
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#define MT9M114_OUTPUT_FORMAT_BAYER (2 << 8)
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#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10 (0 << 10)
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#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_PRE (1 << 10)
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#define MT9M114_OUTPUT_FORMAT_RAW_BAYER_10_POST (2 << 10)
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#define MT9M114_OUTPUT_FORMAT_PROCESSED_BAYER (3 << 10)
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#define MT9M114_OUTPUT_FORMAT_RGB565 (0 << 12)
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#define MT9M114_OUTPUT_FORMAT_RGB555 (1 << 12)
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#define MT9M114_OUTPUT_FORMAT_XRGB444 (2 << 12)
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#define MT9M114_OUTPUT_FORMAT_RGB444X (3 << 12)
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#define MT9M114_REG_LL_ALGO (0xBC04)
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#define MT9M114_REG_SENSOR_CFG_Y_ADDR_START (0xC800)
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#define MT9M114_REG_SENSOR_CFG_X_ADDR_START (0xC802)
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#define MT9M114_REG_SENSOR_CFG_Y_ADDR_END (0xC804)
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#define MT9M114_REG_SENSOR_CFG_X_ADDR_END (0xC806)
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#define MT9M114_REG_SENSOR_CFG_PIXCLK (0xC808)
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#define MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MIN (0xC80E)
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#define MT9M114_REG_SENSOR_CFG_FINE_INTEG_TIME_MAX (0xC810)
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#define MT9M114_REG_SENSOR_CFG_FRAME_LENGTH_LINES (0xC812)
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#define MT9M114_REG_SENSOR_CFG_LINE_LENGTH_PCK (0xC814)
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#define MT9M114_REG_SENSOR_CFG_FINE_CORRECTION (0xC816)
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#define MT9M114_REG_SENSOR_CFG_CPIPE_LAST_ROW (0xC818)
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#define MT9M114_REG_SENSOR_CONTROL_READ_MODE (0xC834)
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#define MT9M114_SENSOR_CONTROL_READ_MODE_HMIRROR (0x1)
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#define MT9M114_SENSOR_CONTROL_READ_MODE_VFLIP (0x2)
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#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN_MASK (0x30)
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#define MT9M114_SENSOR_CONTROL_READ_MODE_HBIN (0x30)
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#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN_MASK (0x300)
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#define MT9M114_SENSOR_CONTROL_READ_MODE_VBIN (0x300)
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#define MT9M114_REG_CAM_MODE_SELECT (0xC84C)
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#define MT9M114_REG_CROP_WINDOW_X_OFFSET (0xC854)
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#define MT9M114_REG_CROP_WINDOW_Y_OFFSET (0xC856)
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#define MT9M114_REG_CROP_WINDOW_WIDTH (0xC858)
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#define MT9M114_REG_CROP_WINDOW_HEIGHT (0xC85A)
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#define MT9M114_REG_CAM_OUTPUT_WIDTH (0xC868)
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#define MT9M114_REG_CAM_OUTPUT_HEIGHT (0xC86A)
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#define MT9M114_REG_CAM_SFX_CONTROL (0xC874)
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#define MT9M114_REG_CAM_AET_MAX_FRAME_RATE (0xC88C)
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#define MT9M114_REG_CAM_AET_MIN_FRAME_RATE (0xC88E)
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#define MT9M114_REG_CAM_AWB_XSCALE (0xC8F2)
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#define MT9M114_REG_CAM_AWB_YSCALE (0xC8F3)
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#define MT9M114_REG_CAM_AWB_X_SHIFT_PRE_ADJ (0xC904)
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#define MT9M114_REG_CAM_AWB_Y_SHIFT_PRE_ADJ (0xC906)
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#define MT9M114_REG_AWB_CLIP_WINDOW_X_START (0xC914)
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#define MT9M114_REG_AWB_CLIP_WINDOW_Y_START (0xC916)
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#define MT9M114_REG_AWB_CLIP_WINDOW_X_END (0xC918)
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#define MT9M114_REG_AWB_CLIP_WINDOW_Y_END (0xC91A)
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#define MT9M114_REG_CAM_LL_START_SATURATION (0xC92A)
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#define MT9M114_REG_AE_INITIAL_WINDOW_X_START (0xC91C)
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#define MT9M114_REG_AE_INITIAL_WINDOW_Y_START (0xC91E)
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#define MT9M114_REG_AE_INITIAL_WINDOW_X_END (0xC920)
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#define MT9M114_REG_AE_INITIAL_WINDOW_Y_END (0xC922)
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#define MT9M114_REG_CAM_SYSCTL_PLL_DIVIDER_M_N (0xC980)
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#define MT9M114_REG_CAM_PORT_OUTPUT_CONTROL (0xC984)
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#define MT9M114_REG_UVC_AE_MODE_CONTROL (0xCC00)
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#define MT9M114_REG_UVC_WHITE_BALANCE_AUTO_CONTROL (0xCC01)
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#define MT9M114_REG_UVC_EXPOSURE_TIME_ABSOLUTE_CTRL (0xCC04)
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#define MT9M114_REG_UVC_BRIGHTNESS_CONTROL (0xCC0A)
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#define MT9M114_REG_UVC_CONTRAST_CONTROL (0xCC0C)
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#define MT9M114_REG_UVC_GAIN_CONTROL (0xCC0E)
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#define MT9M114_REG_UVC_SATURATION_CONTROL (0xCC12)
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#define MT9M114_REG_UVC_MANUAL_EXPOSURE_CONFIG (0xCC20)
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#define MT9M114_REG_SYSMGR_NEXT_STATE (0xDC00)
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#define MT9M114_REG_SYSMGR_CURRENT_STATE (0xDC01)
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#define MT9M114_REG_SYSMGR_CMD_STATUS (0xDC02)
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#define MT9M114_REG_PATCHLDR_LOADER_ADDRESS (0xE000)
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#define MT9M114_REG_PATCHLDR_PATCH_ID (0xE002)
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#define MT9M114_REG_PATCHLDR_FIRMWARE_ID_HI (0xE004)
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#define MT9M114_REG_PATCHLDR_FIRMWARE_ID_LO (0xE006)
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#define MT9M114_REG_PATCHLDR_APPLY_STATUS (0xE008)
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#define MT9M114_REG_AUTO_BINNING_MODE (0xE801)
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#define MT9M114_REG_CMD_HANDLE_WAIT_EVENT_ID (0xFC00)
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#define MT9M114_REG_CMD_HANDLE_NUM_EVENTS (0xFC02)
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#endif //__REG_REGS_H__
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