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692 lines
22 KiB
C
692 lines
22 KiB
C
/**
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******************************************************************************
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* @file stm32n6xx_ll_cacheaxi.h
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* @author MCD Application Team
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* @brief Header file of CACHEAXI LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion ------------------------------------*/
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#ifndef STM32N6xx_LL_CACHEAXI_H
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#define STM32N6xx_LL_CACHEAXI_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes -----------------------------------------------------------------*/
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#include "stm32n6xx.h"
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/** @addtogroup STM32N6xx_LL_Driver
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* @{
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*/
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/** @defgroup CACHEAXI_LL CACHEAXI
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup CACHEAXI_Exported_Constants CACHEAXI Exported Constants
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* @{
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*/
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/** @defgroup CACHEAXI_Command_Operation Command Operation
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* @{
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*/
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#define LL_CACHEAXI_COMMAND_NO_OPERATION (0x00000000)
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#define LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR CACHEAXI_CR2_CACHECMD_0
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#define LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR (CACHEAXI_CR2_CACHECMD_0|CACHEAXI_CR2_CACHECMD_1)
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_LL_EC_GET_FLAG Get Flags Defines
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* @brief Flags defines which can be used with LL_CACHEAXI_ReadReg function
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* @{
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*/
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#define LL_CACHEAXI_SR_ERRF CACHEAXI_SR_ERRF /*!< Cache error flag */
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#define LL_CACHEAXI_SR_BUSYF CACHEAXI_SR_BUSYF /*!< Busy flag */
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#define LL_CACHEAXI_SR_CMDENDF CACHEAXI_SR_CMDENDF /*!< Command end flag */
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#define LL_CACHEAXI_SR_BSYENDF CACHEAXI_SR_BSYENDF /*!< Full invalidate busy end flag */
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#define LL_CACHEAXI_SR_BUSYCMDF CACHEAXI_SR_BUSYCMDF /*!< Command busy flag */
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_LL_EC_CLEAR_FLAG Clear Flags Defines
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* @brief Flags defines which can be used with LL_CACHEAXI_WriteReg function
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* @{
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*/
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#define LL_CACHEAXI_FCR_CERRF CACHEAXI_FCR_CERRF /*!< Cache error flag */
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#define LL_CACHEAXI_FCR_CBSYENDF CACHEAXI_FCR_CBSYENDF /*!< Full invalidate busy end flag */
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#define LL_CACHEAXI_FCR_CCMDENDF CACHEAXI_FCR_CCMDENDF /*!< Command end flag*/
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_LL_EC_IT IT Defines
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* @brief IT defines which can be used with LL_CACHEAXI_ReadReg and LL_CACHEAXI_WriteReg functions
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* @{
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*/
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#define LL_CACHEAXI_IER_BSYENDIE CACHEAXI_IER_BSYENDIE /*!< Busy end interrupt */
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#define LL_CACHEAXI_IER_ERRIE CACHEAXI_IER_ERRIE /*!< Cache error interrupt */
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#define LL_CACHEAXI_IER_CMDENDIE CACHEAXI_IER_CMDENDIE /*!< Command end interrupt */
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_Monitor_Type Monitor type
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* @{
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*/
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#define LL_CACHEAXI_MONITOR_READ_HIT CACHEAXI_CR1_RHITMEN /*!< Read Hit monitoring */
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#define LL_CACHEAXI_MONITOR_READ_MISS CACHEAXI_CR1_RMISSMEN /*!< Read Miss monitoring */
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#define LL_CACHEAXI_MONITOR_WRITE_HIT CACHEAXI_CR1_WHITMEN /*!< Write Hit monitoring */
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#define LL_CACHEAXI_MONITOR_WRITE_MISS CACHEAXI_CR1_WMISSMEN /*!< Write Miss monitoring */
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#define LL_CACHEAXI_MONITOR_READALLOC_MISS CACHEAXI_CR1_RAMMEN /*!< Read-alloc Miss monitoring */
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#define LL_CACHEAXI_MONITOR_WRITEALLOC_MISS CACHEAXI_CR1_WAMMEN /*!< Write-alloc Miss monitoring */
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#define LL_CACHEAXI_MONITOR_WRITETHROUGH CACHEAXI_CR1_WTMEN /*!< Write-through monitoring */
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#define LL_CACHEAXI_MONITOR_EVICTION CACHEAXI_CR1_EVIMEN /*!< Eviction monitoring */
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#define LL_CACHEAXI_MONITOR_ALL (CACHEAXI_CR1_RHITMEN | CACHEAXI_CR1_RMISSMEN \
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| CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_WMISSMEN \
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| CACHEAXI_CR1_RAMMEN | CACHEAXI_CR1_WAMMEN \
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| CACHEAXI_CR1_WTMEN | CACHEAXI_CR1_EVIMEN)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macros --------------------------------------------------------*/
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/** @defgroup CACHEAXI_LL_Exported_Macros CACHEAXI Exported Macros
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* @{
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*/
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/** @defgroup CACHEAXI_LL_EM_WRITE_READ Common write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in CACHEAXI register
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* @param __INSTANCE__ CACHEAXI Instance
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_CACHEAXI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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/**
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* @brief Read a value in CACHEAXI register
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* @param __INSTANCE__ CACHEAXI Instance
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_CACHEAXI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup CACHEAXI_LL_Exported_Functions CACHEAXI Exported Functions
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* @{
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*/
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/** @defgroup CACHEAXI_LL_EF_Configuration Configuration
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* @{
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*/
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/**
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* @brief Enable the selected CACHEAXI instance.
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* @rmtoll CR1 EN LL_CACHEAXI_Enable
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* @param CACHEAXIx CACHEAXI instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_Enable(CACHEAXI_TypeDef *CACHEAXIx)
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{
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SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);
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}
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/**
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* @brief Disable the selected CACHEAXI instance.
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* @rmtoll CR1 EN LL_CACHEAXI_Disable
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* @param CACHEAXIx CACHEAXI instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_Disable(CACHEAXI_TypeDef *CACHEAXIx)
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{
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CLEAR_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN);
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}
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/**
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* @brief Get the selected CACHEAXI instance enable state.
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* @rmtoll CR1 EN LL_CACHEAXI_IsEnabled
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* @param CACHEAXIx CACHEAXI instance
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* @retval 0: CACHEAXI is disabled, 1: CACHEAXI is enabled.
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabled(const CACHEAXI_TypeDef *CACHEAXIx)
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{
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return ((READ_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_EN) == (CACHEAXI_CR1_EN)) ? 1UL : 0UL);
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}
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/**
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* @brief Set the cacheaxi instance start command address.
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* @rmtoll CR2 CMDRSADDRR LL_CACHEAXI_SetStartAddress
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* @param addr cacheaxi command start address(Clean, Invalidate or Clean and Invalidate).
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* @param CACHEAXIx CACHEAXI instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_SetStartAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)
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{
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WRITE_REG(CACHEAXIx->CMDRSADDRR, addr);
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}
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/**
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* @brief Get the cacheaxi command start address.
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* @rmtoll CR2 CMDRSADDRR LL_CACHEAXI_GetStartAddress
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* @param CACHEAXIx CACHEAXI instance
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* @retval Start address of cacheaxi command
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_GetStartAddress(const CACHEAXI_TypeDef *CACHEAXIx)
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{
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return (uint32_t)(READ_REG(CACHEAXIx->CMDRSADDRR));
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}
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/**
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* @brief Set the cacheaxi instance End command address.
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* @rmtoll CR2 CMDREADDRR LL_CACHEAXI_SetEndAddress
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* @param CACHEAXIx CACHEAXI instance
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* @param addr cacheaxi command end address(Clean, Invalidate or Clean and Invalidate).
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_SetEndAddress(CACHEAXI_TypeDef *CACHEAXIx, uint32_t addr)
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{
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WRITE_REG(CACHEAXIx->CMDREADDRR, addr);
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}
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/**
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* @brief Get the cacheaxi command End address.
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* @rmtoll CR2 CMDREADDRR LL_CACHEAXI_GetEndAddress
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* @param CACHEAXIx CACHEAXI instance
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* @retval End address of cacheaxi command
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_GetEndAddress(const CACHEAXI_TypeDef *CACHEAXIx)
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{
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return (uint32_t)(READ_REG(CACHEAXIx->CMDREADDRR));
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}
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/**
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* @brief Set Dcache command.
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* @rmtoll CR2 CACHECMD LL_CACHEAXI_SetCommand
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* @param CACHEAXIx CACHEAXI instance
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* @param Command command to be applied for the cacheaxi
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* Command can be one of the following values:
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* @arg @ref LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR
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* @arg @ref LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR
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* @arg @ref LL_CACHEAXI_COMMAND_NO_OPERATION
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_SetCommand(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Command)
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{
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/* Set cacheaxi command */
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MODIFY_REG(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD, Command);
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}
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/**
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* @brief Set Dcache command.
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* @rmtoll CR2 CACHECMD LL_CACHEAXI_GetCommand
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* @param CACHEAXIx CACHEAXI instance
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CACHEAXI_COMMAND_NO_OPERATION
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* @arg @ref LL_CACHEAXI_COMMAND_CLEAN_BY_ADDR
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* @arg @ref LL_CACHEAXI_COMMAND_CLEAN_INVALIDATE_BY_ADDR
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_GetCommand(const CACHEAXI_TypeDef *CACHEAXIx)
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{
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/*Get Dcache Command */
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return (uint32_t)(READ_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_CACHECMD));
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}
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/**
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* @brief Launch Dcache Command.
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* @rmtoll CR2 CACHECMD LL_CACHEAXI_StartCommand
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* @param CACHEAXIx CACHEAXI instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_StartCommand(CACHEAXI_TypeDef *CACHEAXIx)
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{
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SET_BIT(CACHEAXIx->CR2, CACHEAXI_CR2_STARTCMD);
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}
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/**
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* @brief Invalidate the Data cache.
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* @rmtoll CR1 CACHEINV LL_CACHEAXI_Invalidate
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* @param CACHEAXIx CACHEAXI instance
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_Invalidate(CACHEAXI_TypeDef *CACHEAXIx)
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{
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SET_BIT(CACHEAXIx->CR1, CACHEAXI_CR1_CACHEINV);
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}
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/**
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* @}
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*/
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/** @defgroup CACHEAXI_LL_EF_Monitor Monitor
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* @{
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*/
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/**
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* @brief Enable the hit/miss monitor(s).
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* @rmtoll CR1 (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN) LL_CACHEAXI_EnableMonitors
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* @param CACHEAXIx CACHEAXI instance
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* @param Monitors This parameter can be one or a combination of the following values:
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* @arg LL_CACHEAXI_MONITOR_READ_HIT
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* @arg LL_CACHEAXI_MONITOR_READ_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITE_HIT
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* @arg LL_CACHEAXI_MONITOR_WRITE_MISS
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* @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
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* @arg LL_CACHEAXI_MONITOR_EVICTION
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* @arg LL_CACHEAXI_MONITOR_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_EnableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
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{
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SET_BIT(CACHEAXIx->CR1, Monitors);
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}
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/**
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* @brief Disable the hit/miss monitor(s).
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* @rmtoll CR1 (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN) LL_CACHEAXI_DisableMonitors
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* @param CACHEAXIx CACHEAXI instance
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* @param Monitors This parameter can be one or a combination of the following values:
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* @arg LL_CACHEAXI_MONITOR_READ_HIT
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* @arg LL_CACHEAXI_MONITOR_READ_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITE_HIT
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* @arg LL_CACHEAXI_MONITOR_WRITE_MISS
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* @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
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* @arg LL_CACHEAXI_MONITOR_EVICTION
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* @arg LL_CACHEAXI_MONITOR_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_DisableMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
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{
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CLEAR_BIT(CACHEAXIx->CR1, Monitors);
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}
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/**
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* @brief Return the hit/miss monitor(s) enable state.
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* @rmtoll CR1 (RMISSMEN/RHITMEN/WMISSMEN/WHITMEN/RAMMEN/WAMMEN/WTMEN/EVIMEN) LL_CACHEAXI_IsEnabledMonitors
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* @param CACHEAXIx CACHEAXI instance
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* @param Monitors This parameter can be one or a combination of the following values:
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* @arg LL_CACHEAXI_MONITOR_READ_HIT
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* @arg LL_CACHEAXI_MONITOR_READ_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITE_HIT
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* @arg LL_CACHEAXI_MONITOR_WRITE_MISS
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* @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
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* @arg LL_CACHEAXI_MONITOR_EVICTION
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* @arg LL_CACHEAXI_MONITOR_ALL
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* @retval State of parameter value (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledMonitors(const CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
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{
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return (((READ_BIT(CACHEAXIx->CR1, (CACHEAXI_CR1_WMISSMEN | CACHEAXI_CR1_WHITMEN | CACHEAXI_CR1_RMISSMEN | \
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CACHEAXI_CR1_RHITMEN | CACHEAXI_CR1_RAMMEN | CACHEAXI_CR1_WAMMEN | \
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CACHEAXI_CR1_WTMEN | CACHEAXI_CR1_EVIMEN))\
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& Monitors) == (Monitors)) ? 1UL : 0UL);
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}
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/**
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* @brief Reset the Data Cache performance monitoring.
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* @rmtoll CR1 (RHITMRST/RMISSMRST/WHITMRST/WMISSMRST/RAMMRST/WAMMRST/WTMRST/EVIMRST) LL_CACHEAXI_ResetMonitors
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* @param CACHEAXIx CACHEAXI instance
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* @param Monitors Monitoring type
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* This parameter can be a combination of the following values:
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* @arg LL_CACHEAXI_MONITOR_READ_HIT
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* @arg LL_CACHEAXI_MONITOR_READ_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITE_HIT
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* @arg LL_CACHEAXI_MONITOR_WRITE_MISS
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* @arg LL_CACHEAXI_MONITOR_READALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITEALLOC_MISS
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* @arg LL_CACHEAXI_MONITOR_WRITETHROUGH
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* @arg LL_CACHEAXI_MONITOR_EVICTION
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* @arg LL_CACHEAXI_MONITOR_ALL
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* @retval None
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*/
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__STATIC_INLINE void LL_CACHEAXI_ResetMonitors(CACHEAXI_TypeDef *CACHEAXIx, uint32_t Monitors)
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{
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/* Reset */
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SET_BIT(CACHEAXIx->CR1, (Monitors << 2U));
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/* Release reset */
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CLEAR_BIT(CACHEAXIx->CR1, (Monitors << 2U));
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}
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/**
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* @brief Get the Read Hit monitor Value
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* @rmtoll RHMONR LL_CACHEAXI_Monitor_GetReadHitValue
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* @param CACHEAXIx CACHEAXI instance
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* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadHitValue(CACHEAXI_TypeDef *CACHEAXIx)
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{
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return CACHEAXIx->RHMONR;
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}
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/**
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* @brief Get the Read Miss monitor Value
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* @rmtoll RMMONR LL_CACHEAXI_Monitor_GetReadMissValue
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* @param CACHEAXIx CACHEAXI instance
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* @retval Value between Min_Data=0 and Max_Data=0xFFFF
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadMissValue(CACHEAXI_TypeDef *CACHEAXIx)
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{
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return CACHEAXIx->RMMONR;
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}
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/**
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* @brief Get the Write Hit monitor Value
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* @rmtoll WHMONR LL_CACHEAXI_Monitor_GetWriteHitValue
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* @param CACHEAXIx CACHEAXI instance
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* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteHitValue(CACHEAXI_TypeDef *CACHEAXIx)
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{
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return CACHEAXIx->WHMONR;
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}
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/**
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* @brief Get the Write Miss monitor Value
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* @rmtoll WMMONR LL_CACHEAXI_Monitor_GetWriteMissValue
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* @param CACHEAXIx CACHEAXI instance
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* @retval Value between Min_Data=0 and Max_Data=0xFFFF
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*/
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__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteMissValue(CACHEAXI_TypeDef *CACHEAXIx)
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{
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return CACHEAXIx->WMMONR;
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}
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/**
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* @brief Get the Read-allocate Miss monitor Value
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* @rmtoll WMMONR LL_CACHEAXI_Monitor_GetReadAllocMissValue
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetReadAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return CACHEAXIx->RAMMONR;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the Write-allocate Miss monitor Value
|
|
* @rmtoll WMMONR LL_CACHEAXI_Monitor_GetWriteAllocMissValue
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteAllocMissValue(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return CACHEAXIx->WAMMONR;
|
|
}
|
|
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|
/**
|
|
* @brief Get the Write-through monitor Value
|
|
* @rmtoll WMMONR LL_CACHEAXI_Monitor_GetWriteThroughValue
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetWriteThroughValue(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return CACHEAXIx->WTMONR;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the Eviction monitor Value
|
|
* @rmtoll WMMONR LL_CACHEAXI_Monitor_GetEvictionValue
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_Monitor_GetEvictionValue(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return CACHEAXIx->EVIMONR;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CACHEAXI_LL_EF_IT_Management IT-Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable BusyEnd interrupt.
|
|
* @rmtoll IER BSYENDIE LL_CACHEAXI_EnableIT_BSYEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_EnableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable BusyEnd interrupt.
|
|
* @rmtoll IER BSYENDIE LL_CACHEAXI_DisableIT_BSYEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_DisableIT_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Indicates whether the Busyend interrupt is enabled.
|
|
* @rmtoll IER BSYENDIE LL_CACHEAXI_IsEnabledIT_BSYEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_BSYENDIE) == (CACHEAXI_IER_BSYENDIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable Error interrupt.
|
|
* @rmtoll IER ERRIE LL_CACHEAXI_EnableIT_ERR
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_EnableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Error interrupt.
|
|
* @rmtoll IER ERRIE LL_CACHEAXI_DisableIT_ERR
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_DisableIT_ERR(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Indicates whether the Error interrupt is enabled.
|
|
* @rmtoll IER ERRIE LL_CACHEAXI_IsEnabledIT_ERR
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_ERR(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_ERRIE) == (CACHEAXI_IER_ERRIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable command end interrupt.
|
|
* @rmtoll IER CMDENDIE LL_CACHEAXI_EnableIT_CMDEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_EnableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
SET_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable command end interrupt.
|
|
* @rmtoll IER CMDENDIE LL_CACHEAXI_DisableIT_CMDEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_DisableIT_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
CLEAR_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Indicates whether the command end interrupt is enabled.
|
|
* @rmtoll IER CMDENDIE LL_CACHEAXI_IsEnabledIT_CMDEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsEnabledIT_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->IER, CACHEAXI_IER_CMDENDIE) == (CACHEAXI_IER_CMDENDIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear full invalidate busy end flag.
|
|
* @rmtoll FCR CBSYENDF LL_CACHEAXI_ClearFlag_BSYEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_ClearFlag_BSYEND(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CBSYENDF);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear cache error flag.
|
|
* @rmtoll FCR CERRF LL_CACHEAXI_ClearFlag_ERR
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_ClearFlag_ERR(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CERRF);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear command end flag.
|
|
* @rmtoll FCR CCMDENDF LL_CACHEAXI_ClearFlag_CMDEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CACHEAXI_ClearFlag_CMDEND(CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
WRITE_REG(CACHEAXIx->FCR, CACHEAXI_FCR_CCMDENDF);
|
|
}
|
|
|
|
/**
|
|
* @brief Get flag Dcache BUSY.
|
|
* @rmtoll SR BUSYF LL_CACHEAXI_IsActiveFlag_BUSY
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSY(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYF) == (CACHEAXI_SR_BUSYF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get flag Dcache Busyend.
|
|
* @rmtoll SR BSYENDF LL_CACHEAXI_IsActiveFlag_BSYEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BSYEND(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BSYENDF) == (CACHEAXI_SR_BSYENDF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get flag Dcache Error.
|
|
* @rmtoll SR ERRF LL_CACHEAXI_IsActiveFlag_ERR
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_ERR(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_ERRF) == (CACHEAXI_SR_ERRF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get flag Dcache Busy command.
|
|
* @rmtoll SR BUSYCMDF LL_CACHEAXI_IsActiveFlag_BUSYCMD
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_BUSYCMD(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_BUSYCMDF) == (CACHEAXI_SR_BUSYCMDF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Get flag Dcache command end.
|
|
* @rmtoll SR CMDENDF LL_CACHEAXI_IsActiveFlag_CMDEND
|
|
* @param CACHEAXIx CACHEAXI instance
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CACHEAXI_IsActiveFlag_CMDEND(const CACHEAXI_TypeDef *CACHEAXIx)
|
|
{
|
|
return ((READ_BIT(CACHEAXIx->SR, CACHEAXI_SR_CMDENDF) == (CACHEAXI_SR_CMDENDF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32N6xx_LL_CACHEAXI_H */
|