mirror of
https://github.com/openmv/openmv.git
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289 lines
13 KiB
C
289 lines
13 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2013-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_BOARD_ARCH "OMV4 H7 1024" // 33 chars max
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#define OMV_BOARD_TYPE "H7"
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#define OMV_BOARD_UID_ADDR 0x1FF1E800 // Unique ID address.
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#define OMV_BOARD_UID_SIZE 3 // Unique ID size in words.
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#define OMV_BOARD_UID_OFFSET 4 // Bytes offset for multi-word UIDs.
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// JPEG configuration.
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#define OMV_JPEG_CODEC_ENABLE (1)
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#define OMV_JPEG_QUALITY_LOW (50)
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#define OMV_JPEG_QUALITY_HIGH (90)
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#define OMV_JPEG_QUALITY_THRESHOLD (320 * 240 * 2)
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// GPU Configuration
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#define OMV_GPU_ENABLE (1)
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// CSI drivers configuration.
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#define OMV_OV2640_ENABLE (1)
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#define OMV_OV5640_ENABLE (1)
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#define OMV_OV5640_AF_ENABLE (1)
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#define OMV_OV5640_PLL_CTRL2 (0x64)
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#define OMV_OV5640_PLL_CTRL3 (0x13)
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#define OMV_OV7725_ENABLE (1)
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#define OMV_OV7725_PLL_CONFIG (0x41) // x4
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#define OMV_OV7725_BANDING (0x7F)
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#define OMV_OV9650_ENABLE (1)
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#define OMV_MT9M114_ENABLE (1)
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#define OMV_MT9V0XX_ENABLE (1)
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#define OMV_LEPTON_ENABLE (1)
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#define OMV_PAG7920_ENABLE (1)
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#define OMV_PAJ6100_ENABLE (1)
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#define OMV_PAJ6100_GLITCH_RECONFIG (1)
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#define OMV_FROGEYE2020_ENABLE (1)
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// FIR drivers configuration.
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#define OMV_FIR_MLX90621_ENABLE (1)
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#define OMV_FIR_MLX90640_ENABLE (1)
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#define OMV_FIR_MLX90641_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 16
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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// OpenMV protocol configuration.
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#define OMV_PROTOCOL_MAX_BUFFER_SIZE (512)
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE(HAS_JPEG, HAS_CRC, HAS_SD)
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//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (3)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (3)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_LDO_SUPPLY)
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// Linker script constants (see the linker script template stm32.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_MAIN_MEMORY SRAM1 // Data/BSS memory
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#define OMV_FFS_MEMORY DTCM // Flash filesystem cache memory
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#define OMV_STACK_MEMORY ITCM // stack memory
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#define OMV_STACK_SIZE (64K)
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#define OMV_FB_MEMORY SRAM0 // Framebuffer, fb_alloc
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#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (80K) // minimum fb alloc size
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#define OMV_SB_MEMORY SRAM0 // Streaming buffer memory.
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#define OMV_SB_SIZE (32K) // Streaming buffer size.
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#define OMV_DMA_MEMORY SRAM2 // Misc DMA buffers memory.
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#define OMV_GC_BLOCK0_MEMORY SRAM4 // Main GC block.
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#define OMV_GC_BLOCK0_SIZE (64K)
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#define OMV_GC_BLOCK1_MEMORY SRAM1 // Extra GC block 0.
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#define OMV_GC_BLOCK1_SIZE (267K)
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_LINE_BUF_SIZE (3 * 1024) // Image line buffer round(640 * 2BPP * 2 buffers).
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#define OMV_VOSPI_DMA_BUFFER ".dma_buffer"
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// Memory map.
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#define OMV_FLASH_ORIGIN 0x08000000
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#define OMV_FLASH_LENGTH 2048K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_ITCM_ORIGIN 0x00000000
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#define OMV_ITCM_LENGTH 64K
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#define OMV_SRAM0_ORIGIN 0x24000000
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#define OMV_SRAM0_LENGTH 512K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 280K
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#define OMV_SRAM2_ORIGIN 0x30046000
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#define OMV_SRAM2_LENGTH 8K
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#define OMV_SRAM4_ORIGIN 0x38000000
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#define OMV_SRAM4_LENGTH 64K
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// Flash configuration.
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#define OMV_FLASH_BOOT_ORIGIN 0x08000000
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#define OMV_FLASH_BOOT_LENGTH 128K
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#define OMV_FLASH_FFS_ORIGIN 0x08020000
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#define OMV_FLASH_FFS_LENGTH 128K
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#define OMV_FLASH_TXT_ORIGIN 0x08040000
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#define OMV_FLASH_TXT_LENGTH 1664K
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// ROMFS configuration.
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#define OMV_ROMFS_PART0_ORIGIN 0x081E0000
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#define OMV_ROMFS_PART0_LENGTH 128K
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// MDMA configuration
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#define OMV_MDMA_CHANNEL_DCMI_0 (0)
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#define OMV_MDMA_CHANNEL_DCMI_1 (1)
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#define OMV_MDMA_CHANNEL_JPEG_IN (7) // in has a lower pri than out
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#define OMV_MDMA_CHANNEL_JPEG_OUT (6) // out has a higher pri than in
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// AXI QoS - Low-High (0:15) - default 0
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#define OMV_AXI_QOS_MDMA_R_PRI 15 // Max pri to move data.
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// CSI I2C bus
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#define OMV_CSI_I2C_ID (1)
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#define OMV_CSI_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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// FIR I2C bus
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#define OMV_FIR_I2C_ID (2)
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#define OMV_FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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// Soft I2C bus
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#define OMV_SOFT_I2C_SIOC_PIN (&omv_pin_B10_GPIO)
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#define OMV_SOFT_I2C_SIOD_PIN (&omv_pin_B11_GPIO)
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#define OMV_SOFT_I2C_SPIN_DELAY 64
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// CSI SPI bus
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#define OMV_CSI_SPI_ID (3)
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// WINC1500 WiFi module SPI bus
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#define OMV_WINC_SPI_ID (2)
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#define OMV_WINC_SPI_BAUDRATE (40000000)
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#define OMV_WINC_EN_PIN (&omv_pin_A5_GPIO)
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#define OMV_WINC_RST_PIN (&omv_pin_D12_GPIO)
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#define OMV_WINC_IRQ_PIN (&omv_pin_D13_GPIO)
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// Camera Interface
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#define OMV_CSI_CLK_SOURCE (OMV_CSI_CLK_SOURCE_TIM)
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#define OMV_CSI_CLK_FREQUENCY (12000000)
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#define OMV_CSI_TIM (TIM1)
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#define OMV_CSI_TIM_PIN (&omv_pin_A8_TIM1)
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_DMA_CHANNEL (DMA2_Stream1)
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#define OMV_CSI_DMA_REQUEST (DMA_REQUEST_DCMI)
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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#define OMV_CSI_D0_PIN (&omv_pin_C6_DCMI)
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#define OMV_CSI_D1_PIN (&omv_pin_C7_DCMI)
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#define OMV_CSI_D2_PIN (&omv_pin_E0_DCMI)
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#define OMV_CSI_D3_PIN (&omv_pin_E1_DCMI)
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#define OMV_CSI_D4_PIN (&omv_pin_E4_DCMI)
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#define OMV_CSI_D5_PIN (&omv_pin_B6_DCMI)
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#define OMV_CSI_D6_PIN (&omv_pin_E5_DCMI)
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#define OMV_CSI_D7_PIN (&omv_pin_E6_DCMI)
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#define OMV_CSI_HSYNC_PIN (&omv_pin_A4_DCMI)
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#define OMV_CSI_VSYNC_PIN (&omv_pin_B7_DCMI)
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#define OMV_CSI_PXCLK_PIN (&omv_pin_A6_DCMI)
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#define OMV_CSI_RESET_PIN (&omv_pin_A10_GPIO)
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#define OMV_CSI_POWER_PIN (&omv_pin_D7_GPIO)
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#define OMV_CSI_FSYNC_PIN (&omv_pin_B4_GPIO)
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// Physical I2C buses.
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// I2C bus 1
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#define OMV_I2C1_ID (1)
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#define OMV_I2C1_SCL_PIN (&omv_pin_B8_I2C1)
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#define OMV_I2C1_SDA_PIN (&omv_pin_B9_I2C1)
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// I2C bus 2
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#define OMV_I2C2_ID (2)
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#define OMV_I2C2_SCL_PIN (&omv_pin_B10_I2C2)
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#define OMV_I2C2_SDA_PIN (&omv_pin_B11_I2C2)
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// Physical SPI buses.
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// SPI bus 2
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#define OMV_SPI2_ID (2)
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#define OMV_SPI2_SCLK_PIN (&omv_pin_B13_SPI2)
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#define OMV_SPI2_MISO_PIN (&omv_pin_B14_SPI2)
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#define OMV_SPI2_MOSI_PIN (&omv_pin_B15_SPI2)
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#define OMV_SPI2_SSEL_PIN (&omv_pin_B12_SPI2)
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#define OMV_SPI2_DMA_TX_CHANNEL (DMA1_Stream4)
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#define OMV_SPI2_DMA_TX_REQUEST (DMA_REQUEST_SPI2_TX)
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#define OMV_SPI2_DMA_RX_CHANNEL (DMA1_Stream3)
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#define OMV_SPI2_DMA_RX_REQUEST (DMA_REQUEST_SPI2_RX)
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// SPI bus 3
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#define OMV_SPI3_ID (3)
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#define OMV_SPI3_SCLK_PIN (&omv_pin_B3_SPI3)
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#define OMV_SPI3_MISO_PIN (&omv_pin_B4_SPI3)
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#define OMV_SPI3_MOSI_PIN (&omv_pin_B5_SPI3)
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#define OMV_SPI3_SSEL_PIN (&omv_pin_A15_SPI3)
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#define OMV_SPI3_DMA_TX_CHANNEL (DMA1_Stream7)
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#define OMV_SPI3_DMA_TX_REQUEST (DMA_REQUEST_SPI3_TX)
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#define OMV_SPI3_DMA_RX_CHANNEL (DMA1_Stream2)
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#define OMV_SPI3_DMA_RX_REQUEST (DMA_REQUEST_SPI3_RX)
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// SPI LCD Interface
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#define OMV_SPI_DISPLAY_CONTROLLER (OMV_SPI2_ID)
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#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_B15_SPI2)
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#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_B14_SPI2)
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#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_B13_SPI2)
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#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_B12_GPIO)
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#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_D13_GPIO)
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#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_D12_GPIO)
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#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_A5_GPIO)
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#endif //__OMV_BOARDCONFIG_H__
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