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213 lines
9.0 KiB
C
213 lines
9.0 KiB
C
/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2024 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2024 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_BOARD_ARCH "OMVRT1060 32768 SDRAM" // 33 chars max
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#define OMV_BOARD_TYPE "IMXRT1060"
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#define OMV_BOARD_UID_ADDR 0x401f4410 // Unique ID address.
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#define OMV_BOARD_UID_SIZE 3 // Unique ID size in words.
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#define OMV_BOARD_UID_OFFSET 12 // Bytes offset for multi-word UIDs.
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// JPEG configuration.
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#define OMV_JPEG_CODEC_ENABLE (0)
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#define OMV_JPEG_QUALITY_LOW (50)
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#define OMV_JPEG_QUALITY_HIGH (90)
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#define OMV_JPEG_QUALITY_THRESHOLD (320 * 240 * 2)
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// CSI drivers configuration.
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#define OMV_OV5640_ENABLE (1)
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#define OMV_OV5640_AF_ENABLE (1)
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#define OMV_OV5640_PLL_CTRL2 (0x64)
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#define OMV_OV5640_PLL_CTRL3 (0x13)
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#define OMV_OV7725_ENABLE (1)
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#define OMV_OV7725_PLL_CONFIG (0x41) // x4
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#define OMV_OV7725_BANDING (0x7F)
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#define OMV_MT9M114_ENABLE (1)
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#define OMV_MT9V0XX_ENABLE (1)
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#define OMV_LEPTON_ENABLE (1)
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#define OMV_PAG7920_ENABLE (1)
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#define OMV_PAJ6100_ENABLE (1)
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#define OMV_FROGEYE2020_ENABLE (1)
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// FIR drivers configuration.
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#define OMV_FIR_MLX90621_ENABLE (1)
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#define OMV_FIR_MLX90640_ENABLE (1)
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#define OMV_FIR_MLX90641_ENABLE (1)
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#define OMV_FIR_AMG8833_ENABLE (1)
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// UMM heap block size
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#define OMV_UMM_BLOCK_SIZE 256
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// Protocol hardware capabilities
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#define OMV_PROTOCOL_HW_CAPS OMV_PROTOCOL_HW_CAPS_MAKE( \
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HAS_DRAM, HAS_WIFI, HAS_BT, HAS_SD, HAS_ETH, HAS_USB_HS)
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// USB config.
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#define OMV_USB_IRQN (USB_OTG1_IRQn)
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#define OMV_USB1_IRQ_HANDLER (USB_OTG1_IRQHandler)
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#define OMV_USB2_IRQ_HANDLER (USB_OTG2_IRQHandler)
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#define OMV_USB_PHY_ID (kUSB_ControllerEhci0)
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#define OMV_USB_PHY_D_CAL (0x0CU)
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#define OMV_USB_PHY_TXCAL45DP (0x06U)
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#define OMV_USB_PHY_TXCAL45DM (0x06U)
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// Linker script constants (see the linker script template mimxrt10xx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_MAIN_MEMORY DTCM // Data/BSS memory
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#define OMV_STACK_MEMORY ITCM1 // stack memory
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#define OMV_STACK_SIZE (32K)
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#define OMV_SB_MEMORY DRAM // Streaming buffer memory.
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#define OMV_SB_SIZE (1M) // Streaming buffer size.
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#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
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#define OMV_FB_SIZE (13M) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (10M) // minimum fb alloc size
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#define OMV_FB_OVERLAY_MEMORY OCRM1 // Fast fb_alloc memory.
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#define OMV_FB_OVERLAY_SIZE (512K)
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#define OMV_DMA_MEMORY DTCM // Misc DMA buffers memory.
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#define OMV_GC_BLOCK0_MEMORY OCRM2 // Extra GC block 0.
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#define OMV_GC_BLOCK0_SIZE (64K)
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#define OMV_GC_BLOCK1_MEMORY DTCM // Main GC block
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#define OMV_GC_BLOCK1_SIZE (271K)
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#define OMV_GC_BLOCK2_MEMORY DRAM // Extra GC block 1.
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#define OMV_GC_BLOCK2_SIZE (8M)
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#define OMV_RAMFUNC_MEMORY ITCM2 // RAM code memory.
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#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer.
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#define OMV_VOSPI_DMA_BUFFER ".dma_buffer"
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// Memory configuration.
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#define OMV_DTCM_ORIGIN 0x20000000
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#define OMV_DTCM_LENGTH 384K
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#define OMV_ITCM1_ORIGIN 0x00000000
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#define OMV_ITCM1_LENGTH 32K
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#define OMV_ITCM2_ORIGIN 0x00008000
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#define OMV_ITCM2_LENGTH 32K
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#define OMV_OCRM1_ORIGIN 0x20200000
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#define OMV_OCRM1_LENGTH 512K
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#define OMV_OCRM2_ORIGIN 0x20280000 // Allocated from FlexRAM.
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#define OMV_OCRM2_LENGTH 64K
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#define OMV_DRAM_ORIGIN 0x80000000
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#define OMV_DRAM_LENGTH 32M
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#define OMV_FLEXRAM_CONFIG (0x5AAAAAAF) // OCRAM: 64K DTCM: 384K ITCM: 64K
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// Flash configuration.
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#define OMV_FLASH_ORIGIN 0x60000000
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#define OMV_FLASH_LENGTH 0x00800000
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#define OMV_FLASH_APP_ORIGIN 0x60040000 // 256K reserved for bootloader
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#define OMV_FLASH_APP_LENGTH 0x007C0000
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#define OMV_FLASH_TXT_ORIGIN 0x60043000
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#define OMV_FLASH_TXT_LENGTH 0x00380000
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#define OMV_FLASH_FFS_ORIGIN 0x60400000
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#define OMV_FLASH_FFS_LENGTH 0x00400000
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// ROMFS configuration.
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#define OMV_ROMFS_PART0_ORIGIN 0x60800000
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#define OMV_ROMFS_PART0_LENGTH 8M
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// CSI I2C bus
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#define OMV_CSI_I2C_ID (1)
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#define OMV_CSI_I2C_SPEED (OMV_I2C_SPEED_STANDARD)
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// FIR I2C bus
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#define OMV_FIR_I2C_ID (4)
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#define OMV_FIR_I2C_SPEED (OMV_I2C_SPEED_FULL)
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// CSI SPI bus
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#define OMV_CSI_SPI_ID (4)
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// Physical I2C buses.
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// LPI2C1
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#define OMV_I2C1_ID (1)
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#define OMV_I2C1_SCL_PIN (&omv_pin_LPI2C1_SCL)
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#define OMV_I2C1_SDA_PIN (&omv_pin_LPI2C1_SDA)
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// LPI2C2
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#define OMV_I2C2_ID (2)
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#define OMV_I2C2_SCL_PIN (&omv_pin_LPI2C2_SCL)
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#define OMV_I2C2_SDA_PIN (&omv_pin_LPI2C2_SDA)
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// LPI2C4
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#define OMV_I2C4_ID (4)
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#define OMV_I2C4_SCL_PIN (&omv_pin_LPI2C4_SCL)
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#define OMV_I2C4_SDA_PIN (&omv_pin_LPI2C4_SDA)
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// Physical SPI buses.
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// LPSPI3
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#define OMV_SPI3_ID (3)
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#define OMV_SPI3_SCLK_PIN (&omv_pin_LPSPI3_SCLK)
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#define OMV_SPI3_MISO_PIN (&omv_pin_LPSPI3_MISO)
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#define OMV_SPI3_MOSI_PIN (&omv_pin_LPSPI3_MOSI)
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#define OMV_SPI3_SSEL_PIN (&omv_pin_LPSPI3_SSEL)
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#define OMV_SPI3_DMA (DMA0)
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#define OMV_SPI3_DMA_MUX (DMAMUX)
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#define OMV_SPI3_DMA_TX_CHANNEL (3U)
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#define OMV_SPI3_DMA_RX_CHANNEL (2U)
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// LPSPI4
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#define OMV_SPI4_ID (4)
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#define OMV_SPI4_SCLK_PIN (&omv_pin_LPSPI4_SCLK)
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#define OMV_SPI4_MISO_PIN (&omv_pin_LPSPI4_MISO)
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#define OMV_SPI4_MOSI_PIN (&omv_pin_LPSPI4_MOSI)
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#define OMV_SPI4_SSEL_PIN (&omv_pin_LPSPI4_SSEL)
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#define OMV_SPI4_DMA (DMA0)
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#define OMV_SPI4_DMA_MUX (DMAMUX)
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#define OMV_SPI4_DMA_TX_CHANNEL (1U)
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#define OMV_SPI4_DMA_RX_CHANNEL (0U)
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// SPI LCD Interface
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#define OMV_SPI_DISPLAY_CONTROLLER (OMV_SPI3_ID)
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#define OMV_SPI_DISPLAY_MOSI_PIN (&omv_pin_LPSPI3_MOSI)
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#define OMV_SPI_DISPLAY_MISO_PIN (&omv_pin_LPSPI3_MISO)
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#define OMV_SPI_DISPLAY_SCLK_PIN (&omv_pin_LPSPI3_SCLK)
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#define OMV_SPI_DISPLAY_SSEL_PIN (&omv_pin_LPSPI3_GPIO)
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#define OMV_SPI_DISPLAY_RS_PIN (&omv_pin_P8_GPIO)
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#define OMV_SPI_DISPLAY_RST_PIN (&omv_pin_P7_GPIO)
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#define OMV_SPI_DISPLAY_BL_PIN (&omv_pin_P6_GPIO)
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#define OMV_SPI_DISPLAY_TRIPLE_BUFFER (0)
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#define OMV_SPI_DISPLAY_RX_CLK_DIV (8)
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// Camera interface configuration.
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#define OMV_CSI_BASE (CSI)
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#define OMV_CSI_DMA (DMA0)
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#define OMV_CSI_DMA_MUX (DMAMUX)
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#define OMV_CSI_DMA_CHANNEL_START (4U)
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#define OMV_CSI_DMA_CHANNEL_COUNT (2U)
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#define OMV_CSI_CLK_FREQUENCY (12000000)
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#define OMV_CSI_DMA_MEMCPY_ENABLE (1)
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#define OMV_CSI_HW_SWAP_ENABLE (1)
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#define OMV_CSI_HW_CROP_ENABLE (1)
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#define OMV_CSI_MAX_DEVICES (2)
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#define OMV_CSI_D0_PIN (&omv_pin_DCMI_D0)
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#define OMV_CSI_D1_PIN (&omv_pin_DCMI_D1)
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#define OMV_CSI_D2_PIN (&omv_pin_DCMI_D2)
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#define OMV_CSI_D3_PIN (&omv_pin_DCMI_D3)
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#define OMV_CSI_D4_PIN (&omv_pin_DCMI_D4)
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#define OMV_CSI_D5_PIN (&omv_pin_DCMI_D5)
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#define OMV_CSI_D6_PIN (&omv_pin_DCMI_D6)
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#define OMV_CSI_D7_PIN (&omv_pin_DCMI_D7)
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#define OMV_CSI_HSYNC_PIN (&omv_pin_DCMI_HSYNC)
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#define OMV_CSI_VSYNC_PIN (&omv_pin_DCMI_VSYNC)
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#define OMV_CSI_PXCLK_PIN (&omv_pin_DCMI_PXCLK)
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#define OMV_CSI_MXCLK_PIN (&omv_pin_DCMI_MCLK)
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#define OMV_CSI_RESET_PIN (&omv_pin_DCMI_RESET)
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#define OMV_CSI_POWER_PIN (&omv_pin_DCMI_POWER)
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#define OMV_CSI_FSYNC_PIN (&omv_pin_DCMI_FSYNC)
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#endif //__OMV_BOARDCONFIG_H__
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