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The ST Neural ART code generator marks the HyperRAM mpool as cacheable (CACHEABLE_ON), which causes the NPU stream engines to issue cacheable accesses. However, the N6 memory subsystem does not support cacheable accesses to internal memories, only external ones. Because of this, relocating the HyperRAM region to internal memory results in invalid access behavior: only base addresses are updated during relocation, not the cacheable attributes. In short, buffers generated for HyperRAM must remain in external memory. Marking HyperRAM as non-cacheable is a possible workaround, but may reduce performance if buffers are placed in AXI RAM instead. Forcing the ext_ram_sz allocation to 1MB ensures that the ext_ram_sz is allocated in SDRAM. |
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