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111 lines
3.4 KiB
C
111 lines
3.4 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2013-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Mutex implementation.
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* This is a standard implementation of mutexs on ARM processors following the ARM guide.
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* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHEJCHB.html
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*
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* Note: The Cortex-M0/M0+ does Not have the Load/Store exclusive instructions, on these
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* CPUs the locking function is implemented with atomic access using disable/enable IRQs.
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*/
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#include "mutex.h"
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#include "cmsis_compiler.h"
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#include "py/mphal.h"
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void mutex_init0(omv_mutex_t *mutex) {
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__DMB();
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mutex->tid = 0;
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mutex->lock = 0;
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mutex->last_tid = 0;
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}
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static void _mutex_lock(omv_mutex_t *mutex, uint32_t tid, bool blocking) {
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#if (__ARM_ARCH < 7)
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do {
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__disable_irq();
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if (mutex->lock == 0) {
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mutex->lock = 1;
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mutex->tid = tid;
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}
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__enable_irq();
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} while (mutex->tid != tid && blocking);
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#else
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do {
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// Attempt to lock the mutex
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if (__LDREXW(&mutex->lock) == 0) {
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if (__STREXW(1, &mutex->lock) == 0) {
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// Set TID if mutex is locked
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mutex->tid = tid;
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}
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}
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} while (mutex->tid != tid && blocking);
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#endif
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__DMB();
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}
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void mutex_lock(omv_mutex_t *mutex, uint32_t tid) {
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_mutex_lock(mutex, tid, true);
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}
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int mutex_try_lock(omv_mutex_t *mutex, uint32_t tid) {
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// If the mutex is already locked by the current thread then
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// release it and return without locking, otherwise try to lock it.
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if (mutex->tid == tid) {
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mutex_unlock(mutex, tid);
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} else {
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_mutex_lock(mutex, tid, false);
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}
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return (mutex->tid == tid);
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}
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int mutex_try_lock_alternate(omv_mutex_t *mutex, uint32_t tid) {
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if (mutex->last_tid != tid) {
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if (mutex_try_lock(mutex, tid)) {
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mutex->last_tid = tid;
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return 1;
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}
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}
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return 0;
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}
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int mutex_lock_timeout(omv_mutex_t *mutex, uint32_t tid, uint32_t timeout) {
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mp_uint_t tick_start = mp_hal_ticks_ms();
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while ((mp_hal_ticks_ms() - tick_start) >= timeout) {
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if (mutex_try_lock(mutex, tid)) {
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return 1;
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}
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__WFI();
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}
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return 0;
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}
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void mutex_unlock(omv_mutex_t *mutex, uint32_t tid) {
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if (mutex->tid == tid) {
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__DMB();
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mutex->tid = 0;
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mutex->lock = 0;
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}
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}
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