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222 lines
11 KiB
C
222 lines
11 KiB
C
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file dwc_ospi_private.h
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* @version V1.0.0
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* @brief Private header file for OSPI driver to set up flash in XIP mode.
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* @bug None.
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* @Note None
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******************************************************************************/
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#ifndef OSPI_PRIVATE_H
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#define OSPI_PRIVATE_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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typedef struct
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{
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volatile uint32_t ctrlr0; /* SPI Control Register 0 (0x0) */
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volatile uint32_t ctrlr1; /* SPI Control Register 1 (0x4) */
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volatile uint32_t ssienr; /* SPI Enable Register (0x8) */
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volatile uint32_t mwcr; /* SPI Microwire Control Register (0xC) */
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volatile uint32_t ser; /* SPI Slave Enable Register (0x10) */
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volatile uint32_t baudr; /* SPI Baud Rate Select Register (0x14) */
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volatile uint32_t txftlr; /* SPI Transmit FIFO Threshold Level Register (0x18) */
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volatile uint32_t rxftlr; /* SPI Receive FIFO Threshold Level Register (0x1C) */
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volatile uint32_t txflr; /* SPI Transmit FIFO Level Register (0x20)*/
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volatile uint32_t rxflr; /* SPI Receive FIFO Level Register (0x24)*/
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volatile uint32_t sr; /* SPI Status Register (0x28) */
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volatile uint32_t imr; /* SPI Interrupt Mask Register (0x2C) */
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volatile uint32_t isr; /* SPI Interrupt Status Register (0x30) */
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volatile uint32_t risr; /* SPI Raw Interrupt Status Register (0x34)*/
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volatile uint32_t txoicr; /* SPI Transmit FIFO Overflow Interrupt Clear Register (0x38) */
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volatile uint32_t rxoicr; /* SPI Receive FIFO Overflow Interrupt Clear Register (0x3C) */
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volatile uint32_t rxuicr; /* SPI Receive FIFO Underflow Interrupt Clear Register (0x40) */
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volatile uint32_t msticr; /* SPI Multi-Master Interrupt Clear Register (0x44) */
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volatile uint32_t icr; /* SPI Interrupt Clear Register (0x48) */
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volatile uint32_t dmacr; /* DMA Control Register (0x4C) */
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volatile uint32_t dmatxdlr; /* DMA Transmit Data Level (0x50) */
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volatile uint32_t dmarxdlr; /* DMA Receive Data Level (0x54) */
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volatile uint32_t spi_idr; /* SPI Identification Register (0x58) */
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volatile uint32_t spi_ver_id; /* Synopsys component version (0x5C) */
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volatile uint32_t data_reg; /* SPI DATA Register for both Read and Write (0x60) */
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volatile uint32_t drs[35]; /* SPI DATA Register for both Read and Write (0x64-0xEC) */
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volatile uint32_t rx_sample_dly; /* Rx Sample Delay Register (0xF0) */
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volatile uint32_t spi_ctrlr0; /* SPI Control Register (0xF4) */
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volatile uint32_t txd_drive_edge; /* Transmit Drive Edge Register (0xF8) */
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volatile uint32_t xip_mode_bits; /* eXecute in Place - Mode bits (0xFC) */
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volatile uint32_t xip_incr_inst;
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volatile uint32_t xip_wrap_inst;
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volatile uint32_t xip_ctrl;
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volatile uint32_t xip_ser;
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volatile uint32_t xrxoicr;
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volatile uint32_t xip_cnt_time_out;
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} ssi_regs_t;
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typedef struct {
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volatile uint32_t aes_control; /*!< (@ 0x00000000) AES Control Register */
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volatile uint32_t aes_interrupt; /*!< (@ 0x00000004) AES Interrupt Control Register */
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volatile uint32_t aes_interrupt_mask; /*!< (@ 0x00000008) AES Interrupt Mask Register */
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volatile uint32_t aes_key_0; /*!< (@ 0x0000000C) AES Key 0 Register */
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volatile uint32_t aes_key_1; /*!< (@ 0x00000010) AES Key 1 Register */
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volatile uint32_t aes_key_2; /*!< (@ 0x00000014) AES Key 2 Register */
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volatile uint32_t aes_key_3; /*!< (@ 0x00000018) AES Key 3 Register */
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volatile uint32_t aes_timeout_val; /*!< (@ 0x0000001C) Reserved */
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volatile uint32_t aes_rxds_delay; /*!< (@ 0x00000020) AES RXDS Delay Register */
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} aes_regs_t;
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/* OSPI Address Map */
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#ifndef OSPI0_BASE
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#define OSPI0_BASE 0x83000000UL
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#endif
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#ifndef OSPI1_BASE
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#define OSPI1_BASE 0x83002000UL
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#endif
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#ifndef OSPI0_XIP_BASE
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#define OSPI0_XIP_BASE 0xA0000000UL
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#endif
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#ifndef OSPI1_XIP_BASE
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#define OSPI1_XIP_BASE 0xC0000000UL
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#endif
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#ifndef OSPI0_SIZE
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#define OSPI0_SIZE 0x20000000UL
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#endif
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#ifndef OSPI1_SIZE
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#define OSPI1_SIZE 0x20000000UL
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#endif
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/* APB-E Peripherals */
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#ifndef AES0_BASE
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#define AES0_BASE 0x83001000UL
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#endif
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#ifndef AES1_BASE
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#define AES1_BASE 0x83003000UL
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#endif
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/* Bit fields in CTRLR0 */
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#define CTRLR0_SPI_HE_OFFSET 24U
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#define CTRLR0_SPI_FRF_OFFSET 22U
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#define CTRLR0_CFS_OFFSET 16U
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#define CTRLR0_SSTE_OFFSET 14U
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#define CTRLR0_SRL_OFFSET 13U
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#define CTRLR0_SLV_OE_OFFSET 12U
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#define CTRLR0_TMOD_OFFSET 10U
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#define CTRLR0_TMOD_MASK (3U << CTRLR0_TMOD_OFFSET)
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#define CTRLR0_SCPOL_OFFSET 9U
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#define CTRLR0_SCPH_OFFSET 8U
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#define CTRLR0_FRF_OFFSET 6U
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#define CTRLR0_DFS_OFFSET 0U
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#define CTRLR0_IS_MST (1U << 31)
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#define SPI_TMOD_TR 0x0
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#define TMOD_TO 0x1
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#define TMOD_RO 0x2
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#define TMOD_EPROMREAD 0x3
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/* Bit fields for SPI FRF */
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#define SINGLE 0x0
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#define DUAL 0x1
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#define QUAD 0x2
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#define OCTAL 0x3
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/* Instruction length */
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#define CTRLR0_INST_L_0bit 0x0U
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#define CTRLR0_INST_L_4bit 0x1U
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#define CTRLR0_INST_L_8bit 0x2U
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#define CTRLR0_INST_L_16bit 0x3U
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/* Data frame length */
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#define CTRLR0_DFS_8bit 0x07U
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#define CTRLR0_DFS_16bit 0x0FU
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#define CTRLR0_DFS_32bit 0x1FU
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#define ADDR_L32bit 0x8
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#define INST_L8bit 0x2
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/* Bit fields for Frame Format FRF */
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#define FRF_SPI 0x0
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#define FRF_SSP 0x1
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#define FRF_MICROWIRE 0x2
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7F
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#define SR_BUSY (1U << 0)
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#define SR_TF_NOT_FULL (1U << 1)
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#define SR_TF_EMPTY (1U << 2)
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#define SR_RF_NOT_EMPT (1U << 3)
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#define SR_RF_FULL (1U << 4)
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#define SR_TX_ERR (1U << 5)
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#define SR_DCOL (1U << 6)
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/* Bit fields in CTRLR0 */
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#define CTRLR0_CLK_STRETCH_EN_OFFSET 30U
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#define CTRLR0_XIP_PREFETCH_EN_OFFSET 29U
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#define CTRLR0_XIP_MBL_OFFSET 26U
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#define CTRLR0_SPI_RXDS_SIG_EN_OFFSET 25U
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#define CTRLR0_SPI_DM_EN_OFFSET 24U
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#define CTRLR0_XIP_CONT_EN_OFFSET 21U
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#define CTRLR0_XIP_INST_EN_OFFSET 20U
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#define CTRLR0_XIP_DFS_HC_OFFSET 19U
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#define CTRLR0_SPI_RXDS_EN_OFFSET 18U
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#define CTRLR0_INST_DDR_EN_OFFSET 17U
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#define CTRLR0_SPI_DDR_EN_OFFSET 16U
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#define CTRLR0_WAIT_CYCLES_OFFSET 11U
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#define CTRLR0_INST_L_OFFSET 8U
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#define CTRLR0_XIP_MD_EN_OFFSET 7U
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#define CTRLR0_ADDR_L_OFFSET 2U
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#define CTRLR0_TRANS_TYPE_OFFSET 0U
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#define XIP_CTRL_RXDS_VL_EN_OFFSET 30U
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#define XIP_PREFETCH_EN_OFFSET 29U
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#define XIP_CTRL_XIP_MBL_OFFSET 26U
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#define XIP_CTRL_RXDS_SIG_EN 25U
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#define XIP_CTRL_HYPERBUS_EN_OFFSET 24U
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#define XIP_CTRL_CONT_XFER_EN_OFFSET 23U
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#define XIP_CTRL_INST_EN_OFFSET 22U
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#define XIP_CTRL_RXDS_EN_OFFSET 21U
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#define XIP_CTRL_INST_DDR_EN_OFFSET 20U
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#define XIP_CTRL_DDR_EN_OFFSET 19U
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#define XIP_CTRL_DFC_HC_OFFSET 18U
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#define XIP_CTRL_WAIT_CYCLES_OFFSET 13U
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#define XIP_CTRL_MD_BITS_EN_OFFSET 12U
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#define XIP_CTRL_INST_L_OFFSET 9U
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#define XIP_CTRL_ADDR_L_OFFSET 4U
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#define XIP_CTRL_TRANS_TYPE_OFFSET 2U
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#define XIP_CTRL_FRF_OFFSET 0U
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#define CTRLR0_TRANS_TYPE_MASK 3U
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#define TRANS_TYPE_STANDARD 0U
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#define TRANS_TYPE_FRF_DEFINED 2U
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/* AES_CONTROL fields */
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#define AES_CONTROL_LD_KEY (1U << 7)
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#define AES_CONTROL_XIP_EN (1U << 4)
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#define AES_CONTROL_DECRYPT_EN (1U << 0)
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#define ospi_readl(a, r) (a->regs->r)
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#define ospi_writel(a, r, v) a->regs->r = (v)
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#define spi_enable(cfg) ospi_writel(cfg, ssienr, 1)
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#define spi_disable(cfg) ospi_writel(cfg, ssienr, 0)
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#define spi_set_clk(cfg, div) ospi_writel(cfg, baudr, div)
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#ifdef __cplusplus
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}
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#endif
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#endif /* OSPI_PRIVATE_H */
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