mirror of
https://github.com/openmv/openmv.git
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153 lines
5.8 KiB
C
153 lines
5.8 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2013-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Max integral image.
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#define OMV_MAX_INT_FRAME OMV_CSI_FRAMESIZE_QCIF
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#define OMV_MAX_INT_FRAME_STR "QCIF"
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// Max GS/RGB565/YUV422/Binary image.
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#define OMV_MAX_RAW_FRAME OMV_CSI_FRAMESIZE_QCIF
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#define OMV_MAX_RAW_FRAME_STR "QCIF"
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// Max raw (RGB565/YUV422) image for blob detection.
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#define OMV_MAX_BLOB_FRAME OMV_CSI_FRAMESIZE_QCIF
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#define OMV_MAX_BLOB_FRAME_STR "QCIF"
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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//PLL1 168MHz/48MHz
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#define OMV_OSC_PLL1M (12)
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#define OMV_OSC_PLL1N (336)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (7)
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_5)
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// Memory map.
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#define OMV_FLASH_ORIGIN 0x08000000
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#define OMV_FLASH_LENGTH 512K
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#define OMV_SRAM1_ORIGIN 0x20000000
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#define OMV_SRAM1_LENGTH 128K
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#define OMV_DTCM_ORIGIN 0x10000000
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#define OMV_DTCM_LENGTH 64K
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// Flash configuration.
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#define OMV_FLASH_FFS_ORIGIN 0x08004000
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#define OMV_FLASH_FFS_LENGTH 48K
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#define OMV_FLASH_TXT_ORIGIN 0x08010000
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#define OMV_FLASH_TXT_LENGTH 448K
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/* SCCB/I2C */
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#define SCCB_I2C (I2C1)
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#define SCCB_AF (GPIO_AF4_I2C1)
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#define SCCB_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define SCCB_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define SCCB_PORT (GPIOB)
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#define SCCB_SCL_PIN (GPIO_PIN_8)
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#define SCCB_SDA_PIN (GPIO_PIN_9)
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// Camera interface
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#define OMV_CSI_CLK_FREQUENCY (12000000)
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#define OMV_CSI_TIM (TIM1)
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#define OMV_CSI_TIM_PIN (GPIO_PIN_9)
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#define OMV_CSI_TIM_PORT (GPIOE)
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#define OMV_CSI_TIM_AF (GPIO_AF1_TIM1)
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#define OMV_CSI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define OMV_CSI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define OMV_CSI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_ENABLE() __TIM1_CLK_SLEEP_ENABLE()
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#define OMV_CSI_TIM_CLK_SLEEP_DISABLE() __TIM1_CLK_SLEEP_DISABLE()
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#define OMV_CSI_HW_CROP_ENABLE (1)
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#define OMV_CSI_RESET_PIN (GPIO_PIN_10)
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#define OMV_CSI_RESET_PORT (GPIOA)
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#define OMV_CSI_PWDN_PIN (GPIO_PIN_5)
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#define OMV_CSI_PWDN_PORT (GPIOB)
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#define OMV_CSI_D0_PIN (GPIO_PIN_6)
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#define OMV_CSI_D1_PIN (GPIO_PIN_7)
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#define OMV_CSI_D2_PIN (GPIO_PIN_0)
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#define OMV_CSI_D3_PIN (GPIO_PIN_1)
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#define OMV_CSI_D4_PIN (GPIO_PIN_4)
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#define OMV_CSI_D5_PIN (GPIO_PIN_5)
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#define OMV_CSI_D6_PIN (GPIO_PIN_6)
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#define OMV_CSI_D7_PIN (GPIO_PIN_6)
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#define OMV_CSI_D0_PORT (GPIOC)
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#define OMV_CSI_D1_PORT (GPIOC)
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#define OMV_CSI_D2_PORT (GPIOE)
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#define OMV_CSI_D3_PORT (GPIOE)
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#define OMV_CSI_D4_PORT (GPIOE)
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#define OMV_CSI_D5_PORT (GPIOE)
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#define OMV_CSI_D6_PORT (GPIOE)
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#define OMV_CSI_D7_PORT (GPIOB)
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#define OMV_CSI_HSYNC_PIN (GPIO_PIN_7)
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#define OMV_CSI_VSYNC_PIN (GPIO_PIN_4)
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#define OMV_CSI_PXCLK_PIN (GPIO_PIN_6)
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#define OMV_CSI_HSYNC_PORT (GPIOB)
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#define OMV_CSI_VSYNC_PORT (GPIOA)
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#define OMV_CSI_PXCLK_PORT (GPIOA)
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#define OMV_CSI_RESET_LOW() HAL_GPIO_WritePin(OMV_CSI_RESET_PORT, OMV_CSI_RESET_PIN, GPIO_PIN_RESET)
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#define OMV_CSI_RESET_HIGH() HAL_GPIO_WritePin(OMV_CSI_RESET_PORT, OMV_CSI_RESET_PIN, GPIO_PIN_SET)
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#define OMV_CSI_PWDN_LOW() HAL_GPIO_WritePin(OMV_CSI_PWDN_PORT, OMV_CSI_PWDN_PIN, GPIO_PIN_RESET)
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#define OMV_CSI_PWDN_HIGH() HAL_GPIO_WritePin(OMV_CSI_PWDN_PORT, OMV_CSI_PWDN_PIN, GPIO_PIN_SET)
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/* uSD */
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#define SD_SPI (SPI2)
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#define SD_SPI_AF (GPIO_AF5_SPI2)
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#define SD_CD_PIN (GPIO_PIN_0)
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#define SD_CS_PIN (GPIO_PIN_1)
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#define SD_SCLK_PIN (GPIO_PIN_13)
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#define SD_MISO_PIN (GPIO_PIN_2)
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#define SD_MOSI_PIN (GPIO_PIN_3)
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#define SD_CD_PORT (GPIOC)
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#define SD_CS_PORT (GPIOC)
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#define SD_SCLK_PORT (GPIOB)
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#define SD_MISO_PORT (GPIOC)
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#define SD_MOSI_PORT (GPIOC)
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#define SD_SPI_CLK_ENABLE() __SPI2_CLK_ENABLE()
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#define SD_SPI_CLK_DISABLE() __SPI2_CLK_DISABLE()
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#define SD_SELECT() HAL_GPIO_WritePin(SD_CS_PORT, SD_CS_PIN, GPIO_PIN_RESET)
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#define SD_DESELECT() HAL_GPIO_WritePin(SD_CS_PORT, SD_CS_PIN, GPIO_PIN_SET)
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#endif //__OMV_BOARDCONFIG_H__
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