openmv/lib/cmsis/include/st/stm32n657xx.h
iabdalkader daf2bb30da misc: Restructure repo.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
2025-04-13 08:28:34 +02:00

43083 lines
3.4 MiB

/**
******************************************************************************
* @file stm32n657xx.h
* @author MCD Application Team
* @brief CMSIS STM32N657xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
#ifndef STM32N657xx_H
#define STM32N657xx_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup ST
* @{
*/
/** @addtogroup STM32N657xx
* @{
*/
/** @addtogroup Configuration_of_CMSIS
* @{
*/
/* =========================================================================================================================== */
/* ================ Interrupt Number Definition ================ */
/* =========================================================================================================================== */
typedef enum
{
/* ====================================== ARM Cortex-M55 Specific Interrupt Numbers ======================================== */
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
SecureFault_IRQn = -9, /*!< -9 Secure Fault */
#endif
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
/* ====================================== STM32N6xx Specific Interrupt Numbers ============================================= */
PVD_PVM_IRQn = 0, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection */
DTS_IRQn = 2, /*!< Thermal Sensor interruption */
RCC_IRQn = 3, /*!< RCC non-secure global interrupts through EXTI Line detection */
LOCKUP_IRQn = 4, /*!< LOCKUP / (no Overstack in CM55) */
CACHE_ECC_IRQn = 5, /*!< Error ECC cache interrupt */
TCM_ECC_IRQn = 6, /*!< TCM ECC interrupts */
BKP_ECC_IRQn = 7, /*!< Backup RAM Interrupts */
FPU_IRQn = 8, /*!< FPU interrupt */
RTC_S_IRQn = 10, /*!< RTC secure interrupts through EXTI Line detection */
TAMP_IRQn = 11, /*!< Tamper secure and non-secure interrupts through EXTI Line detection */
RIFSC_TAMPER_IRQn = 12, /*!< RIF Tamper interrupts */
IAC_IRQn = 13, /*!< IAC interrupt */
RCC_S_IRQn = 14, /*!< RCC secure global interrupts through EXTI Line detection */
RTC_IRQn = 16, /*!< RTC non-secure interrupts through EXTI Line detection */
IWDG_IRQn = 18, /*!< Internal Watchdog interrupt */
WWDG_IRQn = 19, /*!< Window Watchdog interrupt */
EXTI0_IRQn = 20, /*!< EXTI Line0 interrupt */
EXTI1_IRQn = 21, /*!< EXTI Line1 interrupt */
EXTI2_IRQn = 22, /*!< EXTI Line2 interrupt */
EXTI3_IRQn = 23, /*!< EXTI Line3 interrupt */
EXTI4_IRQn = 24, /*!< EXTI Line4 interrupt */
EXTI5_IRQn = 25, /*!< EXTI Line5 interrupt */
EXTI6_IRQn = 26, /*!< EXTI Line6 interrupt */
EXTI7_IRQn = 27, /*!< EXTI Line7 interrupt */
EXTI8_IRQn = 28, /*!< EXTI Line8 interrupt */
EXTI9_IRQn = 29, /*!< EXTI Line9 interrupt */
EXTI10_IRQn = 30, /*!< EXTI Line10 interrupt */
EXTI11_IRQn = 31, /*!< EXTI Line11 interrupt */
EXTI12_IRQn = 32, /*!< EXTI Line12 interrupt */
EXTI13_IRQn = 33, /*!< EXTI Line13 interrupt */
EXTI14_IRQn = 34, /*!< EXTI Line14 interrupt */
EXTI15_IRQn = 35, /*!< EXTI Line15 interrupt */
SAES_IRQn = 36, /*!< SAES interrupt */
CRYP_IRQn = 37, /*!< CRYP interrupt */
PKA_IRQn = 38, /*!< PKA interrupt */
HASH_IRQn = 39, /*!< HASH interrupt */
RNG_IRQn = 40, /*!< RNG global interrupt */
MCE1_IRQn = 42, /*!< MCE1 global interrupt */
MCE2_IRQn = 43, /*!< MCE2 global interrupt */
MCE3_IRQn = 44, /*!< MCE3 global interrupt */
MCE4_IRQn = 45, /*!< MCE4 global interrupt */
ADC1_2_IRQn = 46, /*!< ADC1 & ADC2 interrupt */
CSI_IRQn = 47, /*!< CSI global interrupt */
DCMIPP_IRQn = 48, /*!< DCMIPP global interrupt */
PAHB_ERR_IRQn = 52, /*!< PAHB error interrupt */
NPU0_IRQn = 53, /*!< NPU mst_ints[0] line interrupt */
NPU1_IRQn = 54, /*!< NPU mst_ints[1] line interrupt */
NPU2_IRQn = 55, /*!< NPU mst_ints[2] line interrupt */
NPU3_IRQn = 56, /*!< NPU mst_ints[3] line interrupt */
CACHEAXI_IRQn = 57, /*!< NPU cache interrupt */
LTDC_LO_IRQn = 58, /*!< LTDC low-layer global interrupt */
LTDC_LO_ERR_IRQn = 59, /*!< LTDC low-layer error interrupt */
DMA2D_IRQn = 60, /*!< DMA2D global interrupt */
JPEG_IRQn = 61, /*!< JPEG global interrupt */
VENC_IRQn = 62, /*!< VENC global interrupt */
GFXMMU_IRQn = 63, /*!< GFXMMU global interrupt */
GFXTIM_IRQn = 64, /*!< GFXTIM global interrupt */
GPU2D_IRQn = 65, /*!< GPU2D interrupt */
GPU2D_ER_IRQn = 66, /*!< GPU2D error interrupt */
ICACHE_IRQn = 67, /*!< GPU2D cache interrupt */
HPDMA1_Channel0_IRQn = 68, /*!< HPDMA1 Channel 0 global interrupt */
HPDMA1_Channel1_IRQn = 69, /*!< HPDMA1 Channel 1 global interrupt */
HPDMA1_Channel2_IRQn = 70, /*!< HPDMA1 Channel 2 global interrupt */
HPDMA1_Channel3_IRQn = 71, /*!< HPDMA1 Channel 3 global interrupt */
HPDMA1_Channel4_IRQn = 72, /*!< HPDMA1 Channel 4 global interrupt */
HPDMA1_Channel5_IRQn = 73, /*!< HPDMA1 Channel 5 global interrupt */
HPDMA1_Channel6_IRQn = 74, /*!< HPDMA1 Channel 6 global interrupt */
HPDMA1_Channel7_IRQn = 75, /*!< HPDMA1 Channel 7 global interrupt */
HPDMA1_Channel8_IRQn = 76, /*!< HPDMA1 Channel 8 global interrupt */
HPDMA1_Channel9_IRQn = 77, /*!< HPDMA1 Channel 9 global interrupt */
HPDMA1_Channel10_IRQn = 78, /*!< HPDMA1 Channel 10 global interrupt */
HPDMA1_Channel11_IRQn = 79, /*!< HPDMA1 Channel 11 global interrupt */
HPDMA1_Channel12_IRQn = 80, /*!< HPDMA1 Channel 12 global interrupt */
HPDMA1_Channel13_IRQn = 81, /*!< HPDMA1 Channel 13 global interrupt */
HPDMA1_Channel14_IRQn = 82, /*!< HPDMA1 Channel 14 global interrupt */
HPDMA1_Channel15_IRQn = 83, /*!< HPDMA1 Channel 15 global interrupt */
GPDMA1_Channel0_IRQn = 84, /*!< GPDMA1 Channel 0 interrupt */
GPDMA1_Channel1_IRQn = 85, /*!< GPDMA1 Channel 1 interrupt */
GPDMA1_Channel2_IRQn = 86, /*!< GPDMA1 Channel 2 interrupt */
GPDMA1_Channel3_IRQn = 87, /*!< GPDMA1 Channel 3 interrupt */
GPDMA1_Channel4_IRQn = 88, /*!< GPDMA1 Channel 4 interrupt */
GPDMA1_Channel5_IRQn = 89, /*!< GPDMA1 Channel 5 interrupt */
GPDMA1_Channel6_IRQn = 90, /*!< GPDMA1 Channel 6 interrupt */
GPDMA1_Channel7_IRQn = 91, /*!< GPDMA1 Channel 7 interrupt */
GPDMA1_Channel8_IRQn = 92, /*!< GPDMA1 Channel 8 interrupt */
GPDMA1_Channel9_IRQn = 93, /*!< GPDMA1 Channel 9 interrupt */
GPDMA1_Channel10_IRQn = 94, /*!< GPDMA1 Channel 10 interrupt */
GPDMA1_Channel11_IRQn = 95, /*!< GPDMA1 Channel 11 interrupt */
GPDMA1_Channel12_IRQn = 96, /*!< GPDMA1 Channel 12 interrupt */
GPDMA1_Channel13_IRQn = 97, /*!< GPDMA1 Channel 13 interrupt */
GPDMA1_Channel14_IRQn = 98, /*!< GPDMA1 Channel 14 interrupt */
GPDMA1_Channel15_IRQn = 99, /*!< GPDMA1 Channel 15 interrupt */
I2C1_EV_IRQn = 100, /*!< I2C1 event interrupt */
I2C1_ER_IRQn = 101, /*!< I2C1 error interrupt */
I2C2_EV_IRQn = 102, /*!< I2C2 event interrupt */
I2C2_ER_IRQn = 103, /*!< I2C2 error interrupt */
I2C3_EV_IRQn = 104, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 105, /*!< I2C3 error interrupt */
I2C4_EV_IRQn = 106, /*!< I2C4 event interrupt */
I2C4_ER_IRQn = 107, /*!< I2C4 error interrupt */
I3C1_EV_IRQn = 108, /*!< I3C1 event interrupt */
I3C1_ER_IRQn = 109, /*!< I3C1 error interrupt */
I3C2_EV_IRQn = 110, /*!< I3C2 event interrupt */
I3C2_ER_IRQn = 111, /*!< I3C2 error interrupt */
TIM1_BRK_IRQn = 112, /*!< TIM1 Break interrupt */
TIM1_UP_IRQn = 113, /*!< TIM1 Update interrupt */
TIM1_TRG_COM_IRQn = 114, /*!< TIM1 Trigger and Commutation interrupt */
TIM1_CC_IRQn = 115, /*!< TIM1 Capture Compare interrupt */
TIM2_IRQn = 116, /*!< TIM2 global interrupt */
TIM3_IRQn = 117, /*!< TIM3 global interrupt */
TIM4_IRQn = 118, /*!< TIM4 global interrupt */
TIM5_IRQn = 119, /*!< TIM5 global interrupt */
TIM6_IRQn = 120, /*!< TIM6 global interrupt */
TIM7_IRQn = 121, /*!< TIM7 global interrupt */
TIM8_BRK_IRQn = 122, /*!< TIM8 Break interrupt */
TIM8_UP_IRQn = 123, /*!< TIM8 Update interrupt */
TIM8_TRG_COM_IRQn = 124, /*!< TIM8 Trigger and Commutation interrupt */
TIM8_CC_IRQn = 125, /*!< TIM8 Capture Compare interrupt */
TIM9_IRQn = 126, /*!< TIM9 global interrupt */
TIM10_IRQn = 127, /*!< TIM10 global interrupt */
TIM11_IRQn = 128, /*!< TIM11 global interrupt */
TIM12_IRQn = 129, /*!< TIM12 global interrupt */
TIM13_IRQn = 130, /*!< TIM13 global interrupt */
TIM14_IRQn = 131, /*!< TIM14 global interrupt */
TIM15_IRQn = 132, /*!< TIM15 global interrupt */
TIM16_IRQn = 133, /*!< TIM16 global interrupt */
TIM17_IRQn = 134, /*!< TIM17 global interrupt */
TIM18_IRQn = 135, /*!< TIM18 global interrupt */
LPTIM1_IRQn = 136, /*!< LPTIM1 global interrupt */
LPTIM2_IRQn = 137, /*!< LPTIM2 global interrupt */
LPTIM3_IRQn = 138, /*!< LPTIM3 global interrupt */
LPTIM4_IRQn = 139, /*!< LPTIM4 global interrupt */
LPTIM5_IRQn = 140, /*!< LPTIM5 global interrupt */
ADF1_FLT0_IRQn = 141, /*!< ADF1 Filter 0 global interrupt */
MDF1_FLT0_IRQn = 142, /*!< MDF1 Filter 0 global interrupt */
MDF1_FLT1_IRQn = 143, /*!< MDF1 Filter 1 global interrupt */
MDF1_FLT2_IRQn = 144, /*!< MDF1 Filter 2 global interrupt */
MDF1_FLT3_IRQn = 145, /*!< MDF1 Filter 3 global interrupt */
MDF1_FLT4_IRQn = 146, /*!< MDF1 Filter 4 global interrupt */
MDF1_FLT5_IRQn = 147, /*!< MDF1 Filter 5 global interrupt */
SAI1_A_IRQn = 148, /*!< Serial Audio Interface 1 block A interrupt */
SAI1_B_IRQn = 149, /*!< Serial Audio Interface 1 block B interrupt */
SAI2_A_IRQn = 150, /*!< Serial Audio Interface 2 block A interrupt */
SAI2_B_IRQn = 151, /*!< Serial Audio Interface 2 block B interrupt */
SPDIFRX1_IRQn = 152, /*!< SPDIFRX1 interrupt */
SPI1_IRQn = 153, /*!< SPI1 global interrupt */
SPI2_IRQn = 154, /*!< SPI2 global interrupt */
SPI3_IRQn = 155, /*!< SPI3 global interrupt */
SPI4_IRQn = 156, /*!< SPI4 global interrupt */
SPI5_IRQn = 157, /*!< SPI5 global interrupt */
SPI6_IRQn = 158, /*!< SPI6 global interrupt */
USART1_IRQn = 159, /*!< USART1 global interrupt */
USART2_IRQn = 160, /*!< USART2 global interrupt */
USART3_IRQn = 161, /*!< USART3 global interrupt */
UART4_IRQn = 162, /*!< UART4 global interrupt */
UART5_IRQn = 163, /*!< UART5 global interrupt */
USART6_IRQn = 164, /*!< USART3 global interrupt */
UART7_IRQn = 165, /*!< UART7 global interrupt */
UART8_IRQn = 166, /*!< UART8 global interrupt */
UART9_IRQn = 167, /*!< UART9 global interrupt */
USART10_IRQn = 168, /*!< USART10 global interrupt */
LPUART1_IRQn = 169, /*!< LPUART1 global interrupt */
XSPI1_IRQn = 170, /*!< XSPI1 global interrupt */
XSPI2_IRQn = 171, /*!< XSPI2 global interrupt */
XSPI3_IRQn = 172, /*!< XSPI3 global interrupt */
FMC_IRQn = 173, /*!< FMC global interrupt */
SDMMC1_IRQn = 174, /*!< SDMMC1 global interrupt */
SDMMC2_IRQn = 175, /*!< SDMMC2 global interrupt */
UCPD1_IRQn = 176, /*!< UCPD1 global interrupt */
USB1_OTG_HS_IRQn = 177, /*!< USB1 OTG HS interrupt */
USB2_OTG_HS_IRQn = 178, /*!< USB2 OTG HS interrupt */
ETH1_IRQn = 179, /*!< ETH1 global interrupt */
FDCAN1_IT0_IRQn = 180, /*!< FDCAN1 interrupt 0 */
FDCAN1_IT1_IRQn = 181, /*!< FDCAN1 interrupt 1 */
FDCAN2_IT0_IRQn = 182, /*!< FDCAN2 interrupt 0 */
FDCAN2_IT1_IRQn = 183, /*!< FDCAN2 interrupt 1 */
FDCAN3_IT0_IRQn = 184, /*!< FDCAN3 interrupt 0 */
FDCAN3_IT1_IRQn = 185, /*!< FDCAN3 interrupt 1 */
FDCAN_CU_IRQn = 186, /*!< FDCAN Clock Unit interrupt */
MDIOS_IRQn = 187, /*!< MDIOS global interrupt */
DCMI_PSSI_IRQn = 188, /*!< DCMI/PSSI global interrupt */
WAKEUP_PIN_IRQn = 189, /*!< Wake-up pins interrupt */
CTI_INT0_IRQn = 190, /*!< CTI INT0 interrupt */
CTI_INT1_IRQn = 191, /*!< CTI INT1 interrupt */
LTDC_UP_IRQn = 193, /*!< LTDC up-layer global interrupt */
LTDC_UP_ERR_IRQn = 194, /*!< LTDC up-layer error interrupt */
} IRQn_Type;
/* =========================================================================================================================== */
/* ================ Processor and Core Peripheral Section ================ */
/* =========================================================================================================================== */
/**
* @brief Configuration of the Cortex-M55 Processor and Core Peripherals
*/
#define __CM55_REV 0x0101U /*!< Cortex-M55 revision r1p1 */
#define __FPU_PRESENT 1U /*!< CM55 Floating Point Unit present */
#define __DSP_PRESENT 1U /*!< CM55 Digital Signal Processing Unit present */
#define __MPU_PRESENT 1U /*!< CM55 Memory Programming Unit present */
#define __ICACHE_PRESENT 1U /*!< CM55 Instruction cache present */
#define __DCACHE_PRESENT 1U /*!< CM55 Data cache present */
#define __VTOR_PRESENT 1U /*!< CM55 Vector table offset register present */
#define __PMU_PRESENT 1U /*!< CM55 Performance Monitoring Unit present */
#define __PMU_NUM_EVENTCNT 8U /*!< CM55 can monitor up to 8 PMU events */
#define __NVIC_PRIO_BITS 4U /*!< CM55 uses 4 bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __SAUREGION_PRESENT 1U /*!< SAU regions present */
/** @} */ /* End of group Configuration_of_CMSIS */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define CPU_IN_SECURE_STATE
#endif
#define CPU_AS_TRUSTED_DOMAIN
#include <core_cm55.h> /*!< ARM Cortex-M55 processor and core peripherals */
#include "system_stm32n6xx.h" /*!< STM32N6xx System */
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Section ================ */
/* =========================================================================================================================== */
/** @addtogroup STM32N6xx_peripherals
* @{
*/
/**
* @brief Analog to Digital Converter (ADC)
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
__IO uint32_t PCSEL; /*!< ADC channel preselection register, Address offset: 0x1C */
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x020-0x02C */
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x044-0x048 */
__IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
__IO uint32_t OFCFGR1; /*!< ADC offset configuration register 1, Address offset: 0x50 */
__IO uint32_t OFCFGR2; /*!< ADC offset configuration register 2, Address offset: 0x54 */
__IO uint32_t OFCFGR3; /*!< ADC offset configuration register 3, Address offset: 0x58 */
__IO uint32_t OFCFGR4; /*!< ADC offset configuration register 4, Address offset: 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
__IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */
uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x074-0x07C */
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
uint32_t RESERVED4[4]; /*!< Reserved, Address offset: 0x090-0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
__IO uint32_t AWD1LTR; /*!< ADC analog watchdog 1 low threshold register, Address offset: 0xA8 */
__IO uint32_t AWD1HTR; /*!< ADC analog watchdog 1 high threshold register, Address offset: 0xAC */
__IO uint32_t AWD2LTR; /*!< ADC analog watchdog 2 low threshold register, Address offset: 0xB0 */
__IO uint32_t AWD2HTR; /*!< ADC analog watchdog 2 high threshold register, Address offset: 0xB4 */
__IO uint32_t AWD3LTR; /*!< ADC analog watchdog 3 low threshold register, Address offset: 0xB8 */
__IO uint32_t AWD3HTR; /*!< ADC analog watchdog 3 high threshold register, Address offset: 0xBC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xC0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xC4 */
uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x0C8-0x0CC */
__IO uint32_t OR; /*!< ADC option register, Address offset: 0xD0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */
__IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */
__IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */
__IO uint32_t CDR2; /*!< ADC common regular data register for dual mode 32-bit, Address offset: 0x310 */
} ADC_Common_TypeDef;
/**
* @brief Boot and Security
*/
typedef struct
{
__IO uint32_t FVRw[384]; /*!< BSEC fuse word (0-383) value register, Address offset: 0x000-0x5FC */
uint32_t RESERVED0[128]; /*!< Reserved, Address offset: 0x600-0x7FC */
__IO uint32_t SPLOCKx[12]; /*!< BSEC sticky program lock register (0-11), Address offset: 0x800-0x82C */
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x830-0x83C */
__IO uint32_t SWLOCKx[12]; /*!< BSEC sticky write lock register (0-11), Address offset: 0x840-0x86C */
uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x870-0x87C */
__IO uint32_t SRLOCKx[12]; /*!< BSEC sticky reload lock register (0-11), Address offset: 0x880-0x8AC */
uint32_t RESERVED3[4]; /*!< Reserved, Address offset: 0x8B0-0x8BC */
__IO uint32_t OTPVLDRx[12]; /*!< BSEC OTP valid register (0-11), Address offset: 0x8C0-0x8EC */
uint32_t RESERVED4[20]; /*!< Reserved, Address offset: 0x8F0-0x93C */
__IO uint32_t SFSRx[12]; /*!< BSEC shadowed fuses status register (0-11), Address offset: 0x940-0x96C */
uint32_t RESERVED5[165]; /*!< Reserved, Address offset: 0x970-0xC00 */
__IO uint32_t OTPCR; /*!< BSEC OTP control register, Address offset: 0xC04 */
__IO uint32_t WDR; /*!< BSEC write data register, Address offset: 0xC08 */
uint32_t RESERVED6[125]; /*!< Reserved, Address offset: 0xC0C-0xDFC */
__IO uint32_t SCRATCHRx[4]; /*!< BSEC scratch register (0-3), Address offset: 0xE00-0xE0C */
__IO uint32_t LOCKR; /*!< BSEC lock register, Address offset: 0xE10 */
__IO uint32_t JTAGINR; /*!< BSEC JTAG input register, Address offset: 0xE14 */
__IO uint32_t JTAGOUTR; /*!< BSEC JTAG output register, Address offset: 0xE18 */
uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0xE1C-0xE20 */
__IO uint32_t UNMAPR; /*!< BSEC unmap register, Address offset: 0xE24 */
uint32_t RESERVED8[6]; /*!< Reserved, Address offset: 0xE28-0xE3C */
__IO uint32_t SR; /*!< BSEC status register, Address offset: 0xE40 */
__IO uint32_t OTPSR; /*!< BSEC OTP status register, Address offset: 0xE44 */
uint32_t RESERVED9[14]; /*!< Reserved, Address offset: 0xE48-0xE7C */
__IO uint32_t EPOCHRx[2]; /*!< BSEC epoch register (0-1), Address offset: 0xE80-0xE84 */
__IO uint32_t EPOCHSELR; /*!< BSEC epoch select register, Address offset: 0xE88 */
__IO uint32_t DBGCR; /*!< BSEC debug control register, Address offset: 0xE8C */
__IO uint32_t AP_UNLOCK; /*!< BSEC AP unlock, Address offset: 0xE90 */
__IO uint32_t HDPLSR; /*!< BSEC hide protection level status register, Address offset: 0xE94 */
__IO uint32_t HDPLCR; /*!< BSEC hide protection level control register, Address offset: 0xE98 */
__IO uint32_t NEXTLR; /*!< BSEC next hide protection level register, Address offset: 0xE9C */
uint32_t RESERVED10[40]; /*!< Reserved, Address offset: 0xEA0-0xF3C */
__IO uint32_t WOSCRx[8]; /*!< BSEC write once scratch register (0-7), Address offset: 0xF40-0xF5C */
uint32_t RESERVED11[34]; /*!< Reserved, Address offset: 0xF60-0xFE4 */
__IO uint32_t HRCR; /*!< BSEC hot reset count register, Address offset: 0xFE8 */
__IO uint32_t WRCR; /*!< BSEC warm reset count register, Address offset: 0xFEC */
} BSEC_TypeDef;
/**
* @brief Axi Cache
*/
typedef struct
{
__IO uint32_t CR1; /*!< CACHEAXI control register 1, Address offset: 0x00 */
__IO uint32_t SR; /*!< CACHEAXI status register, Address offset: 0x04 */
__IO uint32_t IER; /*!< CACHEAXI interrupt enable register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< CACHEAXI flag clear register, Address offset: 0x0C */
__IO uint32_t RHMONR; /*!< CACHEAXI read hit monitor register, Address offset: 0x10 */
__IO uint32_t RMMONR; /*!< CACHEAXI read miss monitor register, Address offset: 0x14 */
__IO uint32_t RAMMONR; /*!< CACHEAXI read-allocate miss monitor register, Address offset: 0x18 */
__IO uint32_t EVIMONR; /*!< CACHEAXI eviction monitor register, Address offset: 0x1C */
__IO uint32_t WHMONR; /*!< CACHEAXI write-hit monitor register, Address offset: 0x20 */
__IO uint32_t WMMONR; /*!< CACHEAXI write-miss monitor register, Address offset: 0x24 */
__IO uint32_t WAMMONR; /*!< CACHEAXI write-allocate miss monitor register, Address offset: 0x28 */
__IO uint32_t WTMONR; /*!< CACHEAXI write-through monitor register, Address offset: 0x2C */
uint32_t RESERVED1[52]; /*!< Reserved, Address offset: 0x30-0xFC */
__IO uint32_t CR2; /*!< CACHEAXI control register 2, Address offset: 0x100 */
__IO uint32_t CMDRSADDRR; /*!< CACHEAXI command start address register, Address offset: 0x104 */
__IO uint32_t CMDREADDRR; /*!< CACHEAXI command end address register, Address offset: 0x108 */
} CACHEAXI_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED1; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Cryp Processor
*/
typedef struct
{
__IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
__IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
__IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
__IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
__IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
__IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
__IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
__IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
__IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
__IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
__IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
__IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
__IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
__IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
__IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
__IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
__IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
__IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
__IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
__IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
__IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
__IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
__IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
__IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
__IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
__IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
__IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
__IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
__IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
__IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
__IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
__IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
__IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
__IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
__IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
} CRYP_TypeDef;
/*
* @brief (CSI)
*/
typedef struct
{
__IO uint32_t CR; /*!< CSI-2 Host control register Address offset: 0x0000 */
__IO uint32_t PCR; /*!< CSI-2 Host DPHY_RX control register Address offset: 0x0004 */
uint32_t RESERVED0[2]; /*!< Reserved Address offset: 0x0008-0x000C */
__IO uint32_t VC0CFGR1; /*!< CSI-2 Host virtual channel 0 configuration register 1 Address offset: 0x0010 */
__IO uint32_t VC0CFGR2; /*!< CSI-2 Host virtual channel 0 configuration register 2 Address offset: 0x0014 */
__IO uint32_t VC0CFGR3; /*!< CSI-2 Host virtual channel 0 configuration register 3 Address offset: 0x0018 */
__IO uint32_t VC0CFGR4; /*!< CSI-2 Host virtual channel 0 configuration register 4 Address offset: 0x001C */
__IO uint32_t VC1CFGR1; /*!< CSI-2 Host virtual channel 1 configuration register 1 Address offset: 0x0020 */
__IO uint32_t VC1CFGR2; /*!< CSI-2 Host virtual channel 1 configuration register 2 Address offset: 0x0024 */
__IO uint32_t VC1CFGR3; /*!< CSI-2 Host virtual channel 1 configuration register 3 Address offset: 0x0028 */
__IO uint32_t VC1CFGR4; /*!< CSI-2 Host virtual channel 1 configuration register 4 Address offset: 0x002C */
__IO uint32_t VC2CFGR1; /*!< CSI-2 Host virtual channel 2 configuration register 1 Address offset: 0x0030 */
__IO uint32_t VC2CFGR2; /*!< CSI-2 Host virtual channel 2 configuration register 2 Address offset: 0x0034 */
__IO uint32_t VC2CFGR3; /*!< CSI-2 Host virtual channel 2 configuration register 3 Address offset: 0x0038 */
__IO uint32_t VC2CFGR4; /*!< CSI-2 Host virtual channel 2 configuration register 4 Address offset: 0x003C */
__IO uint32_t VC3CFGR1; /*!< CSI-2 Host virtual channel 3 configuration register 1 Address offset: 0x0040 */
__IO uint32_t VC3CFGR2; /*!< CSI-2 Host virtual channel 3 configuration register 2 Address offset: 0x0044 */
__IO uint32_t VC3CFGR3; /*!< CSI-2 Host virtual channel 3 configuration register 3 Address offset: 0x0048 */
__IO uint32_t VC3CFGR4; /*!< CSI-2 Host virtual channel 3 configuration register 4 Address offset: 0x004C */
__IO uint32_t LB0CFGR; /*!< CSI-2 Host line byte 0 configuration register Address offset: 0x0050 */
__IO uint32_t LB1CFGR; /*!< CSI-2 Host line byte 1 configuration register Address offset: 0x0054 */
__IO uint32_t LB2CFGR; /*!< CSI-2 Host line byte 2 configuration register Address offset: 0x0058 */
__IO uint32_t LB3CFGR; /*!< CSI-2 Host line byte 3 configuration register Address offset: 0x005C */
__IO uint32_t TIM0CFGR; /*!< CSI-2 Host timer 0 configuration register Address offset: 0x0060 */
__IO uint32_t TIM1CFGR; /*!< CSI-2 Host timer 1 configuration register Address offset: 0x0064 */
__IO uint32_t TIM2CFGR; /*!< CSI-2 Host timer 2 configuration register Address offset: 0x0068 */
__IO uint32_t TIM3CFGR; /*!< CSI-2 Host timer 3 configuration register Address offset: 0x006C */
__IO uint32_t LMCFGR; /*!< CSI-2 Host lane merger configuration register Address offset: 0x0070 */
__IO uint32_t PRGITR; /*!< CSI-2 Host program interrupt register Address offset: 0x0074 */
__IO uint32_t WDR; /*!< CSI-2 Host watchdog register Address offset: 0x0078 */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x007C */
__IO uint32_t IER0; /*!< CSI-2 Host Interrupt enable register 0 Address offset: 0x0080 */
__IO uint32_t IER1; /*!< CSI-2 Host Interrupt enable register 1 Address offset: 0x0084 */
uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0088-0x008C */
__IO uint32_t SR0; /*!< CSI-2 Host status register 0 Address offset: 0x0090 */
__IO uint32_t SR1; /*!< CSI-2 Host status register 1 Address offset: 0x0094 */
uint32_t RESERVED3[26]; /*!< Reserved Address offset: 0x0098-0x00FC */
__IO uint32_t FCR0; /*!< CSI-2 Host Flag clear register 0 Address offset: 0x0100 */
__IO uint32_t FCR1; /*!< CSI-2 Host Flag clear register 1 Address offset: 0x0104 */
uint32_t RESERVED4[2]; /*!< Reserved Address offset: 0x0108-0x010C */
__IO uint32_t SPDFR; /*!< CSI-2 Host short packet data field register Address offset: 0x0110 */
__IO uint32_t ERR1; /*!< CSI-2 Host error register 1 Address offset: 0x0114 */
__IO uint32_t ERR2; /*!< CSI-2 Host error register 2 Address offset: 0x0118 */
uint32_t RESERVED5[953]; /*!< Reserved Address offset: 0x011C-0x0FFC */
__IO uint32_t PRCR; /*!< CSI PHY reset control register Address offset: 0x1000 */
__IO uint32_t PMCR; /*!< CSI PHY mode control register Address offset: 0x1004 */
__IO uint32_t PFCR; /*!< CSI PHY frequency control register Address offset: 0x1008 */
uint32_t RESERVED6; /*!< Reserved Address offset: 0x100C */
__IO uint32_t PTCR0; /*!< CSI PHY test control register 0 Address offset: 0x1010 */
__IO uint32_t PTCR1; /*!< CSI PHY test control register 1 Address offset: 0x1014 */
__IO uint32_t PTSR; /*!< CSI PHY test status register Address offset: 0x1018 */
uint32_t RESERVED7[1017]; /*!< Reserved Address offset: 0x101C-0x1FFC */
} CSI_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
__IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x10 */
__IO uint32_t APB1HFZ1; /*!< Debug MCU APB1HFZ1 freeze register, Address offset: 0x14 */
__IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x18 */
__IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x1C */
__IO uint32_t APB5FZ1; /*!< Debug MCU APB5FZ1 freeze register, Address offset: 0x20 */
__IO uint32_t AHB1FZ1; /*!< Debug MCU AHB1FZ1 freeze register, Address offset: 0x24 */
__IO uint32_t AHB5FZ1; /*!< Debug MCU AHB5FZ1 freeze register, Address offset: 0x28 */
uint32_t RESERVED2[52]; /*!< Reserved, Address offset: 0x2C-0xF8 */
__IO uint32_t SR; /*!< Debug MCU status register, Address offset: 0xFC */
__IO uint32_t DBG_AUTH_HOST; /*!< Debug MCU authentication host register, Address offset: 0x100 */
__IO uint32_t DBG_AUTH_DEV; /*!< Debug MCU authentication device register, Address offset: 0x104 */
__IO uint32_t DBG_AUTH_ACK; /*!< Debug MCU acknowledge authentication register, Address offset: 0x104 */
} DBGMCU_TypeDef;
/**
* @brief DCMI
*/
typedef struct
{
__IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
__IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
__IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
__IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
__IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
__IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
__IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
__IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
__IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
__IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
__IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
} DCMI_TypeDef;
#define DCMIPP_NUM_OF_PIPES 0x03U
typedef struct
{
uint32_t PxRIxCR1; /*! DCMIPP Pipex ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x400, (x = 1 to 2) */
uint32_t PxRIxCR2; /*! DCMIPP Pipex ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x400, (x = 1 to 2) */
} DCMIPP_Region_TypeDef;
/*
* @brief Digital camera interface pixel pipeline DCMIPP
*/
typedef struct
{
__IO uint32_t IPGR1; /*!< DCMIPP IPPLUG global register 1 Address offset: 0x000 */
__IO uint32_t IPGR2; /*!< DCMIPP IPPLUG global register 2 Address offset: 0x004 */
__IO uint32_t IPGR3; /*!< DCMIPP IPPLUG global register 3 Address offset: 0x008 */
uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x00C-0x018 */
__IO uint32_t IPGR8; /*!< DCMIPP IPPLUG identification register Address offset: 0x01C */
__IO uint32_t IPC1R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x020 + 0x10 * (x - 1), (x = 1 to 5) */
__IO uint32_t IPC1R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x024 + 0x10 * (x - 1), (x = 1 to 5) */
__IO uint32_t IPC1R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x028 + 0x10 * (x - 1), (x = 1 to 5) */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x02C */
__IO uint32_t IPC2R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x030 */
__IO uint32_t IPC2R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x034 */
__IO uint32_t IPC2R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x038 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x03C */
__IO uint32_t IPC3R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x040 */
__IO uint32_t IPC3R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x044 */
__IO uint32_t IPC3R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x04C */
__IO uint32_t IPC4R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x050 */
__IO uint32_t IPC4R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x054 */
__IO uint32_t IPC4R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x058 */
uint32_t RESERVED4; /*!< Reserved Address offset: 0x05C */
__IO uint32_t IPC5R1; /*!< DCMIPP IPPLUG Clientx register 1 Address offset: 0x060 */
__IO uint32_t IPC5R2; /*!< DCMIPP IPPLUG Clientx register 2 Address offset: 0x064 */
__IO uint32_t IPC5R3; /*!< DCMIPP IPPLUG Clientx register 3 Address offset: 0x068 */
uint32_t RESERVED5[38]; /*!< Reserved Address offset: 0x06C-0x100 */
__IO uint32_t PRCR; /*!< DCMIPP parallel interface control register Address offset: 0x104 */
__IO uint32_t PRESCR; /*!< DCMIPP parallel interface embedded synchronization code register Address offset: 0x108 */
__IO uint32_t PRESUR; /*!< DCMIPP parallel interface embedded synchronization unmask register Address offset: 0x10C */
uint32_t RESERVED6[57]; /*!< Reserved Address offset: 0x110-0x1F0 */
__IO uint32_t PRIER; /*!< DCMIPP parallel interface interrupt enable register Address offset: 0x1F4 */
__IO uint32_t PRSR; /*!< DCMIPP parallel interface status register Address offset: 0x1F8 */
__IO uint32_t PRFCR; /*!< DCMIPP parallel interface interrupt clear register Address offset: 0x1FC */
uint32_t RESERVED7; /*!< Reserved Address offset: 0x200 */
__IO uint32_t CMCR; /*!< DCMIPP common configuration register Address offset: 0x204 */
__IO uint32_t CMFRCR; /*!< DCMIPP common frame counter register Address offset: 0x208 */
uint32_t RESERVED8[121]; /*!< Reserved Address offset: 0x20C-0x3EC */
__IO uint32_t CMIER; /*!< DCMIPP common interrupt enable register Address offset: 0x3F0 */
__IO uint32_t CMSR1; /*!< DCMIPP common status register 1 Address offset: 0x3F4 */
__IO uint32_t CMSR2; /*!< DCMIPP common status register 2 Address offset: 0x3F8 */
__IO uint32_t CMFCR; /*!< DCMIPP common interrupt clear register Address offset: 0x3FC */
uint32_t RESERVED9; /*!< Reserved Address offset: 0x400 */
__IO uint32_t P0FSCR; /*!< DCMIPP Pipe0 flow selection configuration register Address offset: 0x404 */
uint32_t RESERVED10[62]; /*!< Reserved Address offset: 0x408-0x4FC */
__IO uint32_t P0FCTCR; /*!< DCMIPP Pipe0 flow control configuration register Address offset: 0x500 */
__IO uint32_t P0SCSTR; /*!< DCMIPP Pipe0 stat/crop start register Address offset: 0x504 */
__IO uint32_t P0SCSZR; /*!< DCMIPP Pipe0 stat/crop size register Address offset: 0x508 */
uint32_t RESERVED11[41]; /*!< Reserved Address offset: 0x50C-0x5AC */
__IO uint32_t P0DCCNTR; /*!< DCMIPP Pipe0 dump counter register Address offset: 0x5B0 */
__IO uint32_t P0DCLMTR; /*!< DCMIPP Pipe0 dump limit register Address offset: 0x5B4 */
uint32_t RESERVED12[2]; /*!< Reserved Address offset: 0x5B8-0x5BC */
__IO uint32_t P0PPCR; /*!< DCMIPP Pipe0 pixel packer configuration register Address offset: 0x5C0 */
__IO uint32_t P0PPM0AR1; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 1 Address offset: 0x5C4 */
__IO uint32_t P0PPM0AR2; /*!< DCMIPP Pipe0 pixel packer Memory0 address register 2 Address offset: 0x5C8 */
uint32_t RESERVED13; /*!< Reserved Address offset: 0x5C8-0x5CC */
__IO uint32_t P0STM0AR; /*!< DCMIPP Pipe0 status Memory0 address register Address offset: 0x5D0 */
uint32_t RESERVED14[8]; /*!< Reserved Address offset: 0x5D4-0x5F0 */
__IO uint32_t P0IER; /*!< DCMIPP Pipe0 interrupt enable register Address offset: 0x5F4 */
__IO uint32_t P0SR; /*!< DCMIPP Pipe0 status register Address offset: 0x5F8 */
__IO uint32_t P0FCR; /*!< DCMIPP Pipe0 interrupt clear register Address offset: 0x5FC */
uint32_t RESERVED15; /*!< Reserved Address offset: 0x600 */
__IO uint32_t P0CFSCR; /*!< DCMIPP Pipe0 current flow selection configuration register Address offset: 0x604 */
uint32_t RESERVED17[62]; /*!< Reserved Address offset: 0x608-0x6FC */
__IO uint32_t P0CFCTCR; /*!< DCMIPP Pipe0 current flow control configuration register Address offset: 0x700 */
__IO uint32_t P0CSCSTR; /*!< DCMIPP Pipe0 current stat/crop start register Address offset: 0x704 */
__IO uint32_t P0CSCSZR; /*!< DCMIPP Pipe0 current stat/crop size register Address offset: 0x708 */
uint32_t RESERVED18[45]; /*!< Reserved Address offset: 0x70C-0x7BC */
__IO uint32_t P0CPPCR; /*!< DCMIPP Pipe0 current pixel packer configuration register Address offset: 0x7C0 */
__IO uint32_t P0CPPM0AR1; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 1 Address offset: 0x7C4 */
__IO uint32_t P0CPPM0AR2; /*!< DCMIPP Pipe0 current pixel packer Memory0 address register 2 Address offset: */
uint32_t RESERVED19[14]; /*!< Reserved Address offset: 0x7C8-0x7FC */
__IO uint32_t P1FSCR; /*!< DCMIPP Pipe1 flow selection configuration register Address offset: 0x804 */
uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0x808-0x81C */
__IO uint32_t P1SRCR; /*!< DCMIPP Pipe1 stat removal configuration register Address offset: 0x820 */
__IO uint32_t P1BPRCR; /*!< DCMIPP Pipe1 bad pixel removal control register Address offset: 0x824 */
__IO uint32_t P1BPRSR; /*!< DCMIPP Pipe1 bad pixel removal status register Address offset: 0x828 */
uint32_t RESERVED21; /*!< Reserved Address offset: 0x82C */
__IO uint32_t P1DECR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x830 */
uint32_t RESERVED22[3]; /*!< Reserved Address offset: 0x834-0x83C */
__IO uint32_t P1BLCCR; /*!< DCMIPP Pipe1 black level calibration control register Address offset: 0x840 */
__IO uint32_t P1EXCR1; /*!< DCMIPP Pipe1 exposure control register 1 Address offset: 0x844 */
__IO uint32_t P1EXCR2; /*!< DCMIPP Pipe1 exposure control register 2 Address offset: 0x848 */
uint32_t RESERVED23; /*!< Reserved Address offset: 0x84C */
__IO uint32_t P1ST1CR; /*!< DCMIPP Pipe1 statistics 1 control register Address offset: 0x850 */
__IO uint32_t P1ST2CR; /*!< DCMIPP Pipe1 statistics 2 control register Address offset: 0x854 */
__IO uint32_t P1ST3CR; /*!< DCMIPP Pipe1 statistics 3 control register Address offset: 0x858 */
__IO uint32_t P1STSTR; /*!< DCMIPP Pipe1 statistics window start register Address offset: 0x85C */
__IO uint32_t P1STSZR; /*!< DCMIPP Pipe1 statistics window size register Address offset: 0x860 */
__IO uint32_t P1ST1SR; /*!< DCMIPP Pipe1 statistics 1 status register Address offset: 0x864 */
__IO uint32_t P1ST2SR; /*!< DCMIPP Pipe1 statistics 2 status register Address offset: 0x868 */
__IO uint32_t P1ST3SR; /*!< DCMIPP Pipe1 statistics 3 status register Address offset: 0x86C */
__IO uint32_t P1DMCR; /*!< DCMIPP Pipe1 demosaicing configuration register Address offset: 0x870 */
uint32_t RESERVED24[3]; /*!< Reserved Address offset: 0x874-0x87C */
__IO uint32_t P1CCCR; /*!< DCMIPP Pipe1 ColorConv configuration register Address offset: 0x880 */
__IO uint32_t P1CCRR1; /*!< DCMIPP Pipe1 ColorConv red coefficient register 1 Address offset: 0x884 */
__IO uint32_t P1CCRR2; /*!< DCMIPP Pipe1 ColorConv red coefficient register 2 Address offset: 0x888 */
__IO uint32_t P1CCGR1; /*!< DCMIPP Pipe1 ColorConv green coefficient register 1 Address offset: 0x88C */
__IO uint32_t P1CCGR2; /*!< DCMIPP Pipe1 ColorConv green coefficient register 2 Address offset: 0x890 */
__IO uint32_t P1CCBR1; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 1 Address offset: 0x894 */
__IO uint32_t P1CCBR2; /*!< DCMIPP Pipe1 ColorConv blue coefficient register 2 Address offset: 0x898 */
uint32_t RESERVED25; /*!< Reserved Address offset: 0x89C */
__IO uint32_t P1CTCR1; /*!< DCMIPP Pipe1 contrast control register 1 Address offset: 0x8A0 */
__IO uint32_t P1CTCR2; /*!< DCMIPP Pipe1 contrast control register 2 Address offset: 0x8A4 */
__IO uint32_t P1CTCR3; /*!< DCMIPP Pipe1 contrast control register 3 Address offset: 0x8A8 */
uint32_t RESERVED26[21]; /*!< Reserved Address offset: 0x8AC-0x8FC */
__IO uint32_t P1FCTCR; /*!< DCMIPP Pipe1 flow control configuration register Address offset: 0x900 */
__IO uint32_t P1CRSTR; /*!< DCMIPP Pipe1 crop window start register Address offset: 0x904 */
__IO uint32_t P1CRSZR; /*!< DCMIPP Pipe1 crop window size register Address offset: 0x908 */
__IO uint32_t P1DCCR; /*!< DCMIPP Pipe1 decimation register Address offset: 0x90C */
__IO uint32_t P1DSCR; /*!< DCMIPP Pipe1 downsize configuration register Address offset: 0x910 */
__IO uint32_t P1DSRTIOR; /*!< DCMIPP Pipe1 downsize ratio register Address offset: 0x914 */
__IO uint32_t P1DSSZR; /*!< DCMIPP Pipe1 downsize destination size register Address offset: 0x918 */
uint32_t RESERVED28; /*!< Reserved Address offset: */
__IO uint32_t P1CMRICR; /*!< DCMIPP Pipe1 common ROI configuration register Address offset: 0x920 */
__IO uint32_t P1RIxCR1; /*!< DCMIPP Pipe1 ROIx configuration register 1 Address offset: 0x924 + (x - 1) * 0x8, (x = 1 to 8) */
__IO uint32_t P1RIxCR2; /*!< DCMIPP Pipe1 ROIx configuration register 2 Address offset: 0x928 + (x - 1) * 0x8, (x = 1 to 8) */
uint32_t RESERVED29[17]; /*!< Reserved Address offset: */
__IO uint32_t P1GMCR; /*!< DCMIPP Pipe1 gamma configuration register Address offset: 0x970 */
uint32_t RESERVED30[3]; /*!< Reserved Address offset: 0x974-0x97C */
__IO uint32_t P1YUVCR; /*!< DCMIPP Pipe1 YUVConv configuration register Address offset: 0x980 */
__IO uint32_t P1YUVRR1; /*!< DCMIPP Pipe1 YUVConv red coefficient register 1 Address offset: 0x984 */
__IO uint32_t P1YUVRR2; /*!< DCMIPP Pipe1 YUVConv red coefficient register 2 Address offset: 0x988 */
__IO uint32_t P1YUVGR1; /*!< DCMIPP Pipe1 YUVConv green coefficient register 1 Address offset: 0x98C */
__IO uint32_t P1YUVGR2; /*!< DCMIPP Pipe1 YUVConv green coefficient register 2 Address offset: 0x990 */
__IO uint32_t P1YUVBR1; /*!< DCMIPP Pipe1 YUVConv blue coefficient register 1 Address offset: 0x994 */
__IO uint32_t P1YUVBR2; /*!< DCMIPP Pipe1 YUV blue coefficient register 2 Address offset: 0x998 */
uint32_t RESERVED31[9]; /*!< Reserved Address offset: 0x99C-0x9BC */
__IO uint32_t P1PPCR; /*!< DCMIPP Pipe1 pixel packer configuration register Address offset: 0x9C0 */
__IO uint32_t P1PPM0AR1; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 1 Address offset: 0x9C4 */
__IO uint32_t P1PPM0AR2; /*!< DCMIPP Pipe1 pixel packer Memory0 address register 2 Address offset: 0x9C8 */
__IO uint32_t P1PPM0PR; /*!< DCMIPP Pipe1 pixel packer Memory0 pitch register Address offset: 0x9CC */
__IO uint32_t P1STM0AR; /*!< DCMIPP Pipe1 status Memory0 address register Address offset: 0x9D0 */
__IO uint32_t P1PPM1AR1; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 1 Address offset: 0x9D4 */
__IO uint32_t P1PPM1AR2; /*!< DCMIPP Pipe1 pixel packer Memory1 address register 2 Address offset: 0x9D8 */
__IO uint32_t P1PPM1PR; /*!< DCMIPP Pipe1 pixel packer Memory1 pitch register Address offset: 0x9DC */
__IO uint32_t P1STM1AR; /*!< DCMIPP Pipe1 status Memory1 address register Address offset: 0x9E0 */
__IO uint32_t P1PPM2AR1; /*!< DCMIPP Pipe1 pixel packer memory2 address register 1 Address offset: 0x9E4 */
__IO uint32_t P1PPM2AR2; /*!< DCMIPP Pipe1 pixel packer memory2 address register 2 Address offset: 0x9E8 */
__IO uint32_t RESERVED34; /*!< Reserved Address offset: 0x9EC */
__IO uint32_t P1STM2AR; /*!< DCMIPP Pipe1 status Memory2 address register Address offset: 0x9F0 */
__IO uint32_t P1IER; /*!< DCMIPP Pipe1 interrupt enable register Address offset: 0x9F4 */
__IO uint32_t P1SR; /*!< DCMIPP Pipe1 status register Address offset: 0x9F8 */
__IO uint32_t P1FCR; /*!< DCMIPP Pipe1 interrupt clear register Address offset: 0x9FC */
uint32_t RESERVED35; /*!< Reserved Address offset: 0xA00 */
__IO uint32_t P1CFSCR; /*!< DCMIPP Pipe1 current flow selection configuration register Address offset: 0xA04 */
uint32_t RESERVED36[7]; /*!< Reserved Address offset: 0xA08-0xA20 */
__IO uint32_t P1CBPRCR; /*!< DCMIPP Pipe1 current bad pixel removal register Address offset: 0xA24 */
uint32_t RESERVED37[6]; /*!< Reserved Address offset: 0xA28-0xA3C */
__IO uint32_t P1CBLCCR; /*!< DCMIPP Pipe1 current black level calibration control register Address offset: 0xA40 */
__IO uint32_t P1CEXCR1; /*!< DCMIPP Pipe1 current exposure control register 1 Address offset: 0xA44 */
__IO uint32_t P1CEXCR2; /*!< DCMIPP Pipe1 current exposure control register 2 Address offset: 0xA48 */
uint32_t RESERVED38; /*!< Reserved Address offset: 0xA4C */
__IO uint32_t P1CST1CR; /*!< DCMIPP Pipe1 current statistics 1 control register Address offset: 0xA50 */
__IO uint32_t P1CST2CR; /*!< DCMIPP Pipe1 current statistics 2 control register Address offset: 0xA54 */
__IO uint32_t P1CST3CR; /*!< DCMIPP Pipe1 current statistics 3 control register Address offset: 0xA58 */
__IO uint32_t P1CSTSTR; /*!< DCMIPP Pipe1 current statistics window start register Address offset: 0xA5C */
__IO uint32_t P1CSTSZR; /*!< DCMIPP Pipe1 current statistics window size register Address offset: 0xA60 */
uint32_t RESERVED39[7]; /*!< Reserved Address offset: 0xA64-0xA7C */
__IO uint32_t P1CCCCR; /*!< DCMIPP Pipe1 current ColorConv configuration register Address offset: 0xA80 */
__IO uint32_t P1CCCRR1; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 1 Address offset: 0xA84 */
__IO uint32_t P1CCCRR2; /*!< DCMIPP Pipe1 current ColorConv red coefficient register 2 Address offset: 0xA88 */
__IO uint32_t P1CCCGR1; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 1 Address offset: 0xA8C */
__IO uint32_t P1CCCGR2; /*!< DCMIPP Pipe1 current ColorConv green coefficient register 2 Address offset: 0xA90 */
__IO uint32_t P1CCCBR1; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 1 Address offset: 0xA94 */
__IO uint32_t P1CCCBR2; /*!< DCMIPP Pipe1 current ColorConv blue coefficient register 2 Address offset: 0xA98 */
uint32_t RESERVED40; /*!< Reserved Address offset: 0xA9C */
__IO uint32_t P1CCTCR1; /*!< DCMIPP Pipe1 current contrast control register 1 Address offset: 0xAA0 */
__IO uint32_t P1CCTCR2; /*!< DCMIPP Pipe1 current contrast control register 2 Address offset: 0xAA4 */
__IO uint32_t P1CCTCR3; /*!< DCMIPP Pipe1 current contrast control register 3 Address offset: 0xAA8 */
uint32_t RESERVED41[21]; /*!< Reserved Address offset: 0xAAC-0xAFC */
__IO uint32_t P1CFCTCR; /*!< DCMIPP Pipe1 current flow control configuration register Address offset: 0xB00 */
__IO uint32_t P1CCRSTR; /*!< DCMIPP Pipe1 current crop window start register Address offset: 0xB04 */
__IO uint32_t P1CCRSZR; /*!< DCMIPP Pipe1 current crop window size register Address offset: 0xB08 */
__IO uint32_t P1CDCCR; /*!< DCMIPP Pipe1 current decimation register Address offset: 0xB0C */
__IO uint32_t P1CDSCR; /*!< DCMIPP Pipe1 current downsize configuration register Address offset: 0xB10 */
__IO uint32_t P1CDSRTIOR; /*!< DCMIPP Pipe1 current downsize ratio register Address offset: 0xB14 */
__IO uint32_t P1CDSSZR; /*!< DCMIPP Pipe1 current downsize destination size register Address offset: 0xB18 */
uint32_t RESERVED43; /*!< Reserved Address offset: 0xB1C */
uint32_t P1CCMRICR; /*!< DCMIPP Pipe1 current common ROI configuration register Address offset: 0xB20 */
__IO uint32_t P1CRIxCR1; /*!< DCMIPP Pipe1 current ROIx configuration register 1 Address offset: 0xB24 + 0x8 * (x - 1), (x = 1 to 8) */
__IO uint32_t P1CRIxCR2; /*!< DCMIPP Pipe1 current ROIx configuration register 2 Address offset: 0xB28 + 0x8 * (x - 1), (x = 1 to 8) */
uint32_t RESERVED44[37]; /*!< Reserved Address offset: 0xB64-0xBBC */
__IO uint32_t P1CPPCR; /*!< DCMIPP Pipe1 current pixel packer configuration register Address offset: 0xBC0 */
__IO uint32_t P1CPPM0AR1; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC4 */
__IO uint32_t P1CPPM0AR2; /*!< DCMIPP Pipe1 current pixel packer Memory0 address register 1 Address offset: 0xBC8 */
__IO uint32_t P1CPPM0PR; /*!< DCMIPP Pipe1 current pixel packer Memory0 pitch register Address offset: 0xBCC */
uint32_t RESERVED45; /*!< Reserved Address offset: 0xBD0 */
__IO uint32_t P1CPPM1AR1; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 1 Address offset: 0xBD4 */
__IO uint32_t P1CPPM1AR2; /*!< DCMIPP Pipe1 current pixel packer Memory1 address register 2 Address offset: 0xBD8 */
__IO uint32_t P1CPPM1PR; /*!< DCMIPP Pipe1 current pixel packer Memory1 pitch register Address offset: 0xBDC */
uint32_t RESERVED47; /*!< Reserved Address offset: 0xBE0 */
__IO uint32_t P1CPPM2AR1; /*!< DCMIPP Pipe1 current pixel packer memory2 address register 1 Address offset: 0xBE4 */
__IO uint32_t P1CPPM2AR2; /*!< DCMIPP Pipe1 current pixel packer Memory2 address register 2 Address offset: 0xBE8 */
uint32_t RESERVED48[6]; /*!< Reserved Address offset: 0xBE8-0xBFC */
__IO uint32_t P2FSCR; /*!< DCMIPP Pipe2 flow selection configuration register Address offset: 0xC04 */
uint32_t RESERVED49[62]; /*!< Reserved Address offset: 0xC08-0xCFC */
__IO uint32_t P2FCTCR; /*!< DCMIPP Pipe2 flow control configuration register Address offset: 0xD00 */
__IO uint32_t P2CRSTR; /*!< DCMIPP Pipe2 crop window start register Address offset: 0xD04 */
__IO uint32_t P2CRSZR; /*!< DCMIPP Pipe2 crop window size register Address offset: 0xD08 */
__IO uint32_t P2DCCR; /*!< DCMIPP Pipe2 decimation register Address offset: 0xD0C */
__IO uint32_t P2DSCR; /*!< DCMIPP Pipe2 downsize configuration register Address offset: 0xD10 */
__IO uint32_t P2DSRTIOR; /*!< DCMIPP Pipe2 downsize ratio register Address offset: 0xD14 */
__IO uint32_t P2DSSZR; /*!< DCMIPP Pipe2 downsize destination size register Address offset: 0xD18 */
uint32_t RESERVED51; /*!< Reserved Address offset: 0xD1C */
__IO uint32_t P2CMRICR; /*!< DCMIPP Pipe2 common ROI configuration register Address offset: 0xD20 */
__IO uint32_t P2RIxCR1; /*!< DCMIPP Pipe2 ROIx configuration register 1 Address offset: 0xD24 + (x - 1) * 0x8, (x = 1 to 8) */
__IO uint32_t P2RIxCR2; /*!< DCMIPP Pipe2 ROIx configuration register 2 Address offset: 0xD28 + (x - 1) * 0x8, (x = 1 to 8) */
uint32_t RESERVED53[17]; /*!< Reserved Address offset: */
__IO uint32_t P2GMCR; /*!< DCMIPP Pipe2 gamma configuration register Address offset: 0xD70 */
uint32_t RESERVED54[19]; /*!< Reserved Address offset: 0xD74-0xDBC */
__IO uint32_t P2PPCR; /*!< DCMIPP Pipe2 pixel packer configuration register Address offset: 0xDC0 */
__IO uint32_t P2PPM0AR1; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 1 Address offset: 0xDC4 */
__IO uint32_t P2PPM0AR2; /*!< DCMIPP Pipe2 pixel packer Memory0 address register 2 Address offset: 0xDC8 */
__IO uint32_t P2PPM0PR; /*!< DCMIPP Pipe2 pixel packer Memory0 pitch register Address offset: 0xDCC */
__IO uint32_t P2STM0AR; /*!< DCMIPP Pipe2 status Memory0 address register Address offset: 0xDD0 */
uint32_t RESERVED55[8]; /*!< Reserved Address offset: 0xDD4-0xDF0 */
__IO uint32_t P2IER; /*!< DCMIPP Pipe2 interrupt enable register Address offset: 0xDF4 */
__IO uint32_t P2SR; /*!< DCMIPP Pipe2 status register Address offset: 0xDF8 */
__IO uint32_t P2FCR; /*!< DCMIPP Pipe2 interrupt clear register Address offset: 0xDFC */
uint32_t RESERVED56; /*!< Reserved Address offset: 0xE00 */
__IO uint32_t P2CFSCR; /*!< DCMIPP Pipe2 current flow selection configuration register Address offset: 0xE04 */
uint32_t RESERVED57[62]; /*!< Reserved Address offset: 0xE08-0xEFC */
__IO uint32_t P2CFCTCR; /*!< DCMIPP Pipe2 current flow control configuration register Address offset: 0xF00 */
__IO uint32_t P2CCRSTR; /*!< DCMIPP Pipe2 current crop window start register Address offset: 0xF04 */
__IO uint32_t P2CCRSZR; /*!< DCMIPP Pipe2 current crop window size register Address offset: 0xF08 */
__IO uint32_t P2CDCCR; /*!< DCMIPP Pipe2 current decimation register Address offset: 0xF0C */
__IO uint32_t P2CDSCR; /*!< DCMIPP Pipe2 current downsize configuration register Address offset: 0xF10 */
__IO uint32_t P2CDSRTIOR; /*!< DCMIPP Pipe2 current downsize ratio register Address offset: 0xF14 */
__IO uint32_t P2CDSSZR; /*!< DCMIPP Pipe2 current downsize destination size register Address offset: 0xF18 */
__IO uint32_t RESERVED59[2]; /*!< Reserved Address offset: 0xF1C-0xF20 */
__IO uint32_t P2CRIxCR1; /*!< Pipe2 current ROIx configuration register 1 Address offset: 0xF24 + (x - 1) * 0x8, (x = 1 to 8)*/
__IO uint32_t P2CRIxCR2; /*!< Pipe2 current ROIx configuration register 2 Address offset: 0xF28 + (x - 1) * 0x8, (x = 1 to 8)*/
uint32_t RESERVED60[37]; /*!< Reserved Address offset: 0xF64-0xFBC */
__IO uint32_t P2CPPCR; /*!< DCMIPP Pipe2 current pixel packer configuration register Address offset: 0xFC0 */
__IO uint32_t P2CPPM0AR1; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 1 Address offset: 0xFC4 */
__IO uint32_t P2CPPM0AR2; /*!< DCMIPP Pipe2 current pixel packer Memory0 address register 2 Address offset: 0xFC8 */
__IO uint32_t P2CPPM0PR; /*!< DCMIPP Pipe2 current pixel packer Memory0 pitch register Address offset: 0xFCC */
uint32_t RESERVED61[7]; /*!< Reserved Address offset: 0xFD0-0xFE8 */
__IO uint32_t HWCFGR2; /*!< DCMIPP hardware configuration register 2 Address offset: 0xFEC */
__IO uint32_t HWCFGR1; /*!< DCMIPP hardware configuration register 1 Address offset: 0xFF0 */
__IO uint32_t VERR; /*!< DCMIPP version register Address offset: 0xFF4 */
__IO uint32_t IPIDR; /*!< DCMIPP identification register Address offset: 0xFF8 */
__IO uint32_t SIDR; /*!< DCMIPP size identification register Address offset: 0xFFC */
} DCMIPP_TypeDef;
/**
* @ brief Delay Block
*/
typedef struct
{
__IO uint32_t CR; /*!< Delay Block Control Register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< Delay Block Configuration Register, Address offset: 0x04 */
} DLYB_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */
__IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */
__IO uint32_t RCFGLOCKR; /*!< DMA configuration lock register, Address offset: 0x08 */
__IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */
__IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */
} DMA_TypeDef;
typedef struct
{
__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */
__IO uint32_t CCIDCFGR; /*!< DMA channel x CID register, Address offset: 0x54 + (x * 0x80) */
uint32_t RESERVED1[1]; /*!< Reserved 1, Address offset: 0x58 + (x * 0x80) */
__IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */
__IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */
__IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */
uint32_t RESERVED2[10]; /*!< Reserved 2, Address offset: 0x68 -- 0x8C + (x * 0x80) */
__IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */
__IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */
__IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */
__IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */
__IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */
__IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */
__IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */
uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 + (x * 0x80) */
__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */
} DMA_Channel_TypeDef;
/**
* @brief DMA2D Controller
*/
typedef struct
{
__IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
__IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
__IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
__IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
__IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
__IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
__IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
__IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
__IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
__IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
__IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
__IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
__IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
__IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
__IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
__IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
__IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
} DMA2D_TypeDef;
/**
* @brief DTS Controller
*/
typedef struct
{
uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x00-0x0F */
__IO uint32_t PVTREG_LOCKR; /*!< DTS PVT Register Lock Register, Address offset: 0x10 */
__IO uint32_t PVTLOCK_SR; /*!< DTS PVT Lock Status Register, Address offset: 0x14 */
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1F */
__IO uint32_t PVTTMR_CR; /*!< DTS PVT Timer Control Register, Address offset: 0x20 */
__IO uint32_t PVTTMR_SR; /*!< DTS PVT Timer Status Register, Address offset: 0x24 */
uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x28-0x3F */
__IO uint32_t PVT_IER; /*!< DTS PVT IRQ Enable Register, Address offset: 0x40 */
uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4F */
__IO uint32_t PVTIRQTRMASKR; /*!< DTS PVT IRQ Timer Mask Register, Address offset: 0x50 */
__IO uint32_t TS_MR; /*!< DTS PVT IRQ TS Mask Register, Address offset: 0x54 */
uint32_t RESERVED5[2]; /*!< Reserved, Address offset: 0x58-0x5F */
__IO uint32_t PVTTR_SR; /*!< DTS PVT IRQ Timer Status Register, Address offset: 0x60 */
__IO uint32_t TS_ISR; /*!< DTS PVT IRQ TS Status Register, Address offset: 0x64 */
uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x68-0x6F */
__IO uint32_t PVTTMRRAW_ISR; /*!< DTS PVT IRQ Timer Raw Status Register, Address offset: 0x70 */
__IO uint32_t TSRAW_ISR; /*!< DTS PVT IRQ TS Raw Status Register, Address offset: 0x74 */
uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x78-0x7F */
__IO uint32_t TSCCLKSYNTHR; /*!< DTS TSC Clock Synthesizer Register, Address offset: 0x80 */
__IO uint32_t TSCSDIFDISABLER; /*!< DTS TSC SDIF Interface Disable Register, Address offset: 0x84 */
__IO uint32_t TSCSDIF_SR; /*!< DTS TSC SDIF Status Register, Address offset: 0x88 */
__IO uint32_t TSCSDIF_CR; /*!< DTS TSC SDIF Register, Address offset: 0x8C */
__IO uint32_t TSCSDIFHALTR; /*!< DTS TSC SDIF Halt Register, Address offset: 0x90 */
__IO uint32_t TSCSDIF_CFGR; /*!< DTS TSC SDIF Control Register, Address offset: 0x94 */
uint32_t RESERVED8[2]; /*!< Reserved, Address offset: 0x98-0x9F */
__IO uint32_t TSCSMPL_CR; /*!< DTS TSC Sample Control Register, Address offset: 0xA0 */
__IO uint32_t TSCSDIFSMPLCLRR; /*!< DTS TSC Sample Clear Register, Address offset: 0xA4 */
__IO uint32_t TSCSMPLCNTR; /*!< DTS TSC Sample Count Register, Address offset: 0xA8 */
} DTS_TypeDef;
/**
* @brief DTS Sensor Controller
*/
typedef struct
{
__IO uint32_t TS_IER; /*!< DTS TSx IRQ Enable Register, Address offset: 0xC0 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TS_ISR; /*!< DTS TSx IRQ Status Register, Address offset: 0xC4 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TS_ICR; /*!< DTS TSx IRQ Clear Register, Address offset: 0xC8 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSIRQTESTR; /*!< DTS TSx IRQ Test Register, Address offset: 0xCC + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSSDIFRDATAR; /*!< DTS TSx SDIF RDATA Register, Address offset: 0xD0 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSSDIFDONER; /*!< DTS TSx SDIF Done Register, Address offset: 0xD4 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSSDIFDATAR; /*!< DTS TSx SDIF Data Register, Address offset: 0xD8 + 0x40 * x, (x = 0 to 1) */
uint32_t RESERVED1[1]; /*!< Reserved, Address offset: 0xDC + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSALARMA_CFGR; /*!< DTS TSx Alarm A Configuration Register, Address offset: 0xE0 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSALARMB_CFGR; /*!< DTS TSx Alarm B Configuration Register, Address offset: 0xE4 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSHLSAMPLER; /*!< DTS TSx High/Low Sample Register, Address offset: 0xE8 + 0x40 * x, (x = 0 to 1) */
__IO uint32_t TSHILORESETR; /*!< DTS TSx High/Low Reset Register, Address offset: 0xEC + 0x40 * x, (x = 0 to 1) */
} DTS_SensorTypeDef;
/**
* @brief Ethernet MAC
*/
typedef struct
{
__IO uint32_t MACCR; /*!< Operating mode configuration register, Address offset: 0x00 */
__IO uint32_t MACECR; /*!< Extended operating mode configuration register, Address offset: 0x04 */
__IO uint32_t MACPFR; /*!< Packet filtering control register , Address offset: 0x08 */
__IO uint32_t MACWTR; /*!< Watchdog timeout register, Address offset: 0x0C */
__IO uint32_t MACHT0R; /*!< Hash Table 0 register, Address offset: 0x10 */
__IO uint32_t MACHT1R; /*!< Hash Table 1 register, Address offset: 0x14 */
uint32_t RESERVED1[14];
__IO uint32_t MACVTCR; /*!< VLAN tag Control register, Address offset: 0x50 */
__IO uint32_t MACVTDR; /*!< VLAN tag data register, Address offset: 0x54 */
__IO uint32_t MACVHTR; /*!< VLAN Hash table register, Address offset: 0x58 */
uint32_t RESERVED2;
__IO uint32_t MACVIR; /*!< VLAN inclusion register, Address offset: 0x60 */
__IO uint32_t MACIVIR; /*!< Inner VLAN inclusion register, Address offset: 0x64 */
uint32_t RESERVED3[2];
__IO uint32_t MACQ0TXFCR; /*!< Tx Queue 0 flow control register, Address offset: 0x70 */
uint32_t RESERVED4[7];
__IO uint32_t MACRXFCR; /*!< Rx flow control register, Address offset: 0x90 */
__IO uint32_t MACRXQCR; /*!< Rx Queue control register, Address offset: 0x94 */
uint32_t RESERVED5[2];
__IO uint32_t MACRXQC0R; /*!< Rx queue control 0 register, Address offset: 0xA0 */
__IO uint32_t MACRXQC1R; /*!< Rx queue control 1 register, Address offset: 0xA4 */
__IO uint32_t MACRXQC2R; /*!< Rx queue control 2 register, Address offset: 0xA8 */
uint32_t RESERVED6;
__IO uint32_t MACISR; /*!< Interrupt status register, Address offset: 0xB0 */
__IO uint32_t MACIER; /*!< Interrupt enable register, Address offset: 0xB4 */
__IO uint32_t MACRXTXSR; /*!< Rx Tx status register, Address offset: 0xB8 */
uint32_t RESERVED7;
__IO uint32_t MACPCSR; /*!< PMT control status register, Address offset: 0xC0 */
__IO uint32_t MACRWKPFR; /*!< Remote wakeup packet filter register, Address offset: 0xC4 */
uint32_t RESERVED8[2];
__IO uint32_t MACLCSR; /*!< LPI control and status register, Address offset: 0xD0 */
__IO uint32_t MACLTCR; /*!< LPI timers control register, Address offset: 0xD4 */
__IO uint32_t MACLETR; /*!< LPI entry timer register, Address offset: 0xD8 */
__IO uint32_t MAC1USTCR; /*!< One-microsecond-tick counter register, Address offset: 0xDC */
uint32_t RESERVED9[6];
__IO uint32_t MACPHYCSR; /*!< PHYIF control status register, Address offset: 0xF8 */
uint32_t RESERVED10[5];
__IO uint32_t MACVR; /*!< Version register, Address offset: 0x110 */
__IO uint32_t MACDR; /*!< Debug register, Address offset: 0x114 */
uint32_t RESERVED11;
__IO uint32_t MACHWF0R; /*!< HW feature 0 register, Address offset: 0x11C */
__IO uint32_t MACHWF1R; /*!< HW feature 1 register, Address offset: 0x120 */
__IO uint32_t MACHWF2R; /*!< HW feature 2 register, Address offset: 0x124 */
__IO uint32_t MACHWF3R; /*!< HW feature 3 register, Address offset: 0x128 */
uint32_t RESERVED12[53];
__IO uint32_t MACMDIOAR; /*!< MDIO address register, Address offset: 0x200 */
__IO uint32_t MACMDIODR; /*!< MDIO data register, Address offset: 0x204 */
uint32_t RESERVED13[2];
__IO uint32_t MACARPAR; /*!< ARP address register, Address offset: 0x210 */
uint32_t RESERVED14[7];
__IO uint32_t MACCSRSWCR; /*!< CSR software control register, Address offset: 0x230 */
__IO uint32_t MACFPECSR; /*!< FPE control and status register, Address offset: 0x234 */
uint32_t RESERVED15[2];
__IO uint32_t MACPRSTIMR; /*!< MAC presentation time register, Address offset: 0x0240 */
__IO uint32_t MACPRSTIMUR; /*!< MAC presentation time update register, Address offset: 0x0244 */
uint32_t RESERVED16[46];
__IO uint32_t MACA0HR; /*!< MAC Address 0 high register, Address offset: 0x0300 */
__IO uint32_t MACA0LR; /*!< MAC Address 0 low register, Address offset: 0x0304 */
__IO uint32_t MACA1HR; /*!< MAC Address 1 high register, Address offset: 0x0308 */
__IO uint32_t MACA1LR; /*!< MAC Address 1 low register, Address offset: 0x030C */
__IO uint32_t MACA2HR; /*!< MAC Address 2 high register, Address offset: 0x0310 */
__IO uint32_t MACA2LR; /*!< MAC Address 2 low register, Address offset: 0x0314 */
__IO uint32_t MACA3HR; /*!< MAC Address 3 high register, Address offset: 0x0318 */
__IO uint32_t MACA3LR; /*!< MAC Address 3 low register, Address offset: 0x031C */
uint32_t RESERVED17[248];
__IO uint32_t MMCCR; /*!< MMC control register, Address offset: 0x0700 */
__IO uint32_t MMCRIR; /*!< MMC Rx interrupt register, Address offset: 0x0704 */
__IO uint32_t MMCTIR; /*!< MMC Tx interrupt register, Address offset: 0x0708 */
__IO uint32_t MMCRIMR; /*!< MMC Rx interrupt mask register, Address offset: 0x070C */
__IO uint32_t MMCTIMR; /*!< MMC Tx interrupt mask register, Address offset: 0x0710 */
uint32_t RESERVED18[14];
__IO uint32_t MMCTSCGPR; /*!< Tx single collision good packets register, Address offset: 0x074C */
__IO uint32_t MMCTMCGPR; /*!< Tx multiple collision good packets register, Address offset: 0x0750 */
uint32_t RESERVED19[5];
__IO uint32_t MMCTPCGR; /*!< Tx packet count good register, Address offset: 0x0768 */
uint32_t RESERVED20[10];
__IO uint32_t MMCRCRCEPR; /*!< Rx CRC error packets register, Address offset: 0x0794 */
__IO uint32_t MMCRAEPR; /*!< Rx alignment error packets register, Address offset: 0x0798 */
uint32_t RESERVED21[10];
__IO uint32_t MMCRUPGR; /*!< Rx unicast packets good register, Address offset: 0x07C4 */
uint32_t RESERVED22[9];
__IO uint32_t MMCTLPIMSTR; /*!< Tx LPI microsecond timer register, Address offset: 0x07EC */
__IO uint32_t MMCTLPITCR; /*!< Tx LPI transition counter register, Address offset: 0x07F0 */
__IO uint32_t MMCRLPIMSTR; /*!< Rx LPI microsecond counter register, Address offset: 0x07F4 */
__IO uint32_t MMCRLPITCR; /*!< Rx LPI transition counter register, Address offset: 0x07F8 */
uint32_t RESERVED23[41];
__IO uint32_t MMCFPETISR; /*!< MMC FPE Tx interrupt status register, Address offset: 0x08A0 */
__IO uint32_t MMCFPETIMR; /*!< MMC FPE Tx interrupt mask register, Address offset: 0x08A4 */
__IO uint32_t MMCFPETFCR; /*!< MMC FPE Tx fragment counter register, - Address offset: 0x08A8 */
__IO uint32_t MMCTHRCR; /*!< MMC Tx hold request counter register, Address offset: 0x08AC */
uint32_t RESERVED24[4];
__IO uint32_t MMCFPERISR; /*!< MMC FPE Rx interrupt status register, Address offset: 0x08C0 */
__IO uint32_t MMCFPERIMR; /*!< MMC FPE Rx interrupt mask register, Address offset: 0x08C4 */
__IO uint32_t MMCRPAER; /*!< MMC Rx packet assembly error register, Address offset: 0x08C8 */
__IO uint32_t MMCRPSMDER; /*!< MMC Rx packet SMD error register, Address offset: 0x08CC */
__IO uint32_t MMCRPAOKR; /*!< MMC Rx packet assembly OK register, Address offset: 0x08D0 */
__IO uint32_t MMCFPERFCR; /*!< MMC Rx FPE fragments counter register, Address offset: 0x08D4 */
uint32_t RESERVED25[10];
__IO uint32_t MACL3L4C0R; /*!< L3 and L4 control 0 register, Address offset: 0x0900 */
__IO uint32_t MACL4A0R; /*!< Layer4 Address filter 0 register, Address offset: 0x0904 */
uint32_t RESERVED26[2];
__IO uint32_t MACL3A0R0R; /*!< Layer3 Address 0 filter 0 register, Address offset: 0x0910 */
__IO uint32_t MACL3A1R0R; /*!< Layer3 Address 1 filter 0 register, Address offset: 0x0914 */
__IO uint32_t MACL3A2R0R; /*!< Layer3 Address 2 filter 0 register, Address offset: 0x0918 */
__IO uint32_t MACL3A3R0R; /*!< Layer3 Address 3 filter 0 register, Address offset: 0x091C */
uint32_t RESERVED27[4];
__IO uint32_t MACL3L4C1R; /*!< L3 and L4 control 1 register, Address offset: 0x0930 */
__IO uint32_t MACL4A1R; /*!< Layer 4 address filter 1 register, Address offset: 0x0934 */
uint32_t RESERVED28[2];
__IO uint32_t MACL3A01R; /*!< Layer3 address 0 filter 1 Register, Address offset: 0x0940 */
__IO uint32_t MACL3A11R; /*!< Layer3 address 1 filter 1 register, Address offset: 0x0944 */
__IO uint32_t MACL3A21R; /*!< Layer3 address 2 filter 1 Register, Address offset: 0x0948 */
__IO uint32_t MACL3A31R; /*!< Layer3 address 3 filter 1 register, Address offset: 0x094C */
uint32_t RESERVED29[72];
__IO uint32_t MACIACR; /*!< MAC Indirect Access Control register, Address offset: 0x0A70 */
__IO uint32_t MACTMRQR; /*!< MAC type-based Rx Queue mapping register, Address offset: 0x0A74 */
uint32_t RESERVED30[34];
__IO uint32_t MACTSCR; /*!< Timestamp control Register, Address offset: 0x0B00 */
__IO uint32_t MACSSIR; /*!< Subsecond increment register, Address offset: 0x0B04 */
__IO uint32_t MACSTSR; /*!< System time seconds register, Address offset: 0x0B08 */
__IO uint32_t MACSTNR; /*!< System time nanoseconds register, Address offset: 0x0B0C */
__IO uint32_t MACSTSUR; /*!< System time seconds update register, Address offset: 0x0B10 */
__IO uint32_t MACSTNUR; /*!< System time nanoseconds update register, Address offset: 0x0B14 */
__IO uint32_t MACTSAR; /*!< Timestamp addend register, Address offset: 0x0B18 */
uint32_t RESERVED31;
__IO uint32_t MACTSSR; /*!< Timestamp status register, Address offset: 0x0B20 */
uint32_t RESERVED32[3];
__IO uint32_t MACTXTSSNR; /*!< Tx timestamp status nanoseconds register, Address offset: 0x0B30 */
__IO uint32_t MACTXTSSSR; /*!< Tx timestamp status seconds register, Address offset: 0x0B34 */
uint32_t RESERVED33[2];
__IO uint32_t MACACR; /*!< Auxiliary control register, Address offset: 0x0B40 */
uint32_t RESERVED34;
__IO uint32_t MACATSNR; /*!< Auxiliary timestamp nanoseconds register, Address offset: 0x0B48 */
__IO uint32_t MACATSSR; /*!< Auxiliary timestamp seconds register, Address offset: 0x0B4C */
__IO uint32_t MACTSIACR; /*!< Timestamp Ingress asymmetric correction register, Address offset: 0x0B50 */
__IO uint32_t MACTSEACR; /*!< Timestamp Egress asymmetric correction register, Address offset: 0x0B54 */
__IO uint32_t MACTSICNR; /*!< Timestamp Ingress correction nanosecond register, Address offset: 0x0B58 */
__IO uint32_t MACTSECNR; /*!< Timestamp Egress correction nanosecond register, Address offset: 0x0B5C */
uint32_t RESERVED35[2];
__IO uint32_t MACTSILR; /*!< Timestamp Ingress Latency register, Address offset: 0x0B68 */
__IO uint32_t MACTSELR; /*!< Timestamp Egress Latency register, Address offset: 0x0B6C */
__IO uint32_t MACPPSCR; /*!< PPS control register, Address offset: 0x0B70 */
uint32_t RESERVED36[3];
__IO uint32_t MACPPSTTS0R; /*!< PPS 0 target time seconds register, Address offset: 0x0B80 */
__IO uint32_t MACPPSTTN0R; /*!< PPS 0 target time nanoseconds register, Address offset: 0x0B84 */
__IO uint32_t MACPPSI0R; /*!< PPS 0 interval register, Address offset: 0x0B88 */
__IO uint32_t MACPPSW0R; /*!< PPS 0 width register, Address offset: 0x0B8C */
__IO uint32_t MACPPSTTS1R; /*!< PPS 1 target time seconds register, Address offset: 0x0B90 */
__IO uint32_t MACPPSTTN1R; /*!< PPS 1 target time nanoseconds register, Address offset: 0x0B94 */
__IO uint32_t MACPPSI1R; /*!< PPS 1 interval register, Address offset: 0x0B98 */
__IO uint32_t MACPPSW1R; /*!< PPS 1 width register, Address offset: 0x0B9C */
uint32_t RESERVED37[8];
__IO uint32_t MACPOCR; /*!< PTP Offload control register, Address offset: 0x0BC0 */
__IO uint32_t MACSPI0R; /*!< PTP Source Port Identity 0 Register, Address offset: 0x0BC4 */
__IO uint32_t MACSPI1R; /*!< PTP Source port identity 1 register, Address offset: 0x0BC8 */
__IO uint32_t MACSPI2R; /*!< PTP Source port identity 2 register, Address offset: 0x0BCC */
__IO uint32_t MACLMIR; /*!< Log message interval register, Address offset: 0x0BD0 */
uint32_t RESERVED38[11];
__IO uint32_t MTLOMR; /*!< Operating mode Register, Address offset: 0x0C00 */
uint32_t RESERVED39[7];
__IO uint32_t MTLISR; /*!< Interrupt status Register, Address offset: 0x0C20 */
uint32_t RESERVED40[3];
__IO uint32_t MTLRXQDMAMR; /*!< Rx Queue and DMA Channel Mapping Register, Address offset: 0x0C30 */
uint32_t RESERVED41[3];
__IO uint32_t MTLTBSCR; /*!< TBS control register, Address offset: 0x0C40 */
uint32_t RESERVED42[3];
__IO uint32_t MTLESTCR; /*!< EST Control Register, Address offset: 0x0C50 */
__IO uint32_t MTLESTECR; /*!< EST Extended Control Register, Address offset: 0x0C54 */
__IO uint32_t MTLESTSR; /*!< EST Status Register, Address offset: 0x0C58 */
uint32_t RESERVED43;
__IO uint32_t MTLESTSCHER; /*!< EST Schedule Error Register, Address offset: 0x0C60 */
__IO uint32_t MTLESTFSER; /*!< EST Frame size Error Register, Address offset: 0x0C64 */
__IO uint32_t MTLESTFSCR; /*!< EST Frame size Capture Register, Address offset: 0x0C68 */
uint32_t RESERVED44;
__IO uint32_t MTLESTIER; /*!< EST Interrupt Enable Register, Address offset: 0x0C70 */
uint32_t RESERVED45[3];
__IO uint32_t MTLESTGCLCR; /*!< EST Gate Control List Register, Address offset: 0x0C80 */
__IO uint32_t MTLESTGCLDR; /*!< EST Gate Control List Data Register, Address offset: 0x0C84 */
uint32_t RESERVED46[2];
__IO uint32_t MTLFPECSR; /*!< FPE Frame Preemption Control Status Register, Address offset: 0x0C90 */
__IO uint32_t MTLFPEAR; /*!< FPE Frame Preemption Advance Register, Address offset: 0x0C94 */
uint32_t RESERVED47[26];
struct {
__IO uint32_t MTLTXQOMR; /*!< Tx queue x operating mode Register, Address offset: 0x0D00 */
__IO uint32_t MTLTXQUR; /*!< Tx queue x underflow register, Address offset: 0x0D04 */
__IO uint32_t MTLTXQDR; /*!< Tx queue x debug register, Address offset: 0x0D08 */
uint32_t RESERVED48[1];
__IO uint32_t MTLTXQ1ECR; /*!< Tx queue 1 ETS control Register, Address offset: 0x0D50 */
__IO uint32_t MTLTXQESR; /*!< Tx queue x ETS status Register, Address offset: 0x0D14 */
__IO uint32_t MTLTXQQWR; /*!< Tx queue x quantum weight register, Address offset: 0x0D18 */
__IO uint32_t MTLTXQ1SSCR; /*!< Tx queue 1 send slope credit Register, Address offset: 0x0D5C */
__IO uint32_t MTLTXQ1HCR; /*!< Tx Queue 1 hiCredit register, Address offset: 0x0D60 */
__IO uint32_t MTLTXQ1LCR; /*!< Tx queue 1 loCredit register, Address offset: 0x0D64 */
uint32_t RESERVED49[1];
__IO uint32_t MTLQICSR; /*!< Queue 0 interrupt control status Register, Address offset: 0x0D2C */
__IO uint32_t MTLRXQOMR; /*!< Rx queue x operating mode register, Address offset: 0x0D30 */
__IO uint32_t MTLRXQMPOCR; /*!< Rx queue x missed packet and overflow counter register, Address offset: 0x0D34 */
__IO uint32_t MTLRXQDR; /*!< Rx queue x debug register, Address offset: 0x0D38 */
__IO uint32_t MTLRXQCR; /*!< Rx queue x control register, Address offset: 0x0D3C */
} MTL_QUEUE[2];
uint32_t RESERVED52[160];
__IO uint32_t DMAMR; /*!< DMA mode register, Address offset: 0x1000 */
__IO uint32_t DMASBMR; /*!< System bus mode register, Address offset: 0x1004 */
__IO uint32_t DMAISR; /*!< Interrupt status register, Address offset: 0x1008 */
__IO uint32_t DMADSR; /*!< Debug status register, Address offset: 0x100C */
uint32_t RESERVED53[4];
__IO uint32_t DMAA4TXACR; /*!< AXI4 transmit channel ACE control register, Address offset: 0x1020 */
__IO uint32_t DMAA4RXACR; /*!< AXI4 receive channel ACE control register, Address offset: 0x1024 */
__IO uint32_t DMAA4DACR; /*!< AXI4 descriptor ACE control register, Address offset: 0x1028 */
uint32_t RESERVED54[5];
__IO uint32_t DMALPIEI; /*!< AXI4 LPI Entry Interval register, Address offset: 0x1040 */
uint32_t RESERVED55[3];
__IO uint32_t DMATBSCTRL0R; /*!< DMA TBS control register 0, Address offset: 0x1050 */
uint32_t RESERVED56[37];
struct {
uint32_t RESERVED57[6];
__IO uint32_t DMACCR; /*!< Channel x control register, Address offset: 0x1100 */
__IO uint32_t DMACTXCR; /*!< Channel x transmit control register, Address offset: 0x1104 */
__IO uint32_t DMACRXCR; /*!< Channel x receive control register, Address offset: 0x1108 */
uint32_t RESERVED58[2];
__IO uint32_t DMACTXDLAR; /*!< Channel x Tx descriptor list address register, Address offset: 0x1114 */
uint32_t RESERVED59;
__IO uint32_t DMACRXDLAR; /*!< Channel x Rx descriptor list address register, Address offset: 0x111C */
__IO uint32_t DMACTXDTPR; /*!< Channel x Tx descriptor tail pointer register, Address offset: 0x1120 */
uint32_t RESERVED60;
__IO uint32_t DMACRXDTPR; /*!< Channel x Rx descriptor tail pointer register, Address offset: 0x1128 */
__IO uint32_t DMACTXRLR; /*!< Channel x Tx descriptor ring length register, Address offset: 0x112C */
__IO uint32_t DMACRXRLR; /*!< Channel x Rx descriptor ring length register, Address offset: 0x1130 */
__IO uint32_t DMACIER; /*!< Channel x interrupt enable register, Address offset: 0x1134 */
__IO uint32_t DMACRXIWTR; /*!< Channel x Rx interrupt watchdog timer register, Address offset: 0x1138 */
__IO uint32_t DMACSFCSR; /*!< Channel x slot function control status register, Address offset: 0x113C */
uint32_t RESERVED61;
__IO uint32_t DMACCATXDR; /*!< Channel x current application transmit descriptor register, Address offset: 0x1144 */
uint32_t RESERVED62;
__IO uint32_t DMACCARXDR; /*!< Channel x current application receive descriptor register, Address offset: 0x114C */
uint32_t RESERVED63;
__IO uint32_t DMACCATXBR; /*!< Channel x current application transmit buffer register, Address offset: 0x1154 */
uint32_t RESERVED64;
__IO uint32_t DMACCARXBR; /*!< Channel x current application receive buffer register, Address offset: 0x115C */
__IO uint32_t DMACSR; /*!< Channel x status register, Address offset: 0x1160 */
__IO uint32_t DMACMFCR; /*!< Channel x missed frame count register, Address offset: 0x1164 */
} DMA_CH[2];
}ETH_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
__IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
__IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
__IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
__IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
__IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */
__IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */
__IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */
__IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */
__IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */
__IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */
__IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */
__IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */
__IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x3C */
__IO uint32_t RTSR3; /*!< EXTI Rising Trigger Selection Register 3, Address offset: 0x40 */
__IO uint32_t FTSR3; /*!< EXTI Falling Trigger Selection Register 3, Address offset: 0x44 */
__IO uint32_t SWIER3; /*!< EXTI Software Interrupt event Register 3, Address offset: 0x48 */
__IO uint32_t RPR3; /*!< EXTI Rising Pending Register 3, Address offset: 0x4C */
__IO uint32_t FPR3; /*!< EXTI Falling Pending Register 3, Address offset: 0x50 */
__IO uint32_t SECCFGR3; /*!< EXTI Security Configuration Register 3, Address offset: 0x54 */
__IO uint32_t PRIVCFGR3; /*!< EXTI Privilege Configuration Register 3, Address offset: 0x58 */
uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x5C */
__IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
__IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */
uint32_t RESERVED4[3]; /*!< Reserved 4, 0x74 -- 0x7C */
__IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
__IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
uint32_t RESERVED5[2]; /*!< Reserved 5, 0x88 -- 0x8C */
__IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */
__IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */
uint32_t RESERVED6[2]; /*!< Reserved 6, 0x98 -- 0x9C */
__IO uint32_t IMR3; /*!< EXTI Interrupt Mask Register 3, Address offset: 0xA0 */
__IO uint32_t EMR3; /*!< EXTI Event Mask Register 3, Address offset: 0xA4 */
} EXTI_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
__IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
__IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
__IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
__IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
__IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
__IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
__IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
__IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
__IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
__IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
__IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
__IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
__IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
__IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
__IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
} FDCAN_GlobalTypeDef;
/**
* @brief TTFD Controller Area Network
*/
typedef struct
{
__IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
__IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
__IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
__IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
__IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
__IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
__IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
__IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
__IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
__IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
__IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
__IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
__IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
__IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
__IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
__IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
__IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
__IO uint32_t RESERVED1[111];/*!< Reserved, 0x144 - 0x2FC */
__IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
} TTCAN_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
__IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
__IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
__IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
__IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
__IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
} FDCAN_ClockCalibrationUnit_TypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
__IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */
uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
__IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */
__IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */
__IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */
__IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */
} FDCAN_Config_TypeDef;
/**
* @brief Flexible Memory Controller Bank1
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank2
*/
typedef struct
{
__IO uint32_t SDCR[2]; /*!< SDRAM device 1/2 control register Address offset: 0x140-0x144 */
__IO uint32_t SDTR; /*!< SDRAM timing register Address offset: 0x148 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x14C */
__IO uint32_t SDCMR; /*!< SDRAM command mode register Address offset: 0x150 */
__IO uint32_t SDRTR; /*!< SDRAM refresh timer register Address offset: 0x154 */
__IO uint32_t SDSR; /*!< SDRAM status register Address offset: 0x158 */
} FMC_Bank5_6_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash Programmable control register Address offset: 0x080 */
__IO uint32_t SR; /*!< FMC status register Address offset: 0x084 */
__IO uint32_t PMEM; /*!< Common memory space timing register Address offset: 0x088 */
__IO uint32_t PATT; /*!< Attribute memory space timing registers Address offset: 0x08C */
__IO uint32_t HPR; /*!< FMC Hamming parity result registers Address offset: 0x090 */
__IO uint32_t HECCR; /*!< FMC Hamming code ECC result register Address offset: 0x094 */
uint32_t RESERVED0[58]; /*!< Reserved Address offset: 0x098-0x17C */
__IO uint32_t IER; /*!< FMC NAND Interrupt Enable Register Address offset: 0x180 */
__IO uint32_t ISR; /*!< FMC Controller Interrupt Status Register Address offset: 0x184 */
__IO uint32_t ICR; /*!< FMC NAND Controller Interrupt Clear Register Address offset: 0x188 */
uint32_t RESERVED1[29]; /*!< Reserved Address offset: 0x18C-0x1FC */
__IO uint32_t CSQCR; /*!< FMC NAND Command Sequencer Control Register Address offset: 0x200 */
__IO uint32_t CSQCFGR1; /*!< FMC NAND Command Sequencer Configuration Register 1 Address offset: 0x204 */
__IO uint32_t CSQCFGR2; /*!< FMC NAND Command Sequencer Configuration Register 2 Address offset: 0x208 */
__IO uint32_t CSQCFGR3; /*!< FMC NAND sequencer configuration register 3 Address offset: 0x20C */
__IO uint32_t CSQAR1; /*!< FMC NAND Command Sequencer Address Register 1 Address offset: 0x210 */
__IO uint32_t CSQAR2; /*!< FMC NAND Command Sequencer Address Register 2 Address offset: 0x214 */
uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x218-0x21C */
__IO uint32_t CSQIER; /*!< FMC NAND Command Sequencer Interrupt Enable Register Address offset: 0x220 */
__IO uint32_t CSQISR; /*!< FMC NAND Command Sequencer Interrupt Status Register Address offset: 0x224 */
__IO uint32_t CSQICR; /*!< FMC NAND Command Sequencer Interrupt Clear Register Address offset: 0x228 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x22C */
__IO uint32_t CSQEMSR; /*!< FMC Command Sequencer Error Mapping Status register Address offset: 0x230 */
uint32_t RESERVED4[7]; /*!< Reserved Address offset: 0x234-0x24C */
__IO uint32_t BCHIER; /*!< FMC BCH Interrupt enable register Address offset: 0x250 */
__IO uint32_t BCHISR; /*!< FMC BCH Interrupt and Status Register Address offset: 0x254 */
__IO uint32_t BCHICR; /*!< FMC BCH Interrupt Clear Register Address offset: 0x258 */
uint32_t RESERVED5; /*!< Reserved Address offset: 0x25C */
__IO uint32_t BCHPBR1; /*!< FMC BCH Parity Bits Register 1 Address offset: 0x260 */
__IO uint32_t BCHPBR2; /*!< FMC BCH Parity Bits Register 2 Address offset: 0x264 */
__IO uint32_t BCHPBR3; /*!< FMC BCH Parity Bits Register 3 Address offset: 0x268 */
__IO uint32_t BCHPBR4; /*!< FMC BCH Parity Bits Register 4 Address offset: 0x26C */
uint32_t RESERVED6[3]; /*!< Reserved Address offset: 0x270-0x278 */
__IO uint32_t BCHDSR0; /*!< FMC BCH Decoder Status register 0 Address offset: 0x27C */
__IO uint32_t BCHDSR1; /*!< FMC BCH Decoder Status register for bank 1 Address offset: 0x280 */
__IO uint32_t BCHDSR2; /*!< FMC BCH Decoder Status register for bank 2 Address offset: 0x284 */
__IO uint32_t BCHDSR3; /*!< FMC BCH Decoder Status register for bank 3 Address offset: 0x288 */
__IO uint32_t BCHDSR4; /*!< FMC BCH Decoder Status register for bank 4 Address offset: 0x28C */
} FMC_Bank3_TypeDef;
/**
* @brief Flexible Memory Controller Common
*/
typedef struct{
__IO uint32_t CFGR; /*!< FMC common configuration register Address offset: 0x020 */
} FMC_Common_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x2C */
__IO uint32_t SECCFGR; /*!< GPIO port secure configuration register, Address offset: 0x30 */
__IO uint32_t PRIVCFGR; /*!< GPIO port privileged configuration register, Address offset: 0x34 */
__IO uint32_t RCFGLOCKR; /*!< GPIO port resource configuration register, Address offset: 0x38 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */
__IO uint32_t DELAYR[2]; /*!< GPIO port delay register, Address offset: 0x40-0x44 */
__IO uint32_t ADVCFGR[2]; /*!< GPIO port advanced configuration register, Address offset: 0x48-0x4C */
} GPIO_TypeDef;
/**
* @brief GFXMMU
*/
typedef struct
{
__IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */
__IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */
__IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved0, Address offset: 0x0C */
__IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */
__IO uint32_t DAR; /*!< GFXMMU default alpha register, Address offset: 0x14 */
uint32_t RESERVED1[2]; /*!< Reserved1, Address offset: 0x18 to 0x1C */
__IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */
__IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
__IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
__IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
uint32_t RESERVED2[1012]; /*!< Reserved2, Address offset: 0x30 to 0xFFC */
__IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
} GFXMMU_TypeDef;
/**
* @brief GFXTIM
*/
typedef struct
{
__IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */
__IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */
__IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */
__IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */
__IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */
__IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
__IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */
uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */
__IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */
__IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */
__IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */
__IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */
__IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */
__IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */
uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */
__IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */
__IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */
__IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */
uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */
__IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */
uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */
__IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */
__IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */
uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */
__IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */
__IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */
__IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */
__IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */
__IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */
__IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */
__IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */
uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */
__IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */
__IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */
__IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */
__IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */
} GFXTIM_TypeDef;
/**
* @brief HASH
*/
typedef struct
{
__IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
__IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
__IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
__IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
__IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
__IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */
} HASH_TypeDef;
/**
* @brief HASH_DIGEST
*/
typedef struct
{
__IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */
} HASH_DIGEST_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Improved Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
__IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */
__IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */
__IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */
__IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */
__IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */
__IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */
__IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */
__IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */
uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */
__IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */
uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */
__IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */
__IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */
__IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */
__IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */
__IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */
uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */
__IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */
__IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */
uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */
__IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */
__IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */
__IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */
uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */
__IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */
__IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */
__IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */
__IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */
__IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */
__IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */
} I3C_TypeDef;
/**
* @brief Illegal Access Controller
*/
typedef struct
{
__IO uint32_t IER[5]; /*!< Interrupt Enable register, Address offset: 0x000 */
uint32_t RESERVED1[27]; /*!< Reserved, Address offset: 0x014-0x07C */
__IO uint32_t ISR[5]; /*!< Interrupt Status register, Address offset: 0x080 */
uint32_t RESERVED2[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
__IO uint32_t ICR[5]; /*!< Interrupt Clear register, Address offset: 0x100 */
} IAC_TypeDef;
/**
* @brief Instruction Cache
*/
typedef struct
{
__IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */
__IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< ICACHE flag clear register, Address offset: 0x0C */
__IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */
__IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */
} ICACHE_TypeDef;
typedef struct
{
__IO uint32_t KR; /*!< IWDG key register Address offset: 0x000 */
__IO uint32_t PR; /*!< IWDG prescaler register Address offset: 0x004 */
__IO uint32_t RLR; /*!< IWDG reload register Address offset: 0x008 */
__IO uint32_t SR; /*!< IWDG status register Address offset: 0x00C */
__IO uint32_t WINR; /*!< IWDG window register Address offset: 0x010 */
__IO uint32_t EWCR; /*!< IWDG early wakeup interrupt register Address offset: 0x014 */
__IO uint32_t ICR; /*!< IWDG interrupt clear register Address offset: 0x018 */
} IWDG_TypeDef;
/**
* @brief JPEG Codec
*/
typedef struct
{
__IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
__IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
__IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
__IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
__IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
__IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
__IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
__IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
__IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
__IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
__IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
__IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
__IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
__IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
__IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
__IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
__IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
__IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
__IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
__IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
__IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
__IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
__IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
__IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
__IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
} JPEG_TypeDef;
/**
* @brief LCD-TFT Display Controller (LTDC)
*/
typedef struct
{
__IO uint32_t IDR; /*!< LTDC identification register Address offset: 0x0 */
__IO uint32_t LCR; /*!< LDTC layer count register Address offset: 0x4 */
__IO uint32_t SSCR; /*!< LTDC synchronization size configuration register Address offset: 0x8 */
__IO uint32_t BPCR; /*!< LTDC back porch configuration register Address offset: 0xc */
__IO uint32_t AWCR; /*!< LTDC active width configuration register Address offset: 0x10 */
__IO uint32_t TWCR; /*!< LTDC total width configuration register Address offset: 0x14 */
__IO uint32_t GCR; /*!< LTDC global control register Address offset: 0x18 */
__IO uint32_t GC1R; /*!< LTDC global configuration 1 register Address offset: 0x1c */
__IO uint32_t GC2R; /*!< LTDC global configuration 2 register Address offset: 0x20 */
__IO uint32_t SRCR; /*!< LTDC shadow reload configuration register Address offset: 0x24 */
__IO uint32_t GCCR; /*!< LTDC gamma correction configuration register Address offset: 0x28 */
__IO uint32_t BCCR; /*!< LTDC background color configuration register Address offset: 0x2c */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x30 */
__IO uint32_t IER; /*!< LTDC interrupt enable register Address offset: 0x34 */
__IO uint32_t ISR; /*!< LTDC interrupt status register Address offset: 0x38 */
__IO uint32_t ICR; /*!< LTDC Interrupt Clear Register Address offset: 0x3c */
__IO uint32_t LIPCR; /*!< LTDC line interrupt position configuration register Address offset: 0x40 */
__IO uint32_t CPSR; /*!< LTDC current position status register Address offset: 0x44 */
__IO uint32_t CDSR; /*!< LTDC current display status register Address offset: 0x48 */
uint32_t RESERVED1[5]; /*!< Reserved Address offset: 0x4c */
__IO uint32_t EDCR; /*!< LTDC external display control register Address offset: 0x60 */
__IO uint32_t IER2; /*!< LTDC interrupt enable register 2 Address offset: 0x64 */
__IO uint32_t ISR2; /*!< LTDC interrupt status register 2 Address offset: 0x68 */
__IO uint32_t ICR2; /*!< LTDC Interrupt Clear Register 2 Address offset: 0x6c */
__IO uint32_t LIPCR2; /*!< LTDC line interrupt position configuration register 2 Address offset: 0x70 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x74 */
__IO uint32_t ECRCR; /*!< LTDC expected CRC register Address offset: 0x78 */
__IO uint32_t CCRCR; /*!< LTDC computed CRC register Address offset: 0x7c */
__IO uint32_t RB0AR; /*!< LTDC rotation buffer 0 address register Address offset: 0x80 */
__IO uint32_t RB1AR; /*!< LTDC rotation buffer 1 address register Address offset: 0x84 */
__IO uint32_t RBPR; /*!< LTDC rotation buffer pitch register Address offset: 0x88 */
__IO uint32_t RIFCR; /*!< LTDC rotation intermediate frame color register Address offset: 0x8c */
__IO uint32_t FUTR; /*!< LTDC FIFO underrun threshold register Address offset: 0x90 */
} LTDC_TypeDef;
/**
* @brief LCD-TFT Display layer x Controller (LTDC)
*/
typedef struct
{
__IO uint32_t C0R; /*!< LTDC layer x configuration 0 register Address offset: 0x100 */
__IO uint32_t C1R; /*!< LTDC layer x configuration 1 register Address offset: 0x104 */
__IO uint32_t RCR; /*!< LTDC layer x reload control register Address offset: 0x108 */
__IO uint32_t CR; /*!< LTDC layer x control register Address offset: 0x10c */
__IO uint32_t WHPCR; /*!< LTDC layer x window horizontal position configuration register Address offset: 0x110 */
__IO uint32_t WVPCR; /*!< LTDC layer x window vertical position configuration register Address offset: 0x114 */
__IO uint32_t CKCR; /*!< LTDC layer x color keying configuration register Address offset: 0x118 */
__IO uint32_t PFCR; /*!< LTDC layer x pixel format configuration register Address offset: 0x11c */
__IO uint32_t CACR; /*!< LTDC layer x constant alpha configuration register Address offset: 0x120 */
__IO uint32_t DCCR; /*!< LTDC layer x default color configuration register Address offset: 0x124 */
__IO uint32_t BFCR; /*!< LTDC layer x blending factors configuration register Address offset: 0x128 */
__IO uint32_t BLCR; /*!< LTDC layer x burst length configuration register Address offset: 0x12c */
__IO uint32_t PCR; /*!< LTDC layer x planar configuration register Address offset: 0x130 */
__IO uint32_t CFBAR; /*!< LTDC layer x color frame buffer address register Address offset: 0x134 */
__IO uint32_t CFBLR; /*!< LTDC layer x color frame buffer length register Address offset: 0x138 */
__IO uint32_t CFBLNR; /*!< LTDC layer x color frame buffer line number register Address offset: 0x13c */
__IO uint32_t AFBA0R; /*!< LTDC layer x auxiliary frame buffer address 0 register Address offset: 0x140 */
__IO uint32_t AFBA1R; /*!< LTDC layer x auxiliary frame buffer address 1 register Address offset: 0x144 */
__IO uint32_t AFBLR; /*!< LTDC layer x auxiliary frame buffer length register Address offset: 0x148 */
__IO uint32_t AFBLNR; /*!< LTDC layer x auxiliary frame buffer line number register Address offset: 0x14c */
__IO uint32_t CLUTWR; /*!< LTDC layer x CLUT write register Address offset: 0x150 */
__IO uint32_t SISR; /*!< LTDC layer x Scaler Input Size register Address offset: 0x154 */
__IO uint32_t SOSR; /*!< LTDC layer x Scaler Output Size register Address offset: 0x158 */
__IO uint32_t SVSFR; /*!< LTDC layer x Scaler Vertical Scaling Factor register Address offset: 0x15c */
__IO uint32_t SVSPR; /*!< LTDC layer x Scaler Vertical Scaling Phase register Address offset: 0x160 */
__IO uint32_t SHSFR; /*!< LTDC layer x Scaler Horizontal Scaling Factor register Address offset: 0x164 */
__IO uint32_t SHSPR; /*!< LTDC layer x Scaler Horizontal Scaling Phase register Address offset: 0x168 */
__IO uint32_t CYR0R; /*!< LTDC layer x Conversion YCbCr RGB 0 register Address offset: 0x16c */
__IO uint32_t CYR1R; /*!< LTDC layer x Conversion YCbCr RGB 1 register Address offset: 0x170 */
__IO uint32_t FPF0R; /*!< LTDC layer x Flexible Pixel Format 0 register Address offset: 0x174 */
__IO uint32_t FPF1R; /*!< LTDC layer x Flexible Pixel Format 1 register Address offset: 0x178 */
} LTDC_Layer_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */
__IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */
__IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */
__IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */
__IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x30 */
__IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */
} LPTIM_TypeDef;
/**
* @brief Memory Cipher Engine (MCE)
*/
typedef struct
{
__IO uint32_t REGCR; /*!< MCE region configuration register, Address offset: 0x040 + 0x10 * (x-1) (x = 1 to 4) */
__IO uint32_t SADDR; /*!< MCE region start address register, Address offset: 0x044 + 0x10 * (x-1) (x = 1 to 4) */
__IO uint32_t EADDR; /*!< MCE region end address register, Address offset: 0x048 + 0x10 * (x-1) (x = 1 to 4) */
} MCE_Region_TypeDef;
typedef struct
{
__IO uint32_t CCCFGR; /*!< MCE cipher context configuration register, Address offset: 0x240 + 0x30 * (x-1) (x = 1 to 2) */
__IO uint32_t CCNR0; /*!< MCE cipher context nonce register 0, Address offset: 0x244 + 0x30 * (x-1) (x = 1 to 2) */
__IO uint32_t CCNR1; /*!< MCE cipher context nonce register 1, Address offset: 0x248 + 0x30 * (x-1) (x = 1 to 2) */
__IO uint32_t CCKEYR0; /*!< MCE cipher context key register 0, Address offset: 0x24C + 0x30 * (x-1) (x = 1 to 2) */
__IO uint32_t CCKEYR1; /*!< MCE cipher context key register 1, Address offset: 0x250 + 0x30 * (x-1) (x = 1 to 2) */
__IO uint32_t CCKEYR2; /*!< MCE cipher context key register 2, Address offset: 0x254 + 0x30 * (x-1) (x = 1 to 2) */
__IO uint32_t CCKEYR3; /*!< MCE cipher context key register 3, Address offset: 0x258 + 0x30 * (x-1) (x = 1 to 2) */
} MCE_Context_TypeDef;
typedef struct
{
__IO uint32_t CR; /*!< MCE configuration register, Address offset: 0x000 */
__IO uint32_t SR; /*!< MCE status register, Address offset: 0x004 */
__IO uint32_t IASR; /*!< MCE illegal access status register, Address offset: 0x008 */
__IO uint32_t IACR; /*!< MCE illegal access clear register, Address offset: 0x00C */
__IO uint32_t IAIER; /*!< MCE illegal access interrupt enable register, Address offset: 0x010 */
uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x014-0x20 */
__IO uint32_t IADDR; /*!< MCE illegal address register, Address offset: 0x024 */
uint32_t RESERVED1[118]; /*!< Reserved, Address offset: 0x028-0x1FC */
__IO uint32_t MKEYR0; /*!< MCE master key register 0, Address offset: 0x200 */
__IO uint32_t MKEYR1; /*!< MCE master key register 1, Address offset: 0x204 */
__IO uint32_t MKEYR2; /*!< MCE master key register 2, Address offset: 0x208 */
__IO uint32_t MKEYR3; /*!< MCE master key register 3, Address offset: 0x20C */
__IO uint32_t MKEYR4; /*!< MCE master key register 4, Address offset: 0x210 */
__IO uint32_t MKEYR5; /*!< MCE master key register 5, Address offset: 0x214 */
__IO uint32_t MKEYR6; /*!< MCE master key register 6, Address offset: 0x218 */
__IO uint32_t MKEYR7; /*!< MCE master key register 7, Address offset: 0x21C */
__IO uint32_t FMKEYR0; /*!< MCE fast master key register 0, Address offset: 0x220 */
__IO uint32_t FMKEYR1; /*!< MCE fast master key register 1, Address offset: 0x224 */
__IO uint32_t FMKEYR2; /*!< MCE fast master key register 2, Address offset: 0x228 */
__IO uint32_t FMKEYR3; /*!< MCE fast master key register 3, Address offset: 0x22C */
__IO uint32_t FMKEYR4; /*!< MCE fast master key register 4, Address offset: 0x230 */
__IO uint32_t FMKEYR5; /*!< MCE fast master key register 5, Address offset: 0x234 */
__IO uint32_t FMKEYR6; /*!< MCE fast master key register 6, Address offset: 0x238 */
__IO uint32_t FMKEYR7; /*!< MCE fast master key register 7, Address offset: 0x23C */
} MCE_TypeDef;
/**
* @brief ADF
*/
typedef struct
{
__IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */
__IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */
uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */
__IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */
} MDF_TypeDef;
/**
* @brief ADF filter
*/
typedef struct
{
__IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */
__IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */
__IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */
__IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */
__IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */
__IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */
__IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */
__IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */
__IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */
__IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */
__IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */
__IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */
__IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */
__IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */
__IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */
__IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */
__IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */
__IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */
uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */
__IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */
__IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */
} MDF_Filter_TypeDef;
/**
* @brief MDIOS
*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t WRFR;
__IO uint32_t CWRFR;
__IO uint32_t RDFR;
__IO uint32_t CRDFR;
__IO uint32_t SR;
__IO uint32_t CLRFR;
uint32_t RESERVED[57];
__IO uint32_t DINR0;
__IO uint32_t DINR1;
__IO uint32_t DINR2;
__IO uint32_t DINR3;
__IO uint32_t DINR4;
__IO uint32_t DINR5;
__IO uint32_t DINR6;
__IO uint32_t DINR7;
__IO uint32_t DINR8;
__IO uint32_t DINR9;
__IO uint32_t DINR10;
__IO uint32_t DINR11;
__IO uint32_t DINR12;
__IO uint32_t DINR13;
__IO uint32_t DINR14;
__IO uint32_t DINR15;
__IO uint32_t DINR16;
__IO uint32_t DINR17;
__IO uint32_t DINR18;
__IO uint32_t DINR19;
__IO uint32_t DINR20;
__IO uint32_t DINR21;
__IO uint32_t DINR22;
__IO uint32_t DINR23;
__IO uint32_t DINR24;
__IO uint32_t DINR25;
__IO uint32_t DINR26;
__IO uint32_t DINR27;
__IO uint32_t DINR28;
__IO uint32_t DINR29;
__IO uint32_t DINR30;
__IO uint32_t DINR31;
__IO uint32_t DOUTR0;
__IO uint32_t DOUTR1;
__IO uint32_t DOUTR2;
__IO uint32_t DOUTR3;
__IO uint32_t DOUTR4;
__IO uint32_t DOUTR5;
__IO uint32_t DOUTR6;
__IO uint32_t DOUTR7;
__IO uint32_t DOUTR8;
__IO uint32_t DOUTR9;
__IO uint32_t DOUTR10;
__IO uint32_t DOUTR11;
__IO uint32_t DOUTR12;
__IO uint32_t DOUTR13;
__IO uint32_t DOUTR14;
__IO uint32_t DOUTR15;
__IO uint32_t DOUTR16;
__IO uint32_t DOUTR17;
__IO uint32_t DOUTR18;
__IO uint32_t DOUTR19;
__IO uint32_t DOUTR20;
__IO uint32_t DOUTR21;
__IO uint32_t DOUTR22;
__IO uint32_t DOUTR23;
__IO uint32_t DOUTR24;
__IO uint32_t DOUTR25;
__IO uint32_t DOUTR26;
__IO uint32_t DOUTR27;
__IO uint32_t DOUTR28;
__IO uint32_t DOUTR29;
__IO uint32_t DOUTR30;
__IO uint32_t DOUTR31;
} MDIOS_TypeDef;
/**
* @brief PSSI
*/
typedef struct
{
__IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */
__IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */
__IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */
__IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */
__IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */
__IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */
__IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
__IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */
} PSSI_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR Control register 1 Address offset: 0x000 */
__IO uint32_t CR2; /*!< PWR Control Register 2 Address offset: 0x004 */
__IO uint32_t CR3; /*!< PWR Control Register 3 Address offset: 0x008 */
__IO uint32_t CR4; /*!< PWR Control Register 4 Address offset: 0x00C */
uint32_t RESERVED0[4]; /*!< Reserved Address offset: 0x010-0x01C */
__IO uint32_t VOSCR; /*!< PWR Voltage scaling control register Address offset: 0x020 */
__IO uint32_t BDCR1; /*!< PWR Backup domain control register 1 Address offset: 0x024 */
__IO uint32_t BDCR2; /*!< PWR Backup domain control register 2 Address offset: 0x028 */
__IO uint32_t DBPCR; /*!< PWR Disable backup protection control register Address offset: 0x02C */
__IO uint32_t CPUCR; /*!< PWR CPU control register Address offset: 0x030 */
__IO uint32_t SVMCR1; /*!< PWR Supply voltage monitoring control register 1 Address offset: 0x034 */
__IO uint32_t SVMCR2; /*!< PWR Supply voltage monitoring control register 2 Address offset: 0x038 */
__IO uint32_t SVMCR3; /*!< PWR Supply voltage monitoring control register 3 Address offset: 0x03C */
uint32_t RESERVED1[4]; /*!< Reserved Address offset: 0x040-0x04C */
__IO uint32_t WKUPCR; /*!< PWR Wakeup control register 1 Address offset: 0x050 */
__IO uint32_t WKUPSR; /*!< PWR Wakeup control register 2 Address offset: 0x054 */
__IO uint32_t WKUPEPR; /*!< PWR Wakeup control register 3 Address offset: 0x058 */
uint32_t RESERVED2[5]; /*!< Reserved Address offset: 0x05C-0x06C */
__IO uint32_t SECCFGR; /*!< PWR Security configuration register Address offset: 0x070 */
__IO uint32_t PRIVCFGR; /*!< PWR Privilege configuration register Address offset: 0x074 */
} PWR_TypeDef;
/**
* @brief PKA
*/
typedef struct
{
__IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */
__IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */
uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */
__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */
} PKA_TypeDef;
/**
* @brief RAMs configuration controller
*/
typedef struct
{
__IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */
__IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */
__IO uint32_t ESEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */
__IO uint32_t EDEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */
__IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */
uint32_t RESERVED[3]; /*!< Reserved, Address offset: 0x18-0x20 */
__IO uint32_t ECCKEYR; /*!< RAM ECC Key Register, Address offset: 0x24 */
__IO uint32_t ERKEYR; /*!< RAM Erase Key Register, Address offset: 0x28 */
}RAMCFG_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC control register Address offset: 0x0000 */
__IO uint32_t SR; /*!< RCC status register Address offset: 0x0004 */
__IO uint32_t STOPCR; /*!< RCC Stop mode control register Address offset: 0x0008 */
uint32_t RESERVED0[5]; /*!< Reserved Address offset: 0x000C-0x001C */
__IO uint32_t CFGR1; /*!< RCC configuration register 1 Address offset: 0x0020 */
__IO uint32_t CFGR2; /*!< RCC configuration register 2 Address offset: 0x0024 */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x0028 */
__IO uint32_t BDCR; /*!< RCC backup domain protection register Address offset: 0x002C */
__IO uint32_t HWRSR; /*!< RCC reset status register for hardware Address offset: 0x0030 */
__IO uint32_t RSR; /*!< RCC reset register Address offset: 0x0034 */
uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x0038-0x003C */
__IO uint32_t LSECFGR; /*!< RCC LSE configuration register Address offset: 0x0040 */
__IO uint32_t MSICFGR; /*!< RCC MSI configuration register Address offset: 0x0044 */
__IO uint32_t HSICFGR; /*!< RCC HSI configuration register Address offset: 0x0048 */
__IO uint32_t HSIMCR; /*!< RCC HSI Monitor control register Address offset: 0x004C */
__IO uint32_t HSIMSR; /*!< RCC HSI Monitor status register Address offset: 0x0050 */
__IO uint32_t HSECFGR; /*!< RCC HSE configuration register Address offset: 0x0054 */
uint32_t RESERVED3[10]; /*!< Reserved Address offset: 0x0058-0x007C */
__IO uint32_t PLL1CFGR1; /*!< RCC PLL1 configuration register 1 Address offset: 0x0080 */
__IO uint32_t PLL1CFGR2; /*!< RCC PLL1 configuration register 2 Address offset: 0x0084 */
__IO uint32_t PLL1CFGR3; /*!< RCC PLL1 configuration register 3 Address offset: 0x0088 */
uint32_t RESERVED4; /*!< Reserved Address offset: 0x008C */
__IO uint32_t PLL2CFGR1; /*!< RCC PLL2 configuration register 1 Address offset: 0x0090 */
__IO uint32_t PLL2CFGR2; /*!< RCC PLL2 configuration register 2 Address offset: 0x0094 */
__IO uint32_t PLL2CFGR3; /*!< RCC PLL2 configuration register 3 Address offset: 0x0098 */
uint32_t RESERVED5; /*!< Reserved Address offset: 0x009C */
__IO uint32_t PLL3CFGR1; /*!< RCC PLL3 configuration register 1 Address offset: 0x00A0 */
__IO uint32_t PLL3CFGR2; /*!< RCC PLL3 configuration register 2 Address offset: 0x00A4 */
__IO uint32_t PLL3CFGR3; /*!< RCC PLL3 configuration register 3 Address offset: 0x00A8 */
uint32_t RESERVED6; /*!< Reserved Address offset: 0x00AC */
__IO uint32_t PLL4CFGR1; /*!< RCC PLL4 configuration register 1 Address offset: 0x00B0 */
__IO uint32_t PLL4CFGR2; /*!< RCC PLL4 configuration register 2 Address offset: 0x00B4 */
__IO uint32_t PLL4CFGR3; /*!< RCC PLL4 configuration register 3 Address offset: 0x00B8 */
uint32_t RESERVED7[2]; /*!< Reserved Address offset: 0x00BC-0x00C0 */
__IO uint32_t IC1CFGR; /*!< RCC IC1 configuration register Address offset: 0x00C4 */
__IO uint32_t IC2CFGR; /*!< RCC IC2 configuration register Address offset: 0x00C8 */
__IO uint32_t IC3CFGR; /*!< RCC IC3 configuration register Address offset: 0x00CC */
__IO uint32_t IC4CFGR; /*!< RCC IC4 configuration register Address offset: 0x00D0 */
__IO uint32_t IC5CFGR; /*!< RCC IC5 configuration register Address offset: 0x00D4 */
__IO uint32_t IC6CFGR; /*!< RCC IC6 configuration register Address offset: 0x00D8 */
__IO uint32_t IC7CFGR; /*!< RCC IC7 configuration register Address offset: 0x00DC */
__IO uint32_t IC8CFGR; /*!< RCC IC8 configuration register Address offset: 0x00E0 */
__IO uint32_t IC9CFGR; /*!< RCC IC9 configuration register Address offset: 0x00E4 */
__IO uint32_t IC10CFGR; /*!< RCC IC10 configuration register Address offset: 0x00E8 */
__IO uint32_t IC11CFGR; /*!< RCC IC11 configuration register Address offset: 0x00EC */
__IO uint32_t IC12CFGR; /*!< RCC IC12 configuration register Address offset: 0x00F0 */
__IO uint32_t IC13CFGR; /*!< RCC IC13 configuration register Address offset: 0x00F4 */
__IO uint32_t IC14CFGR; /*!< RCC IC14 configuration register Address offset: 0x00F8 */
__IO uint32_t IC15CFGR; /*!< RCC IC15 configuration register Address offset: 0x00FC */
__IO uint32_t IC16CFGR; /*!< RCC IC16 configuration register Address offset: 0x0100 */
__IO uint32_t IC17CFGR; /*!< RCC IC17 configuration register Address offset: 0x0104 */
__IO uint32_t IC18CFGR; /*!< RCC IC18 configuration register Address offset: 0x0108 */
__IO uint32_t IC19CFGR; /*!< RCC IC19 configuration register Address offset: 0x010C */
__IO uint32_t IC20CFGR; /*!< RCC IC20 configuration register Address offset: 0x0110 */
uint32_t RESERVED8[4]; /*!< Reserved Address offset: 0x0114-0x0120 */
__IO uint32_t CIER; /*!< RCC clock-source interrupt enable register Address offset: 0x0124 */
__IO uint32_t CIFR; /*!< RCC clock-source interrupt flag register Address offset: 0x0128 */
__IO uint32_t CICR; /*!< RCC clock-source interrupt clear register Address offset: 0x012C */
uint32_t RESERVED9[5]; /*!< Reserved Address offset: 0x0130-0x0140 */
__IO uint32_t CCIPR1; /*!< RCC clock configuration for independent peripheral register 1 Address offset: 0x0144 */
__IO uint32_t CCIPR2; /*!< RCC clock configuration for independent peripheral register 2 Address offset: 0x0148 */
__IO uint32_t CCIPR3; /*!< RCC clock configuration for independent peripheral register 3 Address offset: 0x014C */
__IO uint32_t CCIPR4; /*!< RCC clock configuration for independent peripheral register 4 Address offset: 0x0150 */
__IO uint32_t CCIPR5; /*!< RCC clock configuration for independent peripheral register 5 Address offset: 0x0154 */
__IO uint32_t CCIPR6; /*!< RCC clock configuration for independent peripheral register 6 Address offset: 0x0158 */
__IO uint32_t CCIPR7; /*!< RCC clock configuration for independent peripheral register 7 Address offset: 0x015C */
__IO uint32_t CCIPR8; /*!< RCC clock configuration for independent peripheral register 8 Address offset: 0x0160 */
__IO uint32_t CCIPR9; /*!< RCC clock configuration for independent peripheral register 9 Address offset: 0x0164 */
uint32_t RESERVED10[2]; /*!< Reserved Address offset: 0x0168-0x016C */
__IO uint32_t CCIPR12; /*!< RCC clock configuration for independent peripheral register 12 Address offset: 0x0170 */
__IO uint32_t CCIPR13; /*!< RCC clock configuration for independent peripheral register 13 Address offset: 0x0174 */
__IO uint32_t CCIPR14; /*!< RCC clock configuration for independent peripheral register 14 Address offset: 0x0178 */
uint32_t RESERVED11[35]; /*!< Reserved Address offset: 0x017C-0x0204 */
__IO uint32_t MISCRSTR; /*!< RCC miscellaneous configurations reset register Address offset: 0x0208 */
__IO uint32_t MEMRSTR; /*!< RCC embedded memories reset register Address offset: 0x020C */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 reset register Address offset: 0x0210 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 reset register Address offset: 0x0214 */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 reset register Address offset: 0x0218 */
__IO uint32_t AHB4RSTR; /*!< RCC AHB4 reset register Address offset: 0x021C */
__IO uint32_t AHB5RSTR; /*!< RCC AHB5 reset register Address offset: 0x0220 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 reset register 1 Address offset: 0x0224 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 reset register 2 Address offset: 0x0228 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 reset register Address offset: 0x022C */
uint32_t RESERVED12; /*!< Reserved Address offset: 0x0230 */
__IO uint32_t APB4RSTR1; /*!< RCC APB4 reset register 1 Address offset: 0x0234 */
__IO uint32_t APB4RSTR2; /*!< RCC APB4 reset register 2 Address offset: 0x0238 */
__IO uint32_t APB5RSTR; /*!< RCC APB5 reset register Address offset: 0x023C */
__IO uint32_t DIVENR; /*!< RCC IC dividers enable register Address offset: 0x0240 */
__IO uint32_t BUSENR; /*!< RCC embedded buses enable register Address offset: 0x0244 */
__IO uint32_t MISCENR; /*!< RCC miscellaneous configurations enable register Address offset: 0x0248 */
__IO uint32_t MEMENR; /*!< RCC embedded memories enable register Address offset: 0x024C */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 enable register Address offset: 0x0250 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 enable register Address offset: 0x0254 */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 enable register Address offset: 0x0258 */
__IO uint32_t AHB4ENR; /*!< RCC AHB4 enable register Address offset: 0x025C */
__IO uint32_t AHB5ENR; /*!< RCC AHB5 enable register Address offset: 0x0260 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 enable register 1 Address offset: 0x0264 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 enable register 2 Address offset: 0x0268 */
__IO uint32_t APB2ENR; /*!< RCC APB2 enable register Address offset: 0x026C */
__IO uint32_t APB3ENR; /*!< RCC APB3 enable register Address offset: 0x0270 */
__IO uint32_t APB4ENR1; /*!< RCC APB4 enable register 1 Address offset: 0x0274 */
__IO uint32_t APB4ENR2; /*!< RCC APB4 enable register 2 Address offset: 0x0278 */
__IO uint32_t APB5ENR; /*!< RCC APB5 enable register Address offset: 0x027C */
uint32_t RESERVED13; /*!< Reserved Address offset: 0x0280 */
__IO uint32_t BUSLPENR; /*!< RCC embedded buses sleep enable register Address offset: 0x0284 */
__IO uint32_t MISCLPENR; /*!< RCC miscellaneous configurations sleep enable register Address offset: 0x0288 */
__IO uint32_t MEMLPENR; /*!< RCC embedded memories sleep enable register Address offset: 0x028C */
__IO uint32_t AHB1LPENR; /*!< RCC AHB1 sleep enable register Address offset: 0x0290 */
__IO uint32_t AHB2LPENR; /*!< RCC AHB2 sleep enable register Address offset: 0x0294 */
__IO uint32_t AHB3LPENR; /*!< RCC AHB3 sleep enable register Address offset: 0x0298 */
__IO uint32_t AHB4LPENR; /*!< RCC AHB4 sleep enable register Address offset: 0x029C */
__IO uint32_t AHB5LPENR; /*!< RCC AHB5 sleep enable register Address offset: 0x02A0 */
__IO uint32_t APB1LPENR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x02A4 */
__IO uint32_t APB1LPENR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x02A8 */
__IO uint32_t APB2LPENR; /*!< RCC APB2 sleep enable register Address offset: 0x02AC */
__IO uint32_t APB3LPENR; /*!< RCC APB3 sleep enable register Address offset: 0x02B0 */
__IO uint32_t APB4LPENR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x02B4 */
__IO uint32_t APB4LPENR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x02B8 */
__IO uint32_t APB5LPENR; /*!< RCC APB5 sleep enable register Address offset: 0x02BC */
uint32_t RESERVED14[99]; /*!< Reserved Address offset: 0x02C0-0x0448 */
__IO uint32_t RDCR; /*!< RCC reset duration control register Address offset: 0x044C */
uint32_t RESERVED15[204]; /*!< Reserved Address offset: 0x0450-0x077C */
__IO uint32_t SECCFGR0; /*!< RCC oscillator secure configuration register 0 Address offset: 0x0780 */
__IO uint32_t PRIVCFGR0; /*!< RCC oscillator privilege configuration register 0 Address offset: 0x0784 */
__IO uint32_t LOCKCFGR0; /*!< RCC oscillator lock configuration register 0 Address offset: 0x0788 */
__IO uint32_t PUBCFGR0; /*!< RCC oscillator public configuration register 0 Address offset: 0x078C */
__IO uint32_t SECCFGR1; /*!< RCC PLL secure configuration register 1 Address offset: 0x0790 */
__IO uint32_t PRIVCFGR1; /*!< RCC PLL privilege configuration register 1 Address offset: 0x0794 */
__IO uint32_t LOCKCFGR1; /*!< RCC PLL lock configuration register 1 Address offset: 0x0798 */
__IO uint32_t PUBCFGR1; /*!< RCC PLL public configuration register 1 Address offset: 0x079C */
__IO uint32_t SECCFGR2; /*!< RCC divider secure configuration register 2 Address offset: 0x07A0 */
__IO uint32_t PRIVCFGR2; /*!< RCC divider privilege configuration register 2 Address offset: 0x07A4 */
__IO uint32_t LOCKCFGR2; /*!< RCC divider lock configuration register 2 Address offset: 0x07A8 */
__IO uint32_t PUBCFGR2; /*!< RCC divider public configuration register 2 Address offset: 0x07AC */
__IO uint32_t SECCFGR3; /*!< RCC system secure configuration register 3 Address offset: 0x07B0 */
__IO uint32_t PRIVCFGR3; /*!< RCC system privilege configuration register 3 Address offset: 0x07B4 */
__IO uint32_t LOCKCFGR3; /*!< RCC system lock configuration register 3 Address offset: 0x07B8 */
__IO uint32_t PUBCFGR3; /*!< RCC system public configuration register 3 Address offset: 0x07BC */
__IO uint32_t SECCFGR4; /*!< RCC bus secure configuration register 4 Address offset: 0x07C0 */
__IO uint32_t PRIVCFGR4; /*!< RCC bus privilege configuration register 4 Address offset: 0x07C4 */
__IO uint32_t LOCKCFGR4; /*!< RCC bus lock configuration register 4 Address offset: 0x07C8 */
__IO uint32_t PUBCFGR4; /*!< RCC bus public configuration register 4 Address offset: 0x07CC */
__IO uint32_t PUBCFGR5; /*!< RCC bus public configuration register 4 Address offset: 0x07D0 */
uint32_t RESERVED16[11]; /*!< Reserved Address offset: 0x07D4-0x07FC */
__IO uint32_t CSR; /*!< RCC control Set register Address offset: 0x0800 */
uint32_t RESERVED17; /*!< Reserved Address offset: 0x0804 */
__IO uint32_t STOPCSR; /*!< RCC STOPCSR configuration register Address offset: 0x0808 */
uint32_t RESERVED18[127]; /*!< Reserved Address offset: 0x080C-0x0A00 */
__IO uint32_t MISCRSTSR; /*!< RCC miscellaneous reset register Address offset: 0x0A08 */
__IO uint32_t MEMRSTSR; /*!< RCC memory reset register Address offset: 0x0A0C */
__IO uint32_t AHB1RSTSR; /*!< RCC AHB1 reset register Address offset: 0x0A10 */
__IO uint32_t AHB2RSTSR; /*!< RCC AHB2 reset register Address offset: 0x0A14 */
__IO uint32_t AHB3RSTSR; /*!< RCC AHB3 reset register Address offset: 0x0A18 */
__IO uint32_t AHB4RSTSR; /*!< RCC AHB4 reset register Address offset: 0x0A1C */
__IO uint32_t AHB5RSTSR; /*!< RCC AHB5 reset register Address offset: 0x0A20 */
__IO uint32_t APB1RSTSR1; /*!< RCC APB1 reset register 1 Address offset: 0x0A24 */
__IO uint32_t APB1RSTSR2; /*!< RCC APB1 reset register 2 Address offset: 0x0A28 */
__IO uint32_t APB2RSTSR; /*!< RCC APB2 reset register Address offset: 0x0A2C */
uint32_t RESERVED19; /*!< Reserved Address offset: 0x0A30 */
__IO uint32_t APB4RSTSR1; /*!< RCC APB4 reset register 1 Address offset: 0x0A34 */
__IO uint32_t APB4RSTSR2; /*!< RCC APB4 reset register 2 Address offset: 0x0A38 */
__IO uint32_t APB5RSTSR; /*!< RCC APB5 reset register Address offset: 0x0A3C */
__IO uint32_t DIVENSR; /*!< RCC divider enable register Address offset: 0x0A40 */
__IO uint32_t BUSENSR; /*!< RCC bus enable register Address offset: 0x0A44 */
__IO uint32_t MISCENSR; /*!< RCC miscellaneous enable register Address offset: 0x0A48 */
__IO uint32_t MEMENSR; /*!< RCC memory enable register Address offset: 0x0A4C */
__IO uint32_t AHB1ENSR; /*!< RCC AHB1 enable register Address offset: 0x0A50 */
__IO uint32_t AHB2ENSR; /*!< RCC AHB2 enable register Address offset: 0x0A54 */
__IO uint32_t AHB3ENSR; /*!< RCC AHB3 enable register Address offset: 0x0A58 */
__IO uint32_t AHB4ENSR; /*!< RCC AHB4 enable register Address offset: 0x0A5C */
__IO uint32_t AHB5ENSR; /*!< RCC AHB5 enable register Address offset: 0x0A60 */
__IO uint32_t APB1ENSR1; /*!< RCC APB1 enable register 1 Address offset: 0x0A64 */
__IO uint32_t APB1ENSR2; /*!< RCC APB1 enable register 2 Address offset: 0x0A68 */
__IO uint32_t APB2ENSR; /*!< RCC APB2 enable register Address offset: 0x0A6C */
__IO uint32_t APB3ENSR; /*!< RCC APB3 enable register Address offset: 0x0A70 */
__IO uint32_t APB4ENSR1; /*!< RCC APB4 enable register 1 Address offset: 0x0A74 */
__IO uint32_t APB4ENSR2; /*!< RCC APB4 enable register 2 Address offset: 0x0A78 */
__IO uint32_t APB5ENSR; /*!< RCC APB5 enable register Address offset: 0x0A7C */
uint32_t RESERVED20; /*!< Reserved Address offset: 0x0A80 */
__IO uint32_t BUSLPENSR; /*!< RCC bus sleep enable register Address offset: 0x0A84 */
__IO uint32_t MISCLPENSR; /*!< RCC miscellaneous sleep enable register Address offset: 0x0A88 */
__IO uint32_t MEMLPENSR; /*!< RCC memory sleep enable register Address offset: 0x0A8C */
__IO uint32_t AHB1LPENSR; /*!< RCC AHB1 sleep enable register Address offset: 0x0A90 */
__IO uint32_t AHB2LPENSR; /*!< RCC AHB2 sleep enable register Address offset: 0x0A94 */
__IO uint32_t AHB3LPENSR; /*!< RCC AHB3 sleep enable register Address offset: 0x0A98 */
__IO uint32_t AHB4LPENSR; /*!< RCC AHB4 sleep enable register Address offset: 0x0A9C */
__IO uint32_t AHB5LPENSR; /*!< RCC AHB5 sleep enable register Address offset: 0x0AA0 */
__IO uint32_t APB1LPENSR1; /*!< RCC APB1 sleep enable register 1 Address offset: 0x0AA4 */
__IO uint32_t APB1LPENSR2; /*!< RCC APB1 sleep enable register 2 Address offset: 0x0AA8 */
__IO uint32_t APB2LPENSR; /*!< RCC APB2 sleep enable register Address offset: 0x0AAC */
__IO uint32_t APB3LPENSR; /*!< RCC APB3 sleep enable register Address offset: 0x0AB0 */
__IO uint32_t APB4LPENSR1; /*!< RCC APB4 sleep enable register 1 Address offset: 0x0AB4 */
__IO uint32_t APB4LPENSR2; /*!< RCC APB4 sleep enable register 2 Address offset: 0x0AB8 */
__IO uint32_t APB5LPENSR; /*!< RCC APB5 sleep enable register Address offset: 0x0ABC */
uint32_t RESERVED21[305]; /*!< Reserved Address offset: 0x0AC0-0x0F80 */
__IO uint32_t PRIVCFGSR0; /*!< RCC oscillator privilege configuration set register 0 Address offset: 0x0F84 */
uint32_t RESERVED22; /*!< Reserved Address offset: 0x0F88 */
__IO uint32_t PUBCFGSR0; /*!< RCC oscillator public configuration set register 0 Address offset: 0x0F8C */
uint32_t RESERVED23; /*!< Reserved Address offset: 0x0F90 */
__IO uint32_t PRIVCFGSR1; /*!< RCC PLL privilege configuration set register 1 Address offset: 0x0F94 */
uint32_t RESERVED24; /*!< Reserved Address offset: 0x0F98 */
__IO uint32_t PUBCFGSR1; /*!< RCC PLL public configuration set register 1 Address offset: 0x0F9C */
uint32_t RESERVED25; /*!< Reserved Address offset: 0x0FA0 */
__IO uint32_t PRIVCFGSR2; /*!< RCC divider privilege configuration set register 2 Address offset: 0x0FA4 */
uint32_t RESERVED26; /*!< Reserved Address offset: 0x0FA8 */
__IO uint32_t PUBCFGSR2; /*!< RCC divider public configuration set register 2 Address offset: 0x0FAC */
uint32_t RESERVED27; /*!< Reserved Address offset: 0x0FB0 */
__IO uint32_t PRIVCFGSR3; /*!< RCC system privilege configuration set register 3 Address offset: 0x0FB4 */
uint32_t RESERVED28; /*!< Reserved Address offset: 0x0FB8 */
__IO uint32_t PUBCFGSR3; /*!< RCC system public configuration set register 3 Address offset: 0x0FBC */
uint32_t RESERVED29; /*!< Reserved Address offset: 0x0FC0 */
__IO uint32_t PRIVCFGSR4; /*!< RCC privilege configuration set register 4 Address offset: 0x0FC4 */
uint32_t RESERVED30; /*!< Reserved Address offset: 0x0FC8 */
__IO uint32_t PUBCFGSR4; /*!< RCC public configuration set register 4 Address offset: 0x0FCC */
__IO uint32_t PUBCFGSR5; /*!< RCC public configuration set register 5 Address offset: 0x0FD0 */
uint32_t RESERVED31[11]; /*!< Reserved Address offset: 0x0FD4-0x0FFC */
__IO uint32_t CCR; /*!< RCC control clear register Address offset: 0x1000 */
uint32_t RESERVED32; /*!< Reserved Address offset: 0x1004 */
__IO uint32_t STOPCCR; /*!< RCC Stop mode configuration clear register Address offset: 0x1008 */
uint32_t RESERVED33[127]; /*!< Reserved Address offset: 0x100C-0x1200 */
__IO uint32_t MISCRSTCR; /*!< RCC miscellaneous reset clear register Address offset: 0x1208 */
__IO uint32_t MEMRSTCR; /*!< RCC memory reset clear register Address offset: 0x120C */
__IO uint32_t AHB1RSTCR; /*!< RCC AHB1 reset clear register Address offset: 0x1210 */
__IO uint32_t AHB2RSTCR; /*!< RCC AHB2 reset clear register Address offset: 0x1214 */
__IO uint32_t AHB3RSTCR; /*!< RCC AHB3 reset r clear register Address offset: 0x1218 */
__IO uint32_t AHB4RSTCR; /*!< RCC AHB4 reset clear register Address offset: 0x121C */
__IO uint32_t AHB5RSTCR; /*!< RCC AHB5 reset clear register Address offset: 0x1220 */
__IO uint32_t APB1RSTCR1; /*!< RCC APB1 reset clear register 1 Address offset: 0x1224 */
__IO uint32_t APB1RSTCR2; /*!< RCC APB1 reset clear register 2 Address offset: 0x1228 */
__IO uint32_t APB2RSTCR; /*!< RCC APB2 reset clear register Address offset: 0x122C */
uint32_t RESERVED34; /*!< Reserved Address offset: 0x1230 */
__IO uint32_t APB4RSTCR1; /*!< RCC APB4 reset clear register 1 Address offset: 0x1234 */
__IO uint32_t APB4RSTCR2; /*!< RCC APB4 reset clear register 2 Address offset: 0x1238 */
__IO uint32_t APB5RSTCR; /*!< RCC APB5 reset clear register Address offset: 0x123C */
__IO uint32_t DIVENCR; /*!< RCC divider enable clear register Address offset: 0x1240 */
__IO uint32_t BUSENCR; /*!< RCC bus enable clear register Address offset: 0x1244 */
__IO uint32_t MISCENCR; /*!< RCC miscellaneous enable clear register Address offset: 0x1248 */
__IO uint32_t MEMENCR; /*!< RCC memory enable clear register Address offset: 0x124C */
__IO uint32_t AHB1ENCR; /*!< RCC AHB1 enable clear register Address offset: 0x1250 */
__IO uint32_t AHB2ENCR; /*!< RCC AHB2 enable clear register Address offset: 0x1254 */
__IO uint32_t AHB3ENCR; /*!< RCC AHB3 enable clear register Address offset: 0x1258 */
__IO uint32_t AHB4ENCR; /*!< RCC AHB4 enable clear register Address offset: 0x125C */
__IO uint32_t AHB5ENCR; /*!< RCC AHB5 enable clear register Address offset: 0x1260 */
__IO uint32_t APB1ENCR1; /*!< RCC APB1 enable clear register 1 Address offset: 0x1264 */
__IO uint32_t APB1ENCR2; /*!< RCC APB1 enable clear register 2 Address offset: 0x1268 */
__IO uint32_t APB2ENCR; /*!< RCC APB2 enable clear register Address offset: 0x126C */
__IO uint32_t APB3ENCR; /*!< RCC APB3 enable clear register Address offset: 0x1270 */
__IO uint32_t APB4ENCR1; /*!< RCC APB4 enable clear register 1 Address offset: 0x1274 */
__IO uint32_t APB4ENCR2; /*!< RCC APB4 enable clear register 2 Address offset: 0x1278 */
__IO uint32_t APB5ENCR; /*!< RCC APB5 enable clear register Address offset: 0x127C */
uint32_t RESERVED35; /*!< Reserved Address offset: 0x1280 */
__IO uint32_t BUSLPENCR; /*!< RCC bus sleep enable clear register Address offset: 0x1284 */
__IO uint32_t MISCLPENCR; /*!< RCC miscellaneous sleep enable clear register Address offset: 0x1288 */
__IO uint32_t MEMLPENCR; /*!< RCC memory sleep enable clear register Address offset: 0x128C */
__IO uint32_t AHB1LPENCR; /*!< RCC AHB1 sleep enable clear register Address offset: 0x1290 */
__IO uint32_t AHB2LPENCR; /*!< RCC AHB2 sleep enable clear register Address offset: 0x1294 */
__IO uint32_t AHB3LPENCR; /*!< RCC AHB3 sleep enable clear register Address offset: 0x1298 */
__IO uint32_t AHB4LPENCR; /*!< RCC AHB4 sleep enable clear register Address offset: 0x129C */
__IO uint32_t AHB5LPENCR; /*!< RCC AHB5 sleep enable clear register Address offset: 0x12A0 */
__IO uint32_t APB1LPENCR1; /*!< RCC APB1 sleep enable clear register 1 Address offset: 0x12A4 */
__IO uint32_t APB1LPENCR2; /*!< RCC APB1 sleep enable clear register 2 Address offset: 0x12A8 */
__IO uint32_t APB2LPENCR; /*!< RCC APB2 sleep enable clear register Address offset: 0x12AC */
__IO uint32_t APB3LPENCR; /*!< RCC APB3 sleep enable clear register Address offset: 0x12B0 */
__IO uint32_t APB4LPENCR1; /*!< RCC APB4 sleep enable clear register 1 Address offset: 0x12B4 */
__IO uint32_t APB4LPENCR2; /*!< RCC APB4 sleep enable clear register 2 Address offset: 0x12B8 */
__IO uint32_t APB5LPENCR; /*!< RCC APB5 sleep enable clear register Address offset: 0x12BC */
uint32_t RESERVED36[305]; /*!< Reserved Address offset: 0x12C0-0x1780 */
__IO uint32_t PRIVCFGCR0; /*!< RCC oscillator privilege configuration clear register 0 Address offset: 0x1784 */
uint32_t RESERVED37; /*!< Reserved Address offset: 0x1788 */
__IO uint32_t PUBCFGCR0; /*!< RCC oscillator public configuration clear register 0 Address offset: 0x178C */
uint32_t RESERVED38; /*!< Reserved Address offset: 0x1790 */
__IO uint32_t PRIVCFGCR1; /*!< RCC PLL privilege configuration clear register 1 Address offset: 0x1794 */
uint32_t RESERVED39; /*!< Reserved Address offset: 0x1798 */
__IO uint32_t PUBCFGCR1; /*!< RCC PLL public configuration clear register 1 Address offset: 0x179C */
uint32_t RESERVED40; /*!< Reserved Address offset: 0x17A0 */
__IO uint32_t PRIVCFGCR2; /*!< RCC divider privilege configuration clear register 2 Address offset: 0x17A4 */
uint32_t RESERVED41; /*!< Reserved Address offset: 0x17A8 */
__IO uint32_t PUBCFGCR2; /*!< RCC divider public configuration clear register 2 Address offset: 0x17AC */
uint32_t RESERVED42; /*!< Reserved Address offset: 0x17B0 */
__IO uint32_t PRIVCFGCR3; /*!< RCC system privilege configuration clear register 3 Address offset: 0x17B4 */
uint32_t RESERVED43; /*!< Reserved Address offset: 0x17B8 */
__IO uint32_t PUBCFGCR3; /*!< RCC system public configuration clear register 3 Address offset: 0x17BC */
uint32_t RESERVED44; /*!< Reserved Address offset: 0x17C0 */
__IO uint32_t PRIVCFGCR4; /*!< RCC privilege configuration clear register 4 Address offset: 0x17C4 */
uint32_t RESERVED45; /*!< Reserved Address offset: 0x17C8 */
__IO uint32_t PUBCFGCR4; /*!< RCC public configuration clear register 4 Address offset: 0x17CC */
__IO uint32_t PUBCFGCR5; /*!< RCC public configuration clear register 5 Address offset: 0x17D0 */
} RCC_TypeDef;
/*
* @brief RIFSC Resource Isolation Framework Security Controller (full version) (RIFSC User Spec Rev 1.1)
*/
typedef struct
{
__IO uint32_t RISC_CR; /*!< RIFSC RISC slave configuration register x Address offset: 0x000 */
uint32_t RESERVED0[3]; /*!< Reserved Address offset: 0x004-0x00C */
__IO uint32_t RISC_SECCFGRx[6]; /*!< RIFSC RISC slave security configuration register x Address offset: 0x010-0x24 */
uint32_t RESERVED1[2]; /*!< Reserved Address offset: 0x028-0x02C */
__IO uint32_t RISC_PRIVCFGRx[6]; /*!< RIFSC RISFC slave privileged register x Address offset: 0x030-0x44 */
uint32_t RESERVED2[2]; /*!< Reserved Address offset: 0x048-0x04C */
__IO uint32_t RISC_RCFGLOCKRx[6]; /*!< RIFSC RISC slave resource configuration lock register x Address offset: 0x050 - 0x64 */
uint32_t RESERVED3[742]; /*!< Reserved Address offset: 0x068-0xBFC */
__IO uint32_t RIMC_CR; /*!< RIFSC RIMC master configuration register Address offset: 0xC00 */
uint32_t RESERVED4[3]; /*!< Reserved Address offset: 0xC04-0xC0C */
__IO uint32_t RIMC_ATTRx[13]; /*!< RIFSC RIMC master attribute register x Address offset: 0xC10-0xC40 */
uint32_t RESERVED5[219]; /*!< Reserved Address offset: 0xC40-0xFAC */
__IO uint32_t PPSRx[6]; /*!< RIFSC peripheral protection status register x Address offset: 0xFB0-0xFC4 */
uint32_t RESERVED6[8]; /*!< Reserved Address offset: 0xFC8-0xFE4 */
} RIFSC_TypeDef;
/**
* @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version)
*/
typedef struct
{
__IO uint32_t CFGR; /*!< RISAF Region X configuration register */
__IO uint32_t STARTR; /*!< RISAF Region X start address register */
__IO uint32_t ENDR; /*!< RISAF Region X end address register */
__IO uint32_t CIDCFGR; /*!< RISAF Region X CID configuration register */
__IO uint32_t ACFGR; /*!< RISAF Region X subregion A configuration register */
__IO uint32_t ASTARTR; /*!< RISAF Region X subregion A start address register */
__IO uint32_t AENDR; /*!< RISAF Region X subregion A end address register */
__IO uint32_t ANESTR; /*!< RISAF Region X subregion A nested mode register */
__IO uint32_t BCFGR; /*!< RISAF Region X subregion B configuration register */
__IO uint32_t BSTARTR; /*!< RISAF Region X subregion B start address register */
__IO uint32_t BENDR; /*!< RISAF Region X subregion B end address register */
__IO uint32_t BNESTR; /*!< RISAF Region X subregion B nested mode register */
uint32_t RESERVED0[4]; /*!< Reserved */
} RISAF_Region_TypeDef;
/**
* @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) Illegal Access Register (RIF User Spec Rev 1.0.14)
*/
typedef struct
{
__IO uint32_t IAESR; /*!< RISAF Illegal access error status register */
__IO uint32_t IADDR; /*!< RISAF Illegal address register, */
} RISAF_Illegal_TypeDef;
/**
* @brief RISAF Resource Isolation Slave Unit for Address Space Protection (full version) (RIF User Spec Rev 1.0.14)
*/
typedef struct
{
__IO uint32_t CR; /*!< RISAF Configuration register, Address offset: 0x000 */
__IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x004 */
__IO uint32_t IASR; /*!< RISAF Illegal access status register, Address offset: 0x008 */
__IO uint32_t IACR; /*!< RISAF Illegal access clear register, Address offset: 0x00C */
uint32_t RESERVED1[4]; /*!< Reserved, 0x010-0x01C */
RISAF_Illegal_TypeDef IAR[1]; /*!< RISAF Illegal access error status and address register, 0x020-0x024 */
uint32_t RESERVED2[6]; /*!< Reserved, 0x028-0x03C */
RISAF_Region_TypeDef REG[15]; /*!< RISAF Region X configuration register, 0x040-0x3FC */
} RISAF_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
uint32_t RESERVED;
__IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
} RNG_TypeDef;
/*
* @brief RTC Specific device feature definitions
*/
#define RTC_BKP_NB 32U
#define RTC_TAMP_NB 7U
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
__IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */
__IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
__IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
uint32_t RESERVED3[4];/*!< Reserved, Address offset: 0x58 */
__IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */
__IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */
} RTC_TypeDef;
/**
* @brief SAES Processor
*/
typedef struct
{
__IO uint32_t CR; /*!< SAES control register, Address offset: 0x000 */
__IO uint32_t SR; /*!< SAES status register, Address offset: 0x004 */
__IO uint32_t DINR; /*!< SAES data input register, Address offset: 0x008 */
__IO uint32_t DOUTR; /*!< SAES data output register, Address offset: 0x00C */
__IO uint32_t KEYR0; /*!< SAES key register 0, Address offset: 0x010 */
__IO uint32_t KEYR1; /*!< SAES key register 1, Address offset: 0x014 */
__IO uint32_t KEYR2; /*!< SAES key register 2, Address offset: 0x018 */
__IO uint32_t KEYR3; /*!< SAES key register 3, Address offset: 0x01C */
__IO uint32_t IVR0; /*!< SAES initialization vector register 0, Address offset: 0x020 */
__IO uint32_t IVR1; /*!< SAES initialization vector register 1, Address offset: 0x024 */
__IO uint32_t IVR2; /*!< SAES initialization vector register 2, Address offset: 0x028 */
__IO uint32_t IVR3; /*!< SAES initialization vector register 3, Address offset: 0x02C */
__IO uint32_t KEYR4; /*!< SAES key register 4, Address offset: 0x030 */
__IO uint32_t KEYR5; /*!< SAES key register 5, Address offset: 0x034 */
__IO uint32_t KEYR6; /*!< SAES key register 6, Address offset: 0x038 */
__IO uint32_t KEYR7; /*!< SAES key register 7, Address offset: 0x03C */
uint32_t RESERVED1[48]; /*!< Reserved, Address offset: 0x040 -- 0x0FC */
__IO uint32_t DPACFGR; /*!< SAES DPA configuration register, Address offset: 0x100 */
uint32_t RESERVED2[127]; /*!< Reserved, Address offset: 0x104 -- 0x2FC */
__IO uint32_t IER; /*!< SAES Interrupt Enable Register, Address offset: 0x300 */
__IO uint32_t ISR; /*!< SAES Interrupt Status Register, Address offset: 0x304 */
__IO uint32_t ICR; /*!< SAES Interrupt Clear Register, Address offset: 0x308 */
} SAES_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Secure digital input/output Interface
*/
typedef struct
{
__IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
__IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
__IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
__IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
__I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
__I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
__I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
__I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
__I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
__IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
__IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
__IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
__I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
__I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
__IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
__IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
__IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
__IO uint32_t FIFOTHR; /*!< SDMMC data FIFO threshold register, Address offset: 0x44 */
uint32_t RESERVED0[2]; /*!< Reserved, 0x48 - 0x4C */
__IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
__IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
__IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */
uint32_t RESERVED1[2]; /*!< Reserved, 0x5C - 0x60 */
__IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */
__IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */
uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */
__IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
} SDMMC_TypeDef;
/**
* @brief SPI
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
__IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
__IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
__IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
__IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved, 0x1C */
__IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
__IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
__IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
__IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
__IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
__IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
__IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
} SPI_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @brief USB_OTG_Core_register
*/
typedef struct
{
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */
__IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */
__IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */
__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */
__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */
__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */
__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */
__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */
__IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */
__IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */
__IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */
__IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */
__IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */
__IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */
__IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */
__IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */
__IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */
__IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */
} USB_OTG_GlobalTypeDef;
typedef struct
{
__IO uint32_t USBPHYC_CR; /*!< USB_OTG Control and Status Register, Address offset: 000h */
__IO uint32_t USBPHYC_TRIM1CR; /*!< USB_OTG Interrupt Register, Address offset: 004h */
__IO uint32_t USBPHYC_TRIM2CR; /*!< Core AHB Configuration Register, Address offset: 008h */
} USB_PHY_GlobalTypeDef;
/**
* @brief USB_OTG_device_Registers
*/
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */
__IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */
__IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */
__IO uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */
__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */
__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */
__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */
__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */
__IO uint32_t Reserved20; /*!< Reserved, Address offset: 820h */
__IO uint32_t Reserved9; /*!< Reserved, Address offset: 824h */
__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */
__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */
__IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */
__IO uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */
__IO uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */
} USB_OTG_DeviceTypeDef;
/**
* @brief USB_OTG_IN_Endpoint-Specific_Register
*/
typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */
__IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */
__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */
__IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */
__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */
__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */
__IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */
} USB_OTG_INEndpointTypeDef;
/**
* @brief USB_OTG_OUT_Endpoint-Specific_Registers
*/
typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */
__IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */
__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */
__IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */
__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */
__IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */
} USB_OTG_OUTEndpointTypeDef;
/**
* @brief USB_OTG_Host_Mode_Register_Structures
*/
typedef struct
{
__IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */
__IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */
__IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */
__IO uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */
__IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */
__IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */
__IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */
} USB_OTG_HostTypeDef;
/**
* @brief USB_OTG_Host_Channel_Specific_Registers
*/
typedef struct
{
__IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */
__IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */
__IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */
__IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */
__IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */
__IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */
uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */
} USB_OTG_HostChannelTypeDef;
typedef struct
{
__IO uint32_t USBPHYC_CR; /*!< USB HS PHY Control Register, Address offset: 000h */
__IO uint32_t USBPHYC_TRIM1CR; /*!< USB HS PHY Trimming_1 Register, Address offset: 004h */
__IO uint32_t USBPHYC_TRIM2CR; /*!< USB HS PHY Trimming_2 Register, Address offset: 008h */
} USB_HS_PHYC_GlobalTypeDef;
/**
* @brief SPDIF-RX Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
__IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
__IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
__IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
__IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
__IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
__IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
} SPDIFRX_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t BOOTCR; /*!< SYSCFG boot pin control register, Address offset: 0x00 */
__IO uint32_t CM55CR; /*!< SYSCFG Cortex-M55 control register, Address offset: 0x04 */
__IO uint32_t CM55TCMCR; /*!< SYSCFG Cortex-M55 TCM control register, Address offset: 0x08 */
__IO uint32_t CM55RWMCR; /*!< SYSCFG Cortex-M55 memory RW margin register, Address offset: 0x0C */
__IO uint32_t INITSVTORCR; /*!< SYSCFG Cortex-M55 SVTOR control register, Address offset: 0x10 */
__IO uint32_t INITNSVTORCR; /*!< Cortex-M55 NSVTOR control register, Address offset: 0x14 */
__IO uint32_t CM55RSTCR; /*!< SYSCFG Cortex-M55 reset type control register, Address offset: 0x18 */
__IO uint32_t CM55PAHBWPR; /*!< SYSCFG Cortex-M55 P-AHB write posting control register, Address offset: 0x1C */
__IO uint32_t VENCRAMCR; /*!< SYSCFG VENCRAM control register, Address offset: 0x20 */
__IO uint32_t POTTAMPRSTCR; /*!< SYSCFG potential tamper reset register, Address offset: 0x24 */
__IO uint32_t NPUNICQOSCR; /*!< SYSCFG NPUNIC QoS control register, Address offset: 0x28 */
uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2C-0x30 */
__IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */
__IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */
__IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x44 */
__IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x48 */
__IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x4C */
__IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x50 */
__IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x54 */
__IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x58 */
__IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x5C */
__IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x60 */
__IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */
__IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */
__IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */
__IO uint32_t SEC_AIDCR; /*!< SYSCFG DMA CID secure control register, Address offset: 0x70 */
__IO uint32_t FMC_RETIMECR; /*!< SYSCFG FMC retiming logic control register, Address offset: 0x74 */
__IO uint32_t NPU_ICNCR; /*!< SYSCFG NPU RAM interleaving control register, Address offset: 0x78 */
uint32_t RESERVED3[33]; /*!< Reserved, Address offset: 0x7C-0xFC */
__IO uint32_t BOOTSR; /*!< SYSCFG boot pin status register, Address offset: 0x100 */
__IO uint32_t AHBWP_ERROR_SR; /*!< SYSCFG AHB write posting address error register, Address offset: 0x104 */
uint32_t RESERVED4[446]; /*!< Reserved, Address offset: 0x108-0x3FC */
__IO uint32_t SECPRIV_AIDCR; /*!< SYSCFG DMA CID non-secure control register, Address offset: 0x800 */
uint32_t RESERVED5[507]; /*!< Reserved, Address offset: 0x804-0xFEC */
__IO uint32_t DEVICEID; /*!< SYSCFG Device ID, Address offset: 0xFF0 */
} SYSCFG_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
__IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */
__IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
__IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
__IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */
__IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */
__IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
__IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
__IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */
uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x43 -- 0x4C */
__IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */
__IO uint32_t RPCFGR; /*!< TAMP resources protection configuration register, Address offset: 0x54 */
uint32_t RESERVED5[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
} TAMP_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
uint32_t RESERVED1[221]; /*!< Reserved, 0x6C-0x3D8 */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window Watchdog
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief Extended-SPI Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< XSPI Control Register, Address offset: 0x000 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x004 */
__IO uint32_t DCR1; /*!< XSPI Device Configuration Register 1, Address offset: 0x008 */
__IO uint32_t DCR2; /*!< XSPI Device Configuration Register 2, Address offset: 0x00C */
__IO uint32_t DCR3; /*!< XSPI Device Configuration Register 3, Address offset: 0x010 */
__IO uint32_t DCR4; /*!< XSPI Device Configuration Register 4, Address offset: 0x014 */
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x018 - 0x01C */
__IO uint32_t SR; /*!< XSPI Status Register, Address offset: 0x020 */
__IO uint32_t FCR; /*!< XSPI Flag Clear Register, Address offset: 0x024 */
uint32_t RESERVED3[6]; /*!< Reserved, Address offset: 0x028 - 0x03C */
__IO uint32_t DLR; /*!< XSPI Data Length Register, Address offset: 0x040 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x044 */
__IO uint32_t AR; /*!< XSPI Address Register, Address offset: 0x048 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x04C */
__IO uint32_t DR; /*!< XSPI Data Register, Address offset: 0x050 */
uint32_t RESERVED6[11]; /*!< Reserved, Address offset: 0x054 - 0x07C */
__IO uint32_t PSMKR; /*!< XSPI Polling Status Mask Register, Address offset: 0x080 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x084 */
__IO uint32_t PSMAR; /*!< XSPI Polling Status Match Register, Address offset: 0x088 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x08C */
__IO uint32_t PIR; /*!< XSPI Polling Interval Register, Address offset: 0x090 */
uint32_t RESERVED9[27]; /*!< Reserved, Address offset: 0x094 - 0x0FC */
__IO uint32_t CCR; /*!< XSPI Communication Configuration Register, Address offset: 0x100 */
uint32_t RESERVED10; /*!< Reserved, Address offset: 0x104 */
__IO uint32_t TCR; /*!< XSPI Timing Configuration Register, Address offset: 0x108 */
uint32_t RESERVED11; /*!< Reserved, Address offset: 0x10C */
__IO uint32_t IR; /*!< XSPI Instruction Register, Address offset: 0x110 */
uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x114 - 0x11C */
__IO uint32_t ABR; /*!< XSPI Alternate Bytes Register, Address offset: 0x120 */
uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x124 - 0x12C */
__IO uint32_t LPTR; /*!< XSPI Low-Power Timeout Register, Address offset: 0x130 */
uint32_t RESERVED14[3]; /*!< Reserved, Address offset: 0x134 - 0x13C */
__IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration Register, Address offset: 0x140 */
uint32_t RESERVED15; /*!< Reserved, Address offset: 0x144 */
__IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration Register, Address offset: 0x148 */
uint32_t RESERVED16; /*!< Reserved, Address offset: 0x14C */
__IO uint32_t WPIR; /*!< XSPI Wrap Instruction Register, Address offset: 0x150 */
uint32_t RESERVED17[3]; /*!< Reserved, Address offset: 0x154 - 0x15C */
__IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes Register, Address offset: 0x160 */
uint32_t RESERVED18[7]; /*!< Reserved, Address offset: 0x164 - 0x17C */
__IO uint32_t WCCR; /*!< XSPI Write Communication Configuration Register, Address offset: 0x180 */
uint32_t RESERVED19; /*!< Reserved, Address offset: 0x184 */
__IO uint32_t WTCR; /*!< XSPI Write Timing Configuration Register, Address offset: 0x188 */
uint32_t RESERVED20; /*!< Reserved, Address offset: 0x18C */
__IO uint32_t WIR; /*!< XSPI Write Instruction Register, Address offset: 0x190 */
uint32_t RESERVED21[3]; /*!< Reserved, Address offset: 0x194 - 0x19C */
__IO uint32_t WABR; /*!< XSPI Write Alternate Bytes Register, Address offset: 0x1A0 */
uint32_t RESERVED22[23]; /*!< Reserved, Address offset: 0x1A4 - 0x1FC */
__IO uint32_t HLCR; /*!< XSPI HyperBus Latency Configuration Register, Address offset: 0x200 */
uint32_t RESERVED23[3]; /*!< Reserved, Address offset: 0x204 - 0x20C */
__IO uint32_t CALFCR; /*!< XSPI Full-Cycle Calibration Configuration Register, Address offset: 0x210 */
uint32_t RESERVED24; /*!< Reserved, Address offset: 0x214 */
__IO uint32_t CALMR; /*!< XSPI DLL Master Calibration Configuration Register, Address offset: 0x218 */
uint32_t RESERVED25; /*!< Reserved, Address offset: 0x21C */
__IO uint32_t CALSOR; /*!< XSPI Slave Output Calibration Configuration Register, Address offset: 0x220 */
uint32_t RESERVED26; /*!< Reserved, Address offset: 0x224 */
__IO uint32_t CALSIR; /*!< XSPI Slave Input Calibration Configuration Register, Address offset: 0x228 */
} XSPI_TypeDef;
/**
* @brief XSPI IO Manager
*/
typedef struct
{
__IO uint32_t CR; /*!< XSPI IO Manager Control Register, Address offset: 0x00 */
} XSPIM_TypeDef;
/** @} */ /* End of group STM32N6xx_peripherals */
/* =========================================================================================================================== */
/* ================ Device Specific Peripheral Address Map ================ */
/* =========================================================================================================================== */
/** @addtogroup STM32N6xx_Peripheral_peripheralAddr
* @{
*/
/* Internal RAMs sizes */
#define SRAM1_AXI_SIZE 0x100000UL /*!< SRAM1_AXI = 1024 Kbytes */
#define SRAM2_AXI_SIZE 0x100000UL /*!< SRAM2_AXI = 1024 Kbytes */
#define FLEXRAM_SIZE 0x64000UL /*!< FLEXRAM <= 400 Kbytes */
#define SRAM3_AXI_SIZE 0x70000UL /*!< SRAM3_AXI = 448 Kbytes */
#define SRAM4_AXI_SIZE 0x70000UL /*!< SRAM4_AXI = 448 Kbytes */
#define SRAM5_AXI_SIZE 0x70000UL /*!< SRAM5_AXI = 448 Kbytes */
#define SRAM6_AXI_SIZE 0x70000UL /*!< SRAM6_AXI = 448 Kbytes */
#define SRAM1_AHB_SIZE 0x4000UL /*!< SRAM1_AHB = 16 Kbytes */
#define SRAM2_AHB_SIZE 0x4000UL /*!< SRAM2_AHB = 16 Kbytes */
#define VENC_RAM_SIZE 0x20000UL /*!< VENC RAM = 128 Kbytes */
#define CACHEAXI_RAM_SIZE 0x40000UL /*!< CACHEAXI RAM = 256 Kbytes */
#define BKPSRAM_SIZE 0x2000UL /*!< BKPSRAM = 8 Kbytes */
#define FMC_BASE 0x60000000UL /*!< Base address of : FMC NOR/RAM memories accessible over AXI */
#define FMC_BANK1 FMC_BASE
#define FMC_BANK1_1 FMC_BANK1
#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
#define FMC_BANK5 0xC0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */
#define FMC_BANK5_1 FMC_BANK5
#define FMC_BANK5_2 (FMC_BANK5 + 0x04000000UL)
#define FMC_BANK5_3 (FMC_BANK5 + 0x08000000UL)
#define FMC_BANK5_4 (FMC_BANK5 + 0x0C000000UL)
#define FMC_BANK6 0xD0000000UL /*!< Base address of : FMC SDRAM memories accessible over AXI */
#define FMC_BANK6_1 FMC_BANK6
#define FMC_BANK6_2 (FMC_BANK6 + 0x04000000UL)
#define FMC_BANK6_3 (FMC_BANK6 + 0x08000000UL)
#define FMC_BANK6_4 (FMC_BANK6 + 0x0C000000UL)
#define XSPI1_BASE 0x90000000UL /*!< Base address of : XSPI1 memories accessible over AXI */
#define XSPI2_BASE 0x70000000UL /*!< Base address of : XSPI2 memories accessible over AXI */
#define XSPI3_BASE 0x80000000UL /*!< Base address of : XSPI3 memories accessible over AXI */
/**************************************************************************/
/* */
/* Peripheral and internal SRAMs base addresses - Non secure (aliased_NS) */
/* */
/**************************************************************************/
#define ITCM_BASE_NS 0x00000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */
#define BOOTROM_BASE_NS 0x08000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */
#define DTCM_BASE_NS 0x20000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */
#define SRAM1_AXI_BASE_NS 0x24000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
#define SRAM2_AXI_BASE_NS 0x24100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */
#define SRAM3_AXI_BASE_NS 0x24200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */
#define SRAM4_AXI_BASE_NS 0x24270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
#define SRAM5_AXI_BASE_NS 0x242E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
#define SRAM6_AXI_BASE_NS 0x24350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
#define SRAM_AXI_BASE_NS SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
#define CACHEAXI_RAM_BASE_NS 0x243C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */
#define VENC_RAM_BASE_NS 0x24400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS 0x25000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */
#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS 0x25400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */
#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS 0x25800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */
#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS 0x25C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */
#define STM500_CHANNELS_BASE_NS 0x27F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */
#define SRAM1_AHB_BASE_NS 0x28000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */
#define SRAM2_AHB_BASE_NS 0x28004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */
#define SRAM_AHB_BASE_NS SRAM1_AHB_BASE_NS /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */
#define BKPSRAM_BASE_NS 0x2C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */
#define PERIPH_BASE_NS 0x40000000UL /*!< Base address of : AHB/APB Peripherals */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE_NS PERIPH_BASE_NS
#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL)
#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02000000UL)
#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL)
#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL)
#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL)
#define APB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL)
#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL)
#define APB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08000000UL)
#define AHB5PERIPH_BASE_NS (PERIPH_BASE_NS + 0x08020000UL)
/*!< APB1 peripherals */
#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL)
#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL)
#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL)
#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL)
#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL)
#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL)
#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL)
#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL)
#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL)
#define LPTIM1_BASE_NS (APB1PERIPH_BASE_NS + 0x2400UL)
#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL)
#define TIM10_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL)
#define TIM11_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL)
#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL)
#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL)
#define SPDIFRX_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL)
#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL)
#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL)
#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL)
#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL)
#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL)
#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL)
#define I2C3_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL)
#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL)
#define I3C2_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL)
#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL)
#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL)
#define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL)
#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL)
#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA100UL)
#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL)
#define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL)
#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL)
#define FDCAN3_BASE_NS (APB1PERIPH_BASE_NS + 0xE800UL)
#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xFC00UL)
/*!< AHB1 peripherals */
#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS + 0x1000UL)
#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL)
#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL)
#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL)
#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL)
#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL)
#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL)
#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL)
#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL)
#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL)
#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL)
#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL)
#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL)
#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL)
#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL)
#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL)
#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL)
#define ADC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x2000UL)
#define ADC2_BASE_NS (AHB1PERIPH_BASE_NS + 0x2100UL)
#define ADC12_COMMON_BASE_NS (AHB1PERIPH_BASE_NS + 0x2300UL)
/*!< APB2 peripherals */
#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x0000UL)
#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x0400UL)
#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x1000UL)
#define USART6_BASE_NS (APB2PERIPH_BASE_NS + 0x1400UL)
#define UART9_BASE_NS (APB2PERIPH_BASE_NS + 0x1800UL)
#define USART10_BASE_NS (APB2PERIPH_BASE_NS + 0x1C00UL)
#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL)
#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL)
#define TIM18_BASE_NS (APB2PERIPH_BASE_NS + 0x3C00UL)
#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL)
#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL)
#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL)
#define TIM9_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL)
#define SPI5_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL)
#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL)
#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x0004UL)
#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x0024UL)
#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5C00UL)
#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x0004UL)
#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x0024UL)
/*!< AHB2 peripherals */
#define RAMCFG_BASE_NS (AHB2PERIPH_BASE_NS + 0x3000UL)
#define RAMCFG_SRAM1_AXI_BASE_NS (RAMCFG_BASE_NS)
#define RAMCFG_SRAM2_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0080UL)
#define RAMCFG_SRAM3_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0100UL)
#define RAMCFG_SRAM4_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0180UL)
#define RAMCFG_SRAM5_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0200UL)
#define RAMCFG_SRAM6_AXI_BASE_NS (RAMCFG_BASE_NS + 0x0280UL)
#define RAMCFG_SRAM1_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0300UL)
#define RAMCFG_SRAM2_AHB_BASE_NS (RAMCFG_BASE_NS + 0x0380UL)
#define RAMCFG_VENC_RAM_BASE_NS (RAMCFG_BASE_NS + 0x0400UL)
#define RAMCFG_BKPSRAM_BASE_NS (RAMCFG_BASE_NS + 0x0480UL)
#define RAMCFG_FLEXRAM_BASE_NS (RAMCFG_BASE_NS + 0x0500UL)
#define MDF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x5000UL)
#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x0080UL)
#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x0100UL)
#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x0180UL)
#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x0200UL)
#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x0280UL)
#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x0300UL)
#define ADF1_BASE_NS (AHB2PERIPH_BASE_NS + 0x6000UL)
#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x0080UL)
/*!< APB3 peripherals */
#define DAP_ROM_BASE_NS (APB3PERIPH_BASE_NS + 0x0000UL)
#define DBGMCU_BASE_NS (APB3PERIPH_BASE_NS + 0x1000UL)
#define DFT_APB_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL)
/*!< AHB3 peripherals */
#define RNG_BASE_NS (AHB3PERIPH_BASE_NS + 0x0000UL)
#define HASH_BASE_NS (AHB3PERIPH_BASE_NS + 0x0400UL)
#define HASH_DIGEST_BASE_NS (AHB3PERIPH_BASE_NS + 0x0710UL)
#define CRYP_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL)
#define SAES_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL)
#define PKA_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL)
#define RIFSC_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL)
#define RISAF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x6000UL)
#define RISAF2_BASE_NS (AHB3PERIPH_BASE_NS + 0x7000UL)
#define RISAF3_BASE_NS (AHB3PERIPH_BASE_NS + 0x8000UL)
#define RISAF4_BASE_NS (AHB3PERIPH_BASE_NS + 0x9000UL)
#define RISAF5_BASE_NS (AHB3PERIPH_BASE_NS + 0xA000UL)
#define RISAF6_BASE_NS (AHB3PERIPH_BASE_NS + 0xB000UL)
#define RISAF7_BASE_NS (AHB3PERIPH_BASE_NS + 0xC000UL)
#define RISAF8_BASE_NS (AHB3PERIPH_BASE_NS + 0xD000UL)
#define RISAF9_BASE_NS (AHB3PERIPH_BASE_NS + 0xE000UL)
#define RISAF11_BASE_NS (AHB3PERIPH_BASE_NS + 0x010000UL)
#define RISAF12_BASE_NS (AHB3PERIPH_BASE_NS + 0x011000UL)
#define RISAF13_BASE_NS (AHB3PERIPH_BASE_NS + 0x012000UL)
#define RISAF14_BASE_NS (AHB3PERIPH_BASE_NS + 0x013000UL)
#define RISAF15_BASE_NS (AHB3PERIPH_BASE_NS + 0x014000UL)
#define RISAF21_BASE_NS (AHB3PERIPH_BASE_NS + 0x015000UL)
#define RISAF22_BASE_NS (AHB3PERIPH_BASE_NS + 0x016000UL)
#define RISAF23_BASE_NS (AHB3PERIPH_BASE_NS + 0x017000UL)
/*!< APB4 peripherals */
#define HDP_BASE_NS (APB4PERIPH_BASE_NS + 0x0800UL)
#define LPUART1_BASE_NS (APB4PERIPH_BASE_NS + 0x0C00UL)
#define SPI6_BASE_NS (APB4PERIPH_BASE_NS + 0x1400UL)
#define I2C4_BASE_NS (APB4PERIPH_BASE_NS + 0x1C00UL)
#define LPTIM2_BASE_NS (APB4PERIPH_BASE_NS + 0x2400UL)
#define LPTIM3_BASE_NS (APB4PERIPH_BASE_NS + 0x2800UL)
#define LPTIM4_BASE_NS (APB4PERIPH_BASE_NS + 0x2C00UL)
#define LPTIM5_BASE_NS (APB4PERIPH_BASE_NS + 0x3000UL)
#define VREFBUF_BASE_NS (APB4PERIPH_BASE_NS + 0x3C00UL)
#define RTC_BASE_NS (APB4PERIPH_BASE_NS + 0x4000UL)
#define TAMP_BASE_NS (APB4PERIPH_BASE_NS + 0x4400UL)
#define IWDG_BASE_NS (APB4PERIPH_BASE_NS + 0x4800UL)
#define SERC_BASE_NS (APB4PERIPH_BASE_NS + 0x7C00UL)
#define SYSCFG_BASE_NS (APB4PERIPH_BASE_NS + 0x8000UL)
#define BSEC_BASE_NS (APB4PERIPH_BASE_NS + 0x9000UL)
#define DTS_BASE_NS (APB4PERIPH_BASE_NS + 0xA000UL)
#define DTS_Sensor0_BASE_NS (DTS_BASE_NS + 0x0C0UL)
#define DTS_Sensor1_BASE_NS (DTS_BASE_NS + 0x100UL)
/*!< AHB4 peripherals */
#define GPIOA_BASE_NS (AHB4PERIPH_BASE_NS + 0x0000UL)
#define GPIOB_BASE_NS (AHB4PERIPH_BASE_NS + 0x0400UL)
#define GPIOC_BASE_NS (AHB4PERIPH_BASE_NS + 0x0800UL)
#define GPIOD_BASE_NS (AHB4PERIPH_BASE_NS + 0x0C00UL)
#define GPIOE_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000UL)
#define GPIOF_BASE_NS (AHB4PERIPH_BASE_NS + 0x1400UL)
#define GPIOG_BASE_NS (AHB4PERIPH_BASE_NS + 0x1800UL)
#define GPIOH_BASE_NS (AHB4PERIPH_BASE_NS + 0x1C00UL)
#define GPION_BASE_NS (AHB4PERIPH_BASE_NS + 0x3400UL)
#define GPIOO_BASE_NS (AHB4PERIPH_BASE_NS + 0x3800UL)
#define GPIOP_BASE_NS (AHB4PERIPH_BASE_NS + 0x3C00UL)
#define GPIOQ_BASE_NS (AHB4PERIPH_BASE_NS + 0x4000UL)
#define PWR_BASE_NS (AHB4PERIPH_BASE_NS + 0x4800UL)
#define CRC_BASE_NS (AHB4PERIPH_BASE_NS + 0x4C00UL)
#define EXTI_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL)
#define RCC_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL)
/*!< APB5 peripherals */
#define LTDC_BASE_NS (APB5PERIPH_BASE_NS + 0x1000UL)
#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0100UL)
#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0200UL)
#define DCMIPP_BASE_NS (APB5PERIPH_BASE_NS + 0x2000UL)
#define GFXTIM_BASE_NS (APB5PERIPH_BASE_NS + 0x4000UL)
#define VENC_BASE_NS (APB5PERIPH_BASE_NS + 0x5000UL)
#define CSI_BASE_NS (APB5PERIPH_BASE_NS + 0x6000UL)
/*!< AHB5 peripherals */
#define HPDMA1_BASE_NS (AHB5PERIPH_BASE_NS + 0x0000UL)
#define HPDMA1_Channel0_BASE_NS (HPDMA1_BASE_NS + 0x0050UL)
#define HPDMA1_Channel1_BASE_NS (HPDMA1_BASE_NS + 0x00D0UL)
#define HPDMA1_Channel2_BASE_NS (HPDMA1_BASE_NS + 0x0150UL)
#define HPDMA1_Channel3_BASE_NS (HPDMA1_BASE_NS + 0x01D0UL)
#define HPDMA1_Channel4_BASE_NS (HPDMA1_BASE_NS + 0x0250UL)
#define HPDMA1_Channel5_BASE_NS (HPDMA1_BASE_NS + 0x02D0UL)
#define HPDMA1_Channel6_BASE_NS (HPDMA1_BASE_NS + 0x0350UL)
#define HPDMA1_Channel7_BASE_NS (HPDMA1_BASE_NS + 0x03D0UL)
#define HPDMA1_Channel8_BASE_NS (HPDMA1_BASE_NS + 0x0450UL)
#define HPDMA1_Channel9_BASE_NS (HPDMA1_BASE_NS + 0x04D0UL)
#define HPDMA1_Channel10_BASE_NS (HPDMA1_BASE_NS + 0x0550UL)
#define HPDMA1_Channel11_BASE_NS (HPDMA1_BASE_NS + 0x05D0UL)
#define HPDMA1_Channel12_BASE_NS (HPDMA1_BASE_NS + 0x0650UL)
#define HPDMA1_Channel13_BASE_NS (HPDMA1_BASE_NS + 0x06D0UL)
#define HPDMA1_Channel14_BASE_NS (HPDMA1_BASE_NS + 0x0750UL)
#define HPDMA1_Channel15_BASE_NS (HPDMA1_BASE_NS + 0x07D0UL)
#define DMA2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x1000UL)
#define JPEG_BASE_NS (AHB5PERIPH_BASE_NS + 0x3000UL)
#define FMC_R_BASE_NS (AHB5PERIPH_BASE_NS + 0x4000UL)
#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL)
#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL)
#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL)
#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL)
#define FMC_Common_R_BASE_NS (FMC_R_BASE_NS + 0x0020UL)
#define XSPI1_BASE_NS (AHB5PERIPH_BASE_NS + 0x5000UL)
#define PSSI_BASE_NS (AHB5PERIPH_BASE_NS + 0x6400UL)
#define SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6800UL)
#define DLYB_SDMMC2_BASE_NS (AHB5PERIPH_BASE_NS + 0x6C00UL)
#define SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x7000UL)
#define DLYB_SDMMC1_BASE_NS (AHB5PERIPH_BASE_NS + 0x8000UL)
#define DCMI_BASE_NS (AHB5PERIPH_BASE_NS + 0x8400UL)
#define XSPI2_BASE_NS (AHB5PERIPH_BASE_NS + 0xA000UL)
#define XSPIM_BASE_NS (AHB5PERIPH_BASE_NS + 0xB400UL)
#define MCE1_BASE_NS (AHB5PERIPH_BASE_NS + 0xB800UL)
#define MCE1_REGION1_BASE_NS (MCE1_BASE_NS + 0x040UL)
#define MCE1_REGION2_BASE_NS (MCE1_BASE_NS + 0x050UL)
#define MCE1_REGION3_BASE_NS (MCE1_BASE_NS + 0x060UL)
#define MCE1_REGION4_BASE_NS (MCE1_BASE_NS + 0x070UL)
#define MCE1_CONTEXT1_BASE_NS (MCE1_BASE_NS + 0x240UL)
#define MCE1_CONTEXT2_BASE_NS (MCE1_BASE_NS + 0x270UL)
#define MCE2_BASE_NS (AHB5PERIPH_BASE_NS + 0xBC00UL)
#define MCE2_REGION1_BASE_NS (MCE2_BASE_NS + 0x040UL)
#define MCE2_REGION2_BASE_NS (MCE2_BASE_NS + 0x050UL)
#define MCE2_REGION3_BASE_NS (MCE2_BASE_NS + 0x060UL)
#define MCE2_REGION4_BASE_NS (MCE2_BASE_NS + 0x070UL)
#define MCE2_CONTEXT1_BASE_NS (MCE2_BASE_NS + 0x240UL)
#define MCE2_CONTEXT2_BASE_NS (MCE2_BASE_NS + 0x270UL)
#define MCE3_BASE_NS (AHB5PERIPH_BASE_NS + 0xC000UL)
#define MCE3_REGION1_BASE_NS (MCE3_BASE_NS + 0x040UL)
#define MCE3_REGION2_BASE_NS (MCE3_BASE_NS + 0x050UL)
#define MCE3_REGION3_BASE_NS (MCE3_BASE_NS + 0x060UL)
#define MCE3_REGION4_BASE_NS (MCE3_BASE_NS + 0x070UL)
#define MCE3_CONTEXT1_BASE_NS (MCE3_BASE_NS + 0x240UL)
#define MCE3_CONTEXT2_BASE_NS (MCE3_BASE_NS + 0x270UL)
#define MCE4_BASE_NS (AHB5PERIPH_BASE_NS + 0xE000UL)
#define MCE4_REGION1_BASE_NS (MCE4_BASE_NS + 0x040UL)
#define MCE4_REGION2_BASE_NS (MCE4_BASE_NS + 0x050UL)
#define MCE4_REGION3_BASE_NS (MCE4_BASE_NS + 0x060UL)
#define MCE4_REGION4_BASE_NS (MCE4_BASE_NS + 0x070UL)
#define MCE4_CONTEXT1_BASE_NS (MCE4_BASE_NS + 0x240UL)
#define MCE4_CONTEXT2_BASE_NS (MCE4_BASE_NS + 0x270UL)
#define XSPI3_BASE_NS (AHB5PERIPH_BASE_NS + 0xD000UL)
#define GFXMMU_BASE_NS (AHB5PERIPH_BASE_NS + 0x010000UL)
#define GPU2D_BASE_NS (AHB5PERIPH_BASE_NS + 0x014000UL)
#define GPUCACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL)
#define ICACHE_BASE_NS (AHB5PERIPH_BASE_NS + 0x015000UL)
#define ETH1_BASE_NS (AHB5PERIPH_BASE_NS + 0x016000UL)
#define ETH1_MAC_BASE_NS (ETH1_BASE_NS)
#define USB1_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x01FC00UL)
#define USB2_HS_PHYC_BASE_NS (AHB5PERIPH_BASE_NS + 0x0A0000UL)
#define USB1_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x020000UL)
#define USB2_OTG_HS_BASE_NS (AHB5PERIPH_BASE_NS + 0x060000UL)
#define CACHEAXI_BASE_NS (AHB5PERIPH_BASE_NS + 0x0BFC00UL)
#define NPU_BASE_NS (AHB5PERIPH_BASE_NS + 0x0C0000UL)
/*!< Unique device ID register base address */
#define UID_BASE_NS (0x46009014UL)
/*!< Revision ID base address */
#define REVID_BASE_NS (BOOTROM_BASE_NS + 0x0047ECUL)
#if defined (CPU_IN_SECURE_STATE)
/*********************************************************************/
/* */
/* Peripheral and internal SRAMs base addresses - Secure (aliased_S) */
/* */
/*********************************************************************/
#define ITCM_BASE_S 0x10000000UL /*!< Base address of ITCM from 64 KB up to 256 KB */
#define BOOTROM_BASE_S 0x18000000UL /*!< Base address of 128 KB boot ROM accessible over AXI */
#define DTCM_BASE_S 0x30000000UL /*!< Base address of DTCM from 128 KB up to 256 KB */
#define SRAM1_AXI_BASE_S 0x34000000UL /*!< Base address of up to 1 MB system RAM 1 accessible over AXI */
#define SRAM2_AXI_BASE_S 0x34100000UL /*!< Base address of 1 MB system RAM 2 accessible over AXI */
#define SRAM3_AXI_BASE_S 0x34200000UL /*!< Base address of 448 KB system RAM 3 accessible over AXI */
#define SRAM4_AXI_BASE_S 0x34270000UL /*!< Base address of 448 KB system RAM 4 accessible over AXI */
#define SRAM5_AXI_BASE_S 0x342E0000UL /*!< Base address of 448 KB system RAM 5 accessible over AXI */
#define SRAM6_AXI_BASE_S 0x34350000UL /*!< Base address of 448 KB system RAM 6 accessible over AXI */
#define SRAM_AXI_BASE_S SRAM1_AXI_BASE_NS /*!< Base address of 3.792 MB system RAM accessible over AXI */
#define CACHEAXI_RAM_BASE_S 0x343C0000UL /*!< Base address of 256 KB NPU Cache RAM accessible over AXI */
#define VENC_RAM_BASE_S 0x34400000UL /*!< Base address of 128 KB of Video Encoder RAM accessible over AXI */
#define GFXMMU_VIRTUAL_BUFFER0_BASE_S 0x35000000UL /*!< Base address of 4 MB GFXMMU virtual buffer 0 */
#define GFXMMU_VIRTUAL_BUFFER1_BASE_S 0x35400000UL /*!< Base address of 4 MB GFXMMU virtual buffer 1 */
#define GFXMMU_VIRTUAL_BUFFER2_BASE_S 0x35800000UL /*!< Base address of 4 MB GFXMMU virtual buffer 2 */
#define GFXMMU_VIRTUAL_BUFFER3_BASE_S 0x35C00000UL /*!< Base address of 4 MB GFXMMU virtual buffer 3 */
#define STM500_CHANNELS_BASE_S 0x37F00000UL /*!< Base address of 1 MB of STM500 Channels (System Trace) */
#define SRAM1_AHB_BASE_S 0x38000000UL /*!< Base address of 16 KB system RAM 1 over AXI->AHB Bridge */
#define SRAM2_AHB_BASE_S 0x38004000UL /*!< Base address of 16 KB system RAM 2 over AXI->AHB Bridge */
#define SRAM_AHB_BASE_S SRAM1_AHB_BASE_S /*!< Base address of 32 KB system RAM over AXI->AHB Bridge */
#define BKPSRAM_BASE_S 0x3C000000UL /*!< Base address of 8 KB Backup SRAM over AXI->AHB Bridge */
#define PERIPH_BASE_S 0x50000000UL /*!< Base address of : AHB/APB Peripherals */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE_S PERIPH_BASE_S
#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL)
#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02000000UL)
#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL)
#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL)
#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL)
#define APB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL)
#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL)
#define APB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08000000UL)
#define AHB5PERIPH_BASE_S (PERIPH_BASE_S + 0x08020000UL)
/*!< APB1 peripherals */
#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL)
#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL)
#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL)
#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL)
#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL)
#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL)
#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL)
#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL)
#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL)
#define LPTIM1_BASE_S (APB1PERIPH_BASE_S + 0x2400UL)
#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL)
#define TIM10_BASE_S (APB1PERIPH_BASE_S + 0x3000UL)
#define TIM11_BASE_S (APB1PERIPH_BASE_S + 0x3400UL)
#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL)
#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL)
#define SPDIFRX_BASE_S (APB1PERIPH_BASE_S + 0x4000UL)
#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL)
#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL)
#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL)
#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL)
#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL)
#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL)
#define I2C3_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL)
#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x6000UL)
#define I3C2_BASE_S (APB1PERIPH_BASE_S + 0x6400UL)
#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL)
#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL)
#define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL)
#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL)
#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA100UL)
#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL)
#define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL)
#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL)
#define FDCAN3_BASE_S (APB1PERIPH_BASE_S + 0xE800UL)
#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xFC00UL)
/*!< AHB1 peripherals */
#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S + 0x1000UL)
#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL)
#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL)
#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL)
#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL)
#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL)
#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL)
#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL)
#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL)
#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL)
#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL)
#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL)
#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL)
#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL)
#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL)
#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL)
#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL)
#define ADC1_BASE_S (AHB1PERIPH_BASE_S + 0x2000UL)
#define ADC2_BASE_S (AHB1PERIPH_BASE_S + 0x2100UL)
#define ADC12_COMMON_BASE_S (AHB1PERIPH_BASE_S + 0x2300UL)
/*!< APB2 peripherals */
#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x0000UL)
#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x0400UL)
#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x1000UL)
#define USART6_BASE_S (APB2PERIPH_BASE_S + 0x1400UL)
#define UART9_BASE_S (APB2PERIPH_BASE_S + 0x1800UL)
#define USART10_BASE_S (APB2PERIPH_BASE_S + 0x1C00UL)
#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL)
#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x3400UL)
#define TIM18_BASE_S (APB2PERIPH_BASE_S + 0x3C00UL)
#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL)
#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL)
#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL)
#define TIM9_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL)
#define SPI5_BASE_S (APB2PERIPH_BASE_S + 0x5000UL)
#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5800UL)
#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x0004UL)
#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x0024UL)
#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5C00UL)
#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x0004UL)
#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x0024UL)
/*!< AHB2 peripherals */
#define RAMCFG_BASE_S (AHB2PERIPH_BASE_S + 0x3000UL)
#define RAMCFG_SRAM1_AXI_BASE_S (RAMCFG_BASE_S)
#define RAMCFG_SRAM2_AXI_BASE_S (RAMCFG_BASE_S + 0x0080UL)
#define RAMCFG_SRAM3_AXI_BASE_S (RAMCFG_BASE_S + 0x0100UL)
#define RAMCFG_SRAM4_AXI_BASE_S (RAMCFG_BASE_S + 0x0180UL)
#define RAMCFG_SRAM5_AXI_BASE_S (RAMCFG_BASE_S + 0x0200UL)
#define RAMCFG_SRAM6_AXI_BASE_S (RAMCFG_BASE_S + 0x0280UL)
#define RAMCFG_SRAM1_AHB_BASE_S (RAMCFG_BASE_S + 0x0300UL)
#define RAMCFG_SRAM2_AHB_BASE_S (RAMCFG_BASE_S + 0x0380UL)
#define RAMCFG_VENC_RAM_BASE_S (RAMCFG_BASE_S + 0x0400UL)
#define RAMCFG_BKPSRAM_BASE_S (RAMCFG_BASE_S + 0x0480UL)
#define RAMCFG_FLEXRAM_BASE_S (RAMCFG_BASE_S + 0x0500UL)
#define MDF1_BASE_S (AHB2PERIPH_BASE_S + 0x5000UL)
#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x0080UL)
#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x0100UL)
#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x0180UL)
#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x0200UL)
#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x0280UL)
#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x0300UL)
#define ADF1_BASE_S (AHB2PERIPH_BASE_S + 0x6000UL)
#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x0080UL)
/*!< APB3 peripherals */
#define DAP_ROM_BASE_S (APB3PERIPH_BASE_S + 0x0000UL)
#define DBGMCU_BASE_S (APB3PERIPH_BASE_S + 0x1000UL)
#define DFT_APB_BASE_S (APB3PERIPH_BASE_S + 0x2000UL)
/*!< AHB3 peripherals */
#define RNG_BASE_S (AHB3PERIPH_BASE_S + 0x0000UL)
#define HASH_BASE_S (AHB3PERIPH_BASE_S + 0x0400UL)
#define HASH_DIGEST_BASE_S (AHB3PERIPH_BASE_S + 0x0710UL)
#define CRYP_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL)
#define SAES_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL)
#define PKA_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL)
#define RIFSC_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL)
#define IAC_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL)
#define RISAF1_BASE_S (AHB3PERIPH_BASE_S + 0x6000UL)
#define RISAF2_BASE_S (AHB3PERIPH_BASE_S + 0x7000UL)
#define RISAF3_BASE_S (AHB3PERIPH_BASE_S + 0x8000UL)
#define RISAF4_BASE_S (AHB3PERIPH_BASE_S + 0x9000UL)
#define RISAF5_BASE_S (AHB3PERIPH_BASE_S + 0xA000UL)
#define RISAF6_BASE_S (AHB3PERIPH_BASE_S + 0xB000UL)
#define RISAF7_BASE_S (AHB3PERIPH_BASE_S + 0xC000UL)
#define RISAF8_BASE_S (AHB3PERIPH_BASE_S + 0xD000UL)
#define RISAF9_BASE_S (AHB3PERIPH_BASE_S + 0xE000UL)
#define RISAF11_BASE_S (AHB3PERIPH_BASE_S + 0x010000UL)
#define RISAF12_BASE_S (AHB3PERIPH_BASE_S + 0x011000UL)
#define RISAF13_BASE_S (AHB3PERIPH_BASE_S + 0x012000UL)
#define RISAF14_BASE_S (AHB3PERIPH_BASE_S + 0x013000UL)
#define RISAF15_BASE_S (AHB3PERIPH_BASE_S + 0x014000UL)
#define RISAF21_BASE_S (AHB3PERIPH_BASE_S + 0x015000UL)
#define RISAF22_BASE_S (AHB3PERIPH_BASE_S + 0x016000UL)
#define RISAF23_BASE_S (AHB3PERIPH_BASE_S + 0x017000UL)
/*!< APB4 peripherals */
#define HDP_BASE_S (APB4PERIPH_BASE_S + 0x0800UL)
#define LPUART1_BASE_S (APB4PERIPH_BASE_S + 0x0C00UL)
#define SPI6_BASE_S (APB4PERIPH_BASE_S + 0x1400UL)
#define I2C4_BASE_S (APB4PERIPH_BASE_S + 0x1C00UL)
#define LPTIM2_BASE_S (APB4PERIPH_BASE_S + 0x2400UL)
#define LPTIM3_BASE_S (APB4PERIPH_BASE_S + 0x2800UL)
#define LPTIM4_BASE_S (APB4PERIPH_BASE_S + 0x2C00UL)
#define LPTIM5_BASE_S (APB4PERIPH_BASE_S + 0x3000UL)
#define VREFBUF_BASE_S (APB4PERIPH_BASE_S + 0x3C00UL)
#define RTC_BASE_S (APB4PERIPH_BASE_S + 0x4000UL)
#define TAMP_BASE_S (APB4PERIPH_BASE_S + 0x4400UL)
#define IWDG_BASE_S (APB4PERIPH_BASE_S + 0x4800UL)
#define SERC_BASE_S (APB4PERIPH_BASE_S + 0x7C00UL)
#define SYSCFG_BASE_S (APB4PERIPH_BASE_S + 0x8000UL)
#define BSEC_BASE_S (APB4PERIPH_BASE_S + 0x9000UL)
#define DTS_BASE_S (APB4PERIPH_BASE_S + 0xA000UL)
#define DTS_Sensor0_BASE_S (DTS_BASE_S + 0x0C0UL)
#define DTS_Sensor1_BASE_S (DTS_BASE_S + 0x100UL)
/*!< AHB4 peripherals */
#define GPIOA_BASE_S (AHB4PERIPH_BASE_S + 0x0000UL)
#define GPIOB_BASE_S (AHB4PERIPH_BASE_S + 0x0400UL)
#define GPIOC_BASE_S (AHB4PERIPH_BASE_S + 0x0800UL)
#define GPIOD_BASE_S (AHB4PERIPH_BASE_S + 0x0C00UL)
#define GPIOE_BASE_S (AHB4PERIPH_BASE_S + 0x1000UL)
#define GPIOF_BASE_S (AHB4PERIPH_BASE_S + 0x1400UL)
#define GPIOG_BASE_S (AHB4PERIPH_BASE_S + 0x1800UL)
#define GPIOH_BASE_S (AHB4PERIPH_BASE_S + 0x1C00UL)
#define GPION_BASE_S (AHB4PERIPH_BASE_S + 0x3400UL)
#define GPIOO_BASE_S (AHB4PERIPH_BASE_S + 0x3800UL)
#define GPIOP_BASE_S (AHB4PERIPH_BASE_S + 0x3C00UL)
#define GPIOQ_BASE_S (AHB4PERIPH_BASE_S + 0x4000UL)
#define PWR_BASE_S (AHB4PERIPH_BASE_S + 0x4800UL)
#define CRC_BASE_S (AHB4PERIPH_BASE_S + 0x4C00UL)
#define EXTI_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL)
#define RCC_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL)
/*!< APB5 peripherals */
#define LTDC_BASE_S (APB5PERIPH_BASE_S + 0x1000UL)
#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0100UL)
#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0200UL)
#define DCMIPP_BASE_S (APB5PERIPH_BASE_S + 0x2000UL)
#define GFXTIM_BASE_S (APB5PERIPH_BASE_S + 0x4000UL)
#define VENC_BASE_S (APB5PERIPH_BASE_S + 0x5000UL)
#define CSI_BASE_S (APB5PERIPH_BASE_S + 0x6000UL)
/*!< AHB5 peripherals */
#define HPDMA1_BASE_S (AHB5PERIPH_BASE_S + 0x0000UL)
#define HPDMA1_Channel0_BASE_S (HPDMA1_BASE_S + 0x0050UL)
#define HPDMA1_Channel1_BASE_S (HPDMA1_BASE_S + 0x00D0UL)
#define HPDMA1_Channel2_BASE_S (HPDMA1_BASE_S + 0x0150UL)
#define HPDMA1_Channel3_BASE_S (HPDMA1_BASE_S + 0x01D0UL)
#define HPDMA1_Channel4_BASE_S (HPDMA1_BASE_S + 0x0250UL)
#define HPDMA1_Channel5_BASE_S (HPDMA1_BASE_S + 0x02D0UL)
#define HPDMA1_Channel6_BASE_S (HPDMA1_BASE_S + 0x0350UL)
#define HPDMA1_Channel7_BASE_S (HPDMA1_BASE_S + 0x03D0UL)
#define HPDMA1_Channel8_BASE_S (HPDMA1_BASE_S + 0x0450UL)
#define HPDMA1_Channel9_BASE_S (HPDMA1_BASE_S + 0x04D0UL)
#define HPDMA1_Channel10_BASE_S (HPDMA1_BASE_S + 0x0550UL)
#define HPDMA1_Channel11_BASE_S (HPDMA1_BASE_S + 0x05D0UL)
#define HPDMA1_Channel12_BASE_S (HPDMA1_BASE_S + 0x0650UL)
#define HPDMA1_Channel13_BASE_S (HPDMA1_BASE_S + 0x06D0UL)
#define HPDMA1_Channel14_BASE_S (HPDMA1_BASE_S + 0x0750UL)
#define HPDMA1_Channel15_BASE_S (HPDMA1_BASE_S + 0x07D0UL)
#define DMA2D_BASE_S (AHB5PERIPH_BASE_S + 0x1000UL)
#define JPEG_BASE_S (AHB5PERIPH_BASE_S + 0x3000UL)
#define FMC_R_BASE_S (AHB5PERIPH_BASE_S + 0x4000UL)
#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL)
#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL)
#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL)
#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL)
#define FMC_Common_R_BASE_S (FMC_R_BASE_S + 0x0020UL)
#define XSPI1_BASE_S (AHB5PERIPH_BASE_S + 0x5000UL)
#define PSSI_BASE_S (AHB5PERIPH_BASE_S + 0x6400UL)
#define SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6800UL)
#define DLYB_SDMMC2_BASE_S (AHB5PERIPH_BASE_S + 0x6C00UL)
#define SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x7000UL)
#define DLYB_SDMMC1_BASE_S (AHB5PERIPH_BASE_S + 0x8000UL)
#define DCMI_BASE_S (AHB5PERIPH_BASE_S + 0x8400UL)
#define XSPI2_BASE_S (AHB5PERIPH_BASE_S + 0xA000UL)
#define XSPIM_BASE_S (AHB5PERIPH_BASE_S + 0xB400UL)
#define MCE1_BASE_S (AHB5PERIPH_BASE_S + 0xB800UL)
#define MCE1_REGION1_BASE_S (MCE1_BASE_S + 0x040UL)
#define MCE1_REGION2_BASE_S (MCE1_BASE_S + 0x050UL)
#define MCE1_REGION3_BASE_S (MCE1_BASE_S + 0x060UL)
#define MCE1_REGION4_BASE_S (MCE1_BASE_S + 0x070UL)
#define MCE1_CONTEXT1_BASE_S (MCE1_BASE_S + 0x240UL)
#define MCE1_CONTEXT2_BASE_S (MCE1_BASE_S + 0x270UL)
#define MCE2_BASE_S (AHB5PERIPH_BASE_S + 0xBC00UL)
#define MCE2_REGION1_BASE_S (MCE2_BASE_S + 0x040UL)
#define MCE2_REGION2_BASE_S (MCE2_BASE_S + 0x050UL)
#define MCE2_REGION3_BASE_S (MCE2_BASE_S + 0x060UL)
#define MCE2_REGION4_BASE_S (MCE2_BASE_S + 0x070UL)
#define MCE2_CONTEXT1_BASE_S (MCE2_BASE_S + 0x240UL)
#define MCE2_CONTEXT2_BASE_S (MCE2_BASE_S + 0x270UL)
#define MCE3_BASE_S (AHB5PERIPH_BASE_S + 0xC000UL)
#define MCE3_REGION1_BASE_S (MCE3_BASE_S + 0x040UL)
#define MCE3_REGION2_BASE_S (MCE3_BASE_S + 0x050UL)
#define MCE3_REGION3_BASE_S (MCE3_BASE_S + 0x060UL)
#define MCE3_REGION4_BASE_S (MCE3_BASE_S + 0x070UL)
#define MCE3_CONTEXT1_BASE_S (MCE3_BASE_S + 0x240UL)
#define MCE3_CONTEXT2_BASE_S (MCE3_BASE_S + 0x270UL)
#define MCE4_BASE_S (AHB5PERIPH_BASE_S + 0xE000UL)
#define MCE4_REGION1_BASE_S (MCE4_BASE_S + 0x040UL)
#define MCE4_REGION2_BASE_S (MCE4_BASE_S + 0x050UL)
#define MCE4_REGION3_BASE_S (MCE4_BASE_S + 0x060UL)
#define MCE4_REGION4_BASE_S (MCE4_BASE_S + 0x070UL)
#define MCE4_CONTEXT1_BASE_S (MCE4_BASE_S + 0x240UL)
#define MCE4_CONTEXT2_BASE_S (MCE4_BASE_S + 0x270UL)
#define XSPI3_BASE_S (AHB5PERIPH_BASE_S + 0xD000UL)
#define GFXMMU_BASE_S (AHB5PERIPH_BASE_S + 0x010000UL)
#define GPU2D_BASE_S (AHB5PERIPH_BASE_S + 0x014000UL)
#define GPUCACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL)
#define ICACHE_BASE_S (AHB5PERIPH_BASE_S + 0x015000UL)
#define ETH1_BASE_S (AHB5PERIPH_BASE_S + 0x016000UL)
#define ETH1_MAC_BASE_S (ETH1_BASE_S)
#define USB1_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x01FC00UL)
#define USB2_HS_PHYC_BASE_S (AHB5PERIPH_BASE_S + 0x0A0000UL)
#define USB1_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x020000UL)
#define USB2_OTG_HS_BASE_S (AHB5PERIPH_BASE_S + 0x060000UL)
#define CACHEAXI_BASE_S (AHB5PERIPH_BASE_S + 0x0BFC00UL)
#define NPU_BASE_S (AHB5PERIPH_BASE_S + 0x0C0000UL)
/*!< Unique device ID register base address */
#define UID_BASE_S (0x56009014UL)
/*!< Revision ID base address */
#define REVID_BASE_S (BOOTROM_BASE_S + 0x0047ECUL)
#endif
/** @} */ /* End of group STM32N6xx_Peripheral_peripheralAddr */
/* =========================================================================================================================== */
/* ================ Peripheral declaration ================ */
/* =========================================================================================================================== */
/** @addtogroup STM32N6xx_Peripheral_declaration
* @{
*/
#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS)
#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS)
#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS)
#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS)
#define ADF1_Filter0_NS ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_NS)
#define BSEC_NS ((BSEC_TypeDef *) BSEC_BASE_NS)
#define CACHEAXI_NS ((CACHEAXI_TypeDef *) CACHEAXI_BASE_NS)
#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS)
#define CRYP_NS ((CRYP_TypeDef *) CRYP_BASE_NS)
#define CSI_NS ((CSI_TypeDef *) CSI_BASE_NS)
#define DBGMCU_NS ((DBGMCU_TypeDef *) DBGMCU_BASE_NS)
#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS)
#define DCMIPP_NS ((DCMIPP_TypeDef *) DCMIPP_BASE_NS)
#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS)
#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS)
#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS)
#define DTS_NS ((DTS_TypeDef *) DTS_BASE_NS)
#define DTS_Sensor0_NS ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_NS)
#define DTS_Sensor1_NS ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_NS)
#define ETH1_NS ((ETH_TypeDef *) ETH1_BASE_NS)
#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS)
#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS)
#define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS)
#define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS)
#define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS)
#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS)
#define FMC_Common_R_NS ((FMC_Common_TypeDef *) FMC_Common_R_BASE_NS)
#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS)
#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS)
#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS)
#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS)
#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS)
#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS)
#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS)
#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS)
#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS)
#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS)
#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS)
#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS)
#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS)
#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS)
#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS)
#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS)
#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS)
#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS)
#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS)
#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS)
#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS)
#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS)
#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS)
#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS)
#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS)
#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS)
#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS)
#define GPION_NS ((GPIO_TypeDef *) GPION_BASE_NS)
#define GPIOO_NS ((GPIO_TypeDef *) GPIOO_BASE_NS)
#define GPIOP_NS ((GPIO_TypeDef *) GPIOP_BASE_NS)
#define GPIOQ_NS ((GPIO_TypeDef *) GPIOQ_BASE_NS)
#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS)
#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS)
#define HPDMA1_NS ((DMA_TypeDef *) HPDMA1_BASE_NS)
#define HPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_NS)
#define HPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_NS)
#define HPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_NS)
#define HPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_NS)
#define HPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_NS)
#define HPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_NS)
#define HPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_NS)
#define HPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_NS)
#define HPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_NS)
#define HPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_NS)
#define HPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_NS)
#define HPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_NS)
#define HPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_NS)
#define HPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_NS)
#define HPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_NS)
#define HPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_NS)
#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS)
#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS)
#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS)
#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS)
#define I3C1_NS ((I3C_TypeDef *) I3C1_BASE_NS)
#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS)
#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS)
#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS)
#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS)
#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS)
#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS)
#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS)
#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS)
#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS)
#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS)
#define LTDC_NS ((LTDC_TypeDef *)LTDC_BASE_NS)
#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_NS)
#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_NS)
#define MCE1_NS ((MCE_TypeDef *) MCE1_BASE_NS)
#define MCE1_REGION1_NS ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_NS)
#define MCE1_REGION2_NS ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_NS)
#define MCE1_REGION3_NS ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_NS)
#define MCE1_REGION4_NS ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_NS)
#define MCE1_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_NS)
#define MCE1_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_NS)
#define MCE2_NS ((MCE_TypeDef *) MCE2_BASE_NS)
#define MCE2_REGION1_NS ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_NS)
#define MCE2_REGION2_NS ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_NS)
#define MCE2_REGION3_NS ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_NS)
#define MCE2_REGION4_NS ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_NS)
#define MCE2_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_NS)
#define MCE2_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_NS)
#define MCE3_NS ((MCE_TypeDef *) MCE3_BASE_NS)
#define MCE3_REGION1_NS ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_NS)
#define MCE3_REGION2_NS ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_NS)
#define MCE3_REGION3_NS ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_NS)
#define MCE3_REGION4_NS ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_NS)
#define MCE3_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_NS)
#define MCE3_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_NS)
#define MCE4_NS ((MCE_TypeDef *) MCE4_BASE_NS)
#define MCE4_REGION1_NS ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_NS)
#define MCE4_REGION2_NS ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_NS)
#define MCE4_REGION3_NS ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_NS)
#define MCE4_REGION4_NS ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_NS)
#define MCE4_CONTEXT1_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_NS)
#define MCE4_CONTEXT2_NS ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_NS)
#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS)
#define MDF1_Filter0_NS ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_NS)
#define MDF1_Filter1_NS ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_NS)
#define MDF1_Filter2_NS ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_NS)
#define MDF1_Filter3_NS ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_NS)
#define MDF1_Filter4_NS ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_NS)
#define MDF1_Filter5_NS ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_NS)
#define MDIOS_NS ((MDIOS_TypeDef *) MDIOS_BASE_NS)
#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS)
#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS)
#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS)
#define RAMCFG_NS ((RAMCFG_TypeDef *) RAMCFG_BASE_NS)
#define RAMCFG_SRAM1_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_NS)
#define RAMCFG_SRAM2_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_NS)
#define RAMCFG_SRAM3_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_NS)
#define RAMCFG_SRAM4_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_NS)
#define RAMCFG_SRAM5_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_NS)
#define RAMCFG_SRAM6_AXI_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_NS)
#define RAMCFG_SRAM1_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_NS)
#define RAMCFG_SRAM2_AHB_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_NS)
#define RAMCFG_VENC_RAM_NS ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
#define RAMCFG_BKPSRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_NS)
#define RAMCFG_FLEXRAM_NS ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_NS)
#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS)
#define RIFSC_NS ((RIFSC_TypeDef *) RIFSC_BASE_NS)
#define RISAF1_NS ((RISAF_TypeDef *) RISAF1_BASE_NS)
#define RISAF2_NS ((RISAF_TypeDef *) RISAF2_BASE_NS)
#define RISAF3_NS ((RISAF_TypeDef *) RISAF3_BASE_NS)
#define RISAF4_NS ((RISAF_TypeDef *) RISAF4_BASE_NS)
#define RISAF5_NS ((RISAF_TypeDef *) RISAF5_BASE_NS)
#define RISAF6_NS ((RISAF_TypeDef *) RISAF6_BASE_NS)
#define RISAF7_NS ((RISAF_TypeDef *) RISAF7_BASE_NS)
#define RISAF8_NS ((RISAF_TypeDef *) RISAF8_BASE_NS)
#define RISAF9_NS ((RISAF_TypeDef *) RISAF9_BASE_NS)
#define RISAF11_NS ((RISAF_TypeDef *) RISAF11_BASE_NS)
#define RISAF12_NS ((RISAF_TypeDef *) RISAF12_BASE_NS)
#define RISAF13_NS ((RISAF_TypeDef *) RISAF13_BASE_NS)
#define RISAF14_NS ((RISAF_TypeDef *) RISAF14_BASE_NS)
#define RISAF15_NS ((RISAF_TypeDef *) RISAF15_BASE_NS)
#define RISAF21_NS ((RISAF_TypeDef *) RISAF21_BASE_NS)
#define RISAF22_NS ((RISAF_TypeDef *) RISAF22_BASE_NS)
#define RISAF23_NS ((RISAF_TypeDef *) RISAF23_BASE_NS)
#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS)
#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS)
#define SAES_NS ((SAES_TypeDef *) SAES_BASE_NS)
#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS)
#define SAI1_Block_A_NS ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_NS)
#define SAI1_Block_B_NS ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_NS)
#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS)
#define SAI2_Block_A_NS ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_NS)
#define SAI2_Block_B_NS ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_NS)
#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS)
#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS)
#define SPDIFRX_NS ((SPDIFRX_TypeDef *) SPDIFRX_BASE_NS)
#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS)
#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS)
#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS)
#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS)
#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS)
#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS)
#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS)
#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS)
#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS)
#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS)
#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS)
#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS)
#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS)
#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS)
#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS)
#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS)
#define TIM9_NS ((TIM_TypeDef *) TIM9_BASE_NS)
#define TIM10_NS ((TIM_TypeDef *) TIM10_BASE_NS)
#define TIM11_NS ((TIM_TypeDef *) TIM11_BASE_NS)
#define TIM12_NS ((TIM_TypeDef *) TIM12_BASE_NS)
#define TIM13_NS ((TIM_TypeDef *) TIM13_BASE_NS)
#define TIM14_NS ((TIM_TypeDef *) TIM14_BASE_NS)
#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS)
#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS)
#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS)
#define TIM18_NS ((TIM_TypeDef *) TIM18_BASE_NS)
#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS)
#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS)
#define UART7_NS ((USART_TypeDef *) UART7_BASE_NS)
#define UART8_NS ((USART_TypeDef *) UART8_BASE_NS)
#define UART9_NS ((USART_TypeDef *) UART9_BASE_NS)
#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS)
#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS)
#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS)
#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS)
#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS)
#define USART10_NS ((USART_TypeDef *) USART10_BASE_NS)
#define USB1_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_NS)
#define USB2_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_NS)
#define USB1_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_NS)
#define USB2_HS_PHYC_NS ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_NS)
#define VENC_NS ((VENC_TypeDef *) VENC_BASE_NS)
#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS)
#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS)
#define XSPI1_NS ((XSPI_TypeDef *) XSPI1_BASE_NS)
#define XSPI2_NS ((XSPI_TypeDef *) XSPI2_BASE_NS)
#define XSPI3_NS ((XSPI_TypeDef *) XSPI3_BASE_NS)
#define XSPIM_NS ((XSPIM_TypeDef *) XSPIM_BASE_NS)
#if defined (CPU_IN_SECURE_STATE)
#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S)
#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S)
#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S)
#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S)
#define ADF1_Filter0_S ((MDF_Filter_TypeDef *) ADF1_Filter0_BASE_S)
#define BSEC_S ((BSEC_TypeDef *) BSEC_BASE_S)
#define CACHEAXI_S ((CACHEAXI_TypeDef *) CACHEAXI_BASE_S)
#define CRC_S ((CRC_TypeDef *) CRC_BASE_S)
#define CRYP_S ((CRYP_TypeDef *) CRYP_BASE_S)
#define CSI_S ((CSI_TypeDef *) CSI_BASE_S)
#define DBGMCU_S ((DBGMCU_TypeDef *) DBGMCU_BASE_S)
#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S)
#define DCMIPP_S ((DCMIPP_TypeDef *) DCMIPP_BASE_S)
#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S)
#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S)
#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S)
#define DTS_S ((DTS_TypeDef *) DTS_BASE_S)
#define DTS_Sensor0_S ((DTS_SensorTypeDef *) DTS_Sensor0_BASE_S)
#define DTS_Sensor1_S ((DTS_SensorTypeDef *) DTS_Sensor1_BASE_S)
#define ETH1_S ((ETH_TypeDef *) ETH1_BASE_S)
#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S)
#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S)
#define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S)
#define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S)
#define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S)
#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S)
#define FMC_Common_R_S ((FMC_Common_TypeDef *) FMC_Common_R_BASE_S)
#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S)
#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S)
#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S)
#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S)
#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S)
#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S)
#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S)
#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S)
#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S)
#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S)
#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S)
#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S)
#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S)
#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S)
#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S)
#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S)
#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S)
#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S)
#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S)
#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S)
#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S)
#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S)
#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S)
#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S)
#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S)
#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S)
#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S)
#define GPION_S ((GPIO_TypeDef *) GPION_BASE_S)
#define GPIOO_S ((GPIO_TypeDef *) GPIOO_BASE_S)
#define GPIOP_S ((GPIO_TypeDef *) GPIOP_BASE_S)
#define GPIOQ_S ((GPIO_TypeDef *) GPIOQ_BASE_S)
#define HASH_S ((HASH_TypeDef *) HASH_BASE_S)
#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S)
#define HPDMA1_S ((DMA_TypeDef *) HPDMA1_BASE_S)
#define HPDMA1_Channel0_S ((DMA_Channel_TypeDef *) HPDMA1_Channel0_BASE_S)
#define HPDMA1_Channel1_S ((DMA_Channel_TypeDef *) HPDMA1_Channel1_BASE_S)
#define HPDMA1_Channel2_S ((DMA_Channel_TypeDef *) HPDMA1_Channel2_BASE_S)
#define HPDMA1_Channel3_S ((DMA_Channel_TypeDef *) HPDMA1_Channel3_BASE_S)
#define HPDMA1_Channel4_S ((DMA_Channel_TypeDef *) HPDMA1_Channel4_BASE_S)
#define HPDMA1_Channel5_S ((DMA_Channel_TypeDef *) HPDMA1_Channel5_BASE_S)
#define HPDMA1_Channel6_S ((DMA_Channel_TypeDef *) HPDMA1_Channel6_BASE_S)
#define HPDMA1_Channel7_S ((DMA_Channel_TypeDef *) HPDMA1_Channel7_BASE_S)
#define HPDMA1_Channel8_S ((DMA_Channel_TypeDef *) HPDMA1_Channel8_BASE_S)
#define HPDMA1_Channel9_S ((DMA_Channel_TypeDef *) HPDMA1_Channel9_BASE_S)
#define HPDMA1_Channel10_S ((DMA_Channel_TypeDef *) HPDMA1_Channel10_BASE_S)
#define HPDMA1_Channel11_S ((DMA_Channel_TypeDef *) HPDMA1_Channel11_BASE_S)
#define HPDMA1_Channel12_S ((DMA_Channel_TypeDef *) HPDMA1_Channel12_BASE_S)
#define HPDMA1_Channel13_S ((DMA_Channel_TypeDef *) HPDMA1_Channel13_BASE_S)
#define HPDMA1_Channel14_S ((DMA_Channel_TypeDef *) HPDMA1_Channel14_BASE_S)
#define HPDMA1_Channel15_S ((DMA_Channel_TypeDef *) HPDMA1_Channel15_BASE_S)
#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S)
#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S)
#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S)
#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S)
#define I3C1_S ((I3C_TypeDef *) I3C1_BASE_S)
#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S)
#define IAC_S ((IAC_TypeDef *) IAC_BASE_S)
#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S)
#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S)
#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S)
#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S)
#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S)
#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S)
#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S)
#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S)
#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S)
#define LTDC_S ((LTDC_TypeDef *)LTDC_BASE_S)
#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE_S)
#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE_S)
#define MCE1_S ((MCE_TypeDef *) MCE1_BASE_S)
#define MCE1_REGION1_S ((MCE_Region_TypeDef *) MCE1_REGION1_BASE_S)
#define MCE1_REGION2_S ((MCE_Region_TypeDef *) MCE1_REGION2_BASE_S)
#define MCE1_REGION3_S ((MCE_Region_TypeDef *) MCE1_REGION3_BASE_S)
#define MCE1_REGION4_S ((MCE_Region_TypeDef *) MCE1_REGION4_BASE_S)
#define MCE1_CONTEXT1_S ((MCE_Context_TypeDef *) MCE1_CONTEXT1_BASE_S)
#define MCE1_CONTEXT2_S ((MCE_Context_TypeDef *) MCE1_CONTEXT2_BASE_S)
#define MCE2_S ((MCE_TypeDef *) MCE2_BASE_S)
#define MCE2_REGION1_S ((MCE_Region_TypeDef *) MCE2_REGION1_BASE_S)
#define MCE2_REGION2_S ((MCE_Region_TypeDef *) MCE2_REGION2_BASE_S)
#define MCE2_REGION3_S ((MCE_Region_TypeDef *) MCE2_REGION3_BASE_S)
#define MCE2_REGION4_S ((MCE_Region_TypeDef *) MCE2_REGION4_BASE_S)
#define MCE2_CONTEXT1_S ((MCE_Context_TypeDef *) MCE2_CONTEXT1_BASE_S)
#define MCE2_CONTEXT2_S ((MCE_Context_TypeDef *) MCE2_CONTEXT2_BASE_S)
#define MCE3_S ((MCE_TypeDef *) MCE3_BASE_S)
#define MCE3_REGION1_S ((MCE_Region_TypeDef *) MCE3_REGION1_BASE_S)
#define MCE3_REGION2_S ((MCE_Region_TypeDef *) MCE3_REGION2_BASE_S)
#define MCE3_REGION3_S ((MCE_Region_TypeDef *) MCE3_REGION3_BASE_S)
#define MCE3_REGION4_S ((MCE_Region_TypeDef *) MCE3_REGION4_BASE_S)
#define MCE3_CONTEXT1_S ((MCE_Context_TypeDef *) MCE3_CONTEXT1_BASE_S)
#define MCE3_CONTEXT2_S ((MCE_Context_TypeDef *) MCE3_CONTEXT2_BASE_S)
#define MCE4_S ((MCE_TypeDef *) MCE4_BASE_S)
#define MCE4_REGION1_S ((MCE_Region_TypeDef *) MCE4_REGION1_BASE_S)
#define MCE4_REGION2_S ((MCE_Region_TypeDef *) MCE4_REGION2_BASE_S)
#define MCE4_REGION3_S ((MCE_Region_TypeDef *) MCE4_REGION3_BASE_S)
#define MCE4_REGION4_S ((MCE_Region_TypeDef *) MCE4_REGION4_BASE_S)
#define MCE4_CONTEXT1_S ((MCE_Context_TypeDef *) MCE4_CONTEXT1_BASE_S)
#define MCE4_CONTEXT2_S ((MCE_Context_TypeDef *) MCE4_CONTEXT2_BASE_S)
#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S)
#define MDF1_Filter0_S ((MDF_Filter_TypeDef *) MDF1_Filter0_BASE_S)
#define MDF1_Filter1_S ((MDF_Filter_TypeDef *) MDF1_Filter1_BASE_S)
#define MDF1_Filter2_S ((MDF_Filter_TypeDef *) MDF1_Filter2_BASE_S)
#define MDF1_Filter3_S ((MDF_Filter_TypeDef *) MDF1_Filter3_BASE_S)
#define MDF1_Filter4_S ((MDF_Filter_TypeDef *) MDF1_Filter4_BASE_S)
#define MDF1_Filter5_S ((MDF_Filter_TypeDef *) MDF1_Filter5_BASE_S)
#define MDIOS_S ((MDIOS_TypeDef *) MDIOS_BASE_S)
#define PKA_S ((PKA_TypeDef *) PKA_BASE_S)
#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S)
#define PWR_S ((PWR_TypeDef *) PWR_BASE_S)
#define RAMCFG_S ((RAMCFG_TypeDef *) RAMCFG_BASE_S)
#define RAMCFG_SRAM1_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AXI_BASE_S)
#define RAMCFG_SRAM2_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AXI_BASE_S)
#define RAMCFG_SRAM3_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_AXI_BASE_S)
#define RAMCFG_SRAM4_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_AXI_BASE_S)
#define RAMCFG_SRAM5_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_AXI_BASE_S)
#define RAMCFG_SRAM6_AXI_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_AXI_BASE_S)
#define RAMCFG_SRAM1_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_AHB_BASE_S)
#define RAMCFG_SRAM2_AHB_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_AHB_BASE_S)
#define RAMCFG_VENC_RAM_S ((RAMCFG_TypeDef *) RAMCFG_VENC_RAM_BASE_NS)
#define RAMCFG_BKPSRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPSRAM_BASE_S)
#define RAMCFG_FLEXRAM_S ((RAMCFG_TypeDef *) RAMCFG_FLEXRAM_BASE_S)
#define RCC_S ((RCC_TypeDef *) RCC_BASE_S)
#define RIFSC_S ((RIFSC_TypeDef *) RIFSC_BASE_S)
#define RISAF1_S ((RISAF_TypeDef *) RISAF1_BASE_S)
#define RISAF2_S ((RISAF_TypeDef *) RISAF2_BASE_S)
#define RISAF3_S ((RISAF_TypeDef *) RISAF3_BASE_S)
#define RISAF4_S ((RISAF_TypeDef *) RISAF4_BASE_S)
#define RISAF5_S ((RISAF_TypeDef *) RISAF5_BASE_S)
#define RISAF6_S ((RISAF_TypeDef *) RISAF6_BASE_S)
#define RISAF7_S ((RISAF_TypeDef *) RISAF7_BASE_S)
#define RISAF8_S ((RISAF_TypeDef *) RISAF8_BASE_S)
#define RISAF9_S ((RISAF_TypeDef *) RISAF9_BASE_S)
#define RISAF11_S ((RISAF_TypeDef *) RISAF11_BASE_S)
#define RISAF12_S ((RISAF_TypeDef *) RISAF12_BASE_S)
#define RISAF13_S ((RISAF_TypeDef *) RISAF13_BASE_S)
#define RISAF14_S ((RISAF_TypeDef *) RISAF14_BASE_S)
#define RISAF15_S ((RISAF_TypeDef *) RISAF15_BASE_S)
#define RISAF21_S ((RISAF_TypeDef *) RISAF21_BASE_S)
#define RISAF22_S ((RISAF_TypeDef *) RISAF22_BASE_S)
#define RISAF23_S ((RISAF_TypeDef *) RISAF23_BASE_S)
#define RNG_S ((RNG_TypeDef *) RNG_BASE_S)
#define RTC_S ((RTC_TypeDef *) RTC_BASE_S)
#define SAES_S ((SAES_TypeDef *) SAES_BASE_S)
#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S)
#define SAI1_Block_A_S ((SAI_Block_TypeDef *) SAI1_Block_A_BASE_S)
#define SAI1_Block_B_S ((SAI_Block_TypeDef *) SAI1_Block_B_BASE_S)
#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S)
#define SAI2_Block_A_S ((SAI_Block_TypeDef *) SAI2_Block_A_BASE_S)
#define SAI2_Block_B_S ((SAI_Block_TypeDef *) SAI2_Block_B_BASE_S)
#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S)
#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S)
#define SPDIFRX_S ((SPDIFRX_TypeDef *) SPDIFRX_BASE_S)
#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S)
#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S)
#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S)
#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S)
#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S)
#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S)
#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S)
#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S)
#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S)
#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S)
#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S)
#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S)
#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S)
#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S)
#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S)
#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S)
#define TIM9_S ((TIM_TypeDef *) TIM9_BASE_S)
#define TIM10_S ((TIM_TypeDef *) TIM10_BASE_S)
#define TIM11_S ((TIM_TypeDef *) TIM11_BASE_S)
#define TIM12_S ((TIM_TypeDef *) TIM12_BASE_S)
#define TIM13_S ((TIM_TypeDef *) TIM13_BASE_S)
#define TIM14_S ((TIM_TypeDef *) TIM14_BASE_S)
#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S)
#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S)
#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S)
#define TIM18_S ((TIM_TypeDef *) TIM18_BASE_S)
#define UART4_S ((USART_TypeDef *) UART4_BASE_S)
#define UART5_S ((USART_TypeDef *) UART5_BASE_S)
#define UART7_S ((USART_TypeDef *) UART7_BASE_S)
#define UART8_S ((USART_TypeDef *) UART8_BASE_S)
#define UART9_S ((USART_TypeDef *) UART9_BASE_S)
#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S)
#define USART1_S ((USART_TypeDef *) USART1_BASE_S)
#define USART2_S ((USART_TypeDef *) USART2_BASE_S)
#define USART3_S ((USART_TypeDef *) USART3_BASE_S)
#define USART6_S ((USART_TypeDef *) USART6_BASE_S)
#define USART10_S ((USART_TypeDef *) USART10_BASE_S)
#define USB1_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_BASE_S)
#define USB2_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB2_OTG_HS_BASE_S)
#define USB1_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB1_HS_PHYC_BASE_S)
#define USB2_HS_PHYC_S ((USB_HS_PHYC_GlobalTypeDef *) USB2_HS_PHYC_BASE_S)
#define VENC_S ((VENC_TypeDef *) VENC_BASE_S)
#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S)
#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S)
#define XSPI1_S ((XSPI_TypeDef *) XSPI1_BASE_S)
#define XSPI2_S ((XSPI_TypeDef *) XSPI2_BASE_S)
#define XSPI3_S ((XSPI_TypeDef *) XSPI3_BASE_S)
#define XSPIM_S ((XSPIM_TypeDef *) XSPIM_BASE_S)
#endif
/*!< Peripheral Instance aliases for Non-Secure/Secure execution */
#if defined (CPU_IN_SECURE_STATE)
#define ADC12_COMMON ADC12_COMMON_S
#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S
#define ADC1 ADC1_S
#define ADC1_BASE ADC1_BASE_S
#define ADC2 ADC2_S
#define ADC2_BASE ADC2_BASE_S
#define ADF1 ADF1_S
#define ADF1_BASE ADF1_BASE_S
#define ADF1_Filter0 ADF1_Filter0_S
#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S
#define BSEC BSEC_S
#define BSEC_BASE BSEC_BASE_S
#define CACHEAXI CACHEAXI_S
#define CACHEAXI_BASE CACHEAXI_BASE_S
#define CRC CRC_S
#define CRC_BASE CRC_BASE_S
#define CRYP CRYP_S
#define CRYP_BASE CRYP_BASE_S
#define CSI CSI_S
#define CSI_BASE CSI_BASE_S
#define DBGMCU DBGMCU_S
#define DBGMCU_BASE DBGMCU_BASE_S
#define DCMI DCMI_S
#define DCMI_BASE DCMI_BASE_S
#define DCMIPP DCMIPP_S
#define DCMIPP_BASE DCMIPP_BASE_S
#define DLYB_SDMMC1 DLYB_SDMMC1_S
#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S
#define DLYB_SDMMC2 DLYB_SDMMC2_S
#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S
#define DMA2D DMA2D_S
#define DMA2D_BASE DMA2D_BASE_S
#define DTS DTS_S
#define DTS_BASE DTS_BASE_S
#define DTS_Sensor0 DTS_Sensor0_S
#define DTS_Sensor0_BASE DTS_Sensor0_BASE_S
#define DTS_Sensor1 DTS_Sensor1_S
#define DTS_Sensor1_BASE DTS_Sensor1_BASE_S
#define ETH1 ETH1_S
#define ETH1_BASE ETH1_BASE_S
#define EXTI EXTI_S
#define EXTI_BASE EXTI_BASE_S
#define FDCAN1 FDCAN1_S
#define FDCAN1_BASE FDCAN1_BASE_S
#define FDCAN2 FDCAN2_S
#define FDCAN2_BASE FDCAN2_BASE_S
#define FDCAN3 FDCAN3_S
#define FDCAN3_BASE FDCAN3_BASE_S
#define FDCAN_CCU FDCAN_CCU_S
#define FDCAN_CCU_BASE FDCAN_CCU_BASE_S
#define FDCAN_CONFIG FDCAN_CONFIG_S
#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S
#define FMC_R_BASE FMC_R_BASE_S
#define FMC_Bank1E_R FMC_Bank1E_R_S
#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S
#define FMC_Bank1_R FMC_Bank1_R_S
#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S
#define FMC_Bank3_R FMC_Bank3_R_S
#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S
#define FMC_Bank5_6_R FMC_Bank5_6_R_S
#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S
#define FMC_Common_R FMC_Common_R_S
#define FMC_Common_R_BASE FMC_Common_R_BASE_S
#define GFXMMU GFXMMU_S
#define GFXMMU_BASE GFXMMU_BASE_S
#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S
#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S
#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S
#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S
#define GFXTIM GFXTIM_S
#define GFXTIM_BASE GFXTIM_BASE_S
#define GPDMA1 GPDMA1_S
#define GPDMA1_BASE GPDMA1_BASE_S
#define GPDMA1_Channel0 GPDMA1_Channel0_S
#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S
#define GPDMA1_Channel1 GPDMA1_Channel1_S
#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S
#define GPDMA1_Channel2 GPDMA1_Channel2_S
#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S
#define GPDMA1_Channel3 GPDMA1_Channel3_S
#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S
#define GPDMA1_Channel4 GPDMA1_Channel4_S
#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S
#define GPDMA1_Channel5 GPDMA1_Channel5_S
#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S
#define GPDMA1_Channel6 GPDMA1_Channel6_S
#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S
#define GPDMA1_Channel7 GPDMA1_Channel7_S
#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S
#define GPDMA1_Channel8 GPDMA1_Channel8_S
#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S
#define GPDMA1_Channel9 GPDMA1_Channel9_S
#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S
#define GPDMA1_Channel10 GPDMA1_Channel10_S
#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S
#define GPDMA1_Channel11 GPDMA1_Channel11_S
#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S
#define GPDMA1_Channel12 GPDMA1_Channel12_S
#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S
#define GPDMA1_Channel13 GPDMA1_Channel13_S
#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S
#define GPDMA1_Channel14 GPDMA1_Channel14_S
#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S
#define GPDMA1_Channel15 GPDMA1_Channel15_S
#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S
#define GPIOA GPIOA_S
#define GPIOA_BASE GPIOA_BASE_S
#define GPIOB GPIOB_S
#define GPIOB_BASE GPIOB_BASE_S
#define GPIOC GPIOC_S
#define GPIOC_BASE GPIOC_BASE_S
#define GPIOD GPIOD_S
#define GPIOD_BASE GPIOD_BASE_S
#define GPIOE GPIOE_S
#define GPIOE_BASE GPIOE_BASE_S
#define GPIOF GPIOF_S
#define GPIOF_BASE GPIOF_BASE_S
#define GPIOG GPIOG_S
#define GPIOG_BASE GPIOG_BASE_S
#define GPIOH GPIOH_S
#define GPIOH_BASE GPIOH_BASE_S
#define GPION GPION_S
#define GPION_BASE GPION_BASE_S
#define GPIOO GPIOO_S
#define GPIOO_BASE GPIOO_BASE_S
#define GPIOP GPIOP_S
#define GPIOP_BASE GPIOP_BASE_S
#define GPIOQ GPIOQ_S
#define GPIOQ_BASE GPIOQ_BASE_S
#define GPU2D GPU2D_BASE_S
#define GPU2D_BASE GPU2D_BASE_S
#define HASH HASH_S
#define HASH_BASE HASH_BASE_S
#define HASH_DIGEST HASH_DIGEST_S
#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S
#define HPDMA1 HPDMA1_S
#define HPDMA1_BASE HPDMA1_BASE_S
#define HPDMA1_Channel0 HPDMA1_Channel0_S
#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_S
#define HPDMA1_Channel1 HPDMA1_Channel1_S
#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_S
#define HPDMA1_Channel2 HPDMA1_Channel2_S
#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_S
#define HPDMA1_Channel3 HPDMA1_Channel3_S
#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_S
#define HPDMA1_Channel4 HPDMA1_Channel4_S
#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_S
#define HPDMA1_Channel5 HPDMA1_Channel5_S
#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_S
#define HPDMA1_Channel6 HPDMA1_Channel6_S
#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_S
#define HPDMA1_Channel7 HPDMA1_Channel7_S
#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_S
#define HPDMA1_Channel8 HPDMA1_Channel8_S
#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_S
#define HPDMA1_Channel9 HPDMA1_Channel9_S
#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_S
#define HPDMA1_Channel10 HPDMA1_Channel10_S
#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_S
#define HPDMA1_Channel11 HPDMA1_Channel11_S
#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_S
#define HPDMA1_Channel12 HPDMA1_Channel12_S
#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_S
#define HPDMA1_Channel13 HPDMA1_Channel13_S
#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_S
#define HPDMA1_Channel14 HPDMA1_Channel14_S
#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_S
#define HPDMA1_Channel15 HPDMA1_Channel15_S
#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_S
#define I2C1 I2C1_S
#define I2C1_BASE I2C1_BASE_S
#define I2C2 I2C2_S
#define I2C2_BASE I2C2_BASE_S
#define I2C3 I2C3_S
#define I2C3_BASE I2C3_BASE_S
#define I2C4 I2C4_S
#define I2C4_BASE I2C4_BASE_S
#define I3C1 I3C1_S
#define I3C1_BASE I3C1_BASE_S
#define I3C2 I3C2_S
#define I3C2_BASE I3C2_BASE_S
#define IAC IAC_S
#define IAC_BASE IAC_BASE_S
#define ICACHE ICACHE_S
#define ICACHE_BASE ICACHE_BASE_S
#define IWDG IWDG_S
#define IWDG_BASE IWDG_BASE_S
#define JPEG JPEG_S
#define JPEG_BASE JPEG_BASE_S
#define LPTIM1 LPTIM1_S
#define LPTIM1_BASE LPTIM1_BASE_S
#define LPTIM2 LPTIM2_S
#define LPTIM2_BASE LPTIM2_BASE_S
#define LPTIM3 LPTIM3_S
#define LPTIM3_BASE LPTIM3_BASE_S
#define LPTIM4 LPTIM4_S
#define LPTIM4_BASE LPTIM4_BASE_S
#define LPTIM5 LPTIM5_S
#define LPTIM5_BASE LPTIM5_BASE_S
#define LPUART1 LPUART1_S
#define LPUART1_BASE LPUART1_BASE_S
#define LTDC LTDC_S
#define LTDC_BASE LTDC_BASE_S
#define LTDC_Layer1 LTDC_Layer1_S
#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S
#define LTDC_Layer2 LTDC_Layer2_S
#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S
#define MCE1 MCE1_S
#define MCE1_BASE MCE1_BASE_S
#define MCE1_REGION1 MCE1_REGION1_S
#define MCE1_REGION1_BASE MCE1_REGION1_BASE_S
#define MCE1_REGION2 MCE1_REGION2_S
#define MCE1_REGION2_BASE MCE1_REGION2_BASE_S
#define MCE1_REGION3 MCE1_REGION3_S
#define MCE1_REGION3_BASE MCE1_REGION3_BASE_S
#define MCE1_REGION4 MCE1_REGION4_S
#define MCE1_REGION4_BASE MCE1_REGION4_BASE_S
#define MCE1_CONTEXT1 MCE1_CONTEXT1_S
#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_S
#define MCE1_CONTEXT2 MCE1_CONTEXT2_S
#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_S
#define MCE2 MCE2_S
#define MCE2_BASE MCE2_BASE_S
#define MCE2_REGION1 MCE2_REGION1_S
#define MCE2_REGION1_BASE MCE2_REGION1_BASE_S
#define MCE2_REGION2 MCE2_REGION2_S
#define MCE2_REGION2_BASE MCE2_REGION2_BASE_S
#define MCE2_REGION3 MCE2_REGION3_S
#define MCE2_REGION3_BASE MCE2_REGION3_BASE_S
#define MCE2_REGION4 MCE2_REGION4_S
#define MCE2_REGION4_BASE MCE2_REGION4_BASE_S
#define MCE2_CONTEXT1 MCE2_CONTEXT1_S
#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_S
#define MCE2_CONTEXT2 MCE2_CONTEXT2_S
#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_S
#define MCE3 MCE3_S
#define MCE3_BASE MCE3_BASE_S
#define MCE3_REGION1 MCE3_REGION1_S
#define MCE3_REGION1_BASE MCE3_REGION1_BASE_S
#define MCE3_REGION2 MCE3_REGION2_S
#define MCE3_REGION2_BASE MCE3_REGION2_BASE_S
#define MCE3_REGION3 MCE3_REGION3_S
#define MCE3_REGION3_BASE MCE3_REGION3_BASE_S
#define MCE3_REGION4 MCE3_REGION4_S
#define MCE3_REGION4_BASE MCE3_REGION4_BASE_S
#define MCE3_CONTEXT1 MCE3_CONTEXT1_S
#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_S
#define MCE3_CONTEXT2 MCE3_CONTEXT2_S
#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_S
#define MCE4 MCE4_S
#define MCE4_BASE MCE4_BASE_S
#define MCE4_REGION1 MCE4_REGION1_S
#define MCE4_REGION1_BASE MCE4_REGION1_BASE_S
#define MCE4_REGION2 MCE4_REGION2_S
#define MCE4_REGION2_BASE MCE4_REGION2_BASE_S
#define MCE4_REGION3 MCE4_REGION3_S
#define MCE4_REGION3_BASE MCE4_REGION3_BASE_S
#define MCE4_REGION4 MCE4_REGION4_S
#define MCE4_REGION4_BASE MCE4_REGION4_BASE_S
#define MCE4_CONTEXT1 MCE4_CONTEXT1_S
#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_S
#define MCE4_CONTEXT2 MCE4_CONTEXT2_S
#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_S
#define MDF1 MDF1_S
#define MDF1_BASE MDF1_BASE_S
#define MDF1_Filter0 MDF1_Filter0_S
#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S
#define MDF1_Filter1 MDF1_Filter1_S
#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S
#define MDF1_Filter2 MDF1_Filter2_S
#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S
#define MDF1_Filter3 MDF1_Filter3_S
#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S
#define MDF1_Filter4 MDF1_Filter4_S
#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S
#define MDF1_Filter5 MDF1_Filter5_S
#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S
#define MDIOS MDIOS_S
#define MDIOS_BASE MDIOS_BASE_S
#define NPU_PRESENT
#define NPU_BASE NPU_BASE_S
#define PKA PKA_S
#define PKA_BASE PKA_BASE_S
#define PSSI PSSI_S
#define PSSI_BASE PSSI_BASE_S
#define PWR PWR_S
#define PWR_BASE PWR_BASE_S
#define RAMCFG RAMCFG_S
#define RAMCFG_BASE RAMCFG_BASE_S
#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_S
#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_S
#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_S
#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_S
#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_S
#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_S
#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_S
#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_S
#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_S
#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_S
#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_S
#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_S
#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_S
#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_S
#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_S
#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_S
#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_S
#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_S
#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_S
#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_S
#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_S
#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_S
#define RCC RCC_S
#define RCC_BASE RCC_BASE_S
#define RIFSC RIFSC_S
#define RIFSC_BASE RIFSC_BASE_S
#define RISAF1 RISAF1_S
#define RISAF1_BASE RISAF1_BASE_S
#define RISAF2 RISAF2_S
#define RISAF2_BASE RISAF2_BASE_S
#define RISAF3 RISAF3_S
#define RISAF3_BASE RISAF3_BASE_S
#define RISAF4 RISAF4_S
#define RISAF4_BASE RISAF4_BASE_S
#define RISAF5 RISAF5_S
#define RISAF5_BASE RISAF5_BASE_S
#define RISAF6 RISAF6_S
#define RISAF6_BASE RISAF6_BASE_S
#define RISAF7 RISAF7_S
#define RISAF7_BASE RISAF7_BASE_S
#define RISAF8 RISAF8_S
#define RISAF8_BASE RISAF8_BASE_S
#define RISAF9 RISAF9_S
#define RISAF9_BASE RISAF9_BASE_S
#define RISAF11 RISAF11_S
#define RISAF11_BASE RISAF11_BASE_S
#define RISAF12 RISAF12_S
#define RISAF12_BASE RISAF12_BASE_S
#define RISAF13 RISAF13_S
#define RISAF13_BASE RISAF13_BASE_S
#define RISAF14 RISAF14_S
#define RISAF14_BASE RISAF14_BASE_S
#define RISAF15 RISAF15_S
#define RISAF15_BASE RISAF15_BASE_S
#define RISAF21 RISAF21_S
#define RISAF21_BASE RISAF21_BASE_S
#define RISAF22 RISAF22_S
#define RISAF22_BASE RISAF22_BASE_S
#define RISAF23 RISAF23_S
#define RISAF23_BASE RISAF23_BASE_S
#define RNG RNG_S
#define RNG_BASE RNG_BASE_S
#define RTC RTC_S
#define RTC_BASE RTC_BASE_S
#define SAES SAES_S
#define SAES_BASE SAES_BASE_S
#define SAI1 SAI1_S
#define SAI1_BASE SAI1_BASE_S
#define SAI1_Block_A SAI1_Block_A_S
#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S
#define SAI1_Block_B SAI1_Block_B_S
#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S
#define SAI2 SAI2_S
#define SAI2_BASE SAI2_BASE_S
#define SAI2_Block_A SAI2_Block_A_S
#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S
#define SAI2_Block_B SAI2_Block_B_S
#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S
#define SDMMC1 SDMMC1_S
#define SDMMC1_BASE SDMMC1_BASE_S
#define SDMMC2 SDMMC2_S
#define SDMMC2_BASE SDMMC2_BASE_S
#define SPDIFRX SPDIFRX_S
#define SPDIFRX_BASE SPDIFRX_BASE_S
#define SPI1 SPI1_S
#define SPI1_BASE SPI1_BASE_S
#define SPI2 SPI2_S
#define SPI2_BASE SPI2_BASE_S
#define SPI3 SPI3_S
#define SPI3_BASE SPI3_BASE_S
#define SPI4 SPI4_S
#define SPI4_BASE SPI4_BASE_S
#define SPI5 SPI5_S
#define SPI5_BASE SPI5_BASE_S
#define SPI6 SPI6_S
#define SPI6_BASE SPI6_BASE_S
#define SRAMCAN_BASE SRAMCAN_BASE_S
#define SYSCFG SYSCFG_S
#define SYSCFG_BASE SYSCFG_BASE_S
#define TAMP TAMP_S
#define TAMP_BASE TAMP_BASE_S
#define TIM1 TIM1_S
#define TIM1_BASE TIM1_BASE_S
#define TIM2 TIM2_S
#define TIM2_BASE TIM2_BASE_S
#define TIM3 TIM3_S
#define TIM3_BASE TIM3_BASE_S
#define TIM4 TIM4_S
#define TIM4_BASE TIM4_BASE_S
#define TIM5 TIM5_S
#define TIM5_BASE TIM5_BASE_S
#define TIM6 TIM6_S
#define TIM6_BASE TIM6_BASE_S
#define TIM7 TIM7_S
#define TIM7_BASE TIM7_BASE_S
#define TIM8 TIM8_S
#define TIM8_BASE TIM8_BASE_S
#define TIM9 TIM9_S
#define TIM9_BASE TIM9_BASE_S
#define TIM10 TIM10_S
#define TIM10_BASE TIM10_BASE_S
#define TIM11 TIM11_S
#define TIM11_BASE TIM11_BASE_S
#define TIM12 TIM12_S
#define TIM12_BASE TIM12_BASE_S
#define TIM13 TIM13_S
#define TIM13_BASE TIM13_BASE_S
#define TIM14 TIM14_S
#define TIM14_BASE TIM14_BASE_S
#define TIM15 TIM15_S
#define TIM15_BASE TIM15_BASE_S
#define TIM16 TIM16_S
#define TIM16_BASE TIM16_BASE_S
#define TIM17 TIM17_S
#define TIM17_BASE TIM17_BASE_S
#define TIM18 TIM18_S
#define TIM18_BASE TIM18_BASE_S
#define UART4 UART4_S
#define UART4_BASE UART4_BASE_S
#define UART5 UART5_S
#define UART5_BASE UART5_BASE_S
#define UART7 UART7_S
#define UART7_BASE UART7_BASE_S
#define UART8 UART8_S
#define UART8_BASE UART8_BASE_S
#define UART9 UART9_S
#define UART9_BASE UART9_BASE_S
#define UCPD1 UCPD1_S
#define UCPD1_BASE UCPD1_BASE_S
#define USART1 USART1_S
#define USART1_BASE USART1_BASE_S
#define USART2 USART2_S
#define USART2_BASE USART2_BASE_S
#define USART3 USART3_S
#define USART3_BASE USART3_BASE_S
#define USART6 USART6_S
#define USART6_BASE USART6_BASE_S
#define USART10 USART10_S
#define USART10_BASE USART10_BASE_S
#define USB1_OTG_HS USB1_OTG_HS_S
#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_S
#define USB2_OTG_HS USB2_OTG_HS_S
#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_S
#define USB1_HS_PHYC USB1_HS_PHYC_S
#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_S
#define USB2_HS_PHYC USB2_HS_PHYC_S
#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_S
#define VENC VENC_S
#define VENC_BASE VENC_BASE_S
#define VREFBUF VREFBUF_S
#define VREFBUF_BASE VREFBUF_BASE_S
#define WWDG WWDG_S
#define WWDG_BASE WWDG_BASE_S
#define XSPI1 XSPI1_S
#define XSPI2 XSPI2_S
#define XSPI3 XSPI3_S
#define XSPIM XSPIM_S
#define XSPIM_BASE XSPIM_BASE_S
/*!< Unique device ID register base address */
#define UID_BASE UID_BASE_S
/*!< Revision ID base address */
#define REVID_BASE REVID_BASE_S
#else
#define ADC12_COMMON ADC12_COMMON_NS
#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS
#define ADC1 ADC1_NS
#define ADC1_BASE ADC1_BASE_NS
#define ADC2 ADC2_NS
#define ADC2_BASE ADC2_BASE_NS
#define ADF1 ADF1_NS
#define ADF1_BASE ADF1_BASE_NS
#define ADF1_Filter0 ADF1_Filter0_NS
#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS
#define BSEC BSEC_NS
#define BSEC_BASE BSEC_BASE_NS
#define CACHEAXI CACHEAXI_NS
#define CACHEAXI_BASE CACHEAXI_BASE_NS
#define CRC CRC_NS
#define CRC_BASE CRC_BASE_NS
#define CRYP CRYP_NS
#define CRYP_BASE CRYP_BASE_NS
#define CSI CSI_NS
#define CSI_BASE CSI_BASE_NS
#define DBGMCU DBGMCU_NS
#define DBGMCU_BASE DBGMCU_BASE_NS
#define DCMI DCMI_NS
#define DCMI_BASE DCMI_BASE_NS
#define DCMIPP DCMIPP_NS
#define DCMIPP_BASE DCMIPP_BASE_NS
#define DLYB_SDMMC1 DLYB_SDMMC1_NS
#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS
#define DLYB_SDMMC2 DLYB_SDMMC2_NS
#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS
#define DMA2D DMA2D_NS
#define DMA2D_BASE DMA2D_BASE_NS
#define DTS DTS_NS
#define DTS_BASE DTS_BASE_NS
#define DTS_Sensor0 DTS_Sensor0_NS
#define DTS_Sensor0_BASE DTS_Sensor0_BASE_NS
#define DTS_Sensor1 DTS_Sensor1_NS
#define DTS_Sensor1_BASE DTS_Sensor1_BASE_NS
#define ETH1 ETH1_NS
#define ETH1_BASE ETH1_BASE_NS
#define EXTI EXTI_NS
#define EXTI_BASE EXTI_BASE_NS
#define FDCAN1 FDCAN1_NS
#define FDCAN1_BASE FDCAN1_BASE_NS
#define FDCAN2 FDCAN2_NS
#define FDCAN2_BASE FDCAN2_BASE_NS
#define FDCAN3 FDCAN3_NS
#define FDCAN3_BASE FDCAN3_BASE_NS
#define FDCAN_CCU FDCAN_CCU_NS
#define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS
#define FDCAN_CONFIG FDCAN_CONFIG_NS
#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS
#define FMC_R_BASE FMC_R_BASE_NS
#define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS
#define FMC_Bank1E_R FMC_Bank1E_R_NS
#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS
#define FMC_Bank1_R FMC_Bank1_R_NS
#define FMC_Bank1_Rv FMC_Bank1_R_BASE_NS
#define FMC_Bank3_R FMC_Bank3_R_NS
#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS
#define FMC_Bank5_6_R FMC_Bank5_6_R_NS
#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS
#define FMC_Common_R FMC_Common_R_NS
#define FMC_Common_R_BASE FMC_Common_R_BASE_NS
#define GFXMMU GFXMMU_NS
#define GFXMMU_BASE GFXMMU_BASE_NS
#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS
#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS
#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS
#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS
#define GFXTIM GFXTIM_NS
#define GFXTIM_BASE GFXTIM_BASE_NS
#define GPDMA1 GPDMA1_NS
#define GPDMA1_BASE GPDMA1_BASE_NS
#define GPDMA1_Channel0 GPDMA1_Channel0_NS
#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS
#define GPDMA1_Channel1 GPDMA1_Channel1_NS
#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS
#define GPDMA1_Channel2 GPDMA1_Channel2_NS
#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS
#define GPDMA1_Channel3 GPDMA1_Channel3_NS
#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS
#define GPDMA1_Channel4 GPDMA1_Channel4_NS
#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS
#define GPDMA1_Channel5 GPDMA1_Channel5_NS
#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS
#define GPDMA1_Channel6 GPDMA1_Channel6_NS
#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS
#define GPDMA1_Channel7 GPDMA1_Channel7_NS
#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS
#define GPDMA1_Channel8 GPDMA1_Channel8_NS
#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS
#define GPDMA1_Channel9 GPDMA1_Channel9_NS
#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS
#define GPDMA1_Channel10 GPDMA1_Channel10_NS
#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS
#define GPDMA1_Channel11 GPDMA1_Channel11_NS
#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS
#define GPDMA1_Channel12 GPDMA1_Channel12_NS
#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS
#define GPDMA1_Channel13 GPDMA1_Channel13_NS
#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS
#define GPDMA1_Channel14 GPDMA1_Channel14_NS
#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS
#define GPDMA1_Channel15 GPDMA1_Channel15_NS
#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS
#define GPIOA GPIOA_NS
#define GPIOA_BASE GPIOA_BASE_NS
#define GPIOB GPIOB_NS
#define GPIOB_BASE GPIOB_BASE_NS
#define GPIOC GPIOC_NS
#define GPIOC_BASE GPIOC_BASE_NS
#define GPIOD GPIOD_NS
#define GPIOD_BASE GPIOD_BASE_NS
#define GPIOE GPIOE_NS
#define GPIOE_BASE GPIOE_BASE_NS
#define GPIOF GPIOF_NS
#define GPIOF_BASE GPIOF_BASE_NS
#define GPIOG GPIOG_NS
#define GPIOG_BASE GPIOG_BASE_NS
#define GPIOH GPIOH_NS
#define GPIOH_BASE GPIOH_BASE_NS
#define GPION GPION_NS
#define GPION_BASE GPION_BASE_NS
#define GPIOO GPIOO_NS
#define GPIOO_BASE GPIOO_BASE_NS
#define GPIOP GPIOP_NS
#define GPIOP_BASE GPIOP_BASE_NS
#define GPIOQ GPIOQ_NS
#define GPIOQ_BASE GPIOQ_BASE_NS
#define GPU2D GPU2D_BASE_NS
#define GPU2D_BASE GPU2D_BASE_NS
#define HASH HASH_NS
#define HASH_BASE HASH_BASE_NS
#define HASH_DIGEST HASH_DIGEST_NS
#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS
#define HPDMA1 HPDMA1_NS
#define HPDMA1_BASE HPDMA1_BASE_NS
#define HPDMA1_Channel0 HPDMA1_Channel0_NS
#define HPDMA1_Channel0_BASE HPDMA1_Channel0_BASE_NS
#define HPDMA1_Channel1 HPDMA1_Channel1_NS
#define HPDMA1_Channel1_BASE HPDMA1_Channel1_BASE_NS
#define HPDMA1_Channel2 HPDMA1_Channel2_NS
#define HPDMA1_Channel2_BASE HPDMA1_Channel2_BASE_NS
#define HPDMA1_Channel3 HPDMA1_Channel3_NS
#define HPDMA1_Channel3_BASE HPDMA1_Channel3_BASE_NS
#define HPDMA1_Channel4 HPDMA1_Channel4_NS
#define HPDMA1_Channel4_BASE HPDMA1_Channel4_BASE_NS
#define HPDMA1_Channel5 HPDMA1_Channel5_NS
#define HPDMA1_Channel5_BASE HPDMA1_Channel5_BASE_NS
#define HPDMA1_Channel6 HPDMA1_Channel6_NS
#define HPDMA1_Channel6_BASE HPDMA1_Channel6_BASE_NS
#define HPDMA1_Channel7 HPDMA1_Channel7_NS
#define HPDMA1_Channel7_BASE HPDMA1_Channel7_BASE_NS
#define HPDMA1_Channel8 HPDMA1_Channel8_NS
#define HPDMA1_Channel8_BASE HPDMA1_Channel8_BASE_NS
#define HPDMA1_Channel9 HPDMA1_Channel9_NS
#define HPDMA1_Channel9_BASE HPDMA1_Channel9_BASE_NS
#define HPDMA1_Channel10 HPDMA1_Channel10_NS
#define HPDMA1_Channel10_BASE HPDMA1_Channel10_BASE_NS
#define HPDMA1_Channel11 HPDMA1_Channel11_NS
#define HPDMA1_Channel11_BASE HPDMA1_Channel11_BASE_NS
#define HPDMA1_Channel12 HPDMA1_Channel12_NS
#define HPDMA1_Channel12_BASE HPDMA1_Channel12_BASE_NS
#define HPDMA1_Channel13 HPDMA1_Channel13_NS
#define HPDMA1_Channel13_BASE HPDMA1_Channel13_BASE_NS
#define HPDMA1_Channel14 HPDMA1_Channel14_NS
#define HPDMA1_Channel14_BASE HPDMA1_Channel14_BASE_NS
#define HPDMA1_Channel15 HPDMA1_Channel15_NS
#define HPDMA1_Channel15_BASE HPDMA1_Channel15_BASE_NS
#define I2C1 I2C1_NS
#define I2C1_BASE I2C1_BASE_NS
#define I2C2 I2C2_NS
#define I2C2_BASE I2C2_BASE_NS
#define I2C3 I2C3_NS
#define I2C3_BASE I2C3_BASE_NS
#define I2C4 I2C4_NS
#define I2C4_BASE I2C4_BASE_NS
#define I3C1 I3C1_NS
#define I3C1_BASE I3C1_BASE_NS
#define I3C2 I3C2_NS
#define I3C2_BASE I3C2_BASE_NS
#define ICACHE ICACHE_NS
#define ICACHE_BASE ICACHE_BASE_NS
#define IWDG IWDG_NS
#define IWDG_BASE IWDG_BASE_NS
#define JPEG JPEG_NS
#define JPEG_BASE JPEG_BASE_NS
#define LPTIM1 LPTIM1_NS
#define LPTIM1_BASE LPTIM1_BASE_NS
#define LPTIM2 LPTIM2_NS
#define LPTIM2_BASE LPTIM2_BASE_NS
#define LPTIM3 LPTIM3_NS
#define LPTIM3_BASE LPTIM3_BASE_NS
#define LPTIM4 LPTIM4_NS
#define LPTIM4_BASE LPTIM4_BASE_NS
#define LPTIM5 LPTIM5_NS
#define LPTIM5_BASE LPTIM5_BASE_NS
#define LPUART1 LPUART1_NS
#define LPUART1_BASE LPUART1_BASE_NS
#define LTDC LTDC_NS
#define LTDC_BASE LTDC_BASE_NS
#define LTDC_Layer1 LTDC_Layer1_NS
#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS
#define LTDC_Layer2 LTDC_Layer2_NS
#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS
#define MCE1 MCE1_NS
#define MCE1_BASE MCE1_BASE_NS
#define MCE1_REGION1 MCE1_REGION1_NS
#define MCE1_REGION1_BASE MCE1_REGION1_BASE_NS
#define MCE1_REGION2 MCE1_REGION2_NS
#define MCE1_REGION2_BASE MCE1_REGION2_BASE_NS
#define MCE1_REGION3 MCE1_REGION3_NS
#define MCE1_REGION3_BASE MCE1_REGION3_BASE_NS
#define MCE1_REGION4 MCE1_REGION4_NS
#define MCE1_REGION4_BASE MCE1_REGION4_BASE_NS
#define MCE1_CONTEXT1 MCE1_CONTEXT1_NS
#define MCE1_CONTEXT1_BASE MCE1_CONTEXT1_BASE_NS
#define MCE1_CONTEXT2 MCE1_CONTEXT2_NS
#define MCE1_CONTEXT2_BASE MCE1_CONTEXT2_BASE_NS
#define MCE2 MCE2_NS
#define MCE2_BASE MCE2_BASE_NS
#define MCE2_REGION1 MCE2_REGION1_NS
#define MCE2_REGION1_BASE MCE2_REGION1_BASE_NS
#define MCE2_REGION2 MCE2_REGION2_NS
#define MCE2_REGION2_BASE MCE2_REGION2_BASE_NS
#define MCE2_REGION3 MCE2_REGION3_NS
#define MCE2_REGION3_BASE MCE2_REGION3_BASE_NS
#define MCE2_REGION4 MCE2_REGION4_NS
#define MCE2_REGION4_BASE MCE2_REGION4_BASE_NS
#define MCE2_CONTEXT1 MCE2_CONTEXT1_NS
#define MCE2_CONTEXT1_BASE MCE2_CONTEXT1_BASE_NS
#define MCE2_CONTEXT2 MCE2_CONTEXT2_NS
#define MCE2_CONTEXT2_BASE MCE2_CONTEXT2_BASE_NS
#define MCE3 MCE3_NS
#define MCE3_BASE MCE3_BASE_NS
#define MCE3_REGION1 MCE3_REGION1_NS
#define MCE3_REGION1_BASE MCE3_REGION1_BASE_NS
#define MCE3_REGION2 MCE3_REGION2_NS
#define MCE3_REGION2_BASE MCE3_REGION2_BASE_NS
#define MCE3_REGION3 MCE3_REGION3_NS
#define MCE3_REGION3_BASE MCE3_REGION3_BASE_NS
#define MCE3_REGION4 MCE3_REGION4_NS
#define MCE3_REGION4_BASE MCE3_REGION4_BASE_NS
#define MCE3_CONTEXT1 MCE3_CONTEXT1_NS
#define MCE3_CONTEXT1_BASE MCE3_CONTEXT1_BASE_NS
#define MCE3_CONTEXT2 MCE3_CONTEXT2_NS
#define MCE3_CONTEXT2_BASE MCE3_CONTEXT2_BASE_NS
#define MCE4 MCE4_NS
#define MCE4_BASE MCE4_BASE_NS
#define MCE4_REGION1 MCE4_REGION1_NS
#define MCE4_REGION1_BASE MCE4_REGION1_BASE_NS
#define MCE4_REGION2 MCE4_REGION2_NS
#define MCE4_REGION2_BASE MCE4_REGION2_BASE_NS
#define MCE4_REGION3 MCE4_REGION3_NS
#define MCE4_REGION3_BASE MCE4_REGION3_BASE_NS
#define MCE4_REGION4 MCE4_REGION4_NS
#define MCE4_REGION4_BASE MCE4_REGION4_BASE_NS
#define MCE4_CONTEXT1 MCE4_CONTEXT1_NS
#define MCE4_CONTEXT1_BASE MCE4_CONTEXT1_BASE_NS
#define MCE4_CONTEXT2 MCE4_CONTEXT2_NS
#define MCE4_CONTEXT2_BASE MCE4_CONTEXT2_BASE_NS
#define MDF1 MDF1_NS
#define MDF1_BASE MDF1_BASE_NS
#define MDF1_Filter0 MDF1_Filter0_NS
#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS
#define MDF1_Filter1 MDF1_Filter1_NS
#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS
#define MDF1_Filter2 MDF1_Filter2_NS
#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS
#define MDF1_Filter3 MDF1_Filter3_NS
#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS
#define MDF1_Filter4 MDF1_Filter4_NS
#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS
#define MDF1_Filter5 MDF1_Filter5_NS
#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS
#define MDIOS MDIOS_NS
#define MDIOS_BASE MDIOS_BASE_NS
#define NPU_PRESENT
#define NPU_BASE NPU_BASE_NS
#define PKA PKA_NS
#define PKA_BASE PKA_BASE_NS
#define PSSI PSSI_NS
#define PSSI_BASE PSSI_BASE_NS
#define PWR PWR_NS
#define PWR_BASE PWR_BASE_NS
#define RAMCFG RAMCFG_NS
#define RAMCFG_BASE RAMCFG_BASE_NS
#define RAMCFG_SRAM1_AXI RAMCFG_SRAM1_AXI_NS
#define RAMCFG_SRAM1_AXI_BASE RAMCFG_SRAM1_AXI_BASE_NS
#define RAMCFG_SRAM2_AXI RAMCFG_SRAM2_AXI_NS
#define RAMCFG_SRAM2_AXI_BASE RAMCFG_SRAM2_AXI_BASE_NS
#define RAMCFG_SRAM3_AXI RAMCFG_SRAM3_AXI_NS
#define RAMCFG_SRAM3_AXI_BASE RAMCFG_SRAM3_AXI_BASE_NS
#define RAMCFG_SRAM4_AXI RAMCFG_SRAM4_AXI_NS
#define RAMCFG_SRAM4_AXI_BASE RAMCFG_SRAM4_AXI_BASE_NS
#define RAMCFG_SRAM5_AXI RAMCFG_SRAM5_AXI_NS
#define RAMCFG_SRAM5_AXI_BASE RAMCFG_SRAM5_AXI_BASE_NS
#define RAMCFG_SRAM6_AXI RAMCFG_SRAM6_AXI_NS
#define RAMCFG_SRAM6_AXI_BASE RAMCFG_SRAM6_AXI_BASE_NS
#define RAMCFG_SRAM1_AHB RAMCFG_SRAM1_AHB_NS
#define RAMCFG_SRAM1_AHB_BASE RAMCFG_SRAM1_AHB_BASE_NS
#define RAMCFG_SRAM2_AHB RAMCFG_SRAM2_AHB_NS
#define RAMCFG_SRAM2_AHB_BASE RAMCFG_SRAM2_AHB_BASE_NS
#define RAMCFG_VENC_RAM RAMCFG_VENC_RAM_NS
#define RAMCFG_VENC_RAM_BASE RAMCFG_VENC_RAM_BASE_NS
#define RAMCFG_BKPSRAM RAMCFG_BKPSRAM_NS
#define RAMCFG_BKPSRAM_BASE RAMCFG_BKPSRAM_BASE_NS
#define RAMCFG_FLEXRAM RAMCFG_FLEXRAM_NS
#define RAMCFG_FLEXRAM_BASE RAMCFG_FLEXRAM_BASE_NS
#define RCC RCC_NS
#define RCC_BASE RCC_BASE_NS
#define RIFSC RIFSC_NS
#define RIFSC_BASE RIFSC_BASE_NS
#define RISAF1 RISAF1_NS
#define RISAF1_BASE RISAF1_BASE_NS
#define RISAF2 RISAF2_NS
#define RISAF2_BASE RISAF2_BASE_NS
#define RISAF3 RISAF3_NS
#define RISAF3_BASE RISAF3_BASE_NS
#define RISAF4 RISAF4_NS
#define RISAF4_BASE RISAF4_BASE_NS
#define RISAF5 RISAF5_NS
#define RISAF5_BASE RISAF5_BASE_NS
#define RISAF6 RISAF6_NS
#define RISAF6_BASE RISAF6_BASE_NS
#define RISAF7 RISAF7_NS
#define RISAF7_BASE RISAF7_BASE_NS
#define RISAF8 RISAF8_NS
#define RISAF8_BASE RISAF8_BASE_NS
#define RISAF9 RISAF9_NS
#define RISAF9_BASE RISAF9_BASE_NS
#define RISAF11 RISAF11_NS
#define RISAF11_BASE RISAF11_BASE_NS
#define RISAF12 RISAF12_NS
#define RISAF12_BASE RISAF12_BASE_NS
#define RISAF13 RISAF13_NS
#define RISAF13_BASE RISAF13_BASE_NS
#define RISAF14 RISAF14_NS
#define RISAF14_BASE RISAF14_BASE_NS
#define RISAF15 RISAF15_NS
#define RISAF15_BASE RISAF15_BASE_NS
#define RISAF21 RISAF21_NS
#define RISAF21_BASE RISAF21_BASE_NS
#define RISAF22 RISAF22_NS
#define RISAF22_BASE RISAF22_BASE_NS
#define RISAF23 RISAF23_NS
#define RISAF23_BASE RISAF23_BASE_NS
#define RNG RNG_NS
#define RNG_BASE RNG_BASE_NS
#define RTC RTC_NS
#define RTC_BASE RTC_BASE_NS
#define SAES SAES_NS
#define SAES_BASE SAES_BASE_NS
#define SAI1 SAI1_NS
#define SAI1_BASE SAI1_BASE_NS
#define SAI1_Block_A SAI1_Block_A_NS
#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS
#define SAI1_Block_B SAI1_Block_B_NS
#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS
#define SAI2 SAI2_NS
#define SAI2_BASE SAI2_BASE_NS
#define SAI2_Block_A SAI2_Block_A_NS
#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS
#define SAI2_Block_B SAI2_Block_B_NS
#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS
#define SDMMC1 SDMMC1_NS
#define SDMMC1_BASE SDMMC1_BASE_NS
#define SDMMC2 SDMMC2_NS
#define SDMMC2_BASE SDMMC2_BASE_NS
#define SPDIFRX SPDIFRX_NS
#define SPDIFRX_BASE SPDIFRX_BASE_NS
#define SPI1 SPI1_NS
#define SPI1_BASE SPI1_BASE_NS
#define SPI2 SPI2_NS
#define SPI2_BASE SPI2_BASE_NS
#define SPI3 SPI3_NS
#define SPI3_BASE SPI3_BASE_NS
#define SPI4 SPI4_NS
#define SPI4_BASE SPI4_BASE_NS
#define SPI5 SPI5_NS
#define SPI5_BASE SPI5_BASE_NS
#define SPI6 SPI6_NS
#define SPI6_BASE SPI6_BASE_NS
#define SRAMCAN_BASE SRAMCAN_BASE_NS
#define SYSCFG SYSCFG_NS
#define SYSCFG_BASE SYSCFG_BASE_NS
#define TAMP TAMP_NS
#define TAMP_BASE TAMP_BASE_NS
#define TIM1 TIM1_NS
#define TIM1_BASE TIM1_BASE_NS
#define TIM2 TIM2_NS
#define TIM2_BASE TIM2_BASE_NS
#define TIM3 TIM3_NS
#define TIM3_BASE TIM3_BASE_NS
#define TIM4 TIM4_NS
#define TIM4_BASE TIM4_BASE_NS
#define TIM5 TIM5_NS
#define TIM5_BASE TIM5_BASE_NS
#define TIM6 TIM6_NS
#define TIM6_BASE TIM6_BASE_NS
#define TIM7 TIM7_NS
#define TIM7_BASE TIM7_BASE_NS
#define TIM8 TIM8_NS
#define TIM8_BASE TIM8_BASE_NS
#define TIM9 TIM9_NS
#define TIM9_BASE TIM9_BASE_NS
#define TIM10 TIM10_NS
#define TIM10_BASE TIM10_BASE_NS
#define TIM11 TIM11_NS
#define TIM11_BASE TIM11_BASE_NS
#define TIM12 TIM12_NS
#define TIM12_BASE TIM12_BASE_NS
#define TIM13 TIM13_NS
#define TIM13_BASE TIM13_BASE_NS
#define TIM14 TIM14_NS
#define TIM14_BASE TIM14_BASE_NS
#define TIM15 TIM15_NS
#define TIM15_BASE TIM15_BASE_NS
#define TIM16 TIM16_NS
#define TIM16_BASE TIM16_BASE_NS
#define TIM17 TIM17_NS
#define TIM17_BASE TIM17_BASE_NS
#define TIM18 TIM18_NS
#define TIM18_BASE TIM18_BASE_NS
#define UART4 UART4_NS
#define UART4_BASE UART4_BASE_NS
#define UART5 UART5_NS
#define UART5_BASE UART5_BASE_NS
#define UART7 UART7_NS
#define UART7_BASE UART7_BASE_NS
#define UART8 UART8_NS
#define UART8_BASE UART8_BASE_NS
#define UART9 UART9_NS
#define UART9_BASE UART9_BASE_NS
#define UCPD1 UCPD1_NS
#define UCPD1_BASE UCPD1_BASE_NS
#define USART1 USART1_NS
#define USART1_BASE USART1_BASE_NS
#define USART2 USART2_NS
#define USART2_BASE USART2_BASE_NS
#define USART3 USART3_NS
#define USART3_BASE USART3_BASE_NS
#define USART6 USART6_NS
#define USART6_BASE USART6_BASE_NS
#define USART10 USART10_NS
#define USART10_BASE USART10_BASE_NS
#define USB1_OTG_HS USB1_OTG_HS_NS
#define USB1_OTG_HS_BASE USB1_OTG_HS_BASE_NS
#define USB2_OTG_HS USB2_OTG_HS_NS
#define USB2_OTG_HS_BASE USB2_OTG_HS_BASE_NS
#define USB1_HS_PHYC USB1_HS_PHYC_NS
#define USB1_HS_PHYC_BASE USB1_HS_PHYC_BASE_NS
#define USB2_HS_PHYC USB2_HS_PHYC_NS
#define USB2_HS_PHYC_BASE USB2_HS_PHYC_BASE_NS
#define VENC VENC_NS
#define VENC_BASE VENC_BASE_NS
#define VREFBUF VREFBUF_NS
#define VREFBUF_BASE VREFBUF_BASE_NS
#define WWDG WWDG_NS
#define WWDG_BASE WWDG_BASE_NS
#define XSPI1 XSPI1_NS
#define XSPI2 XSPI2_NS
#define XSPI3 XSPI3_NS
#define XSPIM XSPIM_NS
#define XSPIM_BASE XSPIM_BASE_NS
/*!< Unique device ID register base address */
#define UID_BASE UID_BASE_NS
/*!< Revision ID base address */
#define REVID_BASE REVID_BASE_NS
#endif
/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
/** @addtogroup STM32N6xx_Peripheral_Timing_Definition
* @{
*/
#define LSI_STARTUP_TIME 16000U /*!< LSI Maximum startup time in us : 4 cycles @ 250 Hz = 16 ms */
/** @} */ /* End of group STM32N6xx_Peripheral_Timing_Definition */
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* */
/* Analog to Digital Converter (ADC) */
/* */
/******************************************************************************/
/* Specific device feature definitions */
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR1 register ******************/
#define ADC_CFGR1_DMNGT_Pos (0U)
#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */
#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC data management configuration */
#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */
#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */
#define ADC_CFGR1_RES_Pos (2U)
#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */
#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */
#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR1_EXTSEL_Pos (5U)
#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR1_EXTEN_Pos (10U)
#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR1_OVRMOD_Pos (12U)
#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR1_CONT_Pos (13U)
#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR1_AUTDLY_Pos (14U)
#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR1_DISCEN_Pos (16U)
#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR1_DISCNUM_Pos (17U)
#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR1_JDISCEN_Pos (20U)
#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR1_AWD1SGL_Pos (22U)
#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR1_AWD1EN_Pos (23U)
#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR1_JAWD1EN_Pos (24U)
#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR1_JAUTO_Pos (25U)
#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR1_AWD1CH_Pos (26U)
#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_BULB_Pos (13U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC bulb sampling mode */
#define ADC_CFGR2_SWTRIG_Pos (14U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC software trigger bit for sampling time control trigger mode */
#define ADC_CFGR2_SMPTRIG_Pos (15U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC sampling time control trigger mode */
#define ADC_CFGR2_OVSR_Pos (16U)
#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_LSHIFT_Pos (28U)
#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC left shift factor */
#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
#define ADC_SMPR2_SMP19_Pos (27U)
#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
/******************** Bit definition for ADC_PCSEL register *****************/
#define ADC_PCSEL_PCSEL_Pos (0U)
#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC channel preselection */
#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
#define ADC_DR_RDATA_0 (0x00000001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
#define ADC_DR_RDATA_1 (0x00000002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
#define ADC_DR_RDATA_2 (0x00000004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
#define ADC_DR_RDATA_3 (0x00000008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
#define ADC_DR_RDATA_4 (0x00000010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
#define ADC_DR_RDATA_5 (0x00000020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
#define ADC_DR_RDATA_6 (0x00000040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
#define ADC_DR_RDATA_7 (0x00000080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
#define ADC_DR_RDATA_8 (0x00000100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
#define ADC_DR_RDATA_9 (0x00000200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
#define ADC_DR_RDATA_10 (0x00000400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
#define ADC_DR_RDATA_11 (0x00000800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
#define ADC_DR_RDATA_12 (0x00001000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
#define ADC_DR_RDATA_13 (0x00002000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
#define ADC_DR_RDATA_14 (0x00004000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
#define ADC_DR_RDATA_15 (0x00008000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
#define ADC_DR_RDATA_16 (0x00010000UL << ADC_DR_RDATA_Pos) /*!< 0x00010000 */
#define ADC_DR_RDATA_17 (0x00020000UL << ADC_DR_RDATA_Pos) /*!< 0x00020000 */
#define ADC_DR_RDATA_18 (0x00040000UL << ADC_DR_RDATA_Pos) /*!< 0x00040000 */
#define ADC_DR_RDATA_19 (0x00080000UL << ADC_DR_RDATA_Pos) /*!< 0x00080000 */
#define ADC_DR_RDATA_20 (0x00100000UL << ADC_DR_RDATA_Pos) /*!< 0x00100000 */
#define ADC_DR_RDATA_21 (0x00200000UL << ADC_DR_RDATA_Pos) /*!< 0x00200000 */
#define ADC_DR_RDATA_22 (0x00400000UL << ADC_DR_RDATA_Pos) /*!< 0x00400000 */
#define ADC_DR_RDATA_23 (0x00800000UL << ADC_DR_RDATA_Pos) /*!< 0x00800000 */
#define ADC_DR_RDATA_24 (0x01000000UL << ADC_DR_RDATA_Pos) /*!< 0x01000000 */
#define ADC_DR_RDATA_25 (0x02000000UL << ADC_DR_RDATA_Pos) /*!< 0x02000000 */
#define ADC_DR_RDATA_26 (0x04000000UL << ADC_DR_RDATA_Pos) /*!< 0x04000000 */
#define ADC_DR_RDATA_27 (0x08000000UL << ADC_DR_RDATA_Pos) /*!< 0x08000000 */
#define ADC_DR_RDATA_28 (0x10000000UL << ADC_DR_RDATA_Pos) /*!< 0x10000000 */
#define ADC_DR_RDATA_29 (0x20000000UL << ADC_DR_RDATA_Pos) /*!< 0x20000000 */
#define ADC_DR_RDATA_30 (0x40000000UL << ADC_DR_RDATA_Pos) /*!< 0x40000000 */
#define ADC_DR_RDATA_31 (0x80000000UL << ADC_DR_RDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFCFGR1 register ***************/
#define ADC_OFCFGR1_POSOFF_Pos (24U)
#define ADC_OFCFGR1_POSOFF_Msk (0x01UL << ADC_OFCFGR1_POSOFF_Pos) /*!< 0x01000000 */
#define ADC_OFCFGR1_POSOFF ADC_OFCFGR1_POSOFF_Msk /*!< ADC offset instance 1 positive offset enable */
#define ADC_OFCFGR1_USAT_Pos (25U)
#define ADC_OFCFGR1_USAT_Msk (0x01UL << ADC_OFCFGR1_USAT_Pos) /*!< 0x02000000 */
#define ADC_OFCFGR1_USAT ADC_OFCFGR1_USAT_Msk /*!< ADC offset instance 1 unsigned saturation value */
#define ADC_OFCFGR1_SSAT_Pos (26U)
#define ADC_OFCFGR1_SSAT_Msk (0x01UL << ADC_OFCFGR1_SSAT_Pos) /*!< 0x04000000 */
#define ADC_OFCFGR1_SSAT ADC_OFCFGR1_SSAT_Msk /*!< ADC offset instance 1 signed satuaration enable */
#define ADC_OFCFGR1_OFFSET_CH_Pos (27U)
#define ADC_OFCFGR1_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR1_OFFSET_CH_Pos) /*!< 0xF8000000 */
#define ADC_OFCFGR1_OFFSET_CH ADC_OFCFGR1_OFFSET_CH_Msk /*!< ADC offset instance 1 channel selection */
#define ADC_OFCFGR1_OFFSET_CH_0 (0x01UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFCFGR1_OFFSET_CH_1 (0x02UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFCFGR1_OFFSET_CH_2 (0x03UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFCFGR1_OFFSET_CH_3 (0x04UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFCFGR1_OFFSET_CH_4 (0x05UL << ADC_OFCFGR1_OFFSET1_CH_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFCFGR2 register ***************/
#define ADC_OFCFGR2_POSOFF_Pos (24U)
#define ADC_OFCFGR2_POSOFF_Msk (0x01UL << ADC_OFCFGR2_POSOFF_Pos) /*!< 0x01000000 */
#define ADC_OFCFGR2_POSOFF ADC_OFCFGR2_POSOFF_Msk /*!< ADC offset instance 2 positive offset enable */
#define ADC_OFCFGR2_USAT_Pos (25U)
#define ADC_OFCFGR2_USAT_Msk (0x01UL << ADC_OFCFGR2_USAT_Pos) /*!< 0x02000000 */
#define ADC_OFCFGR2_USAT ADC_OFCFGR2_USAT_Msk /*!< ADC offset instance 2 unsigned saturation value */
#define ADC_OFCFGR2_SSAT_Pos (26U)
#define ADC_OFCFGR2_SSAT_Msk (0x01UL << ADC_OFCFGR2_SSAT_Pos) /*!< 0x04000000 */
#define ADC_OFCFGR2_SSAT ADC_OFCFGR2_SSAT_Msk /*!< ADC offset instance 2 signed satuaration enable */
#define ADC_OFCFGR2_OFFSET_CH_Pos (27U)
#define ADC_OFCFGR2_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR2_OFFSET_CH_Pos) /*!< 0xF8000000 */
#define ADC_OFCFGR2_OFFSET_CH ADC_OFCFGR2_OFFSET_CH_Msk /*!< ADC offset instance 2 channel selection */
#define ADC_OFCFGR2_OFFSET_CH_0 (0x01UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFCFGR2_OFFSET_CH_1 (0x02UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFCFGR2_OFFSET_CH_2 (0x03UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFCFGR2_OFFSET_CH_3 (0x04UL << ADC_OFCFGR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFCFGR2_OFFSET_CH_4 (0x05UL << ADC_OFCFGR2_OFFSET1_CH_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFCFGR3 register ***************/
#define ADC_OFCFGR3_POSOFF_Pos (24U)
#define ADC_OFCFGR3_POSOFF_Msk (0x01UL << ADC_OFCFGR3_POSOFF_Pos) /*!< 0x01000000 */
#define ADC_OFCFGR3_POSOFF ADC_OFCFGR3_POSOFF_Msk /*!< ADC offset instance 3 positive offset enable */
#define ADC_OFCFGR3_USAT_Pos (25U)
#define ADC_OFCFGR3_USAT_Msk (0x01UL << ADC_OFCFGR3_USAT_Pos) /*!< 0x02000000 */
#define ADC_OFCFGR3_USAT ADC_OFCFGR3_USAT_Msk /*!< ADC offset instance 3 unsigned saturation value */
#define ADC_OFCFGR3_SSAT_Pos (26U)
#define ADC_OFCFGR3_SSAT_Msk (0x01UL << ADC_OFCFGR3_SSAT_Pos) /*!< 0x04000000 */
#define ADC_OFCFGR3_SSAT ADC_OFCFGR3_SSAT_Msk /*!< ADC offset instance 3 signed satuaration enable */
#define ADC_OFCFGR3_OFFSET_CH_Pos (27U)
#define ADC_OFCFGR3_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR3_OFFSET_CH_Pos) /*!< 0xF8000000 */
#define ADC_OFCFGR3_OFFSET_CH ADC_OFCFGR3_OFFSET_CH_Msk /*!< ADC offset instance 3 channel selection for the data offset */
#define ADC_OFCFGR3_OFFSET_CH_0 (0x01UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFCFGR3_OFFSET_CH_1 (0x02UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFCFGR3_OFFSET_CH_2 (0x03UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFCFGR3_OFFSET_CH_3 (0x04UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFCFGR3_OFFSET_CH_4 (0x05UL << ADC_OFCFGR3_OFFSET3_CH_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFCFGR4 register ***************/
#define ADC_OFCFGR4_POSOFF_Pos (24U)
#define ADC_OFCFGR4_POSOFF_Msk (0x01UL << ADC_OFCFGR4_POSOFF_Pos) /*!< 0x01000000 */
#define ADC_OFCFGR4_POSOFF ADC_OFCFGR4_POSOFF_Msk /*!< ADC offset instance 4 positive offset enable */
#define ADC_OFCFGR4_USAT_Pos (25U)
#define ADC_OFCFGR4_USAT_Msk (0x01UL << ADC_OFCFGR4_USAT_Pos) /*!< 0x02000000 */
#define ADC_OFCFGR4_USAT ADC_OFCFGR4_USAT_Msk /*!< ADC offset instance 4 unsigned saturation value */
#define ADC_OFCFGR4_SSAT_Pos (26U)
#define ADC_OFCFGR4_SSAT_Msk (0x01UL << ADC_OFCFGR4_SSAT_Pos) /*!< 0x04000000 */
#define ADC_OFCFGR4_SSAT ADC_OFCFGR4_SSAT_Msk /*!< ADC offset instance 4 signed satuaration enable */
#define ADC_OFCFGR4_OFFSET_CH_Pos (27U)
#define ADC_OFCFGR4_OFFSET_CH_Msk (0x1FUL << ADC_OFCFGR4_OFFSET_CH_Pos) /*!< 0xF8000000 */
#define ADC_OFCFGR4_OFFSET_CH ADC_OFCFGR4_OFFSET_CH_Msk /*!< ADC offset instance 4 channel selection for the data offset */
#define ADC_OFCFGR4_OFFSET_CH_0 (0x01UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFCFGR4_OFFSET_CH_1 (0x02UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFCFGR4_OFFSET_CH_2 (0x03UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFCFGR4_OFFSET_CH_3 (0x04UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFCFGR4_OFFSET_CH_4 (0x05UL << ADC_OFCFGR4_OFFSET4_CH_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET_Pos (0U)
#define ADC_OFR1_OFFSET_Msk (0x03FFFFFUL << ADC_OFR1_OFFSET_Pos) /*!< 0x003FFFFF */
#define ADC_OFR1_OFFSET ADC_OFR1_OFFSET_Msk /*!< ADC offset instance 1 offset level */
#define ADC_OFR1_OFFSET_0 (0x0000001UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000001 */
#define ADC_OFR1_OFFSET_1 (0x0000002UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000002 */
#define ADC_OFR1_OFFSET_2 (0x0000004UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000004 */
#define ADC_OFR1_OFFSET_3 (0x0000008UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000008 */
#define ADC_OFR1_OFFSET_4 (0x0000010UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000010 */
#define ADC_OFR1_OFFSET_5 (0x0000020UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000020 */
#define ADC_OFR1_OFFSET_6 (0x0000040UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000040 */
#define ADC_OFR1_OFFSET_7 (0x0000080UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000080 */
#define ADC_OFR1_OFFSET_8 (0x0000100UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000100 */
#define ADC_OFR1_OFFSET_9 (0x0000200UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000200 */
#define ADC_OFR1_OFFSET_10 (0x0000400UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000400 */
#define ADC_OFR1_OFFSET_11 (0x0000800UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00000800 */
#define ADC_OFR1_OFFSET_12 (0x0001000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00001000 */
#define ADC_OFR1_OFFSET_13 (0x0002000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00002000 */
#define ADC_OFR1_OFFSET_14 (0x0004000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00004000 */
#define ADC_OFR1_OFFSET_15 (0x0008000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00008000 */
#define ADC_OFR1_OFFSET_16 (0x0010000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00010000 */
#define ADC_OFR1_OFFSET_17 (0x0020000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00020000 */
#define ADC_OFR1_OFFSET_18 (0x0040000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00040000 */
#define ADC_OFR1_OFFSET_19 (0x0080000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00080000 */
#define ADC_OFR1_OFFSET_20 (0x0100000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00100000 */
#define ADC_OFR1_OFFSET_21 (0x0200000UL << ADC_OFR1_OFFSET_Pos) /*!< 0x00200000 */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET_Pos (0U)
#define ADC_OFR2_OFFSET_Msk (0x03FFFFFUL << ADC_OFR2_OFFSET_Pos) /*!< 0x003FFFFF */
#define ADC_OFR2_OFFSET ADC_OFR2_OFFSET_Msk /*!< ADC offset instance 2 offset level */
#define ADC_OFR2_OFFSET_0 (0x0000001UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000001 */
#define ADC_OFR2_OFFSET_1 (0x0000002UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000002 */
#define ADC_OFR2_OFFSET_2 (0x0000004UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000004 */
#define ADC_OFR2_OFFSET_3 (0x0000008UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000008 */
#define ADC_OFR2_OFFSET_4 (0x0000010UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000010 */
#define ADC_OFR2_OFFSET_5 (0x0000020UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000020 */
#define ADC_OFR2_OFFSET_6 (0x0000040UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000040 */
#define ADC_OFR2_OFFSET_7 (0x0000080UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000080 */
#define ADC_OFR2_OFFSET_8 (0x0000100UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000100 */
#define ADC_OFR2_OFFSET_9 (0x0000200UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000200 */
#define ADC_OFR2_OFFSET_10 (0x0000400UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000400 */
#define ADC_OFR2_OFFSET_11 (0x0000800UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00000800 */
#define ADC_OFR2_OFFSET_12 (0x0001000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00001000 */
#define ADC_OFR2_OFFSET_13 (0x0002000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00002000 */
#define ADC_OFR2_OFFSET_14 (0x0004000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00004000 */
#define ADC_OFR2_OFFSET_15 (0x0008000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00008000 */
#define ADC_OFR2_OFFSET_16 (0x0010000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00010000 */
#define ADC_OFR2_OFFSET_17 (0x0020000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00020000 */
#define ADC_OFR2_OFFSET_18 (0x0040000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00040000 */
#define ADC_OFR2_OFFSET_19 (0x0080000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00080000 */
#define ADC_OFR2_OFFSET_20 (0x0100000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00100000 */
#define ADC_OFR2_OFFSET_21 (0x0200000UL << ADC_OFR2_OFFSET_Pos) /*!< 0x00200000 */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET_Pos (0U)
#define ADC_OFR3_OFFSET_Msk (0x03FFFFFUL << ADC_OFR3_OFFSET_Pos) /*!< 0x003FFFFF */
#define ADC_OFR3_OFFSET ADC_OFR3_OFFSET_Msk /*!< ADC offset instance 3 offset level */
#define ADC_OFR3_OFFSET_0 (0x0000001UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000001 */
#define ADC_OFR3_OFFSET_1 (0x0000002UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000002 */
#define ADC_OFR3_OFFSET_2 (0x0000004UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000004 */
#define ADC_OFR3_OFFSET_3 (0x0000008UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000008 */
#define ADC_OFR3_OFFSET_4 (0x0000010UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000010 */
#define ADC_OFR3_OFFSET_5 (0x0000020UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000020 */
#define ADC_OFR3_OFFSET_6 (0x0000040UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000040 */
#define ADC_OFR3_OFFSET_7 (0x0000080UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000080 */
#define ADC_OFR3_OFFSET_8 (0x0000100UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000100 */
#define ADC_OFR3_OFFSET_9 (0x0000200UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000200 */
#define ADC_OFR3_OFFSET_10 (0x0000400UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000400 */
#define ADC_OFR3_OFFSET_11 (0x0000800UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00000800 */
#define ADC_OFR3_OFFSET_12 (0x0001000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00001000 */
#define ADC_OFR3_OFFSET_13 (0x0002000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00002000 */
#define ADC_OFR3_OFFSET_14 (0x0004000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00004000 */
#define ADC_OFR3_OFFSET_15 (0x0008000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00008000 */
#define ADC_OFR3_OFFSET_16 (0x0010000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00010000 */
#define ADC_OFR3_OFFSET_17 (0x0020000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00020000 */
#define ADC_OFR3_OFFSET_18 (0x0040000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00040000 */
#define ADC_OFR3_OFFSET_19 (0x0080000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00080000 */
#define ADC_OFR3_OFFSET_20 (0x0100000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00100000 */
#define ADC_OFR3_OFFSET_21 (0x0200000UL << ADC_OFR3_OFFSET_Pos) /*!< 0x00200000 */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET_Pos (0U)
#define ADC_OFR4_OFFSET_Msk (0x03FFFFFUL << ADC_OFR4_OFFSET_Pos) /*!< 0x003FFFFF */
#define ADC_OFR4_OFFSET ADC_OFR4_OFFSET_Msk /*!< ADC offset instance 4 offset level */
#define ADC_OFR4_OFFSET_0 (0x0000001UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000001 */
#define ADC_OFR4_OFFSET_1 (0x0000002UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000002 */
#define ADC_OFR4_OFFSET_2 (0x0000004UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000004 */
#define ADC_OFR4_OFFSET_3 (0x0000008UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000008 */
#define ADC_OFR4_OFFSET_4 (0x0000010UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000010 */
#define ADC_OFR4_OFFSET_5 (0x0000020UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000020 */
#define ADC_OFR4_OFFSET_6 (0x0000040UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000040 */
#define ADC_OFR4_OFFSET_7 (0x0000080UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000080 */
#define ADC_OFR4_OFFSET_8 (0x0000100UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000100 */
#define ADC_OFR4_OFFSET_9 (0x0000200UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000200 */
#define ADC_OFR4_OFFSET_10 (0x0000400UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000400 */
#define ADC_OFR4_OFFSET_11 (0x0000800UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00000800 */
#define ADC_OFR4_OFFSET_12 (0x0001000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00001000 */
#define ADC_OFR4_OFFSET_13 (0x0002000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00002000 */
#define ADC_OFR4_OFFSET_14 (0x0004000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00004000 */
#define ADC_OFR4_OFFSET_15 (0x0008000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00008000 */
#define ADC_OFR4_OFFSET_16 (0x0010000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00010000 */
#define ADC_OFR4_OFFSET_17 (0x0020000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00020000 */
#define ADC_OFR4_OFFSET_18 (0x0040000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00040000 */
#define ADC_OFR4_OFFSET_19 (0x0080000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00080000 */
#define ADC_OFR4_OFFSET_20 (0x0100000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00100000 */
#define ADC_OFR4_OFFSET_21 (0x0200000UL << ADC_OFR4_OFFSET_Pos) /*!< 0x00200000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< Gain compensation coefficient */
#define ADC_GCOMP_GCOMP_Pos (31U)
#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x80000000 */
#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< Gain compensation mode */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR2 register ********************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR3 register ********************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_JDR4 register ********************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_AWD1TR_LT register *************/
#define ADC_AWD1LTR_LTR_Pos (0U)
#define ADC_AWD1LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD1LTR_LTR_Pos) /*!< 0x007FFFFF */
#define ADC_AWD1LTR_LTR ADC_AWD1LTR_LTR_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_AWD1LTR_LTR_0 (0x000001UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000001 */
#define ADC_AWD1LTR_LTR_1 (0x000002UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000002 */
#define ADC_AWD1LTR_LTR_2 (0x000004UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000004 */
#define ADC_AWD1LTR_LTR_3 (0x000008UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000008 */
#define ADC_AWD1LTR_LTR_4 (0x000010UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000010 */
#define ADC_AWD1LTR_LTR_5 (0x000020UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000020 */
#define ADC_AWD1LTR_LTR_6 (0x000040UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000040 */
#define ADC_AWD1LTR_LTR_7 (0x000080UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000080 */
#define ADC_AWD1LTR_LTR_8 (0x000100UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000100 */
#define ADC_AWD1LTR_LTR_9 (0x000200UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000200 */
#define ADC_AWD1LTR_LTR_10 (0x000400UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000400 */
#define ADC_AWD1LTR_LTR_11 (0x000800UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00000800 */
#define ADC_AWD1LTR_LTR_12 (0x001000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00001000 */
#define ADC_AWD1LTR_LTR_13 (0x002000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00002000 */
#define ADC_AWD1LTR_LTR_14 (0x004000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00004000 */
#define ADC_AWD1LTR_LTR_15 (0x008000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00008000 */
#define ADC_AWD1LTR_LTR_16 (0x010000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00010000 */
#define ADC_AWD1LTR_LTR_17 (0x020000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00020000 */
#define ADC_AWD1LTR_LTR_18 (0x040000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00040000 */
#define ADC_AWD1LTR_LTR_19 (0x080000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00080000 */
#define ADC_AWD1LTR_LTR_20 (0x100000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00100000 */
#define ADC_AWD1LTR_LTR_21 (0x200000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00200000 */
#define ADC_AWD1LTR_LTR_22 (0x400000UL << ADC_AWD1LTR_LTR_Pos) /*!< 0x00400000 */
/******************** Bit definition for ADC_AWD1TR_HT register *******************/
#define ADC_AWD1HTR_HTR_Pos (0U)
#define ADC_AWD1HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD1HTR_HTR_Pos) /*!< 0x007FFFFF */
#define ADC_AWD1HTR_HTR ADC_AWD1HTR_HTR_Msk /*!< ADC analog watchdog 1 threshold high */
#define ADC_AWD1HTR_HTR_0 (0x000001UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000001 */
#define ADC_AWD1HTR_HTR_1 (0x000002UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000002 */
#define ADC_AWD1HTR_HTR_2 (0x000004UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000004 */
#define ADC_AWD1HTR_HTR_3 (0x000008UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000008 */
#define ADC_AWD1HTR_HTR_4 (0x000010UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000010 */
#define ADC_AWD1HTR_HTR_5 (0x000020UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000020 */
#define ADC_AWD1HTR_HTR_6 (0x000040UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000040 */
#define ADC_AWD1HTR_HTR_7 (0x000080UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000080 */
#define ADC_AWD1HTR_HTR_8 (0x000100UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000100 */
#define ADC_AWD1HTR_HTR_9 (0x000200UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000200 */
#define ADC_AWD1HTR_HTR_10 (0x000400UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000400 */
#define ADC_AWD1HTR_HTR_11 (0x000800UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00000800 */
#define ADC_AWD1HTR_HTR_12 (0x001000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00001000 */
#define ADC_AWD1HTR_HTR_13 (0x002000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00002000 */
#define ADC_AWD1HTR_HTR_14 (0x004000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00004000 */
#define ADC_AWD1HTR_HTR_15 (0x008000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00008000 */
#define ADC_AWD1HTR_HTR_16 (0x010000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00010000 */
#define ADC_AWD1HTR_HTR_17 (0x020000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00020000 */
#define ADC_AWD1HTR_HTR_18 (0x040000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00040000 */
#define ADC_AWD1HTR_HTR_19 (0x080000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00080000 */
#define ADC_AWD1HTR_HTR_20 (0x100000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00100000 */
#define ADC_AWD1HTR_HTR_21 (0x200000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00200000 */
#define ADC_AWD1HTR_HTR_22 (0x400000UL << ADC_AWD1HTR_HTR_Pos) /*!< 0x00400000 */
#define ADC_AWD1HTR_AWDFILT_Pos (29U)
#define ADC_AWD1HTR_AWDFILT_Msk (0x7UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000007 */
#define ADC_AWD1HTR_AWDFILT ADC_AWD1HTR_AWDFILT_Msk /*!< ADC analog watchdog 1 filtering */
#define ADC_AWD1HTR_AWDFILT_0 (0x000001UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000001 */
#define ADC_AWD1HTR_AWDFILT_1 (0x000002UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000002 */
#define ADC_AWD1HTR_AWDFILT_2 (0x000004UL << ADC_AWD1HTR_AWDFILT_Pos) /*!< 0x00000004 */
/******************** Bit definition for ADC_AWD2TR_LT register *******************/
#define ADC_AWD2LTR_LTR_Pos (0U)
#define ADC_AWD2LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD2LTR_LTR_Pos) /*!< 0x007FFFFF */
#define ADC_AWD2LTR_LTR ADC_AWD2LTR_LTR_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_AWD2LTR_LTR_0 (0x000001UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000001 */
#define ADC_AWD2LTR_LTR_1 (0x000002UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000002 */
#define ADC_AWD2LTR_LTR_2 (0x000004UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000004 */
#define ADC_AWD2LTR_LTR_3 (0x000008UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000008 */
#define ADC_AWD2LTR_LTR_4 (0x000010UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000010 */
#define ADC_AWD2LTR_LTR_5 (0x000020UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000020 */
#define ADC_AWD2LTR_LTR_6 (0x000040UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000040 */
#define ADC_AWD2LTR_LTR_7 (0x000080UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000080 */
#define ADC_AWD2LTR_LTR_8 (0x000100UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000100 */
#define ADC_AWD2LTR_LTR_9 (0x000200UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000200 */
#define ADC_AWD2LTR_LTR_10 (0x000400UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000400 */
#define ADC_AWD2LTR_LTR_11 (0x000800UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00000800 */
#define ADC_AWD2LTR_LTR_12 (0x001000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00001000 */
#define ADC_AWD2LTR_LTR_13 (0x002000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00002000 */
#define ADC_AWD2LTR_LTR_14 (0x004000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00004000 */
#define ADC_AWD2LTR_LTR_15 (0x008000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00008000 */
#define ADC_AWD2LTR_LTR_16 (0x010000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00010000 */
#define ADC_AWD2LTR_LTR_17 (0x020000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00020000 */
#define ADC_AWD2LTR_LTR_18 (0x040000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00040000 */
#define ADC_AWD2LTR_LTR_19 (0x080000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00080000 */
#define ADC_AWD2LTR_LTR_20 (0x100000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00100000 */
#define ADC_AWD2LTR_LTR_21 (0x200000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00200000 */
#define ADC_AWD2LTR_LTR_22 (0x400000UL << ADC_AWD2LTR_LTR_Pos) /*!< 0x00400000 */
/******************** Bit definition for ADC_AWD2TR_HT register *******************/
#define ADC_AWD2HTR_HTR_Pos (0U)
#define ADC_AWD2HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD2HTR_HTR_Pos) /*!< 0x007FFFFF */
#define ADC_AWD2HTR_HTR ADC_AWD2HTR_HTR_Msk /*!< ADC analog watchdog 2 threshold high */
#define ADC_AWD2HTR_HTR_0 (0x000001UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000001 */
#define ADC_AWD2HTR_HTR_1 (0x000002UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000002 */
#define ADC_AWD2HTR_HTR_2 (0x000004UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000004 */
#define ADC_AWD2HTR_HTR_3 (0x000008UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000008 */
#define ADC_AWD2HTR_HTR_4 (0x000010UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000010 */
#define ADC_AWD2HTR_HTR_5 (0x000020UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000020 */
#define ADC_AWD2HTR_HTR_6 (0x000040UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000040 */
#define ADC_AWD2HTR_HTR_7 (0x000080UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000080 */
#define ADC_AWD2HTR_HTR_8 (0x000100UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000100 */
#define ADC_AWD2HTR_HTR_9 (0x000200UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000200 */
#define ADC_AWD2HTR_HTR_10 (0x000400UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000400 */
#define ADC_AWD2HTR_HTR_11 (0x000800UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00000800 */
#define ADC_AWD2HTR_HTR_12 (0x001000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00001000 */
#define ADC_AWD2HTR_HTR_13 (0x002000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00002000 */
#define ADC_AWD2HTR_HTR_14 (0x004000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00004000 */
#define ADC_AWD2HTR_HTR_15 (0x008000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00008000 */
#define ADC_AWD2HTR_HTR_16 (0x010000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00010000 */
#define ADC_AWD2HTR_HTR_17 (0x020000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00020000 */
#define ADC_AWD2HTR_HTR_18 (0x040000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00040000 */
#define ADC_AWD2HTR_HTR_19 (0x080000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00080000 */
#define ADC_AWD2HTR_HTR_20 (0x100000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00100000 */
#define ADC_AWD2HTR_HTR_21 (0x200000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00200000 */
#define ADC_AWD2HTR_HTR_22 (0x400000UL << ADC_AWD2HTR_HTR_Pos) /*!< 0x00400000 */
/******************** Bit definition for ADC_AWD3TR_LT register *******************/
#define ADC_AWD3LTR_LTR_Pos (0U)
#define ADC_AWD3LTR_LTR_Msk (0x007FFFFFUL << ADC_AWD3LTR_LTR_Pos) /*!< 0x007FFFFF */
#define ADC_AWD3LTR_LTR ADC_AWD3LTR_LTR_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_AWD3LTR_LTR_0 (0x000001UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000001 */
#define ADC_AWD3LTR_LTR_1 (0x000002UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000002 */
#define ADC_AWD3LTR_LTR_2 (0x000004UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000004 */
#define ADC_AWD3LTR_LTR_3 (0x000008UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000008 */
#define ADC_AWD3LTR_LTR_4 (0x000010UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000010 */
#define ADC_AWD3LTR_LTR_5 (0x000020UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000020 */
#define ADC_AWD3LTR_LTR_6 (0x000040UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000040 */
#define ADC_AWD3LTR_LTR_7 (0x000080UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000080 */
#define ADC_AWD3LTR_LTR_8 (0x000100UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000100 */
#define ADC_AWD3LTR_LTR_9 (0x000200UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000200 */
#define ADC_AWD3LTR_LTR_10 (0x000400UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000400 */
#define ADC_AWD3LTR_LTR_11 (0x000800UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00000800 */
#define ADC_AWD3LTR_LTR_12 (0x001000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00001000 */
#define ADC_AWD3LTR_LTR_13 (0x002000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00002000 */
#define ADC_AWD3LTR_LTR_14 (0x004000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00004000 */
#define ADC_AWD3LTR_LTR_15 (0x008000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00008000 */
#define ADC_AWD3LTR_LTR_16 (0x010000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00010000 */
#define ADC_AWD3LTR_LTR_17 (0x020000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00020000 */
#define ADC_AWD3LTR_LTR_18 (0x040000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00040000 */
#define ADC_AWD3LTR_LTR_19 (0x080000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00080000 */
#define ADC_AWD3LTR_LTR_20 (0x100000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00100000 */
#define ADC_AWD3LTR_LTR_21 (0x200000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00200000 */
#define ADC_AWD3LTR_LTR_22 (0x400000UL << ADC_AWD3LTR_LTR_Pos) /*!< 0x00400000 */
/******************** Bit definition for ADC_AWD3TR_HT register *******************/
#define ADC_AWD3HTR_HTR_Pos (0U)
#define ADC_AWD3HTR_HTR_Msk (0x007FFFFFUL << ADC_AWD3HTR_HTR_Pos) /*!< 0x007FFFFF */
#define ADC_AWD3HTR_HTR ADC_AWD3HTR_HTR_Msk /*!< ADC analog watchdog 3 threshold high */
#define ADC_AWD3HTR_HTR_0 (0x000001UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000001 */
#define ADC_AWD3HTR_HTR_1 (0x000002UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000002 */
#define ADC_AWD3HTR_HTR_2 (0x000004UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000004 */
#define ADC_AWD3HTR_HTR_3 (0x000008UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000008 */
#define ADC_AWD3HTR_HTR_4 (0x000010UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000010 */
#define ADC_AWD3HTR_HTR_5 (0x000020UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000020 */
#define ADC_AWD3HTR_HTR_6 (0x000040UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000040 */
#define ADC_AWD3HTR_HTR_7 (0x000080UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000080 */
#define ADC_AWD3HTR_HTR_8 (0x000100UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000100 */
#define ADC_AWD3HTR_HTR_9 (0x000200UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000200 */
#define ADC_AWD3HTR_HTR_10 (0x000400UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000400 */
#define ADC_AWD3HTR_HTR_11 (0x000800UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00000800 */
#define ADC_AWD3HTR_HTR_12 (0x001000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00001000 */
#define ADC_AWD3HTR_HTR_13 (0x002000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00002000 */
#define ADC_AWD3HTR_HTR_14 (0x004000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00004000 */
#define ADC_AWD3HTR_HTR_15 (0x008000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00008000 */
#define ADC_AWD3HTR_HTR_16 (0x010000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00010000 */
#define ADC_AWD3HTR_HTR_17 (0x020000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00020000 */
#define ADC_AWD3HTR_HTR_18 (0x040000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00040000 */
#define ADC_AWD3HTR_HTR_19 (0x080000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00080000 */
#define ADC_AWD3HTR_HTR_20 (0x100000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00100000 */
#define ADC_AWD3HTR_HTR_21 (0x200000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00200000 */
#define ADC_AWD3HTR_HTR_22 (0x400000UL << ADC_AWD3HTR_HTR_Pos) /*!< 0x00400000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode selection */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x3FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000003FF */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
#define ADC_CALFACT_CALFACT_S_7 (0x80UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
#define ADC_CALFACT_CALFACT_S_8 (0x100UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
#define ADC_CALFACT_CALFACT_S_9 (0x200UL<< ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x3FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x03FF0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
#define ADC_CALFACT_CALFACT_D_7 (0x80UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
#define ADC_CALFACT_CALFACT_D_8 (0x100UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
#define ADC_CALFACT_CALFACT_D_9 (0x200UL<< ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
#define ADC_CALFACT_CALADDOS_Pos (31U)
#define ADC_CALFACT_CALADDOS_Msk (0x01UL << ADC_CALFACT_CALADDOS_Pos) /*!< 0x80000000 */
#define ADC_CALFACT_CALADDOS ADC_CALFACT_CALADDOS_Msk /*!< ADC calibration additional offset mode */
/******************** Bit definition for ADC_OR option register ***************/
#define ADC_OR_OP0_Pos (0U)
#define ADC_OR_OP0_Msk (0x1UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */
#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC internal reference voltage buffer */
#define ADC_OR_OP1_Pos (1U)
#define ADC_OR_OP1_Msk (0x1UL << ADC_OR_OP1_Pos) /*!< 0x00000002 */
#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC internal bandgap */
#define ADC_OR_OP2_Pos (2U)
#define ADC_OR_OP2_Msk (0x1UL << ADC_OR_OP2_Pos) /*!< 0x00000004 */
#define ADC_OR_OP2 ADC_OR_OP2_Msk /*!< ADC internal path to VDDCORE */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DAMDF_Pos (14U)
#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< ADC multimode data format */
#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VBATEN_Pos (24U)
#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************** Bit definition for ADC_CDR2 register ******************/
#define ADC_CDR2_RDATA_ALT_Pos (0U)
#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< ADC multimode master or slave (alternated) group regular conversion data */
/******************************************************************************/
/* */
/* BSEC unit (Boot and Security) */
/* */
/******************************************************************************/
/****************** Bit definition for BSEC_FVRw register *******************/
#define BSEC_FVRw_FV_Pos (0U)
#define BSEC_FVRw_FV_Msk (0xFFFFFFFFUL << BSEC_FVRw_FV_Pos) /*!< 0xFFFFFFFF */
#define BSEC_FVRw_FV BSEC_FVRw_FV_Msk /*!< Fuse value */
/***************** Bit definition for BSEC_SPLOCKx register *****************/
#define BSEC_SPLOCKx_SPLOCK0_Pos (0U)
#define BSEC_SPLOCKx_SPLOCK0_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK0_Pos) /*!< 0x00000001 */
#define BSEC_SPLOCKx_SPLOCK0 BSEC_SPLOCKx_SPLOCK0_Msk /*!< Sticky programming lock for word (32*x) */
#define BSEC_SPLOCKx_SPLOCK1_Pos (1U)
#define BSEC_SPLOCKx_SPLOCK1_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK1_Pos) /*!< 0x00000002 */
#define BSEC_SPLOCKx_SPLOCK1 BSEC_SPLOCKx_SPLOCK1_Msk /*!< Sticky programming lock for word (1+32*x) */
#define BSEC_SPLOCKx_SPLOCK2_Pos (2U)
#define BSEC_SPLOCKx_SPLOCK2_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK2_Pos) /*!< 0x00000004 */
#define BSEC_SPLOCKx_SPLOCK2 BSEC_SPLOCKx_SPLOCK2_Msk /*!< Sticky programming lock for word (2+32*x) */
#define BSEC_SPLOCKx_SPLOCK3_Pos (3U)
#define BSEC_SPLOCKx_SPLOCK3_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK3_Pos) /*!< 0x00000008 */
#define BSEC_SPLOCKx_SPLOCK3 BSEC_SPLOCKx_SPLOCK3_Msk /*!< Sticky programming lock for word (3+32*x) */
#define BSEC_SPLOCKx_SPLOCK4_Pos (4U)
#define BSEC_SPLOCKx_SPLOCK4_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK4_Pos) /*!< 0x00000010 */
#define BSEC_SPLOCKx_SPLOCK4 BSEC_SPLOCKx_SPLOCK4_Msk /*!< Sticky programming lock for word (4+32*x) */
#define BSEC_SPLOCKx_SPLOCK5_Pos (5U)
#define BSEC_SPLOCKx_SPLOCK5_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK5_Pos) /*!< 0x00000020 */
#define BSEC_SPLOCKx_SPLOCK5 BSEC_SPLOCKx_SPLOCK5_Msk /*!< Sticky programming lock for word (5+32*x) */
#define BSEC_SPLOCKx_SPLOCK6_Pos (6U)
#define BSEC_SPLOCKx_SPLOCK6_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK6_Pos) /*!< 0x00000040 */
#define BSEC_SPLOCKx_SPLOCK6 BSEC_SPLOCKx_SPLOCK6_Msk /*!< Sticky programming lock for word (6+32*x) */
#define BSEC_SPLOCKx_SPLOCK7_Pos (7U)
#define BSEC_SPLOCKx_SPLOCK7_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK7_Pos) /*!< 0x00000080 */
#define BSEC_SPLOCKx_SPLOCK7 BSEC_SPLOCKx_SPLOCK7_Msk /*!< Sticky programming lock for word (7+32*x) */
#define BSEC_SPLOCKx_SPLOCK8_Pos (8U)
#define BSEC_SPLOCKx_SPLOCK8_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK8_Pos) /*!< 0x00000100 */
#define BSEC_SPLOCKx_SPLOCK8 BSEC_SPLOCKx_SPLOCK8_Msk /*!< Sticky programming lock for word (8+32*x) */
#define BSEC_SPLOCKx_SPLOCK9_Pos (9U)
#define BSEC_SPLOCKx_SPLOCK9_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK9_Pos) /*!< 0x00000200 */
#define BSEC_SPLOCKx_SPLOCK9 BSEC_SPLOCKx_SPLOCK9_Msk /*!< Sticky programming lock for word (9+32*x) */
#define BSEC_SPLOCKx_SPLOCK10_Pos (10U)
#define BSEC_SPLOCKx_SPLOCK10_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK10_Pos) /*!< 0x00000400 */
#define BSEC_SPLOCKx_SPLOCK10 BSEC_SPLOCKx_SPLOCK10_Msk /*!< Sticky programming lock for word (10+32*x) */
#define BSEC_SPLOCKx_SPLOCK11_Pos (11U)
#define BSEC_SPLOCKx_SPLOCK11_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK11_Pos) /*!< 0x00000800 */
#define BSEC_SPLOCKx_SPLOCK11 BSEC_SPLOCKx_SPLOCK11_Msk /*!< Sticky programming lock for word (11+32*x) */
#define BSEC_SPLOCKx_SPLOCK12_Pos (12U)
#define BSEC_SPLOCKx_SPLOCK12_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK12_Pos) /*!< 0x00001000 */
#define BSEC_SPLOCKx_SPLOCK12 BSEC_SPLOCKx_SPLOCK12_Msk /*!< Sticky programming lock for word (12+32*x) */
#define BSEC_SPLOCKx_SPLOCK13_Pos (13U)
#define BSEC_SPLOCKx_SPLOCK13_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK13_Pos) /*!< 0x00002000 */
#define BSEC_SPLOCKx_SPLOCK13 BSEC_SPLOCKx_SPLOCK13_Msk /*!< Sticky programming lock for word (13+32*x) */
#define BSEC_SPLOCKx_SPLOCK14_Pos (14U)
#define BSEC_SPLOCKx_SPLOCK14_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK14_Pos) /*!< 0x00004000 */
#define BSEC_SPLOCKx_SPLOCK14 BSEC_SPLOCKx_SPLOCK14_Msk /*!< Sticky programming lock for word (14+32*x) */
#define BSEC_SPLOCKx_SPLOCK15_Pos (15U)
#define BSEC_SPLOCKx_SPLOCK15_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK15_Pos) /*!< 0x00008000 */
#define BSEC_SPLOCKx_SPLOCK15 BSEC_SPLOCKx_SPLOCK15_Msk /*!< Sticky programming lock for word (15+32*x) */
#define BSEC_SPLOCKx_SPLOCK16_Pos (16U)
#define BSEC_SPLOCKx_SPLOCK16_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK16_Pos) /*!< 0x00010000 */
#define BSEC_SPLOCKx_SPLOCK16 BSEC_SPLOCKx_SPLOCK16_Msk /*!< Sticky programming lock for word (16+32*x) */
#define BSEC_SPLOCKx_SPLOCK17_Pos (17U)
#define BSEC_SPLOCKx_SPLOCK17_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK17_Pos) /*!< 0x00020000 */
#define BSEC_SPLOCKx_SPLOCK17 BSEC_SPLOCKx_SPLOCK17_Msk /*!< Sticky programming lock for word (17+32*x) */
#define BSEC_SPLOCKx_SPLOCK18_Pos (18U)
#define BSEC_SPLOCKx_SPLOCK18_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK18_Pos) /*!< 0x00040000 */
#define BSEC_SPLOCKx_SPLOCK18 BSEC_SPLOCKx_SPLOCK18_Msk /*!< Sticky programming lock for word (18+32*x) */
#define BSEC_SPLOCKx_SPLOCK19_Pos (19U)
#define BSEC_SPLOCKx_SPLOCK19_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK19_Pos) /*!< 0x00080000 */
#define BSEC_SPLOCKx_SPLOCK19 BSEC_SPLOCKx_SPLOCK19_Msk /*!< Sticky programming lock for word (19+32*x) */
#define BSEC_SPLOCKx_SPLOCK20_Pos (20U)
#define BSEC_SPLOCKx_SPLOCK20_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK20_Pos) /*!< 0x00100000 */
#define BSEC_SPLOCKx_SPLOCK20 BSEC_SPLOCKx_SPLOCK20_Msk /*!< Sticky programming lock for word (20+32*x) */
#define BSEC_SPLOCKx_SPLOCK21_Pos (21U)
#define BSEC_SPLOCKx_SPLOCK21_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK21_Pos) /*!< 0x00200000 */
#define BSEC_SPLOCKx_SPLOCK21 BSEC_SPLOCKx_SPLOCK21_Msk /*!< Sticky programming lock for word (21+32*x) */
#define BSEC_SPLOCKx_SPLOCK22_Pos (22U)
#define BSEC_SPLOCKx_SPLOCK22_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK22_Pos) /*!< 0x00400000 */
#define BSEC_SPLOCKx_SPLOCK22 BSEC_SPLOCKx_SPLOCK22_Msk /*!< Sticky programming lock for word (22+32*x) */
#define BSEC_SPLOCKx_SPLOCK23_Pos (23U)
#define BSEC_SPLOCKx_SPLOCK23_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK23_Pos) /*!< 0x00800000 */
#define BSEC_SPLOCKx_SPLOCK23 BSEC_SPLOCKx_SPLOCK23_Msk /*!< Sticky programming lock for word (23+32*x) */
#define BSEC_SPLOCKx_SPLOCK24_Pos (24U)
#define BSEC_SPLOCKx_SPLOCK24_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK24_Pos) /*!< 0x01000000 */
#define BSEC_SPLOCKx_SPLOCK24 BSEC_SPLOCKx_SPLOCK24_Msk /*!< Sticky programming lock for word (24+32*x) */
#define BSEC_SPLOCKx_SPLOCK25_Pos (25U)
#define BSEC_SPLOCKx_SPLOCK25_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK25_Pos) /*!< 0x02000000 */
#define BSEC_SPLOCKx_SPLOCK25 BSEC_SPLOCKx_SPLOCK25_Msk /*!< Sticky programming lock for word (25+32*x) */
#define BSEC_SPLOCKx_SPLOCK26_Pos (26U)
#define BSEC_SPLOCKx_SPLOCK26_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK26_Pos) /*!< 0x04000000 */
#define BSEC_SPLOCKx_SPLOCK26 BSEC_SPLOCKx_SPLOCK26_Msk /*!< Sticky programming lock for word (26+32*x) */
#define BSEC_SPLOCKx_SPLOCK27_Pos (27U)
#define BSEC_SPLOCKx_SPLOCK27_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK27_Pos) /*!< 0x08000000 */
#define BSEC_SPLOCKx_SPLOCK27 BSEC_SPLOCKx_SPLOCK27_Msk /*!< Sticky programming lock for word (27+32*x) */
#define BSEC_SPLOCKx_SPLOCK28_Pos (28U)
#define BSEC_SPLOCKx_SPLOCK28_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK28_Pos) /*!< 0x10000000 */
#define BSEC_SPLOCKx_SPLOCK28 BSEC_SPLOCKx_SPLOCK28_Msk /*!< Sticky programming lock for word (28+32*x) */
#define BSEC_SPLOCKx_SPLOCK29_Pos (29U)
#define BSEC_SPLOCKx_SPLOCK29_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK29_Pos) /*!< 0x20000000 */
#define BSEC_SPLOCKx_SPLOCK29 BSEC_SPLOCKx_SPLOCK29_Msk /*!< Sticky programming lock for word (29+32*x) */
#define BSEC_SPLOCKx_SPLOCK30_Pos (30U)
#define BSEC_SPLOCKx_SPLOCK30_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK30_Pos) /*!< 0x40000000 */
#define BSEC_SPLOCKx_SPLOCK30 BSEC_SPLOCKx_SPLOCK30_Msk /*!< Sticky programming lock for word (30+32*x) */
#define BSEC_SPLOCKx_SPLOCK31_Pos (31U)
#define BSEC_SPLOCKx_SPLOCK31_Msk (0x1UL << BSEC_SPLOCKx_SPLOCK31_Pos) /*!< 0x80000000 */
#define BSEC_SPLOCKx_SPLOCK31 BSEC_SPLOCKx_SPLOCK31_Msk /*!< Sticky programming lock for word (31+32*x) */
/***************** Bit definition for BSEC_SWLOCKx register *****************/
#define BSEC_SWLOCKx_SWLOCK0_Pos (0U)
#define BSEC_SWLOCKx_SWLOCK0_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK0_Pos) /*!< 0x00000001 */
#define BSEC_SWLOCKx_SWLOCK0 BSEC_SWLOCKx_SWLOCK0_Msk /*!< Sticky write lock for shadow register (32*x) */
#define BSEC_SWLOCKx_SWLOCK1_Pos (1U)
#define BSEC_SWLOCKx_SWLOCK1_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK1_Pos) /*!< 0x00000002 */
#define BSEC_SWLOCKx_SWLOCK1 BSEC_SWLOCKx_SWLOCK1_Msk /*!< Sticky write lock for shadow register (1+32*x) */
#define BSEC_SWLOCKx_SWLOCK2_Pos (2U)
#define BSEC_SWLOCKx_SWLOCK2_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK2_Pos) /*!< 0x00000004 */
#define BSEC_SWLOCKx_SWLOCK2 BSEC_SWLOCKx_SWLOCK2_Msk /*!< Sticky write lock for shadow register (2+32*x) */
#define BSEC_SWLOCKx_SWLOCK3_Pos (3U)
#define BSEC_SWLOCKx_SWLOCK3_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK3_Pos) /*!< 0x00000008 */
#define BSEC_SWLOCKx_SWLOCK3 BSEC_SWLOCKx_SWLOCK3_Msk /*!< Sticky write lock for shadow register (3+32*x) */
#define BSEC_SWLOCKx_SWLOCK4_Pos (4U)
#define BSEC_SWLOCKx_SWLOCK4_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK4_Pos) /*!< 0x00000010 */
#define BSEC_SWLOCKx_SWLOCK4 BSEC_SWLOCKx_SWLOCK4_Msk /*!< Sticky write lock for shadow register (4+32*x) */
#define BSEC_SWLOCKx_SWLOCK5_Pos (5U)
#define BSEC_SWLOCKx_SWLOCK5_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK5_Pos) /*!< 0x00000020 */
#define BSEC_SWLOCKx_SWLOCK5 BSEC_SWLOCKx_SWLOCK5_Msk /*!< Sticky write lock for shadow register (5+32*x) */
#define BSEC_SWLOCKx_SWLOCK6_Pos (6U)
#define BSEC_SWLOCKx_SWLOCK6_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK6_Pos) /*!< 0x00000040 */
#define BSEC_SWLOCKx_SWLOCK6 BSEC_SWLOCKx_SWLOCK6_Msk /*!< Sticky write lock for shadow register (6+32*x) */
#define BSEC_SWLOCKx_SWLOCK7_Pos (7U)
#define BSEC_SWLOCKx_SWLOCK7_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK7_Pos) /*!< 0x00000080 */
#define BSEC_SWLOCKx_SWLOCK7 BSEC_SWLOCKx_SWLOCK7_Msk /*!< Sticky write lock for shadow register (7+32*x) */
#define BSEC_SWLOCKx_SWLOCK8_Pos (8U)
#define BSEC_SWLOCKx_SWLOCK8_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK8_Pos) /*!< 0x00000100 */
#define BSEC_SWLOCKx_SWLOCK8 BSEC_SWLOCKx_SWLOCK8_Msk /*!< Sticky write lock for shadow register (8+32*x) */
#define BSEC_SWLOCKx_SWLOCK9_Pos (9U)
#define BSEC_SWLOCKx_SWLOCK9_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK9_Pos) /*!< 0x00000200 */
#define BSEC_SWLOCKx_SWLOCK9 BSEC_SWLOCKx_SWLOCK9_Msk /*!< Sticky write lock for shadow register (9+32*x) */
#define BSEC_SWLOCKx_SWLOCK10_Pos (10U)
#define BSEC_SWLOCKx_SWLOCK10_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK10_Pos) /*!< 0x00000400 */
#define BSEC_SWLOCKx_SWLOCK10 BSEC_SWLOCKx_SWLOCK10_Msk /*!< Sticky write lock for shadow register (10+32*x) */
#define BSEC_SWLOCKx_SWLOCK11_Pos (11U)
#define BSEC_SWLOCKx_SWLOCK11_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK11_Pos) /*!< 0x00000800 */
#define BSEC_SWLOCKx_SWLOCK11 BSEC_SWLOCKx_SWLOCK11_Msk /*!< Sticky write lock for shadow register (11+32*x) */
#define BSEC_SWLOCKx_SWLOCK12_Pos (12U)
#define BSEC_SWLOCKx_SWLOCK12_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK12_Pos) /*!< 0x00001000 */
#define BSEC_SWLOCKx_SWLOCK12 BSEC_SWLOCKx_SWLOCK12_Msk /*!< Sticky write lock for shadow register (12+32*x) */
#define BSEC_SWLOCKx_SWLOCK13_Pos (13U)
#define BSEC_SWLOCKx_SWLOCK13_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK13_Pos) /*!< 0x00002000 */
#define BSEC_SWLOCKx_SWLOCK13 BSEC_SWLOCKx_SWLOCK13_Msk /*!< Sticky write lock for shadow register (13+32*x) */
#define BSEC_SWLOCKx_SWLOCK14_Pos (14U)
#define BSEC_SWLOCKx_SWLOCK14_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK14_Pos) /*!< 0x00004000 */
#define BSEC_SWLOCKx_SWLOCK14 BSEC_SWLOCKx_SWLOCK14_Msk /*!< Sticky write lock for shadow register (14+32*x) */
#define BSEC_SWLOCKx_SWLOCK15_Pos (15U)
#define BSEC_SWLOCKx_SWLOCK15_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK15_Pos) /*!< 0x00008000 */
#define BSEC_SWLOCKx_SWLOCK15 BSEC_SWLOCKx_SWLOCK15_Msk /*!< Sticky write lock for shadow register (15+32*x) */
#define BSEC_SWLOCKx_SWLOCK16_Pos (16U)
#define BSEC_SWLOCKx_SWLOCK16_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK16_Pos) /*!< 0x00010000 */
#define BSEC_SWLOCKx_SWLOCK16 BSEC_SWLOCKx_SWLOCK16_Msk /*!< Sticky write lock for shadow register (16+32*x) */
#define BSEC_SWLOCKx_SWLOCK17_Pos (17U)
#define BSEC_SWLOCKx_SWLOCK17_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK17_Pos) /*!< 0x00020000 */
#define BSEC_SWLOCKx_SWLOCK17 BSEC_SWLOCKx_SWLOCK17_Msk /*!< Sticky write lock for shadow register (17+32*x) */
#define BSEC_SWLOCKx_SWLOCK18_Pos (18U)
#define BSEC_SWLOCKx_SWLOCK18_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK18_Pos) /*!< 0x00040000 */
#define BSEC_SWLOCKx_SWLOCK18 BSEC_SWLOCKx_SWLOCK18_Msk /*!< Sticky write lock for shadow register (18+32*x) */
#define BSEC_SWLOCKx_SWLOCK19_Pos (19U)
#define BSEC_SWLOCKx_SWLOCK19_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK19_Pos) /*!< 0x00080000 */
#define BSEC_SWLOCKx_SWLOCK19 BSEC_SWLOCKx_SWLOCK19_Msk /*!< Sticky write lock for shadow register (19+32*x) */
#define BSEC_SWLOCKx_SWLOCK20_Pos (20U)
#define BSEC_SWLOCKx_SWLOCK20_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK20_Pos) /*!< 0x00100000 */
#define BSEC_SWLOCKx_SWLOCK20 BSEC_SWLOCKx_SWLOCK20_Msk /*!< Sticky write lock for shadow register (20+32*x) */
#define BSEC_SWLOCKx_SWLOCK21_Pos (21U)
#define BSEC_SWLOCKx_SWLOCK21_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK21_Pos) /*!< 0x00200000 */
#define BSEC_SWLOCKx_SWLOCK21 BSEC_SWLOCKx_SWLOCK21_Msk /*!< Sticky write lock for shadow register (21+32*x) */
#define BSEC_SWLOCKx_SWLOCK22_Pos (22U)
#define BSEC_SWLOCKx_SWLOCK22_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK22_Pos) /*!< 0x00400000 */
#define BSEC_SWLOCKx_SWLOCK22 BSEC_SWLOCKx_SWLOCK22_Msk /*!< Sticky write lock for shadow register (22+32*x) */
#define BSEC_SWLOCKx_SWLOCK23_Pos (23U)
#define BSEC_SWLOCKx_SWLOCK23_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK23_Pos) /*!< 0x00800000 */
#define BSEC_SWLOCKx_SWLOCK23 BSEC_SWLOCKx_SWLOCK23_Msk /*!< Sticky write lock for shadow register (23+32*x) */
#define BSEC_SWLOCKx_SWLOCK24_Pos (24U)
#define BSEC_SWLOCKx_SWLOCK24_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK24_Pos) /*!< 0x01000000 */
#define BSEC_SWLOCKx_SWLOCK24 BSEC_SWLOCKx_SWLOCK24_Msk /*!< Sticky write lock for shadow register (24+32*x) */
#define BSEC_SWLOCKx_SWLOCK25_Pos (25U)
#define BSEC_SWLOCKx_SWLOCK25_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK25_Pos) /*!< 0x02000000 */
#define BSEC_SWLOCKx_SWLOCK25 BSEC_SWLOCKx_SWLOCK25_Msk /*!< Sticky write lock for shadow register (25+32*x) */
#define BSEC_SWLOCKx_SWLOCK26_Pos (26U)
#define BSEC_SWLOCKx_SWLOCK26_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK26_Pos) /*!< 0x04000000 */
#define BSEC_SWLOCKx_SWLOCK26 BSEC_SWLOCKx_SWLOCK26_Msk /*!< Sticky write lock for shadow register (26+32*x) */
#define BSEC_SWLOCKx_SWLOCK27_Pos (27U)
#define BSEC_SWLOCKx_SWLOCK27_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK27_Pos) /*!< 0x08000000 */
#define BSEC_SWLOCKx_SWLOCK27 BSEC_SWLOCKx_SWLOCK27_Msk /*!< Sticky write lock for shadow register (27+32*x) */
#define BSEC_SWLOCKx_SWLOCK28_Pos (28U)
#define BSEC_SWLOCKx_SWLOCK28_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK28_Pos) /*!< 0x10000000 */
#define BSEC_SWLOCKx_SWLOCK28 BSEC_SWLOCKx_SWLOCK28_Msk /*!< Sticky write lock for shadow register (28+32*x) */
#define BSEC_SWLOCKx_SWLOCK29_Pos (29U)
#define BSEC_SWLOCKx_SWLOCK29_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK29_Pos) /*!< 0x20000000 */
#define BSEC_SWLOCKx_SWLOCK29 BSEC_SWLOCKx_SWLOCK29_Msk /*!< Sticky write lock for shadow register (29+32*x) */
#define BSEC_SWLOCKx_SWLOCK30_Pos (30U)
#define BSEC_SWLOCKx_SWLOCK30_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK30_Pos) /*!< 0x40000000 */
#define BSEC_SWLOCKx_SWLOCK30 BSEC_SWLOCKx_SWLOCK30_Msk /*!< Sticky write lock for shadow register (30+32*x) */
#define BSEC_SWLOCKx_SWLOCK31_Pos (31U)
#define BSEC_SWLOCKx_SWLOCK31_Msk (0x1UL << BSEC_SWLOCKx_SWLOCK31_Pos) /*!< 0x80000000 */
#define BSEC_SWLOCKx_SWLOCK31 BSEC_SWLOCKx_SWLOCK31_Msk /*!< Sticky write lock for shadow register (31+32*x) */
/***************** Bit definition for BSEC_SRLOCKx register *****************/
#define BSEC_SRLOCKx_SRLOCK0_Pos (0U)
#define BSEC_SRLOCKx_SRLOCK0_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK0_Pos) /*!< 0x00000001 */
#define BSEC_SRLOCKx_SRLOCK0 BSEC_SRLOCKx_SRLOCK0_Msk /*!< Sticky reload lock for fuse word (32*x) */
#define BSEC_SRLOCKx_SRLOCK1_Pos (1U)
#define BSEC_SRLOCKx_SRLOCK1_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK1_Pos) /*!< 0x00000002 */
#define BSEC_SRLOCKx_SRLOCK1 BSEC_SRLOCKx_SRLOCK1_Msk /*!< Sticky reload lock for fuse word (1+32*x) */
#define BSEC_SRLOCKx_SRLOCK2_Pos (2U)
#define BSEC_SRLOCKx_SRLOCK2_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK2_Pos) /*!< 0x00000004 */
#define BSEC_SRLOCKx_SRLOCK2 BSEC_SRLOCKx_SRLOCK2_Msk /*!< Sticky reload lock for fuse word (2+32*x) */
#define BSEC_SRLOCKx_SRLOCK3_Pos (3U)
#define BSEC_SRLOCKx_SRLOCK3_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK3_Pos) /*!< 0x00000008 */
#define BSEC_SRLOCKx_SRLOCK3 BSEC_SRLOCKx_SRLOCK3_Msk /*!< Sticky reload lock for fuse word (3+32*x) */
#define BSEC_SRLOCKx_SRLOCK4_Pos (4U)
#define BSEC_SRLOCKx_SRLOCK4_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK4_Pos) /*!< 0x00000010 */
#define BSEC_SRLOCKx_SRLOCK4 BSEC_SRLOCKx_SRLOCK4_Msk /*!< Sticky reload lock for fuse word (4+32*x) */
#define BSEC_SRLOCKx_SRLOCK5_Pos (5U)
#define BSEC_SRLOCKx_SRLOCK5_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK5_Pos) /*!< 0x00000020 */
#define BSEC_SRLOCKx_SRLOCK5 BSEC_SRLOCKx_SRLOCK5_Msk /*!< Sticky reload lock for fuse word (5+32*x) */
#define BSEC_SRLOCKx_SRLOCK6_Pos (6U)
#define BSEC_SRLOCKx_SRLOCK6_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK6_Pos) /*!< 0x00000040 */
#define BSEC_SRLOCKx_SRLOCK6 BSEC_SRLOCKx_SRLOCK6_Msk /*!< Sticky reload lock for fuse word (6+32*x) */
#define BSEC_SRLOCKx_SRLOCK7_Pos (7U)
#define BSEC_SRLOCKx_SRLOCK7_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK7_Pos) /*!< 0x00000080 */
#define BSEC_SRLOCKx_SRLOCK7 BSEC_SRLOCKx_SRLOCK7_Msk /*!< Sticky reload lock for fuse word (7+32*x) */
#define BSEC_SRLOCKx_SRLOCK8_Pos (8U)
#define BSEC_SRLOCKx_SRLOCK8_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK8_Pos) /*!< 0x00000100 */
#define BSEC_SRLOCKx_SRLOCK8 BSEC_SRLOCKx_SRLOCK8_Msk /*!< Sticky reload lock for fuse word (8+32*x) */
#define BSEC_SRLOCKx_SRLOCK9_Pos (9U)
#define BSEC_SRLOCKx_SRLOCK9_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK9_Pos) /*!< 0x00000200 */
#define BSEC_SRLOCKx_SRLOCK9 BSEC_SRLOCKx_SRLOCK9_Msk /*!< Sticky reload lock for fuse word (9+32*x) */
#define BSEC_SRLOCKx_SRLOCK10_Pos (10U)
#define BSEC_SRLOCKx_SRLOCK10_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK10_Pos) /*!< 0x00000400 */
#define BSEC_SRLOCKx_SRLOCK10 BSEC_SRLOCKx_SRLOCK10_Msk /*!< Sticky reload lock for fuse word (10+2*x) */
#define BSEC_SRLOCKx_SRLOCK11_Pos (11U)
#define BSEC_SRLOCKx_SRLOCK11_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK11_Pos) /*!< 0x00000800 */
#define BSEC_SRLOCKx_SRLOCK11 BSEC_SRLOCKx_SRLOCK11_Msk /*!< Sticky reload lock for fuse word (11+32*x) */
#define BSEC_SRLOCKx_SRLOCK12_Pos (12U)
#define BSEC_SRLOCKx_SRLOCK12_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK12_Pos) /*!< 0x00001000 */
#define BSEC_SRLOCKx_SRLOCK12 BSEC_SRLOCKx_SRLOCK12_Msk /*!< Sticky reload lock for fuse word (12+32*x) */
#define BSEC_SRLOCKx_SRLOCK13_Pos (13U)
#define BSEC_SRLOCKx_SRLOCK13_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK13_Pos) /*!< 0x00002000 */
#define BSEC_SRLOCKx_SRLOCK13 BSEC_SRLOCKx_SRLOCK13_Msk /*!< Sticky reload lock for fuse word (13+32*x) */
#define BSEC_SRLOCKx_SRLOCK14_Pos (14U)
#define BSEC_SRLOCKx_SRLOCK14_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK14_Pos) /*!< 0x00004000 */
#define BSEC_SRLOCKx_SRLOCK14 BSEC_SRLOCKx_SRLOCK14_Msk /*!< Sticky reload lock for fuse word (14+32*x) */
#define BSEC_SRLOCKx_SRLOCK15_Pos (15U)
#define BSEC_SRLOCKx_SRLOCK15_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK15_Pos) /*!< 0x00008000 */
#define BSEC_SRLOCKx_SRLOCK15 BSEC_SRLOCKx_SRLOCK15_Msk /*!< Sticky reload lock for fuse word (15+32*x) */
#define BSEC_SRLOCKx_SRLOCK16_Pos (16U)
#define BSEC_SRLOCKx_SRLOCK16_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK16_Pos) /*!< 0x00010000 */
#define BSEC_SRLOCKx_SRLOCK16 BSEC_SRLOCKx_SRLOCK16_Msk /*!< Sticky reload lock for fuse word (16+32*x) */
#define BSEC_SRLOCKx_SRLOCK17_Pos (17U)
#define BSEC_SRLOCKx_SRLOCK17_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK17_Pos) /*!< 0x00020000 */
#define BSEC_SRLOCKx_SRLOCK17 BSEC_SRLOCKx_SRLOCK17_Msk /*!< Sticky reload lock for fuse word (17+32*x) */
#define BSEC_SRLOCKx_SRLOCK18_Pos (18U)
#define BSEC_SRLOCKx_SRLOCK18_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK18_Pos) /*!< 0x00040000 */
#define BSEC_SRLOCKx_SRLOCK18 BSEC_SRLOCKx_SRLOCK18_Msk /*!< Sticky reload lock for fuse word (18+32*x) */
#define BSEC_SRLOCKx_SRLOCK19_Pos (19U)
#define BSEC_SRLOCKx_SRLOCK19_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK19_Pos) /*!< 0x00080000 */
#define BSEC_SRLOCKx_SRLOCK19 BSEC_SRLOCKx_SRLOCK19_Msk /*!< Sticky reload lock for fuse word (19+32*x) */
#define BSEC_SRLOCKx_SRLOCK20_Pos (20U)
#define BSEC_SRLOCKx_SRLOCK20_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK20_Pos) /*!< 0x00100000 */
#define BSEC_SRLOCKx_SRLOCK20 BSEC_SRLOCKx_SRLOCK20_Msk /*!< Sticky reload lock for fuse word (20+32*x) */
#define BSEC_SRLOCKx_SRLOCK21_Pos (21U)
#define BSEC_SRLOCKx_SRLOCK21_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK21_Pos) /*!< 0x00200000 */
#define BSEC_SRLOCKx_SRLOCK21 BSEC_SRLOCKx_SRLOCK21_Msk /*!< Sticky reload lock for fuse word (21+32*x) */
#define BSEC_SRLOCKx_SRLOCK22_Pos (22U)
#define BSEC_SRLOCKx_SRLOCK22_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK22_Pos) /*!< 0x00400000 */
#define BSEC_SRLOCKx_SRLOCK22 BSEC_SRLOCKx_SRLOCK22_Msk /*!< Sticky reload lock for fuse word (22+32*x) */
#define BSEC_SRLOCKx_SRLOCK23_Pos (23U)
#define BSEC_SRLOCKx_SRLOCK23_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK23_Pos) /*!< 0x00800000 */
#define BSEC_SRLOCKx_SRLOCK23 BSEC_SRLOCKx_SRLOCK23_Msk /*!< Sticky reload lock for fuse word (23+32*x) */
#define BSEC_SRLOCKx_SRLOCK24_Pos (24U)
#define BSEC_SRLOCKx_SRLOCK24_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK24_Pos) /*!< 0x01000000 */
#define BSEC_SRLOCKx_SRLOCK24 BSEC_SRLOCKx_SRLOCK24_Msk /*!< Sticky reload lock for fuse word (24+32*x) */
#define BSEC_SRLOCKx_SRLOCK25_Pos (25U)
#define BSEC_SRLOCKx_SRLOCK25_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK25_Pos) /*!< 0x02000000 */
#define BSEC_SRLOCKx_SRLOCK25 BSEC_SRLOCKx_SRLOCK25_Msk /*!< Sticky reload lock for fuse word (25+32*x) */
#define BSEC_SRLOCKx_SRLOCK26_Pos (26U)
#define BSEC_SRLOCKx_SRLOCK26_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK26_Pos) /*!< 0x04000000 */
#define BSEC_SRLOCKx_SRLOCK26 BSEC_SRLOCKx_SRLOCK26_Msk /*!< Sticky reload lock for fuse word (26+32*x) */
#define BSEC_SRLOCKx_SRLOCK27_Pos (27U)
#define BSEC_SRLOCKx_SRLOCK27_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK27_Pos) /*!< 0x08000000 */
#define BSEC_SRLOCKx_SRLOCK27 BSEC_SRLOCKx_SRLOCK27_Msk /*!< Sticky reload lock for fuse word (27+32*x) */
#define BSEC_SRLOCKx_SRLOCK28_Pos (28U)
#define BSEC_SRLOCKx_SRLOCK28_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK28_Pos) /*!< 0x10000000 */
#define BSEC_SRLOCKx_SRLOCK28 BSEC_SRLOCKx_SRLOCK28_Msk /*!< Sticky reload lock for fuse word (28+32*x) */
#define BSEC_SRLOCKx_SRLOCK29_Pos (29U)
#define BSEC_SRLOCKx_SRLOCK29_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK29_Pos) /*!< 0x20000000 */
#define BSEC_SRLOCKx_SRLOCK29 BSEC_SRLOCKx_SRLOCK29_Msk /*!< Sticky reload lock for fuse word (29+32*x) */
#define BSEC_SRLOCKx_SRLOCK30_Pos (30U)
#define BSEC_SRLOCKx_SRLOCK30_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK30_Pos) /*!< 0x40000000 */
#define BSEC_SRLOCKx_SRLOCK30 BSEC_SRLOCKx_SRLOCK30_Msk /*!< Sticky reload lock for fuse word (30+32*x) */
#define BSEC_SRLOCKx_SRLOCK31_Pos (31U)
#define BSEC_SRLOCKx_SRLOCK31_Msk (0x1UL << BSEC_SRLOCKx_SRLOCK31_Pos) /*!< 0x80000000 */
#define BSEC_SRLOCKx_SRLOCK31 BSEC_SRLOCKx_SRLOCK31_Msk /*!< Sticky reload lock for fuse word (31+32*x) */
/**************** Bit definition for BSEC_OTPVLDRx register *****************/
#define BSEC_OTPVLDRx_VLDF0_Pos (0U)
#define BSEC_OTPVLDRx_VLDF0_Msk (0x1UL << BSEC_OTPVLDRx_VLDF0_Pos) /*!< 0x00000001 */
#define BSEC_OTPVLDRx_VLDF0 BSEC_OTPVLDRx_VLDF0_Msk /*!< Valid flag for shadow register (32*x) */
#define BSEC_OTPVLDRx_VLDF1_Pos (1U)
#define BSEC_OTPVLDRx_VLDF1_Msk (0x1UL << BSEC_OTPVLDRx_VLDF1_Pos) /*!< 0x00000002 */
#define BSEC_OTPVLDRx_VLDF1 BSEC_OTPVLDRx_VLDF1_Msk /*!< Valid flag for shadow register (1+32*x) */
#define BSEC_OTPVLDRx_VLDF2_Pos (2U)
#define BSEC_OTPVLDRx_VLDF2_Msk (0x1UL << BSEC_OTPVLDRx_VLDF2_Pos) /*!< 0x00000004 */
#define BSEC_OTPVLDRx_VLDF2 BSEC_OTPVLDRx_VLDF2_Msk /*!< Valid flag for shadow register (2+32*x) */
#define BSEC_OTPVLDRx_VLDF3_Pos (3U)
#define BSEC_OTPVLDRx_VLDF3_Msk (0x1UL << BSEC_OTPVLDRx_VLDF3_Pos) /*!< 0x00000008 */
#define BSEC_OTPVLDRx_VLDF3 BSEC_OTPVLDRx_VLDF3_Msk /*!< Valid flag for shadow register (3+32*x) */
#define BSEC_OTPVLDRx_VLDF4_Pos (4U)
#define BSEC_OTPVLDRx_VLDF4_Msk (0x1UL << BSEC_OTPVLDRx_VLDF4_Pos) /*!< 0x00000010 */
#define BSEC_OTPVLDRx_VLDF4 BSEC_OTPVLDRx_VLDF4_Msk /*!< Valid flag for shadow register (4+32*x) */
#define BSEC_OTPVLDRx_VLDF5_Pos (5U)
#define BSEC_OTPVLDRx_VLDF5_Msk (0x1UL << BSEC_OTPVLDRx_VLDF5_Pos) /*!< 0x00000020 */
#define BSEC_OTPVLDRx_VLDF5 BSEC_OTPVLDRx_VLDF5_Msk /*!< Valid flag for shadow register (5+32*x) */
#define BSEC_OTPVLDRx_VLDF6_Pos (6U)
#define BSEC_OTPVLDRx_VLDF6_Msk (0x1UL << BSEC_OTPVLDRx_VLDF6_Pos) /*!< 0x00000040 */
#define BSEC_OTPVLDRx_VLDF6 BSEC_OTPVLDRx_VLDF6_Msk /*!< Valid flag for shadow register (6+32*x) */
#define BSEC_OTPVLDRx_VLDF7_Pos (7U)
#define BSEC_OTPVLDRx_VLDF7_Msk (0x1UL << BSEC_OTPVLDRx_VLDF7_Pos) /*!< 0x00000080 */
#define BSEC_OTPVLDRx_VLDF7 BSEC_OTPVLDRx_VLDF7_Msk /*!< Valid flag for shadow register (7+32*x) */
#define BSEC_OTPVLDRx_VLDF8_Pos (8U)
#define BSEC_OTPVLDRx_VLDF8_Msk (0x1UL << BSEC_OTPVLDRx_VLDF8_Pos) /*!< 0x00000100 */
#define BSEC_OTPVLDRx_VLDF8 BSEC_OTPVLDRx_VLDF8_Msk /*!< Valid flag for shadow register (8+32*x) */
#define BSEC_OTPVLDRx_VLDF9_Pos (9U)
#define BSEC_OTPVLDRx_VLDF9_Msk (0x1UL << BSEC_OTPVLDRx_VLDF9_Pos) /*!< 0x00000200 */
#define BSEC_OTPVLDRx_VLDF9 BSEC_OTPVLDRx_VLDF9_Msk /*!< Valid flag for shadow register (9+32*x) */
#define BSEC_OTPVLDRx_VLDF10_Pos (10U)
#define BSEC_OTPVLDRx_VLDF10_Msk (0x1UL << BSEC_OTPVLDRx_VLDF10_Pos) /*!< 0x00000400 */
#define BSEC_OTPVLDRx_VLDF10 BSEC_OTPVLDRx_VLDF10_Msk /*!< Valid flag for shadow register (10+32*x) */
#define BSEC_OTPVLDRx_VLDF11_Pos (11U)
#define BSEC_OTPVLDRx_VLDF11_Msk (0x1UL << BSEC_OTPVLDRx_VLDF11_Pos) /*!< 0x00000800 */
#define BSEC_OTPVLDRx_VLDF11 BSEC_OTPVLDRx_VLDF11_Msk /*!< Valid flag for shadow register (11+32*x) */
#define BSEC_OTPVLDRx_VLDF12_Pos (12U)
#define BSEC_OTPVLDRx_VLDF12_Msk (0x1UL << BSEC_OTPVLDRx_VLDF12_Pos) /*!< 0x00001000 */
#define BSEC_OTPVLDRx_VLDF12 BSEC_OTPVLDRx_VLDF12_Msk /*!< Valid flag for shadow register (12+32*x) */
#define BSEC_OTPVLDRx_VLDF13_Pos (13U)
#define BSEC_OTPVLDRx_VLDF13_Msk (0x1UL << BSEC_OTPVLDRx_VLDF13_Pos) /*!< 0x00002000 */
#define BSEC_OTPVLDRx_VLDF13 BSEC_OTPVLDRx_VLDF13_Msk /*!< Valid flag for shadow register (13+32*x) */
#define BSEC_OTPVLDRx_VLDF14_Pos (14U)
#define BSEC_OTPVLDRx_VLDF14_Msk (0x1UL << BSEC_OTPVLDRx_VLDF14_Pos) /*!< 0x00004000 */
#define BSEC_OTPVLDRx_VLDF14 BSEC_OTPVLDRx_VLDF14_Msk /*!< Valid flag for shadow register (14+32*x) */
#define BSEC_OTPVLDRx_VLDF15_Pos (15U)
#define BSEC_OTPVLDRx_VLDF15_Msk (0x1UL << BSEC_OTPVLDRx_VLDF15_Pos) /*!< 0x00008000 */
#define BSEC_OTPVLDRx_VLDF15 BSEC_OTPVLDRx_VLDF15_Msk /*!< Valid flag for shadow register (15+32*x) */
#define BSEC_OTPVLDRx_VLDF16_Pos (16U)
#define BSEC_OTPVLDRx_VLDF16_Msk (0x1UL << BSEC_OTPVLDRx_VLDF16_Pos) /*!< 0x00010000 */
#define BSEC_OTPVLDRx_VLDF16 BSEC_OTPVLDRx_VLDF16_Msk /*!< Valid flag for shadow register (16+32*x) */
#define BSEC_OTPVLDRx_VLDF17_Pos (17U)
#define BSEC_OTPVLDRx_VLDF17_Msk (0x1UL << BSEC_OTPVLDRx_VLDF17_Pos) /*!< 0x00020000 */
#define BSEC_OTPVLDRx_VLDF17 BSEC_OTPVLDRx_VLDF17_Msk /*!< Valid flag for shadow register (17+32*x) */
#define BSEC_OTPVLDRx_VLDF18_Pos (18U)
#define BSEC_OTPVLDRx_VLDF18_Msk (0x1UL << BSEC_OTPVLDRx_VLDF18_Pos) /*!< 0x00040000 */
#define BSEC_OTPVLDRx_VLDF18 BSEC_OTPVLDRx_VLDF18_Msk /*!< Valid flag for shadow register (18+32*x) */
#define BSEC_OTPVLDRx_VLDF19_Pos (19U)
#define BSEC_OTPVLDRx_VLDF19_Msk (0x1UL << BSEC_OTPVLDRx_VLDF19_Pos) /*!< 0x00080000 */
#define BSEC_OTPVLDRx_VLDF19 BSEC_OTPVLDRx_VLDF19_Msk /*!< Valid flag for shadow register (19+32*x) */
#define BSEC_OTPVLDRx_VLDF20_Pos (20U)
#define BSEC_OTPVLDRx_VLDF20_Msk (0x1UL << BSEC_OTPVLDRx_VLDF20_Pos) /*!< 0x00100000 */
#define BSEC_OTPVLDRx_VLDF20 BSEC_OTPVLDRx_VLDF20_Msk /*!< Valid flag for shadow register (20+32*x) */
#define BSEC_OTPVLDRx_VLDF21_Pos (21U)
#define BSEC_OTPVLDRx_VLDF21_Msk (0x1UL << BSEC_OTPVLDRx_VLDF21_Pos) /*!< 0x00200000 */
#define BSEC_OTPVLDRx_VLDF21 BSEC_OTPVLDRx_VLDF21_Msk /*!< Valid flag for shadow register (21+32*x) */
#define BSEC_OTPVLDRx_VLDF22_Pos (22U)
#define BSEC_OTPVLDRx_VLDF22_Msk (0x1UL << BSEC_OTPVLDRx_VLDF22_Pos) /*!< 0x00400000 */
#define BSEC_OTPVLDRx_VLDF22 BSEC_OTPVLDRx_VLDF22_Msk /*!< Valid flag for shadow register (22+32*x) */
#define BSEC_OTPVLDRx_VLDF23_Pos (23U)
#define BSEC_OTPVLDRx_VLDF23_Msk (0x1UL << BSEC_OTPVLDRx_VLDF23_Pos) /*!< 0x00800000 */
#define BSEC_OTPVLDRx_VLDF23 BSEC_OTPVLDRx_VLDF23_Msk /*!< Valid flag for shadow register (23+32*x) */
#define BSEC_OTPVLDRx_VLDF24_Pos (24U)
#define BSEC_OTPVLDRx_VLDF24_Msk (0x1UL << BSEC_OTPVLDRx_VLDF24_Pos) /*!< 0x01000000 */
#define BSEC_OTPVLDRx_VLDF24 BSEC_OTPVLDRx_VLDF24_Msk /*!< Valid flag for shadow register (24+32*x) */
#define BSEC_OTPVLDRx_VLDF25_Pos (25U)
#define BSEC_OTPVLDRx_VLDF25_Msk (0x1UL << BSEC_OTPVLDRx_VLDF25_Pos) /*!< 0x02000000 */
#define BSEC_OTPVLDRx_VLDF25 BSEC_OTPVLDRx_VLDF25_Msk /*!< Valid flag for shadow register (25+32*x) */
#define BSEC_OTPVLDRx_VLDF26_Pos (26U)
#define BSEC_OTPVLDRx_VLDF26_Msk (0x1UL << BSEC_OTPVLDRx_VLDF26_Pos) /*!< 0x04000000 */
#define BSEC_OTPVLDRx_VLDF26 BSEC_OTPVLDRx_VLDF26_Msk /*!< Valid flag for shadow register (26+32*x) */
#define BSEC_OTPVLDRx_VLDF27_Pos (27U)
#define BSEC_OTPVLDRx_VLDF27_Msk (0x1UL << BSEC_OTPVLDRx_VLDF27_Pos) /*!< 0x08000000 */
#define BSEC_OTPVLDRx_VLDF27 BSEC_OTPVLDRx_VLDF27_Msk /*!< Valid flag for shadow register (27+32*x) */
#define BSEC_OTPVLDRx_VLDF28_Pos (28U)
#define BSEC_OTPVLDRx_VLDF28_Msk (0x1UL << BSEC_OTPVLDRx_VLDF28_Pos) /*!< 0x10000000 */
#define BSEC_OTPVLDRx_VLDF28 BSEC_OTPVLDRx_VLDF28_Msk /*!< Valid flag for shadow register (28+32*x) */
#define BSEC_OTPVLDRx_VLDF29_Pos (29U)
#define BSEC_OTPVLDRx_VLDF29_Msk (0x1UL << BSEC_OTPVLDRx_VLDF29_Pos) /*!< 0x20000000 */
#define BSEC_OTPVLDRx_VLDF29 BSEC_OTPVLDRx_VLDF29_Msk /*!< Valid flag for shadow register (29+32*x) */
#define BSEC_OTPVLDRx_VLDF30_Pos (30U)
#define BSEC_OTPVLDRx_VLDF30_Msk (0x1UL << BSEC_OTPVLDRx_VLDF30_Pos) /*!< 0x40000000 */
#define BSEC_OTPVLDRx_VLDF30 BSEC_OTPVLDRx_VLDF30_Msk /*!< Valid flag for shadow register (30+32*x) */
#define BSEC_OTPVLDRx_VLDF31_Pos (31U)
#define BSEC_OTPVLDRx_VLDF31_Msk (0x1UL << BSEC_OTPVLDRx_VLDF31_Pos) /*!< 0x80000000 */
#define BSEC_OTPVLDRx_VLDF31 BSEC_OTPVLDRx_VLDF31_Msk /*!< Valid flag for shadow register (31+32*x) */
/****************** Bit definition for BSEC_SFSRx register ******************/
#define BSEC_SFSRx_SFW0_Pos (0U)
#define BSEC_SFSRx_SFW0_Msk (0x1UL << BSEC_SFSRx_SFW0_Pos) /*!< 0x00000001 */
#define BSEC_SFSRx_SFW0 BSEC_SFSRx_SFW0_Msk /*!< Shadowed fuse word (32*x) */
#define BSEC_SFSRx_SFW1_Pos (1U)
#define BSEC_SFSRx_SFW1_Msk (0x1UL << BSEC_SFSRx_SFW1_Pos) /*!< 0x00000002 */
#define BSEC_SFSRx_SFW1 BSEC_SFSRx_SFW1_Msk /*!< Shadowed fuse word (1+32*x) */
#define BSEC_SFSRx_SFW2_Pos (2U)
#define BSEC_SFSRx_SFW2_Msk (0x1UL << BSEC_SFSRx_SFW2_Pos) /*!< 0x00000004 */
#define BSEC_SFSRx_SFW2 BSEC_SFSRx_SFW2_Msk /*!< Shadowed fuse word (2+32*x) */
#define BSEC_SFSRx_SFW3_Pos (3U)
#define BSEC_SFSRx_SFW3_Msk (0x1UL << BSEC_SFSRx_SFW3_Pos) /*!< 0x00000008 */
#define BSEC_SFSRx_SFW3 BSEC_SFSRx_SFW3_Msk /*!< Shadowed fuse word (3+32*x) */
#define BSEC_SFSRx_SFW4_Pos (4U)
#define BSEC_SFSRx_SFW4_Msk (0x1UL << BSEC_SFSRx_SFW4_Pos) /*!< 0x00000010 */
#define BSEC_SFSRx_SFW4 BSEC_SFSRx_SFW4_Msk /*!< Shadowed fuse word (4+32*x) */
#define BSEC_SFSRx_SFW5_Pos (5U)
#define BSEC_SFSRx_SFW5_Msk (0x1UL << BSEC_SFSRx_SFW5_Pos) /*!< 0x00000020 */
#define BSEC_SFSRx_SFW5 BSEC_SFSRx_SFW5_Msk /*!< Shadowed fuse word (5+32*x) */
#define BSEC_SFSRx_SFW6_Pos (6U)
#define BSEC_SFSRx_SFW6_Msk (0x1UL << BSEC_SFSRx_SFW6_Pos) /*!< 0x00000040 */
#define BSEC_SFSRx_SFW6 BSEC_SFSRx_SFW6_Msk /*!< Shadowed fuse word (6+32*x) */
#define BSEC_SFSRx_SFW7_Pos (7U)
#define BSEC_SFSRx_SFW7_Msk (0x1UL << BSEC_SFSRx_SFW7_Pos) /*!< 0x00000080 */
#define BSEC_SFSRx_SFW7 BSEC_SFSRx_SFW7_Msk /*!< Shadowed fuse word (7+32*x) */
#define BSEC_SFSRx_SFW8_Pos (8U)
#define BSEC_SFSRx_SFW8_Msk (0x1UL << BSEC_SFSRx_SFW8_Pos) /*!< 0x00000100 */
#define BSEC_SFSRx_SFW8 BSEC_SFSRx_SFW8_Msk /*!< Shadowed fuse word (8+32*x) */
#define BSEC_SFSRx_SFW9_Pos (9U)
#define BSEC_SFSRx_SFW9_Msk (0x1UL << BSEC_SFSRx_SFW9_Pos) /*!< 0x00000200 */
#define BSEC_SFSRx_SFW9 BSEC_SFSRx_SFW9_Msk /*!< Shadowed fuse word (9+32*x) */
#define BSEC_SFSRx_SFW10_Pos (10U)
#define BSEC_SFSRx_SFW10_Msk (0x1UL << BSEC_SFSRx_SFW10_Pos) /*!< 0x00000400 */
#define BSEC_SFSRx_SFW10 BSEC_SFSRx_SFW10_Msk /*!< Shadowed fuse word (10+32*x) */
#define BSEC_SFSRx_SFW11_Pos (11U)
#define BSEC_SFSRx_SFW11_Msk (0x1UL << BSEC_SFSRx_SFW11_Pos) /*!< 0x00000800 */
#define BSEC_SFSRx_SFW11 BSEC_SFSRx_SFW11_Msk /*!< Shadowed fuse word (11+32*x) */
#define BSEC_SFSRx_SFW12_Pos (12U)
#define BSEC_SFSRx_SFW12_Msk (0x1UL << BSEC_SFSRx_SFW12_Pos) /*!< 0x00001000 */
#define BSEC_SFSRx_SFW12 BSEC_SFSRx_SFW12_Msk /*!< Shadowed fuse word (12+32*x) */
#define BSEC_SFSRx_SFW13_Pos (13U)
#define BSEC_SFSRx_SFW13_Msk (0x1UL << BSEC_SFSRx_SFW13_Pos) /*!< 0x00002000 */
#define BSEC_SFSRx_SFW13 BSEC_SFSRx_SFW13_Msk /*!< Shadowed fuse word (13+32*x) */
#define BSEC_SFSRx_SFW14_Pos (14U)
#define BSEC_SFSRx_SFW14_Msk (0x1UL << BSEC_SFSRx_SFW14_Pos) /*!< 0x00004000 */
#define BSEC_SFSRx_SFW14 BSEC_SFSRx_SFW14_Msk /*!< Shadowed fuse word (14+32*x) */
#define BSEC_SFSRx_SFW15_Pos (15U)
#define BSEC_SFSRx_SFW15_Msk (0x1UL << BSEC_SFSRx_SFW15_Pos) /*!< 0x00008000 */
#define BSEC_SFSRx_SFW15 BSEC_SFSRx_SFW15_Msk /*!< Shadowed fuse word (15+32*x) */
#define BSEC_SFSRx_SFW16_Pos (16U)
#define BSEC_SFSRx_SFW16_Msk (0x1UL << BSEC_SFSRx_SFW16_Pos) /*!< 0x00010000 */
#define BSEC_SFSRx_SFW16 BSEC_SFSRx_SFW16_Msk /*!< Shadowed fuse word (16+32*x) */
#define BSEC_SFSRx_SFW17_Pos (17U)
#define BSEC_SFSRx_SFW17_Msk (0x1UL << BSEC_SFSRx_SFW17_Pos) /*!< 0x00020000 */
#define BSEC_SFSRx_SFW17 BSEC_SFSRx_SFW17_Msk /*!< Shadowed fuse word (17+32*x) */
#define BSEC_SFSRx_SFW18_Pos (18U)
#define BSEC_SFSRx_SFW18_Msk (0x1UL << BSEC_SFSRx_SFW18_Pos) /*!< 0x00040000 */
#define BSEC_SFSRx_SFW18 BSEC_SFSRx_SFW18_Msk /*!< Shadowed fuse word (18+32*x) */
#define BSEC_SFSRx_SFW19_Pos (19U)
#define BSEC_SFSRx_SFW19_Msk (0x1UL << BSEC_SFSRx_SFW19_Pos) /*!< 0x00080000 */
#define BSEC_SFSRx_SFW19 BSEC_SFSRx_SFW19_Msk /*!< Shadowed fuse word (19+32*x) */
#define BSEC_SFSRx_SFW20_Pos (20U)
#define BSEC_SFSRx_SFW20_Msk (0x1UL << BSEC_SFSRx_SFW20_Pos) /*!< 0x00100000 */
#define BSEC_SFSRx_SFW20 BSEC_SFSRx_SFW20_Msk /*!< Shadowed fuse word (20+32*x) */
#define BSEC_SFSRx_SFW21_Pos (21U)
#define BSEC_SFSRx_SFW21_Msk (0x1UL << BSEC_SFSRx_SFW21_Pos) /*!< 0x00200000 */
#define BSEC_SFSRx_SFW21 BSEC_SFSRx_SFW21_Msk /*!< Shadowed fuse word (21+32*x) */
#define BSEC_SFSRx_SFW22_Pos (22U)
#define BSEC_SFSRx_SFW22_Msk (0x1UL << BSEC_SFSRx_SFW22_Pos) /*!< 0x00400000 */
#define BSEC_SFSRx_SFW22 BSEC_SFSRx_SFW22_Msk /*!< Shadowed fuse word (22+32*x) */
#define BSEC_SFSRx_SFW23_Pos (23U)
#define BSEC_SFSRx_SFW23_Msk (0x1UL << BSEC_SFSRx_SFW23_Pos) /*!< 0x00800000 */
#define BSEC_SFSRx_SFW23 BSEC_SFSRx_SFW23_Msk /*!< Shadowed fuse word (23+32*x) */
#define BSEC_SFSRx_SFW24_Pos (24U)
#define BSEC_SFSRx_SFW24_Msk (0x1UL << BSEC_SFSRx_SFW24_Pos) /*!< 0x01000000 */
#define BSEC_SFSRx_SFW24 BSEC_SFSRx_SFW24_Msk /*!< Shadowed fuse word (24+32*x) */
#define BSEC_SFSRx_SFW25_Pos (25U)
#define BSEC_SFSRx_SFW25_Msk (0x1UL << BSEC_SFSRx_SFW25_Pos) /*!< 0x02000000 */
#define BSEC_SFSRx_SFW25 BSEC_SFSRx_SFW25_Msk /*!< Shadowed fuse word (25+32*x) */
#define BSEC_SFSRx_SFW26_Pos (26U)
#define BSEC_SFSRx_SFW26_Msk (0x1UL << BSEC_SFSRx_SFW26_Pos) /*!< 0x04000000 */
#define BSEC_SFSRx_SFW26 BSEC_SFSRx_SFW26_Msk /*!< Shadowed fuse word (26+32*x) */
#define BSEC_SFSRx_SFW27_Pos (27U)
#define BSEC_SFSRx_SFW27_Msk (0x1UL << BSEC_SFSRx_SFW27_Pos) /*!< 0x08000000 */
#define BSEC_SFSRx_SFW27 BSEC_SFSRx_SFW27_Msk /*!< Shadowed fuse word (27+32*x) */
#define BSEC_SFSRx_SFW28_Pos (28U)
#define BSEC_SFSRx_SFW28_Msk (0x1UL << BSEC_SFSRx_SFW28_Pos) /*!< 0x10000000 */
#define BSEC_SFSRx_SFW28 BSEC_SFSRx_SFW28_Msk /*!< Shadowed fuse word (28+32*x) */
#define BSEC_SFSRx_SFW29_Pos (29U)
#define BSEC_SFSRx_SFW29_Msk (0x1UL << BSEC_SFSRx_SFW29_Pos) /*!< 0x20000000 */
#define BSEC_SFSRx_SFW29 BSEC_SFSRx_SFW29_Msk /*!< Shadowed fuse word (29+32*x) */
#define BSEC_SFSRx_SFW30_Pos (30U)
#define BSEC_SFSRx_SFW30_Msk (0x1UL << BSEC_SFSRx_SFW30_Pos) /*!< 0x40000000 */
#define BSEC_SFSRx_SFW30 BSEC_SFSRx_SFW30_Msk /*!< Shadowed fuse word (30+32*x) */
#define BSEC_SFSRx_SFW31_Pos (31U)
#define BSEC_SFSRx_SFW31_Msk (0x1UL << BSEC_SFSRx_SFW31_Pos) /*!< 0x80000000 */
#define BSEC_SFSRx_SFW31 BSEC_SFSRx_SFW31_Msk /*!< Shadowed fuse word (31+32*x) */
/****************** Bit definition for BSEC_OTPCR register ******************/
#define BSEC_OTPCR_ADDR_Pos (0U)
#define BSEC_OTPCR_ADDR_Msk (0x1FFUL << BSEC_OTPCR_ADDR_Pos) /*!< 0x000001FF */
#define BSEC_OTPCR_ADDR BSEC_OTPCR_ADDR_Msk /*!< Fuse word address */
#define BSEC_OTPCR_PROG_Pos (13U)
#define BSEC_OTPCR_PROG_Msk (0x1UL << BSEC_OTPCR_PROG_Pos) /*!< 0x00002000 */
#define BSEC_OTPCR_PROG BSEC_OTPCR_PROG_Msk /*!< Fuse word programming */
#define BSEC_OTPCR_PPLOCK_Pos (14U)
#define BSEC_OTPCR_PPLOCK_Msk (0x1UL << BSEC_OTPCR_PPLOCK_Pos) /*!< 0x00004000 */
#define BSEC_OTPCR_PPLOCK BSEC_OTPCR_PPLOCK_Msk /*!< Permanent programming lock */
#define BSEC_OTPCR_LASTCID_Pos (19U)
#define BSEC_OTPCR_LASTCID_Msk (0x7UL << BSEC_OTPCR_LASTCID_Pos) /*!< 0x00380000 */
#define BSEC_OTPCR_LASTCID BSEC_OTPCR_LASTCID_Msk /*!< Last CID */
/******************* Bit definition for BSEC_WDR register *******************/
#define BSEC_WDR_WRDATA_Pos (0U)
#define BSEC_WDR_WRDATA_Msk (0xFFFFFFFFUL << BSEC_WDR_WRDATA_Pos) /*!< 0xFFFFFFFF */
#define BSEC_WDR_WRDATA BSEC_WDR_WRDATA_Msk /*!< OTP write data */
/**************** Bit definition for BSEC_SCRATCHRx register ****************/
#define BSEC_SCRATCHRx_SDATA_Pos (0U)
#define BSEC_SCRATCHRx_SDATA_Msk (0xFFFFFFFFUL << BSEC_SCRATCHRx_SDATA_Pos) /*!< 0xFFFFFFFF */
#define BSEC_SCRATCHRx_SDATA BSEC_SCRATCHRx_SDATA_Msk /*!< Scratch data */
/****************** Bit definition for BSEC_LOCKR register ******************/
#define BSEC_LOCKR_GWLOCK_Pos (0U)
#define BSEC_LOCKR_GWLOCK_Msk (0x1UL << BSEC_LOCKR_GWLOCK_Pos) /*!< 0x00000001 */
#define BSEC_LOCKR_GWLOCK BSEC_LOCKR_GWLOCK_Msk /*!< Global write lock */
#define BSEC_LOCKR_HKLOCK_Pos (2U)
#define BSEC_LOCKR_HKLOCK_Msk (0x1UL << BSEC_LOCKR_HKLOCK_Pos) /*!< 0x00000004 */
#define BSEC_LOCKR_HKLOCK BSEC_LOCKR_HKLOCK_Msk /*!< Hardware key lock */
/***************** Bit definition for BSEC_JTAGINR register *****************/
#define BSEC_JTAGINR_JDATAIN_Pos (0U)
#define BSEC_JTAGINR_JDATAIN_Msk (0xFFFFFFFFUL << BSEC_JTAGINR_JDATAIN_Pos) /*!< 0xFFFFFFFF */
#define BSEC_JTAGINR_JDATAIN BSEC_JTAGINR_JDATAIN_Msk /*!< JTAG input data */
/**************** Bit definition for BSEC_JTAGOUTR register *****************/
#define BSEC_JTAGOUTR_JDATAOUT_Pos (0U)
#define BSEC_JTAGOUTR_JDATAOUT_Msk (0xFFFFFFFFUL << BSEC_JTAGOUTR_JDATAOUT_Pos) /*!< 0xFFFFFFFF */
#define BSEC_JTAGOUTR_JDATAOUT BSEC_JTAGOUTR_JDATAOUT_Msk /*!< JTAG output data */
/***************** Bit definition for BSEC_UNMAPR register ******************/
#define BSEC_UNMAPR_UNMAP_Pos (0U)
#define BSEC_UNMAPR_UNMAP_Msk (0xFFFFFFFFUL << BSEC_UNMAPR_UNMAP_Pos) /*!< 0xFFFFFFFF */
#define BSEC_UNMAPR_UNMAP BSEC_UNMAPR_UNMAP_Msk /*!< Unmap key */
/******************* Bit definition for BSEC_SR register ********************/
#define BSEC_SR_HVALID_Pos (1U)
#define BSEC_SR_HVALID_Msk (0x1UL << BSEC_SR_HVALID_Pos) /*!< 0x00000002 */
#define BSEC_SR_HVALID BSEC_SR_HVALID_Msk /*!< Hardware key valid */
#define BSEC_SR_DBGREQ_Pos (16U)
#define BSEC_SR_DBGREQ_Msk (0x1UL << BSEC_SR_DBGREQ_Pos) /*!< 0x00010000 */
#define BSEC_SR_DBGREQ BSEC_SR_DBGREQ_Msk /*!< Debug request */
#define BSEC_SR_NVSTATE_Pos (26U)
#define BSEC_SR_NVSTATE_Msk (0x3FUL << BSEC_SR_NVSTATE_Pos) /*!< 0xFC000000 */
#define BSEC_SR_NVSTATE BSEC_SR_NVSTATE_Msk /*!< Non-volatile state */
/****************** Bit definition for BSEC_OTPSR register ******************/
#define BSEC_OTPSR_BUSY_Pos (0U)
#define BSEC_OTPSR_BUSY_Msk (0x1UL << BSEC_OTPSR_BUSY_Pos) /*!< 0x00000001 */
#define BSEC_OTPSR_BUSY BSEC_OTPSR_BUSY_Msk /*!< Busy flag */
#define BSEC_OTPSR_INIT_DONE_Pos (1U)
#define BSEC_OTPSR_INIT_DONE_Msk (0x1UL << BSEC_OTPSR_INIT_DONE_Pos) /*!< 0x00000002 */
#define BSEC_OTPSR_INIT_DONE BSEC_OTPSR_INIT_DONE_Msk /*!< Initialization done */
#define BSEC_OTPSR_HIDEUP_Pos (2U)
#define BSEC_OTPSR_HIDEUP_Msk (0x1UL << BSEC_OTPSR_HIDEUP_Pos) /*!< 0x00000004 */
#define BSEC_OTPSR_HIDEUP BSEC_OTPSR_HIDEUP_Msk /*!< Hide upper fuse words */
#define BSEC_OTPSR_OTPNVIR_Pos (4U)
#define BSEC_OTPSR_OTPNVIR_Msk (0x1UL << BSEC_OTPSR_OTPNVIR_Pos) /*!< 0x00000010 */
#define BSEC_OTPSR_OTPNVIR BSEC_OTPSR_OTPNVIR_Msk /*!< OTP not virgin */
#define BSEC_OTPSR_OTPERR_Pos (5U)
#define BSEC_OTPSR_OTPERR_Msk (0x1UL << BSEC_OTPSR_OTPERR_Pos) /*!< 0x00000020 */
#define BSEC_OTPSR_OTPERR BSEC_OTPSR_OTPERR_Msk /*!< OTP with error */
#define BSEC_OTPSR_OTPSEC_Pos (6U)
#define BSEC_OTPSR_OTPSEC_Msk (0x1UL << BSEC_OTPSR_OTPSEC_Pos) /*!< 0x00000040 */
#define BSEC_OTPSR_OTPSEC BSEC_OTPSR_OTPSEC_Msk /*!< OTP with single error correction */
#define BSEC_OTPSR_PROGFAIL_Pos (16U)
#define BSEC_OTPSR_PROGFAIL_Msk (0x1UL << BSEC_OTPSR_PROGFAIL_Pos) /*!< 0x00010000 */
#define BSEC_OTPSR_PROGFAIL BSEC_OTPSR_PROGFAIL_Msk /*!< Programming failed */
#define BSEC_OTPSR_DISTURBF_Pos (17U)
#define BSEC_OTPSR_DISTURBF_Msk (0x1UL << BSEC_OTPSR_DISTURBF_Pos) /*!< 0x00020000 */
#define BSEC_OTPSR_DISTURBF BSEC_OTPSR_DISTURBF_Msk /*!< Disturb flag */
#define BSEC_OTPSR_DEDF_Pos (18U)
#define BSEC_OTPSR_DEDF_Msk (0x1UL << BSEC_OTPSR_DEDF_Pos) /*!< 0x00040000 */
#define BSEC_OTPSR_DEDF BSEC_OTPSR_DEDF_Msk /*!< Double error detection flag */
#define BSEC_OTPSR_SECF_Pos (19U)
#define BSEC_OTPSR_SECF_Msk (0x1UL << BSEC_OTPSR_SECF_Pos) /*!< 0x00080000 */
#define BSEC_OTPSR_SECF BSEC_OTPSR_SECF_Msk /*!< Single error correction flag */
#define BSEC_OTPSR_PPLF_Pos (20U)
#define BSEC_OTPSR_PPLF_Msk (0x1UL << BSEC_OTPSR_PPLF_Pos) /*!< 0x00100000 */
#define BSEC_OTPSR_PPLF BSEC_OTPSR_PPLF_Msk /*!< Permanent programming lock flag */
#define BSEC_OTPSR_PPLMF_Pos (21U)
#define BSEC_OTPSR_PPLMF_Msk (0x1UL << BSEC_OTPSR_PPLMF_Pos) /*!< 0x00200000 */
#define BSEC_OTPSR_PPLMF BSEC_OTPSR_PPLMF_Msk /*!< Permanent programming lock mismatch flag */
#define BSEC_OTPSR_AMEF_Pos (22U)
#define BSEC_OTPSR_AMEF_Msk (0x1UL << BSEC_OTPSR_AMEF_Pos) /*!< 0x00400000 */
#define BSEC_OTPSR_AMEF BSEC_OTPSR_AMEF_Msk /*!< Addresses mismatch error flag */
/***************** Bit definition for BSEC_EPOCHRx register *****************/
#define BSEC_EPOCHRx_EPOCH_Pos (0U)
#define BSEC_EPOCHRx_EPOCH_Msk (0xFFFFFFFFUL << BSEC_EPOCHRx_EPOCH_Pos) /*!< 0xFFFFFFFF */
#define BSEC_EPOCHRx_EPOCH BSEC_EPOCHRx_EPOCH_Msk /*!< Epoch */
/**************** Bit definition for BSEC_EPOCHSELR register ****************/
#define BSEC_EPOCHSELR_EPSEL_Pos (0U)
#define BSEC_EPOCHSELR_EPSEL_Msk (0x1UL << BSEC_EPOCHSELR_EPSEL_Pos) /*!< 0x00000001 */
#define BSEC_EPOCHSELR_EPSEL BSEC_EPOCHSELR_EPSEL_Msk /*!< Epoch selection */
/****************** Bit definition for BSEC_DBGCR register ******************/
#define BSEC_DBGCR_UNLOCK_Pos (8U)
#define BSEC_DBGCR_UNLOCK_Msk (0xFFUL << BSEC_DBGCR_UNLOCK_Pos) /*!< 0x0000FF00 */
#define BSEC_DBGCR_UNLOCK BSEC_DBGCR_UNLOCK_Msk /*!< Non-secure debug authorization */
#define BSEC_DBGCR_AUTH_HDPL_Pos (16U)
#define BSEC_DBGCR_AUTH_HDPL_Msk (0xFFUL << BSEC_DBGCR_AUTH_HDPL_Pos) /*!< 0x00FF0000 */
#define BSEC_DBGCR_AUTH_HDPL BSEC_DBGCR_AUTH_HDPL_Msk /*!< Level at which debug may be opened */
#define BSEC_DBGCR_AUTH_SEC_Pos (24U)
#define BSEC_DBGCR_AUTH_SEC_Msk (0xFFUL << BSEC_DBGCR_AUTH_SEC_Pos) /*!< 0xFF000000 */
#define BSEC_DBGCR_AUTH_SEC BSEC_DBGCR_AUTH_SEC_Msk /*!< Secure debug authorization */
/*************** Bit definition for BSEC_AP_UNLOCK register *****************/
#define BSEC_AP_UNLOCK_UNLOCK_Pos (0U)
#define BSEC_AP_UNLOCK_UNLOCK_Msk (0xFFUL << BSEC_AP_UNLOCK_UNLOCK_Pos) /*!< 0x000000FF */
#define BSEC_AP_UNLOCK_UNLOCK BSEC_AP_UNLOCK_UNLOCK_Msk /*!< Unlock DBG_MCU AP interface */
/***************** Bit definition for BSEC_HDPLSR register ******************/
#define BSEC_HDPLSR_HDPL_Pos (0U)
#define BSEC_HDPLSR_HDPL_Msk (0xFFUL << BSEC_HDPLSR_HDPL_Pos) /*!< 0x000000FF */
#define BSEC_HDPLSR_HDPL BSEC_HDPLSR_HDPL_Msk /*!< Current HDPL */
/***************** Bit definition for BSEC_HDPLCR register ******************/
#define BSEC_HDPLCR_INCR_HDPL_Pos (0U)
#define BSEC_HDPLCR_INCR_HDPL_Msk (0xFFFFFFFFUL << BSEC_HDPLCR_INCR_HDPL_Pos) /*!< 0xFFFFFFFF */
#define BSEC_HDPLCR_INCR_HDPL BSEC_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL */
/***************** Bit definition for BSEC_NEXTLR register ******************/
#define BSEC_NEXTLR_INCR_Pos (0U)
#define BSEC_NEXTLR_INCR_Msk (0x3UL << BSEC_NEXTLR_INCR_Pos) /*!< 0x00000003 */
#define BSEC_NEXTLR_INCR BSEC_NEXTLR_INCR_Msk /*!< Increment */
/***************** Bit definition for BSEC_WOSCRx register ******************/
#define BSEC_WOSCRx_WOSDATA_Pos (0U)
#define BSEC_WOSCRx_WOSDATA_Msk (0xFFFFFFFFUL << BSEC_WOSCRx_WOSDATA_Pos) /*!< 0xFFFFFFFF */
#define BSEC_WOSCRx_WOSDATA BSEC_WOSCRx_WOSDATA_Msk /*!< Write once scratch data */
/****************** Bit definition for BSEC_HRCR register *******************/
#define BSEC_HRCR_HRC_Pos (0U)
#define BSEC_HRCR_HRC_Msk (0xFFFFFFFFUL << BSEC_HRCR_HRC_Pos) /*!< 0xFFFFFFFF */
#define BSEC_HRCR_HRC BSEC_HRCR_HRC_Msk /*!< Hot reset counter */
/****************** Bit definition for BSEC_WRCR register *******************/
#define BSEC_WRCR_WRC_Pos (0U)
#define BSEC_WRCR_WRC_Msk (0xFFFFFFFFUL << BSEC_WRCR_WRC_Pos) /*!< 0xFFFFFFFF */
#define BSEC_WRCR_WRC BSEC_WRCR_WRC_Msk /*!< Warm reset counter */
/******************************************************************************/
/* */
/* CACHEAXI */
/* */
/******************************************************************************/
/**************** Bit definition for CACHEAXI_CR1 register ******************/
#define CACHEAXI_CR1_EN_Pos (0U)
#define CACHEAXI_CR1_EN_Msk (0x1UL << CACHEAXI_CR1_EN_Pos) /*!< 0x00000001 */
#define CACHEAXI_CR1_EN CACHEAXI_CR1_EN_Msk /*!< Enable */
#define CACHEAXI_CR1_CACHEINV_Pos (1U)
#define CACHEAXI_CR1_CACHEINV_Msk (0x1UL << CACHEAXI_CR1_CACHEINV_Pos) /*!< 0x00000002 */
#define CACHEAXI_CR1_CACHEINV CACHEAXI_CR1_CACHEINV_Msk /*!< Cache invalidation */
#define CACHEAXI_CR1_RHITMEN_Pos (16U)
#define CACHEAXI_CR1_RHITMEN_Msk (0x1UL << CACHEAXI_CR1_RHITMEN_Pos) /*!< 0x00010000 */
#define CACHEAXI_CR1_RHITMEN CACHEAXI_CR1_RHITMEN_Msk /*!< Read Hit monitor enable */
#define CACHEAXI_CR1_RMISSMEN_Pos (17U)
#define CACHEAXI_CR1_RMISSMEN_Msk (0x1UL << CACHEAXI_CR1_RMISSMEN_Pos) /*!< 0x00020000 */
#define CACHEAXI_CR1_RMISSMEN CACHEAXI_CR1_RMISSMEN_Msk /*!< Read Miss monitor enable */
#define CACHEAXI_CR1_RHITMRST_Pos (18U)
#define CACHEAXI_CR1_RHITMRST_Msk (0x1UL << CACHEAXI_CR1_RHITMRST_Pos) /*!< 0x00040000 */
#define CACHEAXI_CR1_RHITMRST CACHEAXI_CR1_RHITMRST_Msk /*!< Read Hit monitor reset */
#define CACHEAXI_CR1_RMISSMRST_Pos (19U)
#define CACHEAXI_CR1_RMISSMRST_Msk (0x1UL << CACHEAXI_CR1_RMISSMRST_Pos) /*!< 0x00080000 */
#define CACHEAXI_CR1_RMISSMRST CACHEAXI_CR1_RMISSMRST_Msk /*!< Read Miss monitor reset */
#define CACHEAXI_CR1_WHITMEN_Pos (20U)
#define CACHEAXI_CR1_WHITMEN_Msk (0x1UL << CACHEAXI_CR1_WHITMEN_Pos) /*!< 0x00100000 */
#define CACHEAXI_CR1_WHITMEN CACHEAXI_CR1_WHITMEN_Msk /*!< Write Hit monitor enable */
#define CACHEAXI_CR1_WMISSMEN_Pos (21U)
#define CACHEAXI_CR1_WMISSMEN_Msk (0x1UL << CACHEAXI_CR1_WMISSMEN_Pos) /*!< 0x00200000 */
#define CACHEAXI_CR1_WMISSMEN CACHEAXI_CR1_WMISSMEN_Msk /*!< Write Miss monitor enable */
#define CACHEAXI_CR1_WHITMRST_Pos (22U)
#define CACHEAXI_CR1_WHITMRST_Msk (0x1UL << CACHEAXI_CR1_WHITMRST_Pos) /*!< 0x00400000 */
#define CACHEAXI_CR1_WHITMRST CACHEAXI_CR1_WHITMRST_Msk /*!< Write Hit monitor reset */
#define CACHEAXI_CR1_WMISSMRST_Pos (23U)
#define CACHEAXI_CR1_WMISSMRST_Msk (0x1UL << CACHEAXI_CR1_WMISSMRST_Pos) /*!< 0x00800000 */
#define CACHEAXI_CR1_WMISSMRST CACHEAXI_CR1_WMISSMRST_Msk /*!< Write Miss monitor reset */
#define CACHEAXI_CR1_RAMMEN_Pos (24U)
#define CACHEAXI_CR1_RAMMEN_Msk (0x1UL << CACHEAXI_CR1_RAMMEN_Pos) /*!< 0x01000000 */
#define CACHEAXI_CR1_RAMMEN CACHEAXI_CR1_RAMMEN_Msk /*!< Read-allocate miss monitor enable */
#define CACHEAXI_CR1_WAMMEN_Pos (25U)
#define CACHEAXI_CR1_WAMMEN_Msk (0x1UL << CACHEAXI_CR1_WAMMEN_Pos) /*!< 0x02000000 */
#define CACHEAXI_CR1_WAMMEN CACHEAXI_CR1_WAMMEN_Msk /*!< Write-allocate miss monitor enable */
#define CACHEAXI_CR1_RAMMRST_Pos (26U)
#define CACHEAXI_CR1_RAMMRST_Msk (0x1UL << CACHEAXI_CR1_RAMMRST_Pos) /*!< 0x04000000 */
#define CACHEAXI_CR1_RAMMRST CACHEAXI_CR1_RAMMRST_Msk /*!< Read-allocate miss monitor reset */
#define CACHEAXI_CR1_WAMMRST_Pos (27U)
#define CACHEAXI_CR1_WAMMRST_Msk (0x1UL << CACHEAXI_CR1_WAMMRST_Pos) /*!< 0x08000000 */
#define CACHEAXI_CR1_WAMMRST CACHEAXI_CR1_WAMMRST_Msk /*!< Write-allocate miss monitor reset */
#define CACHEAXI_CR1_WTMEN_Pos (28U)
#define CACHEAXI_CR1_WTMEN_Msk (0x1UL << CACHEAXI_CR1_WTMEN_Pos) /*!< 0x10000000 */
#define CACHEAXI_CR1_WTMEN CACHEAXI_CR1_WTMEN_Msk /*!< Write-through monitor enable */
#define CACHEAXI_CR1_EVIMEN_Pos (29U)
#define CACHEAXI_CR1_EVIMEN_Msk (0x1UL << CACHEAXI_CR1_EVIMEN_Pos) /*!< 0x20000000 */
#define CACHEAXI_CR1_EVIMEN CACHEAXI_CR1_EVIMEN_Msk /*!< Eviction monitor enable */
#define CACHEAXI_CR1_WTMRST_Pos (30U)
#define CACHEAXI_CR1_WTMRST_Msk (0x1UL << CACHEAXI_CR1_WTMRST_Pos) /*!< 0x40000000 */
#define CACHEAXI_CR1_WTMRST CACHEAXI_CR1_WTMRST_Msk /*!< Write-through monitor reset */
#define CACHEAXI_CR1_EVIMRST_Pos (31U)
#define CACHEAXI_CR1_EVIMRST_Msk (0x1UL << CACHEAXI_CR1_EVIMRST_Pos) /*!< 0x80000000 */
#define CACHEAXI_CR1_EVIMRST CACHEAXI_CR1_EVIMRST_Msk /*!< Eviction monitor reset */
/****************** Bit definition for CACHEAXI_SR register *******************/
#define CACHEAXI_SR_BUSYF_Pos (0U)
#define CACHEAXI_SR_BUSYF_Msk (0x1UL << CACHEAXI_SR_BUSYF_Pos) /*!< 0x00000001 */
#define CACHEAXI_SR_BUSYF CACHEAXI_SR_BUSYF_Msk /*!< Busy flag */
#define CACHEAXI_SR_BSYENDF_Pos (1U)
#define CACHEAXI_SR_BSYENDF_Msk (0x1UL << CACHEAXI_SR_BSYENDF_Pos) /*!< 0x00000002 */
#define CACHEAXI_SR_BSYENDF CACHEAXI_SR_BSYENDF_Msk /*!< Busy end flag */
#define CACHEAXI_SR_ERRF_Pos (2U)
#define CACHEAXI_SR_ERRF_Msk (0x1UL << CACHEAXI_SR_ERRF_Pos) /*!< 0x00000004 */
#define CACHEAXI_SR_ERRF CACHEAXI_SR_ERRF_Msk /*!< Cache error flag */
#define CACHEAXI_SR_BUSYCMDF_Pos (3U)
#define CACHEAXI_SR_BUSYCMDF_Msk (0x1UL << CACHEAXI_SR_BUSYCMDF_Pos) /*!< 0x00000008 */
#define CACHEAXI_SR_BUSYCMDF CACHEAXI_SR_BUSYCMDF_Msk /*!< Busy command flag */
#define CACHEAXI_SR_CMDENDF_Pos (4U)
#define CACHEAXI_SR_CMDENDF_Msk (0x1UL << CACHEAXI_SR_CMDENDF_Pos) /*!< 0x00000010 */
#define CACHEAXI_SR_CMDENDF CACHEAXI_SR_CMDENDF_Msk /*!< Command end flag */
/****************** Bit definition for CACHEAXI_IER register ******************/
#define CACHEAXI_IER_BSYENDIE_Pos (1U)
#define CACHEAXI_IER_BSYENDIE_Msk (0x1UL << CACHEAXI_IER_BSYENDIE_Pos) /*!< 0x00000002 */
#define CACHEAXI_IER_BSYENDIE CACHEAXI_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */
#define CACHEAXI_IER_ERRIE_Pos (2U)
#define CACHEAXI_IER_ERRIE_Msk (0x1UL << CACHEAXI_IER_ERRIE_Pos) /*!< 0x00000004 */
#define CACHEAXI_IER_ERRIE CACHEAXI_IER_ERRIE_Msk /*!< Cache error interrupt enable */
#define CACHEAXI_IER_CMDENDIE_Pos (4U)
#define CACHEAXI_IER_CMDENDIE_Msk (0x1UL << CACHEAXI_IER_CMDENDIE_Pos) /*!< 0x00000010 */
#define CACHEAXI_IER_CMDENDIE CACHEAXI_IER_CMDENDIE_Msk /*!< Command end interrupt enable */
/****************** Bit definition for CACHEAXI_FCR register ******************/
#define CACHEAXI_FCR_CBSYENDF_Pos (1U)
#define CACHEAXI_FCR_CBSYENDF_Msk (0x1UL << CACHEAXI_FCR_CBSYENDF_Pos) /*!< 0x00000002 */
#define CACHEAXI_FCR_CBSYENDF CACHEAXI_FCR_CBSYENDF_Msk /*!< Busy end flag clear */
#define CACHEAXI_FCR_CERRF_Pos (2U)
#define CACHEAXI_FCR_CERRF_Msk (0x1UL << CACHEAXI_FCR_CERRF_Pos) /*!< 0x00000004 */
#define CACHEAXI_FCR_CERRF CACHEAXI_FCR_CERRF_Msk /*!< Cache error flag clear */
#define CACHEAXI_FCR_CCMDENDF_Pos (4U)
#define CACHEAXI_FCR_CCMDENDF_Msk (0x1UL << CACHEAXI_FCR_CCMDENDF_Pos) /*!< 0x00000010 */
#define CACHEAXI_FCR_CCMDENDF CACHEAXI_FCR_CCMDENDF_Msk /*!< Command end flag clear */
/****************** Bit definition for CACHEAXI_RHMONR register ****************/
#define CACHEAXI_RHMONR_RHITMON_Pos (0U)
#define CACHEAXI_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_RHMONR_RHITMON CACHEAXI_RHMONR_RHITMON_Msk /*!< Cache read hit monitor register */
/****************** Bit definition for CACHEAXI_RMMONR register ****************/
#define CACHEAXI_RMMONR_RMISSMON_Pos (0U)
#define CACHEAXI_RMMONR_RMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_RMMONR_RMISSMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_RMMONR_RMISSMON CACHEAXI_RMMONR_RMISSMON_Msk /*!< Cache read miss monitor register */
/****************** Bit definition for CACHEAXI_RAMMONR register ****************/
#define CACHEAXI_RAMMONR_RAMMON_Pos (0U)
#define CACHEAXI_RAMMONR_RAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_RAMMONR_RAMMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_RAMMONR_RAMMON CACHEAXI_RAMMONR_RAMMON_Msk /*!< Cache read-allocate miss monitor counter */
/****************** Bit definition for CACHEAXI_EVIMONR register ****************/
#define CACHEAXI_EVIMONR_EVIMON_Pos (0U)
#define CACHEAXI_EVIMONR_EVIMON_Msk (0xFFFFFFFFUL << CACHEAXI_EVIMONR_EVIMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_EVIMONR_EVIMON CACHEAXI_EVIMONR_EVIMON_Msk /*!< Cache eviction monitor counter */
/****************** Bit definition for CACHEAXI_WHMONR register ****************/
#define CACHEAXI_WHMONR_WHITMON_Pos (0U)
#define CACHEAXI_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << CACHEAXI_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_WHMONR_WHITMON CACHEAXI_WHMONR_WHITMON_Msk /*!< Cache write hit monitor register */
/****************** Bit definition for CACHEAXI_WMMONR register ****************/
#define CACHEAXI_WMMONR_WMISSMON_Pos (0U)
#define CACHEAXI_WMMONR_WMISSMON_Msk (0xFFFFFFFFUL << CACHEAXI_WMMONR_WMISSMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_WMMONR_WMISSMON CACHEAXI_WMMONR_WMISSMON_Msk /*!< Cache write miss monitor register */
/****************** Bit definition for CACHEAXI_WAMMONR register ****************/
#define CACHEAXI_WAMMONR_WAMMON_Pos (0U)
#define CACHEAXI_WAMMONR_WAMMON_Msk (0xFFFFFFFFUL << CACHEAXI_WAMMONR_WAMMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_WAMMONR_WAMMON CACHEAXI_WAMMONR_WAMMON_Msk /*!< Cache write-allocate miss monitor register */
/****************** Bit definition for CACHEAXI_WTMONR register ****************/
#define CACHEAXI_WTMONR_WTMON_Pos (0U)
#define CACHEAXI_WTMONR_WTMON_Msk (0xFFFFFFFFUL << CACHEAXI_WTMONR_WTMON_Pos) /*!< 0xFFFFFFFF */
#define CACHEAXI_WTMONR_WTMON CACHEAXI_WTMONR_WTMON_Msk /*!< Cache write-through monitor register */
/**************** Bit definition for CACHEAXI_CR2 register ******************/
#define CACHEAXI_CR2_STARTCMD_Pos (0U)
#define CACHEAXI_CR2_STARTCMD_Msk (0x1UL << CACHEAXI_CR2_STARTCMD_Pos) /*!< 0x00000001 */
#define CACHEAXI_CR2_STARTCMD CACHEAXI_CR2_STARTCMD_Msk /*!< Starts maintenance range command */
#define CACHEAXI_CR2_CACHECMD_Pos (1U)
#define CACHEAXI_CR2_CACHECMD_Msk (0x3UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000006 */
#define CACHEAXI_CR2_CACHECMD CACHEAXI_CR2_CACHECMD_Msk /*!< Cache command maintenance operation */
#define CACHEAXI_CR2_CACHECMD_0 (0x1UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000002 */
#define CACHEAXI_CR2_CACHECMD_1 (0x2UL << CACHEAXI_CR2_CACHECMD_Pos) /*!< 0x00000004 */
/****************** Bit definition for CACHEAXI_CMDRSADDRR register ****************/
#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos (0U)
#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFC0 */
#define CACHEAXI_CMDRSADDRR_CMDSTARTADDR CACHEAXI_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */
/****************** Bit definition for CACHEAXI_CMDREADDRR register ****************/
#define CACHEAXI_CMDREADDRR_CMDENDADDR_Pos (0U)
#define CACHEAXI_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFC0UL << CACHEAXI_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFC0 */
#define CACHEAXI_CMDREADDRR_CMDENDADDR CACHEAXI_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x3UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000180 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
#define CRC_CR_REV_OUT_0 (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT_1 (0x2UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000100 */
#define CRC_CR_RTYPE_IN_Pos (9U)
#define CRC_CR_RTYPE_IN_Msk (0x1UL << CRC_CR_RTYPE_IN_Pos) /*!< 0x00000200 */
#define CRC_CR_RTYPE_IN CRC_CR_RTYPE_IN_Msk /*!< Reverse type input */
#define CRC_CR_RTYPE_OUT_Pos (10U)
#define CRC_CR_RTYPE_OUT_Msk (0x1UL << CRC_CR_RTYPE_OUT_Pos) /*!< 0x00000400 */
#define CRC_CR_RTYPE_OUT CRC_CR_RTYPE_OUT_Msk /*!< Reverse type output*/
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* Cryp Processor */
/* */
/******************************************************************************/
/******************* Bits definition for CRYP_CR register ********************/
#define CRYP_CR_ALGODIR_Pos (2U)
#define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
#define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk /*!< Algorithm direction (Encrypt/Decrypt) */
#define CRYP_CR_ALGOMODE_Pos (3U)
#define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
#define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk /*!< Algorithm mode */
#define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
#define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
#define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_3 (0x10000UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080000 */
#define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
#define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
#define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
#define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
#define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
#define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
#define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
#define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
#define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
#define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
#define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
#define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
#define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
#define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
#define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
#define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
#define CRYP_CR_DATATYPE_Pos (6U)
#define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
#define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk /*!< Data Type selection */
#define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
#define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
#define CRYP_CR_KEYSIZE_Pos (8U)
#define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
#define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk /*!< Key Size selection */
#define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
#define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
#define CRYP_CR_FFLUSH_Pos (14U)
#define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
#define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk /*!< CRYP FIFO Flush */
#define CRYP_CR_CRYPEN_Pos (15U)
#define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
#define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk /*!< CRYP processor enable */
#define CRYP_CR_GCM_CCMPH_Pos (16U)
#define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
#define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk /*!< GCM or CCM Phase selection */
#define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
#define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
#define CRYP_CR_NPBLB_Pos (20U)
#define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
#define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk /*!< Number of Padding Bytes in Last Block of payload */
#define CRYP_CR_KMOD_Pos (24U)
#define CRYP_CR_KMOD_Msk (0x3UL << CRYP_CR_KMOD_Pos) /*!< 0x03000000 */
#define CRYP_CR_KMOD CRYP_CR_KMOD_Msk /*!< Key mode selection */
#define CRYP_CR_KMOD_0 (0x1UL << CRYP_CR_KMOD_Pos) /*!< 0x01000000 */
#define CRYP_CR_KMOD_1 (0x2UL << CRYP_CR_KMOD_Pos) /*!< 0x02000000 */
#define CRYP_CR_IPRST_Pos (31U)
#define CRYP_CR_IPRST_Msk (0x1UL << CRYP_CR_IPRST_Pos) /*!< 0x80000000 */
#define CRYP_CR_IPRST CRYP_CR_IPRST_Msk /*!< CRYP peripheral software reset */
/****************** Bits definition for CRYP_SR register *********************/
#define CRYP_SR_IFEM_Pos (0U)
#define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
#define CRYP_SR_IFEM CRYP_SR_IFEM_Msk /*!< Input FIFO empty flag */
#define CRYP_SR_IFNF_Pos (1U)
#define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
#define CRYP_SR_IFNF CRYP_SR_IFNF_Msk /*!< Input FIFO not full flag */
#define CRYP_SR_OFNE_Pos (2U)
#define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
#define CRYP_SR_OFNE CRYP_SR_OFNE_Msk /*!< Output FIFO not empty flag */
#define CRYP_SR_OFFU_Pos (3U)
#define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
#define CRYP_SR_OFFU CRYP_SR_OFFU_Msk /*!< Output FIFO full flag */
#define CRYP_SR_BUSY_Pos (4U)
#define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
#define CRYP_SR_BUSY CRYP_SR_BUSY_Msk /*!< Busy bit */
#define CRYP_SR_KERF_Pos (6U)
#define CRYP_SR_KERF_Msk (0x1UL << CRYP_SR_KERF_Pos) /*!< 0x00000040 */
#define CRYP_SR_KERF CRYP_SR_KERF_Msk /*!< Key error flag */
#define CRYP_SR_KEYVALID_Pos (7U)
#define CRYP_SR_KEYVALID_Msk (0x1UL << CRYP_SR_KEYVALID_Pos) /*!< 0x00000080 */
#define CRYP_SR_KEYVALID CRYP_SR_KEYVALID_Msk /*!< Key valid flag */
/******************* Bit definition for CRYP_DIN register *******************/
#define CRYP_DIN_DATAIN_Pos (0U)
#define CRYP_DIN_DATAIN_Msk (0xFFFFFFFFUL << CRYP_DIN_DATAIN_Pos) /*!< 0xFFFFFFFF */
#define CRYP_DIN_DATAIN CRYP_DIN_DATAIN_Msk /*!< CRYP Data Input */
/******************* Bit definition for CRYP_DIN register *******************/
#define CRYP_DOUT_DATAOUT_Pos (0U)
#define CRYP_DOUT_DATAOUT_Msk (0xFFFFFFFFUL << CRYP_DOUT_DATAOUT_Pos) /*!< 0xFFFFFFFF */
#define CRYP_DOUT_DATAOUT CRYP_DOUT_DATAOUT_Msk /*!< CRYP Data Output */
/****************** Bits definition for CRYP_DMACR register ******************/
#define CRYP_DMACR_DIEN_Pos (0U)
#define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
#define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk /*!< DMA Input Enable */
#define CRYP_DMACR_DOEN_Pos (1U)
#define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
#define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk /*!< DMA Output Enable */
/***************** Bits definition for CRYP_IMSCR register ******************/
#define CRYP_IMSCR_INIM_Pos (0U)
#define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
#define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk /*!< Input FIFO service interrupt mask */
#define CRYP_IMSCR_OUTIM_Pos (1U)
#define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
#define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk /*!< Output FIFO service interrupt mask */
/****************** Bits definition for CRYP_RISR register *******************/
#define CRYP_RISR_INRIS_Pos (0U)
#define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */
#define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk /*!< Input FIFO service raw interrupt status */
#define CRYP_RISR_OUTRIS_Pos (1U)
#define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */
#define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk /*!< Output FIFO service raw interrupt mask */
/****************** Bits definition for CRYP_MISR register *******************/
#define CRYP_MISR_INMIS_Pos (0U)
#define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
#define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk /*!< Input FIFO service masked interrupt status */
#define CRYP_MISR_OUTMIS_Pos (1U)
#define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
#define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk /*!< Output FIFO service masked interrupt status */
/******************* Bit definition for CRYP_K0LR register ******************/
#define CRYP_K0LR_K_Pos (0U)
#define CRYP_K0LR_K_Msk (0xFFFFFFFFUL << CRYP_K0LR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_K0LR_K CRYP_K0LR_K_Msk /*!< AES key bit x (x= 224 to 255) */
/******************* Bit definition for CRYP_K0RR register ******************/
#define CRYP_K0RR_K_Pos (0U)
#define CRYP_K0RR_K_Msk (0xFFFFFFFFUL << CRYP_K0RR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_K0RR_K CRYP_K0RR_K_Msk /*!< AES key bit x (x= 192 to 223) */
/******************* Bit definition for CRYP_IV1LR register ******************/
#define CRYP_IV1LR_K_Pos (0U)
#define CRYP_IV1LR_K_Msk (0xFFFFFFFFUL << CRYP_IV1LR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_IV1LR_K CRYP_IV1LR_K_Msk /*!< AES key bit x (x= 160 to 291) */
/******************* Bit definition for CRYP_IV1RR register ******************/
#define CRYP_IV1RR_K_Pos (0U)
#define CRYP_IV1RR_K_Msk (0xFFFFFFFFUL << CRYP_IV1RR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_IV1RR_K CRYP_IV1RR_K_Msk /*!< AES key bit x (x= 128 to 159) */
/******************* Bit definition for CRYP_K2LR register ******************/
#define CRYP_K2LR_K_Pos (0U)
#define CRYP_K2LR_K_Msk (0xFFFFFFFFUL << CRYP_K2LR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_K2LR_K CRYP_K2LR_K_Msk /*!< AES key bit x (x= 96 to 127) */
/******************* Bit definition for CRYP_K2RR register ******************/
#define CRYP_K2RR_K_Pos (0U)
#define CRYP_K2RR_K_Msk (0xFFFFFFFFUL << CRYP_K2RR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_K2RR_K CRYP_K2RR_K_Msk /*!< AES key bit x (x= 64 to 95) */
/******************* Bit definition for CRYP_K3LR register ******************/
#define CRYP_K3LR_K_Pos (0U)
#define CRYP_K3LR_K_Msk (0xFFFFFFFFUL << CRYP_K3LR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_K3LR_K CRYP_K3LR_K_Msk /*!< AES key bit x (x= 32 to 63) */
/******************* Bit definition for CRYP_K3RR register ******************/
#define CRYP_K3RR_K_Pos (0U)
#define CRYP_K3RR_K_Msk (0xFFFFFFFFUL << CRYP_K3RR_K_Pos) /*!< 0xFFFFFFFF */
#define CRYP_K3RR_K CRYP_K3RR_K_Msk /*!< AES key bit x (x= 0 to 31) */
/******************* Bit definition for CRYP_IV0LR register ******************/
#define CRYP_IV0LR_IV_Pos (0U)
#define CRYP_IV0LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0LR_IV_Pos) /*!< 0xFFFFFFFF */
#define CRYP_IV0LR_IV CRYP_IV0LR_IV_Msk /*!< Initialization vector bit x (x= 0 to 31) */
/******************* Bit definition for CRYP_IV0RR register ******************/
#define CRYP_IV0RR_IV_Pos (0U)
#define CRYP_IV0RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV0RR_IV_Pos) /*!< 0xFFFFFFFF */
#define CRYP_IV0RR_IV CRYP_IV0RR_IV_Msk /*!< Initialization vector bit x (x= 32 to 63) */
/******************* Bit definition for CRYP_IV1LR register ******************/
#define CRYP_IV1LR_IV_Pos (0U)
#define CRYP_IV1LR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1LR_IV_Pos) /*!< 0xFFFFFFFF */
#define CRYP_IV1LR_IV CRYP_IV1LR_IV_Msk /*!< Initialization vector bit x (x= 64 to 95) */
/******************* Bit definition for CRYP_IV1RR register ******************/
#define CRYP_IV1RR_IV_Pos (0U)
#define CRYP_IV1RR_IV_Msk (0xFFFFFFFFUL << CRYP_IV1RR_IV_Pos) /*!< 0xFFFFFFFF */
#define CRYP_IV1RR_IV CRYP_IV1RR_IV_Msk /*!< Initialization vector bit x (x= 96 to 127) */
/******************* Bit definition for CRYP_CSGCMCCM0R register ******************/
#define CRYP_CSGCMCCM0R_CSGCMCCM0_Pos (0U)
#define CRYP_CSGCMCCM0R_CSGCMCCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM0R_CSGCMCCM0_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM0R_CSGCMCCM0 CRYP_CSGCMCCM0R_CSGCMCCM0_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCMCCM1R register ******************/
#define CRYP_CSGCMCCM1R_CSGCMCCM1_Pos (0U)
#define CRYP_CSGCMCCM1R_CSGCMCCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM1R_CSGCMCCM1_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM1R_CSGCMCCM1 CRYP_CSGCMCCM1R_CSGCMCCM1_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCMCCM2R register ******************/
#define CRYP_CSGCMCCM2R_CSGCMCCM2_Pos (0U)
#define CRYP_CSGCMCCM2R_CSGCMCCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM2R_CSGCMCCM2_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM2R_CSGCMCCM2 CRYP_CSGCMCCM2R_CSGCMCCM2_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCMCCM3R register ******************/
#define CRYP_CSGCMCCM3R_CSGCMCCM3_Pos (0U)
#define CRYP_CSGCMCCM3R_CSGCMCCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM3R_CSGCMCCM3_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM3R_CSGCMCCM3 CRYP_CSGCMCCM3R_CSGCMCCM3_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCMCCM4R register ******************/
#define CRYP_CSGCMCCM4R_CSGCMCCM4_Pos (0U)
#define CRYP_CSGCMCCM4R_CSGCMCCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM4R_CSGCMCCM4_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM4R_CSGCMCCM4 CRYP_CSGCMCCM4R_CSGCMCCM4_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCMCCM5R register ******************/
#define CRYP_CSGCMCCM5R_CSGCMCCM5_Pos (0U)
#define CRYP_CSGCMCCM5R_CSGCMCCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM5R_CSGCMCCM5_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM5R_CSGCMCCM5 CRYP_CSGCMCCM5R_CSGCMCCM5_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCMCCM6R register ******************/
#define CRYP_CSGCMCCM6R_CSGCMCCM6_Pos (0U)
#define CRYP_CSGCMCCM6R_CSGCMCCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM6R_CSGCMCCM6_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM6R_CSGCMCCM6 CRYP_CSGCMCCM6R_CSGCMCCM6_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCMCCM7R register ******************/
#define CRYP_CSGCMCCM7R_CSGCMCCM7_Pos (0U)
#define CRYP_CSGCMCCM7R_CSGCMCCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCMCCM7R_CSGCMCCM7_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCMCCM7R_CSGCMCCM7 CRYP_CSGCMCCM7R_CSGCMCCM7_Msk /*!< CRYP internal state registers for GCM, GMAC and CCM modes */
/******************* Bit definition for CRYP_CSGCM0R register ******************/
#define CRYP_CSGCM0R_CSGCM0_Pos (0U)
#define CRYP_CSGCM0R_CSGCM0_Msk (0xFFFFFFFFUL << CRYP_CSGCM0R_CSGCM0_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM0R_CSGCM0 CRYP_CSGCM0R_CSGCM0_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************* Bit definition for CRYP_CSGCM1R register ******************/
#define CRYP_CSGCM1R_CSGCM1_Pos (0U)
#define CRYP_CSGCM1R_CSGCM1_Msk (0xFFFFFFFFUL << CRYP_CSGCM1R_CSGCM1_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM1R_CSGCM1 CRYP_CSGCM1R_CSGCM1_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************* Bit definition for CRYP_CSGCM2R register ******************/
#define CRYP_CSGCM2R_CSGCM2_Pos (0U)
#define CRYP_CSGCM2R_CSGCM2_Msk (0xFFFFFFFFUL << CRYP_CSGCM2R_CSGCM2_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM2R_CSGCM2 CRYP_CSGCM2R_CSGCM2_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************* Bit definition for CRYP_CSGCM3R register ******************/
#define CRYP_CSGCM3R_CSGCM3_Pos (0U)
#define CRYP_CSGCM3R_CSGCM3_Msk (0xFFFFFFFFUL << CRYP_CSGCM3R_CSGCM3_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM3R_CSGCM3 CRYP_CSGCM3R_CSGCM3_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************* Bit definition for CRYP_CSGCM4R register ******************/
#define CRYP_CSGCM4R_CSGCM4_Pos (0U)
#define CRYP_CSGCM4R_CSGCM4_Msk (0xFFFFFFFFUL << CRYP_CSGCM4R_CSGCM4_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM4R_CSGCM4 CRYP_CSGCM4R_CSGCM4_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************* Bit definition for CRYP_CSGCM5R register ******************/
#define CRYP_CSGCM5R_CSGCM5_Pos (0U)
#define CRYP_CSGCM5R_CSGCM5_Msk (0xFFFFFFFFUL << CRYP_CSGCM5R_CSGCM5_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM5R_CSGCM5 CRYP_CSGCM5R_CSGCM5_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************* Bit definition for CRYP_CSGCM6R register ******************/
#define CRYP_CSGCM6R_CSGCM6_Pos (0U)
#define CRYP_CSGCM6R_CSGCM6_Msk (0xFFFFFFFFUL << CRYP_CSGCM6R_CSGCM6_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM6R_CSGCM6 CRYP_CSGCM6R_CSGCM6_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************* Bit definition for CRYP_CSGCM7R register ******************/
#define CRYP_CSGCM7R_CSGCM7_Pos (0U)
#define CRYP_CSGCM7R_CSGCM7_Msk (0xFFFFFFFFUL << CRYP_CSGCM7R_CSGCM7_Pos) /*!< 0xFFFFFFFF */
#define CRYP_CSGCM7R_CSGCM7 CRYP_CSGCM7R_CSGCM7_Msk /*!< CRYP internal state registers for GCM and GMAC modes */
/******************************************************************************/
/* */
/* (CSI) */
/* */
/******************************************************************************/
/******************** Bit definition for CSI_CR register ********************/
#define CSI_CR_CSIEN_Pos (0U)
#define CSI_CR_CSIEN_Msk (0x1UL << CSI_CR_CSIEN_Pos) /*!< 0x00000001 */
#define CSI_CR_CSIEN CSI_CR_CSIEN_Msk /*!< CSI-2 enable */
#define CSI_CR_VC0START_Pos (2U)
#define CSI_CR_VC0START_Msk (0x1UL << CSI_CR_VC0START_Pos) /*!< 0x00000004 */
#define CSI_CR_VC0START CSI_CR_VC0START_Msk /*!< Virtual channel 0 start */
#define CSI_CR_VC0STOP_Pos (3U)
#define CSI_CR_VC0STOP_Msk (0x1UL << CSI_CR_VC0STOP_Pos) /*!< 0x00000008 */
#define CSI_CR_VC0STOP CSI_CR_VC0STOP_Msk /*!< Virtual channel 0 stop */
#define CSI_CR_VC1START_Pos (6U)
#define CSI_CR_VC1START_Msk (0x1UL << CSI_CR_VC1START_Pos) /*!< 0x00000040 */
#define CSI_CR_VC1START CSI_CR_VC1START_Msk /*!< Virtual channel 1 start */
#define CSI_CR_VC1STOP_Pos (7U)
#define CSI_CR_VC1STOP_Msk (0x1UL << CSI_CR_VC1STOP_Pos) /*!< 0x00000080 */
#define CSI_CR_VC1STOP CSI_CR_VC1STOP_Msk /*!< Virtual channel 1 stop */
#define CSI_CR_VC2START_Pos (10U)
#define CSI_CR_VC2START_Msk (0x1UL << CSI_CR_VC2START_Pos) /*!< 0x00000400 */
#define CSI_CR_VC2START CSI_CR_VC2START_Msk /*!< Virtual channel 2 start */
#define CSI_CR_VC2STOP_Pos (11U)
#define CSI_CR_VC2STOP_Msk (0x1UL << CSI_CR_VC2STOP_Pos) /*!< 0x00000800 */
#define CSI_CR_VC2STOP CSI_CR_VC2STOP_Msk /*!< Virtual channel 2 stop */
#define CSI_CR_VC3START_Pos (14U)
#define CSI_CR_VC3START_Msk (0x1UL << CSI_CR_VC3START_Pos) /*!< 0x00004000 */
#define CSI_CR_VC3START CSI_CR_VC3START_Msk /*!< Virtual channel 3 start */
#define CSI_CR_VC3STOP_Pos (15U)
#define CSI_CR_VC3STOP_Msk (0x1UL << CSI_CR_VC3STOP_Pos) /*!< 0x00008000 */
#define CSI_CR_VC3STOP CSI_CR_VC3STOP_Msk /*!< Virtual channel 3 stop */
/******************* Bit definition for CSI_PCR register ********************/
#define CSI_PCR_PWRDOWN_Pos (0U)
#define CSI_PCR_PWRDOWN_Msk (0x1UL << CSI_PCR_PWRDOWN_Pos) /*!< 0x00000001 */
#define CSI_PCR_PWRDOWN CSI_PCR_PWRDOWN_Msk /*!< Virtual channel 3 start */
#define CSI_PCR_CLEN_Pos (1U)
#define CSI_PCR_CLEN_Msk (0x1UL << CSI_PCR_CLEN_Pos) /*!< 0x00000002 */
#define CSI_PCR_CLEN CSI_PCR_CLEN_Msk /*!< Clock lane enable */
#define CSI_PCR_DL0EN_Pos (2U)
#define CSI_PCR_DL0EN_Msk (0x1UL << CSI_PCR_DL0EN_Pos) /*!< 0x00000004 */
#define CSI_PCR_DL0EN CSI_PCR_DL0EN_Msk /*!< D-PHY_RX data lane 0 enable */
#define CSI_PCR_DL1EN_Pos (3U)
#define CSI_PCR_DL1EN_Msk (0x1UL << CSI_PCR_DL1EN_Pos) /*!< 0x00000008 */
#define CSI_PCR_DL1EN CSI_PCR_DL1EN_Msk /*!< D-PHY_RX data lane 1 enable */
/***************** Bit definition for CSI_VC0CFGR1 register *****************/
#define CSI_VC0CFGR1_ALLDT_Pos (0U)
#define CSI_VC0CFGR1_ALLDT_Msk (0x1UL << CSI_VC0CFGR1_ALLDT_Pos) /*!< 0x00000001 */
#define CSI_VC0CFGR1_ALLDT CSI_VC0CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */
#define CSI_VC0CFGR1_DT0EN_Pos (1U)
#define CSI_VC0CFGR1_DT0EN_Msk (0x1UL << CSI_VC0CFGR1_DT0EN_Pos) /*!< 0x00000002 */
#define CSI_VC0CFGR1_DT0EN CSI_VC0CFGR1_DT0EN_Msk /*!< Data type 0 enable */
#define CSI_VC0CFGR1_DT1EN_Pos (2U)
#define CSI_VC0CFGR1_DT1EN_Msk (0x1UL << CSI_VC0CFGR1_DT1EN_Pos) /*!< 0x00000004 */
#define CSI_VC0CFGR1_DT1EN CSI_VC0CFGR1_DT1EN_Msk /*!< Data type 1 enable */
#define CSI_VC0CFGR1_DT2EN_Pos (3U)
#define CSI_VC0CFGR1_DT2EN_Msk (0x1UL << CSI_VC0CFGR1_DT2EN_Pos) /*!< 0x00000008 */
#define CSI_VC0CFGR1_DT2EN CSI_VC0CFGR1_DT2EN_Msk /*!< Data type 2 enable */
#define CSI_VC0CFGR1_DT3EN_Pos (4U)
#define CSI_VC0CFGR1_DT3EN_Msk (0x1UL << CSI_VC0CFGR1_DT3EN_Pos) /*!< 0x00000010 */
#define CSI_VC0CFGR1_DT3EN CSI_VC0CFGR1_DT3EN_Msk /*!< Data type 3 enable */
#define CSI_VC0CFGR1_DT4EN_Pos (5U)
#define CSI_VC0CFGR1_DT4EN_Msk (0x1UL << CSI_VC0CFGR1_DT4EN_Pos) /*!< 0x00000020 */
#define CSI_VC0CFGR1_DT4EN CSI_VC0CFGR1_DT4EN_Msk /*!< Data type 4 enable */
#define CSI_VC0CFGR1_DT5EN_Pos (6U)
#define CSI_VC0CFGR1_DT5EN_Msk (0x1UL << CSI_VC0CFGR1_DT5EN_Pos) /*!< 0x00000040 */
#define CSI_VC0CFGR1_DT5EN CSI_VC0CFGR1_DT5EN_Msk /*!< Data type 5 enable */
#define CSI_VC0CFGR1_DT6EN_Pos (7U)
#define CSI_VC0CFGR1_DT6EN_Msk (0x1UL << CSI_VC0CFGR1_DT6EN_Pos) /*!< 0x00000080 */
#define CSI_VC0CFGR1_DT6EN CSI_VC0CFGR1_DT6EN_Msk /*!< Data type 6 enable */
#define CSI_VC0CFGR1_CDTFT_Pos (8U)
#define CSI_VC0CFGR1_CDTFT_Msk (0x1FUL << CSI_VC0CFGR1_CDTFT_Pos) /*!< 0x00001F00 */
#define CSI_VC0CFGR1_CDTFT CSI_VC0CFGR1_CDTFT_Msk /*!< Common format for all data types */
#define CSI_VC0CFGR1_DT0_Pos (16U)
#define CSI_VC0CFGR1_DT0_Msk (0x3FUL << CSI_VC0CFGR1_DT0_Pos) /*!< 0x003F0000 */
#define CSI_VC0CFGR1_DT0 CSI_VC0CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */
#define CSI_VC0CFGR1_DT0FT_Pos (24U)
#define CSI_VC0CFGR1_DT0FT_Msk (0x1FUL << CSI_VC0CFGR1_DT0FT_Pos) /*!< 0x1F000000 */
#define CSI_VC0CFGR1_DT0FT CSI_VC0CFGR1_DT0FT_Msk /*!< Data type 0 format */
/***************** Bit definition for CSI_VC0CFGR2 register *****************/
#define CSI_VC0CFGR2_DT1_Pos (0U)
#define CSI_VC0CFGR2_DT1_Msk (0x3FUL << CSI_VC0CFGR2_DT1_Pos) /*!< 0x0000003F */
#define CSI_VC0CFGR2_DT1 CSI_VC0CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */
#define CSI_VC0CFGR2_DT1FT_Pos (8U)
#define CSI_VC0CFGR2_DT1FT_Msk (0x1FUL << CSI_VC0CFGR2_DT1FT_Pos) /*!< 0x00001F00 */
#define CSI_VC0CFGR2_DT1FT CSI_VC0CFGR2_DT1FT_Msk /*!< Data type 1 format */
#define CSI_VC0CFGR2_DT2_Pos (16U)
#define CSI_VC0CFGR2_DT2_Msk (0x3FUL << CSI_VC0CFGR2_DT2_Pos) /*!< 0x003F0000 */
#define CSI_VC0CFGR2_DT2 CSI_VC0CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */
#define CSI_VC0CFGR2_DT2FT_Pos (24U)
#define CSI_VC0CFGR2_DT2FT_Msk (0x1FUL << CSI_VC0CFGR2_DT2FT_Pos) /*!< 0x1F000000 */
#define CSI_VC0CFGR2_DT2FT CSI_VC0CFGR2_DT2FT_Msk /*!< Data type 2 format */
/***************** Bit definition for CSI_VC0CFGR3 register *****************/
#define CSI_VC0CFGR3_DT3_Pos (0U)
#define CSI_VC0CFGR3_DT3_Msk (0x3FUL << CSI_VC0CFGR3_DT3_Pos) /*!< 0x0000003F */
#define CSI_VC0CFGR3_DT3 CSI_VC0CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */
#define CSI_VC0CFGR3_DT3FT_Pos (8U)
#define CSI_VC0CFGR3_DT3FT_Msk (0x1FUL << CSI_VC0CFGR3_DT3FT_Pos) /*!< 0x00001F00 */
#define CSI_VC0CFGR3_DT3FT CSI_VC0CFGR3_DT3FT_Msk /*!< Data type 3 format */
#define CSI_VC0CFGR3_DT4_Pos (16U)
#define CSI_VC0CFGR3_DT4_Msk (0x3FUL << CSI_VC0CFGR3_DT4_Pos) /*!< 0x003F0000 */
#define CSI_VC0CFGR3_DT4 CSI_VC0CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */
#define CSI_VC0CFGR3_DT4FT_Pos (24U)
#define CSI_VC0CFGR3_DT4FT_Msk (0x1FUL << CSI_VC0CFGR3_DT4FT_Pos) /*!< 0x1F000000 */
#define CSI_VC0CFGR3_DT4FT CSI_VC0CFGR3_DT4FT_Msk /*!< Data type 4 format */
/***************** Bit definition for CSI_VC0CFGR4 register *****************/
#define CSI_VC0CFGR4_DT5_Pos (0U)
#define CSI_VC0CFGR4_DT5_Msk (0x3FUL << CSI_VC0CFGR4_DT5_Pos) /*!< 0x0000003F */
#define CSI_VC0CFGR4_DT5 CSI_VC0CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */
#define CSI_VC0CFGR4_DT5FT_Pos (8U)
#define CSI_VC0CFGR4_DT5FT_Msk (0x1FUL << CSI_VC0CFGR4_DT5FT_Pos) /*!< 0x00001F00 */
#define CSI_VC0CFGR4_DT5FT CSI_VC0CFGR4_DT5FT_Msk /*!< Data type 5 format */
#define CSI_VC0CFGR4_DT6_Pos (16U)
#define CSI_VC0CFGR4_DT6_Msk (0x3FUL << CSI_VC0CFGR4_DT6_Pos) /*!< 0x003F0000 */
#define CSI_VC0CFGR4_DT6 CSI_VC0CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */
#define CSI_VC0CFGR4_DT6FT_Pos (24U)
#define CSI_VC0CFGR4_DT6FT_Msk (0x1FUL << CSI_VC0CFGR4_DT6FT_Pos) /*!< 0x1F000000 */
#define CSI_VC0CFGR4_DT6FT CSI_VC0CFGR4_DT6FT_Msk /*!< Data type 6 format */
/***************** Bit definition for CSI_VC1CFGR1 register *****************/
#define CSI_VC1CFGR1_ALLDT_Pos (0U)
#define CSI_VC1CFGR1_ALLDT_Msk (0x1UL << CSI_VC1CFGR1_ALLDT_Pos) /*!< 0x00000001 */
#define CSI_VC1CFGR1_ALLDT CSI_VC1CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */
#define CSI_VC1CFGR1_DT0EN_Pos (1U)
#define CSI_VC1CFGR1_DT0EN_Msk (0x1UL << CSI_VC1CFGR1_DT0EN_Pos) /*!< 0x00000002 */
#define CSI_VC1CFGR1_DT0EN CSI_VC1CFGR1_DT0EN_Msk /*!< Data type 0 enable */
#define CSI_VC1CFGR1_DT1EN_Pos (2U)
#define CSI_VC1CFGR1_DT1EN_Msk (0x1UL << CSI_VC1CFGR1_DT1EN_Pos) /*!< 0x00000004 */
#define CSI_VC1CFGR1_DT1EN CSI_VC1CFGR1_DT1EN_Msk /*!< Data type 1 enable */
#define CSI_VC1CFGR1_DT2EN_Pos (3U)
#define CSI_VC1CFGR1_DT2EN_Msk (0x1UL << CSI_VC1CFGR1_DT2EN_Pos) /*!< 0x00000008 */
#define CSI_VC1CFGR1_DT2EN CSI_VC1CFGR1_DT2EN_Msk /*!< Data type 2 enable */
#define CSI_VC1CFGR1_DT3EN_Pos (4U)
#define CSI_VC1CFGR1_DT3EN_Msk (0x1UL << CSI_VC1CFGR1_DT3EN_Pos) /*!< 0x00000010 */
#define CSI_VC1CFGR1_DT3EN CSI_VC1CFGR1_DT3EN_Msk /*!< Data type 3 enable */
#define CSI_VC1CFGR1_DT4EN_Pos (5U)
#define CSI_VC1CFGR1_DT4EN_Msk (0x1UL << CSI_VC1CFGR1_DT4EN_Pos) /*!< 0x00000020 */
#define CSI_VC1CFGR1_DT4EN CSI_VC1CFGR1_DT4EN_Msk /*!< Data type 4 enable */
#define CSI_VC1CFGR1_DT5EN_Pos (6U)
#define CSI_VC1CFGR1_DT5EN_Msk (0x1UL << CSI_VC1CFGR1_DT5EN_Pos) /*!< 0x00000040 */
#define CSI_VC1CFGR1_DT5EN CSI_VC1CFGR1_DT5EN_Msk /*!< Data type 5 enable */
#define CSI_VC1CFGR1_DT6EN_Pos (7U)
#define CSI_VC1CFGR1_DT6EN_Msk (0x1UL << CSI_VC1CFGR1_DT6EN_Pos) /*!< 0x00000080 */
#define CSI_VC1CFGR1_DT6EN CSI_VC1CFGR1_DT6EN_Msk /*!< Data type 6 enable */
#define CSI_VC1CFGR1_CDTFT_Pos (8U)
#define CSI_VC1CFGR1_CDTFT_Msk (0x1FUL << CSI_VC1CFGR1_CDTFT_Pos) /*!< 0x00001F00 */
#define CSI_VC1CFGR1_CDTFT CSI_VC1CFGR1_CDTFT_Msk /*!< Common format for all data types */
#define CSI_VC1CFGR1_DT0_Pos (16U)
#define CSI_VC1CFGR1_DT0_Msk (0x3FUL << CSI_VC1CFGR1_DT0_Pos) /*!< 0x003F0000 */
#define CSI_VC1CFGR1_DT0 CSI_VC1CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */
#define CSI_VC1CFGR1_DT0FT_Pos (24U)
#define CSI_VC1CFGR1_DT0FT_Msk (0x1FUL << CSI_VC1CFGR1_DT0FT_Pos) /*!< 0x1F000000 */
#define CSI_VC1CFGR1_DT0FT CSI_VC1CFGR1_DT0FT_Msk /*!< Data type 0 format */
/***************** Bit definition for CSI_VC1CFGR2 register *****************/
#define CSI_VC1CFGR2_DT1_Pos (0U)
#define CSI_VC1CFGR2_DT1_Msk (0x3FUL << CSI_VC1CFGR2_DT1_Pos) /*!< 0x0000003F */
#define CSI_VC1CFGR2_DT1 CSI_VC1CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */
#define CSI_VC1CFGR2_DT1FT_Pos (8U)
#define CSI_VC1CFGR2_DT1FT_Msk (0x1FUL << CSI_VC1CFGR2_DT1FT_Pos) /*!< 0x00001F00 */
#define CSI_VC1CFGR2_DT1FT CSI_VC1CFGR2_DT1FT_Msk /*!< Data type 1 format */
#define CSI_VC1CFGR2_DT2_Pos (16U)
#define CSI_VC1CFGR2_DT2_Msk (0x3FUL << CSI_VC1CFGR2_DT2_Pos) /*!< 0x003F0000 */
#define CSI_VC1CFGR2_DT2 CSI_VC1CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */
#define CSI_VC1CFGR2_DT2FT_Pos (24U)
#define CSI_VC1CFGR2_DT2FT_Msk (0x1FUL << CSI_VC1CFGR2_DT2FT_Pos) /*!< 0x1F000000 */
#define CSI_VC1CFGR2_DT2FT CSI_VC1CFGR2_DT2FT_Msk /*!< Data type 2 format */
/***************** Bit definition for CSI_VC1CFGR3 register *****************/
#define CSI_VC1CFGR3_DT3_Pos (0U)
#define CSI_VC1CFGR3_DT3_Msk (0x3FUL << CSI_VC1CFGR3_DT3_Pos) /*!< 0x0000003F */
#define CSI_VC1CFGR3_DT3 CSI_VC1CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */
#define CSI_VC1CFGR3_DT3FT_Pos (8U)
#define CSI_VC1CFGR3_DT3FT_Msk (0x1FUL << CSI_VC1CFGR3_DT3FT_Pos) /*!< 0x00001F00 */
#define CSI_VC1CFGR3_DT3FT CSI_VC1CFGR3_DT3FT_Msk /*!< Data type 3 format */
#define CSI_VC1CFGR3_DT4_Pos (16U)
#define CSI_VC1CFGR3_DT4_Msk (0x3FUL << CSI_VC1CFGR3_DT4_Pos) /*!< 0x003F0000 */
#define CSI_VC1CFGR3_DT4 CSI_VC1CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */
#define CSI_VC1CFGR3_DT4FT_Pos (24U)
#define CSI_VC1CFGR3_DT4FT_Msk (0x1FUL << CSI_VC1CFGR3_DT4FT_Pos) /*!< 0x1F000000 */
#define CSI_VC1CFGR3_DT4FT CSI_VC1CFGR3_DT4FT_Msk /*!< Data type 4 format */
/***************** Bit definition for CSI_VC1CFGR4 register *****************/
#define CSI_VC1CFGR4_DT5_Pos (0U)
#define CSI_VC1CFGR4_DT5_Msk (0x3FUL << CSI_VC1CFGR4_DT5_Pos) /*!< 0x0000003F */
#define CSI_VC1CFGR4_DT5 CSI_VC1CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */
#define CSI_VC1CFGR4_DT5FT_Pos (8U)
#define CSI_VC1CFGR4_DT5FT_Msk (0x1FUL << CSI_VC1CFGR4_DT5FT_Pos) /*!< 0x00001F00 */
#define CSI_VC1CFGR4_DT5FT CSI_VC1CFGR4_DT5FT_Msk /*!< Data type 5 format */
#define CSI_VC1CFGR4_DT6_Pos (16U)
#define CSI_VC1CFGR4_DT6_Msk (0x3FUL << CSI_VC1CFGR4_DT6_Pos) /*!< 0x003F0000 */
#define CSI_VC1CFGR4_DT6 CSI_VC1CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */
#define CSI_VC1CFGR4_DT6FT_Pos (24U)
#define CSI_VC1CFGR4_DT6FT_Msk (0x1FUL << CSI_VC1CFGR4_DT6FT_Pos) /*!< 0x1F000000 */
#define CSI_VC1CFGR4_DT6FT CSI_VC1CFGR4_DT6FT_Msk /*!< Data type 6 format */
/***************** Bit definition for CSI_VC2CFGR1 register *****************/
#define CSI_VC2CFGR1_ALLDT_Pos (0U)
#define CSI_VC2CFGR1_ALLDT_Msk (0x1UL << CSI_VC2CFGR1_ALLDT_Pos) /*!< 0x00000001 */
#define CSI_VC2CFGR1_ALLDT CSI_VC2CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */
#define CSI_VC2CFGR1_DT0EN_Pos (1U)
#define CSI_VC2CFGR1_DT0EN_Msk (0x1UL << CSI_VC2CFGR1_DT0EN_Pos) /*!< 0x00000002 */
#define CSI_VC2CFGR1_DT0EN CSI_VC2CFGR1_DT0EN_Msk /*!< Data type 0 enable */
#define CSI_VC2CFGR1_DT1EN_Pos (2U)
#define CSI_VC2CFGR1_DT1EN_Msk (0x1UL << CSI_VC2CFGR1_DT1EN_Pos) /*!< 0x00000004 */
#define CSI_VC2CFGR1_DT1EN CSI_VC2CFGR1_DT1EN_Msk /*!< Data type 1 enable */
#define CSI_VC2CFGR1_DT2EN_Pos (3U)
#define CSI_VC2CFGR1_DT2EN_Msk (0x1UL << CSI_VC2CFGR1_DT2EN_Pos) /*!< 0x00000008 */
#define CSI_VC2CFGR1_DT2EN CSI_VC2CFGR1_DT2EN_Msk /*!< Data type 2 enable */
#define CSI_VC2CFGR1_DT3EN_Pos (4U)
#define CSI_VC2CFGR1_DT3EN_Msk (0x1UL << CSI_VC2CFGR1_DT3EN_Pos) /*!< 0x00000010 */
#define CSI_VC2CFGR1_DT3EN CSI_VC2CFGR1_DT3EN_Msk /*!< Data type 3 enable */
#define CSI_VC2CFGR1_DT4EN_Pos (5U)
#define CSI_VC2CFGR1_DT4EN_Msk (0x1UL << CSI_VC2CFGR1_DT4EN_Pos) /*!< 0x00000020 */
#define CSI_VC2CFGR1_DT4EN CSI_VC2CFGR1_DT4EN_Msk /*!< Data type 4 enable */
#define CSI_VC2CFGR1_DT5EN_Pos (6U)
#define CSI_VC2CFGR1_DT5EN_Msk (0x1UL << CSI_VC2CFGR1_DT5EN_Pos) /*!< 0x00000040 */
#define CSI_VC2CFGR1_DT5EN CSI_VC2CFGR1_DT5EN_Msk /*!< Data type 5 enable */
#define CSI_VC2CFGR1_DT6EN_Pos (7U)
#define CSI_VC2CFGR1_DT6EN_Msk (0x1UL << CSI_VC2CFGR1_DT6EN_Pos) /*!< 0x00000080 */
#define CSI_VC2CFGR1_DT6EN CSI_VC2CFGR1_DT6EN_Msk /*!< Data type 6 enable */
#define CSI_VC2CFGR1_CDTFT_Pos (8U)
#define CSI_VC2CFGR1_CDTFT_Msk (0x1FUL << CSI_VC2CFGR1_CDTFT_Pos) /*!< 0x00001F00 */
#define CSI_VC2CFGR1_CDTFT CSI_VC2CFGR1_CDTFT_Msk /*!< Common format for all data types */
#define CSI_VC2CFGR1_DT0_Pos (16U)
#define CSI_VC2CFGR1_DT0_Msk (0x3FUL << CSI_VC2CFGR1_DT0_Pos) /*!< 0x003F0000 */
#define CSI_VC2CFGR1_DT0 CSI_VC2CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */
#define CSI_VC2CFGR1_DT0FT_Pos (24U)
#define CSI_VC2CFGR1_DT0FT_Msk (0x1FUL << CSI_VC2CFGR1_DT0FT_Pos) /*!< 0x1F000000 */
#define CSI_VC2CFGR1_DT0FT CSI_VC2CFGR1_DT0FT_Msk /*!< Data type 0 format */
/***************** Bit definition for CSI_VC2CFGR2 register *****************/
#define CSI_VC2CFGR2_DT1_Pos (0U)
#define CSI_VC2CFGR2_DT1_Msk (0x3FUL << CSI_VC2CFGR2_DT1_Pos) /*!< 0x0000003F */
#define CSI_VC2CFGR2_DT1 CSI_VC2CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */
#define CSI_VC2CFGR2_DT1FT_Pos (8U)
#define CSI_VC2CFGR2_DT1FT_Msk (0x1FUL << CSI_VC2CFGR2_DT1FT_Pos) /*!< 0x00001F00 */
#define CSI_VC2CFGR2_DT1FT CSI_VC2CFGR2_DT1FT_Msk /*!< Data type 1 format */
#define CSI_VC2CFGR2_DT2_Pos (16U)
#define CSI_VC2CFGR2_DT2_Msk (0x3FUL << CSI_VC2CFGR2_DT2_Pos) /*!< 0x003F0000 */
#define CSI_VC2CFGR2_DT2 CSI_VC2CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */
#define CSI_VC2CFGR2_DT2FT_Pos (24U)
#define CSI_VC2CFGR2_DT2FT_Msk (0x1FUL << CSI_VC2CFGR2_DT2FT_Pos) /*!< 0x1F000000 */
#define CSI_VC2CFGR2_DT2FT CSI_VC2CFGR2_DT2FT_Msk /*!< Data type 2 format */
/***************** Bit definition for CSI_VC2CFGR3 register *****************/
#define CSI_VC2CFGR3_DT3_Pos (0U)
#define CSI_VC2CFGR3_DT3_Msk (0x3FUL << CSI_VC2CFGR3_DT3_Pos) /*!< 0x0000003F */
#define CSI_VC2CFGR3_DT3 CSI_VC2CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */
#define CSI_VC2CFGR3_DT3FT_Pos (8U)
#define CSI_VC2CFGR3_DT3FT_Msk (0x1FUL << CSI_VC2CFGR3_DT3FT_Pos) /*!< 0x00001F00 */
#define CSI_VC2CFGR3_DT3FT CSI_VC2CFGR3_DT3FT_Msk /*!< Data type 3 format */
#define CSI_VC2CFGR3_DT4_Pos (16U)
#define CSI_VC2CFGR3_DT4_Msk (0x3FUL << CSI_VC2CFGR3_DT4_Pos) /*!< 0x003F0000 */
#define CSI_VC2CFGR3_DT4 CSI_VC2CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */
#define CSI_VC2CFGR3_DT4FT_Pos (24U)
#define CSI_VC2CFGR3_DT4FT_Msk (0x1FUL << CSI_VC2CFGR3_DT4FT_Pos) /*!< 0x1F000000 */
#define CSI_VC2CFGR3_DT4FT CSI_VC2CFGR3_DT4FT_Msk /*!< Data type 4 format */
/***************** Bit definition for CSI_VC2CFGR4 register *****************/
#define CSI_VC2CFGR4_DT5_Pos (0U)
#define CSI_VC2CFGR4_DT5_Msk (0x3FUL << CSI_VC2CFGR4_DT5_Pos) /*!< 0x0000003F */
#define CSI_VC2CFGR4_DT5 CSI_VC2CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */
#define CSI_VC2CFGR4_DT5FT_Pos (8U)
#define CSI_VC2CFGR4_DT5FT_Msk (0x1FUL << CSI_VC2CFGR4_DT5FT_Pos) /*!< 0x00001F00 */
#define CSI_VC2CFGR4_DT5FT CSI_VC2CFGR4_DT5FT_Msk /*!< Data type 5 format */
#define CSI_VC2CFGR4_DT6_Pos (16U)
#define CSI_VC2CFGR4_DT6_Msk (0x3FUL << CSI_VC2CFGR4_DT6_Pos) /*!< 0x003F0000 */
#define CSI_VC2CFGR4_DT6 CSI_VC2CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */
#define CSI_VC2CFGR4_DT6FT_Pos (24U)
#define CSI_VC2CFGR4_DT6FT_Msk (0x1FUL << CSI_VC2CFGR4_DT6FT_Pos) /*!< 0x1F000000 */
#define CSI_VC2CFGR4_DT6FT CSI_VC2CFGR4_DT6FT_Msk /*!< Data type 6 format */
/***************** Bit definition for CSI_VC3CFGR1 register *****************/
#define CSI_VC3CFGR1_ALLDT_Pos (0U)
#define CSI_VC3CFGR1_ALLDT_Msk (0x1UL << CSI_VC3CFGR1_ALLDT_Pos) /*!< 0x00000001 */
#define CSI_VC3CFGR1_ALLDT CSI_VC3CFGR1_ALLDT_Msk /*!< All data types enable for the virtual channel x */
#define CSI_VC3CFGR1_DT0EN_Pos (1U)
#define CSI_VC3CFGR1_DT0EN_Msk (0x1UL << CSI_VC3CFGR1_DT0EN_Pos) /*!< 0x00000002 */
#define CSI_VC3CFGR1_DT0EN CSI_VC3CFGR1_DT0EN_Msk /*!< Data type 0 enable */
#define CSI_VC3CFGR1_DT1EN_Pos (2U)
#define CSI_VC3CFGR1_DT1EN_Msk (0x1UL << CSI_VC3CFGR1_DT1EN_Pos) /*!< 0x00000004 */
#define CSI_VC3CFGR1_DT1EN CSI_VC3CFGR1_DT1EN_Msk /*!< Data type 1 enable */
#define CSI_VC3CFGR1_DT2EN_Pos (3U)
#define CSI_VC3CFGR1_DT2EN_Msk (0x1UL << CSI_VC3CFGR1_DT2EN_Pos) /*!< 0x00000008 */
#define CSI_VC3CFGR1_DT2EN CSI_VC3CFGR1_DT2EN_Msk /*!< Data type 2 enable */
#define CSI_VC3CFGR1_DT3EN_Pos (4U)
#define CSI_VC3CFGR1_DT3EN_Msk (0x1UL << CSI_VC3CFGR1_DT3EN_Pos) /*!< 0x00000010 */
#define CSI_VC3CFGR1_DT3EN CSI_VC3CFGR1_DT3EN_Msk /*!< Data type 3 enable */
#define CSI_VC3CFGR1_DT4EN_Pos (5U)
#define CSI_VC3CFGR1_DT4EN_Msk (0x1UL << CSI_VC3CFGR1_DT4EN_Pos) /*!< 0x00000020 */
#define CSI_VC3CFGR1_DT4EN CSI_VC3CFGR1_DT4EN_Msk /*!< Data type 4 enable */
#define CSI_VC3CFGR1_DT5EN_Pos (6U)
#define CSI_VC3CFGR1_DT5EN_Msk (0x1UL << CSI_VC3CFGR1_DT5EN_Pos) /*!< 0x00000040 */
#define CSI_VC3CFGR1_DT5EN CSI_VC3CFGR1_DT5EN_Msk /*!< Data type 5 enable */
#define CSI_VC3CFGR1_DT6EN_Pos (7U)
#define CSI_VC3CFGR1_DT6EN_Msk (0x1UL << CSI_VC3CFGR1_DT6EN_Pos) /*!< 0x00000080 */
#define CSI_VC3CFGR1_DT6EN CSI_VC3CFGR1_DT6EN_Msk /*!< Data type 6 enable */
#define CSI_VC3CFGR1_CDTFT_Pos (8U)
#define CSI_VC3CFGR1_CDTFT_Msk (0x1FUL << CSI_VC3CFGR1_CDTFT_Pos) /*!< 0x00001F00 */
#define CSI_VC3CFGR1_CDTFT CSI_VC3CFGR1_CDTFT_Msk /*!< Common format for all data types */
#define CSI_VC3CFGR1_DT0_Pos (16U)
#define CSI_VC3CFGR1_DT0_Msk (0x3FUL << CSI_VC3CFGR1_DT0_Pos) /*!< 0x003F0000 */
#define CSI_VC3CFGR1_DT0 CSI_VC3CFGR1_DT0_Msk /*!< Data type 0 class selection for virtual channel x */
#define CSI_VC3CFGR1_DT0FT_Pos (24U)
#define CSI_VC3CFGR1_DT0FT_Msk (0x1FUL << CSI_VC3CFGR1_DT0FT_Pos) /*!< 0x1F000000 */
#define CSI_VC3CFGR1_DT0FT CSI_VC3CFGR1_DT0FT_Msk /*!< Data type 0 format */
/***************** Bit definition for CSI_VC3CFGR2 register *****************/
#define CSI_VC3CFGR2_DT1_Pos (0U)
#define CSI_VC3CFGR2_DT1_Msk (0x3FUL << CSI_VC3CFGR2_DT1_Pos) /*!< 0x0000003F */
#define CSI_VC3CFGR2_DT1 CSI_VC3CFGR2_DT1_Msk /*!< Data type 1 class selection for virtual channel x */
#define CSI_VC3CFGR2_DT1FT_Pos (8U)
#define CSI_VC3CFGR2_DT1FT_Msk (0x1FUL << CSI_VC3CFGR2_DT1FT_Pos) /*!< 0x00001F00 */
#define CSI_VC3CFGR2_DT1FT CSI_VC3CFGR2_DT1FT_Msk /*!< Data type 1 format */
#define CSI_VC3CFGR2_DT2_Pos (16U)
#define CSI_VC3CFGR2_DT2_Msk (0x3FUL << CSI_VC3CFGR2_DT2_Pos) /*!< 0x003F0000 */
#define CSI_VC3CFGR2_DT2 CSI_VC3CFGR2_DT2_Msk /*!< Data type 2 class selection for virtual channel x */
#define CSI_VC3CFGR2_DT2FT_Pos (24U)
#define CSI_VC3CFGR2_DT2FT_Msk (0x1FUL << CSI_VC3CFGR2_DT2FT_Pos) /*!< 0x1F000000 */
#define CSI_VC3CFGR2_DT2FT CSI_VC3CFGR2_DT2FT_Msk /*!< Data type 2 format */
/***************** Bit definition for CSI_VC3CFGR3 register *****************/
#define CSI_VC3CFGR3_DT3_Pos (0U)
#define CSI_VC3CFGR3_DT3_Msk (0x3FUL << CSI_VC3CFGR3_DT3_Pos) /*!< 0x0000003F */
#define CSI_VC3CFGR3_DT3 CSI_VC3CFGR3_DT3_Msk /*!< Data type 3 class selection for virtual channel x */
#define CSI_VC3CFGR3_DT3FT_Pos (8U)
#define CSI_VC3CFGR3_DT3FT_Msk (0x1FUL << CSI_VC3CFGR3_DT3FT_Pos) /*!< 0x00001F00 */
#define CSI_VC3CFGR3_DT3FT CSI_VC3CFGR3_DT3FT_Msk /*!< Data type 3 format */
#define CSI_VC3CFGR3_DT4_Pos (16U)
#define CSI_VC3CFGR3_DT4_Msk (0x3FUL << CSI_VC3CFGR3_DT4_Pos) /*!< 0x003F0000 */
#define CSI_VC3CFGR3_DT4 CSI_VC3CFGR3_DT4_Msk /*!< Data type 4 class selection for virtual channel x */
#define CSI_VC3CFGR3_DT4FT_Pos (24U)
#define CSI_VC3CFGR3_DT4FT_Msk (0x1FUL << CSI_VC3CFGR3_DT4FT_Pos) /*!< 0x1F000000 */
#define CSI_VC3CFGR3_DT4FT CSI_VC3CFGR3_DT4FT_Msk /*!< Data type 4 format */
/***************** Bit definition for CSI_VC3CFGR4 register *****************/
#define CSI_VC3CFGR4_DT5_Pos (0U)
#define CSI_VC3CFGR4_DT5_Msk (0x3FUL << CSI_VC3CFGR4_DT5_Pos) /*!< 0x0000003F */
#define CSI_VC3CFGR4_DT5 CSI_VC3CFGR4_DT5_Msk /*!< Data type 5 class selection for virtual channel x */
#define CSI_VC3CFGR4_DT5FT_Pos (8U)
#define CSI_VC3CFGR4_DT5FT_Msk (0x1FUL << CSI_VC3CFGR4_DT5FT_Pos) /*!< 0x00001F00 */
#define CSI_VC3CFGR4_DT5FT CSI_VC3CFGR4_DT5FT_Msk /*!< Data type 5 format */
#define CSI_VC3CFGR4_DT6_Pos (16U)
#define CSI_VC3CFGR4_DT6_Msk (0x3FUL << CSI_VC3CFGR4_DT6_Pos) /*!< 0x003F0000 */
#define CSI_VC3CFGR4_DT6 CSI_VC3CFGR4_DT6_Msk /*!< Data type 6 class selection for virtual channel x */
#define CSI_VC3CFGR4_DT6FT_Pos (24U)
#define CSI_VC3CFGR4_DT6FT_Msk (0x1FUL << CSI_VC3CFGR4_DT6FT_Pos) /*!< 0x1F000000 */
#define CSI_VC3CFGR4_DT6FT CSI_VC3CFGR4_DT6FT_Msk /*!< Data type 6 format */
/***************** Bit definition for CSI_LB0CFGR register ******************/
#define CSI_LB0CFGR_BYTECNT_Pos (0U)
#define CSI_LB0CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB0CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */
#define CSI_LB0CFGR_BYTECNT CSI_LB0CFGR_BYTECNT_Msk /*!< Byte counter */
#define CSI_LB0CFGR_LINECNT_Pos (16U)
#define CSI_LB0CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB0CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */
#define CSI_LB0CFGR_LINECNT CSI_LB0CFGR_LINECNT_Msk /*!< Line counter */
/***************** Bit definition for CSI_LB1CFGR register ******************/
#define CSI_LB1CFGR_BYTECNT_Pos (0U)
#define CSI_LB1CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB1CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */
#define CSI_LB1CFGR_BYTECNT CSI_LB1CFGR_BYTECNT_Msk /*!< Byte counter */
#define CSI_LB1CFGR_LINECNT_Pos (16U)
#define CSI_LB1CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB1CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */
#define CSI_LB1CFGR_LINECNT CSI_LB1CFGR_LINECNT_Msk /*!< Line counter */
/***************** Bit definition for CSI_LB2CFGR register ******************/
#define CSI_LB2CFGR_BYTECNT_Pos (0U)
#define CSI_LB2CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB2CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */
#define CSI_LB2CFGR_BYTECNT CSI_LB2CFGR_BYTECNT_Msk /*!< Byte counter */
#define CSI_LB2CFGR_LINECNT_Pos (16U)
#define CSI_LB2CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB2CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */
#define CSI_LB2CFGR_LINECNT CSI_LB2CFGR_LINECNT_Msk /*!< Line counter */
/***************** Bit definition for CSI_LB3CFGR register ******************/
#define CSI_LB3CFGR_BYTECNT_Pos (0U)
#define CSI_LB3CFGR_BYTECNT_Msk (0xFFFFUL << CSI_LB3CFGR_BYTECNT_Pos) /*!< 0x0000FFFF */
#define CSI_LB3CFGR_BYTECNT CSI_LB3CFGR_BYTECNT_Msk /*!< Byte counter */
#define CSI_LB3CFGR_LINECNT_Pos (16U)
#define CSI_LB3CFGR_LINECNT_Msk (0xFFFFUL << CSI_LB3CFGR_LINECNT_Pos) /*!< 0xFFFF0000 */
#define CSI_LB3CFGR_LINECNT CSI_LB3CFGR_LINECNT_Msk /*!< Line counter */
/***************** Bit definition for CSI_TIM0CFGR register *****************/
#define CSI_TIM0CFGR_COUNT_Pos (0U)
#define CSI_TIM0CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM0CFGR_COUNT_Pos) /*!< 0x01FFFFFF */
#define CSI_TIM0CFGR_COUNT CSI_TIM0CFGR_COUNT_Msk /*!< Clock cycle counter */
/***************** Bit definition for CSI_TIM1CFGR register *****************/
#define CSI_TIM1CFGR_COUNT_Pos (0U)
#define CSI_TIM1CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM1CFGR_COUNT_Pos) /*!< 0x01FFFFFF */
#define CSI_TIM1CFGR_COUNT CSI_TIM1CFGR_COUNT_Msk /*!< Clock cycle counter */
/***************** Bit definition for CSI_TIM2CFGR register *****************/
#define CSI_TIM2CFGR_COUNT_Pos (0U)
#define CSI_TIM2CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM2CFGR_COUNT_Pos) /*!< 0x01FFFFFF */
#define CSI_TIM2CFGR_COUNT CSI_TIM2CFGR_COUNT_Msk /*!< Clock cycle counter */
/***************** Bit definition for CSI_TIM3CFGR register *****************/
#define CSI_TIM3CFGR_COUNT_Pos (0U)
#define CSI_TIM3CFGR_COUNT_Msk (0x1FFFFFFUL << CSI_TIM3CFGR_COUNT_Pos) /*!< 0x01FFFFFF */
#define CSI_TIM3CFGR_COUNT CSI_TIM3CFGR_COUNT_Msk /*!< Clock cycle counter */
/****************** Bit definition for CSI_LMCFGR register ******************/
#define CSI_LMCFGR_LANENB_Pos (8U)
#define CSI_LMCFGR_LANENB_Msk (0x7UL << CSI_LMCFGR_LANENB_Pos) /*!< 0x00000700 */
#define CSI_LMCFGR_LANENB CSI_LMCFGR_LANENB_Msk /*!< Number of lanes */
#define CSI_LMCFGR_DL0MAP_Pos (16U)
#define CSI_LMCFGR_DL0MAP_Msk (0x7UL << CSI_LMCFGR_DL0MAP_Pos) /*!< 0x00070000 */
#define CSI_LMCFGR_DL0MAP CSI_LMCFGR_DL0MAP_Msk /*!< Physical mapping of logical data lane 0 */
#define CSI_LMCFGR_DL1MAP_Pos (20U)
#define CSI_LMCFGR_DL1MAP_Msk (0x7UL << CSI_LMCFGR_DL1MAP_Pos) /*!< 0x00700000 */
#define CSI_LMCFGR_DL1MAP CSI_LMCFGR_DL1MAP_Msk /*!< Physical mapping of logical data lane 1 */
/****************** Bit definition for CSI_PRGITR register ******************/
#define CSI_PRGITR_LB0VC_Pos (0U)
#define CSI_PRGITR_LB0VC_Msk (0x3UL << CSI_PRGITR_LB0VC_Pos) /*!< 0x00000003 */
#define CSI_PRGITR_LB0VC CSI_PRGITR_LB0VC_Msk /*!< Line/Byte counter 0 linked to a virtual channel */
#define CSI_PRGITR_LB0EN_Pos (3U)
#define CSI_PRGITR_LB0EN_Msk (0x1UL << CSI_PRGITR_LB0EN_Pos) /*!< 0x00000008 */
#define CSI_PRGITR_LB0EN CSI_PRGITR_LB0EN_Msk /*!< Line/Byte 0counter enable */
#define CSI_PRGITR_LB1VC_Pos (4U)
#define CSI_PRGITR_LB1VC_Msk (0x3UL << CSI_PRGITR_LB1VC_Pos) /*!< 0x00000030 */
#define CSI_PRGITR_LB1VC CSI_PRGITR_LB1VC_Msk /*!< Line/Byte counter 1 linked to a virtual channel */
#define CSI_PRGITR_LB1EN_Pos (7U)
#define CSI_PRGITR_LB1EN_Msk (0x1UL << CSI_PRGITR_LB1EN_Pos) /*!< 0x00000080 */
#define CSI_PRGITR_LB1EN CSI_PRGITR_LB1EN_Msk /*!< Line/Byte 1 counter enable */
#define CSI_PRGITR_LB2VC_Pos (8U)
#define CSI_PRGITR_LB2VC_Msk (0x3UL << CSI_PRGITR_LB2VC_Pos) /*!< 0x00000300 */
#define CSI_PRGITR_LB2VC CSI_PRGITR_LB2VC_Msk /*!< Line/Byte counter 2 linked to a virtual channel */
#define CSI_PRGITR_LB2EN_Pos (11U)
#define CSI_PRGITR_LB2EN_Msk (0x1UL << CSI_PRGITR_LB2EN_Pos) /*!< 0x00000800 */
#define CSI_PRGITR_LB2EN CSI_PRGITR_LB2EN_Msk /*!< Line/Byte 2 counter enable */
#define CSI_PRGITR_LB3VC_Pos (12U)
#define CSI_PRGITR_LB3VC_Msk (0x3UL << CSI_PRGITR_LB3VC_Pos) /*!< 0x00003000 */
#define CSI_PRGITR_LB3VC CSI_PRGITR_LB3VC_Msk /*!< Line/Byte counter 3 linked to a virtual channel */
#define CSI_PRGITR_LB3EN_Pos (15U)
#define CSI_PRGITR_LB3EN_Msk (0x1UL << CSI_PRGITR_LB3EN_Pos) /*!< 0x00008000 */
#define CSI_PRGITR_LB3EN CSI_PRGITR_LB3EN_Msk /*!< Line/Byte 3 counter enable */
#define CSI_PRGITR_TIM0VC_Pos (16U)
#define CSI_PRGITR_TIM0VC_Msk (0x3UL << CSI_PRGITR_TIM0VC_Pos) /*!< 0x00030000 */
#define CSI_PRGITR_TIM0VC CSI_PRGITR_TIM0VC_Msk /*!< TIM0 base time linked to a virtual channel */
#define CSI_PRGITR_TIM0EOF_Pos (18U)
#define CSI_PRGITR_TIM0EOF_Msk (0x1UL << CSI_PRGITR_TIM0EOF_Pos) /*!< 0x00040000 */
#define CSI_PRGITR_TIM0EOF CSI_PRGITR_TIM0EOF_Msk /*!< TIM0 base time starting from the end of frame */
#define CSI_PRGITR_TIM0EN_Pos (19U)
#define CSI_PRGITR_TIM0EN_Msk (0x1UL << CSI_PRGITR_TIM0EN_Pos) /*!< 0x00080000 */
#define CSI_PRGITR_TIM0EN CSI_PRGITR_TIM0EN_Msk /*!< TIM0 base time enable */
#define CSI_PRGITR_TIM1VC_Pos (20U)
#define CSI_PRGITR_TIM1VC_Msk (0x3UL << CSI_PRGITR_TIM1VC_Pos) /*!< 0x00300000 */
#define CSI_PRGITR_TIM1VC CSI_PRGITR_TIM1VC_Msk /*!< TIM1 base time linked to a virtual channel */
#define CSI_PRGITR_TIM1EOF_Pos (22U)
#define CSI_PRGITR_TIM1EOF_Msk (0x1UL << CSI_PRGITR_TIM1EOF_Pos) /*!< 0x00400000 */
#define CSI_PRGITR_TIM1EOF CSI_PRGITR_TIM1EOF_Msk /*!< TIM1 base time starting from the end of frame */
#define CSI_PRGITR_TIM1EN_Pos (23U)
#define CSI_PRGITR_TIM1EN_Msk (0x1UL << CSI_PRGITR_TIM1EN_Pos) /*!< 0x00800000 */
#define CSI_PRGITR_TIM1EN CSI_PRGITR_TIM1EN_Msk /*!< TIM1 base time enable */
#define CSI_PRGITR_TIM2VC_Pos (24U)
#define CSI_PRGITR_TIM2VC_Msk (0x3UL << CSI_PRGITR_TIM2VC_Pos) /*!< 0x03000000 */
#define CSI_PRGITR_TIM2VC CSI_PRGITR_TIM2VC_Msk /*!< TIM2 base time linked to a virtual channel */
#define CSI_PRGITR_TIM2EOF_Pos (26U)
#define CSI_PRGITR_TIM2EOF_Msk (0x1UL << CSI_PRGITR_TIM2EOF_Pos) /*!< 0x04000000 */
#define CSI_PRGITR_TIM2EOF CSI_PRGITR_TIM2EOF_Msk /*!< TIM2 base time starting from the end of frame */
#define CSI_PRGITR_TIM2EN_Pos (27U)
#define CSI_PRGITR_TIM2EN_Msk (0x1UL << CSI_PRGITR_TIM2EN_Pos) /*!< 0x08000000 */
#define CSI_PRGITR_TIM2EN CSI_PRGITR_TIM2EN_Msk /*!< TIM2 base time enable */
#define CSI_PRGITR_TIM3VC_Pos (28U)
#define CSI_PRGITR_TIM3VC_Msk (0x3UL << CSI_PRGITR_TIM3VC_Pos) /*!< 0x30000000 */
#define CSI_PRGITR_TIM3VC CSI_PRGITR_TIM3VC_Msk /*!< TIM3 base time linked to a virtual channel */
#define CSI_PRGITR_TIM3EOF_Pos (30U)
#define CSI_PRGITR_TIM3EOF_Msk (0x1UL << CSI_PRGITR_TIM3EOF_Pos) /*!< 0x40000000 */
#define CSI_PRGITR_TIM3EOF CSI_PRGITR_TIM3EOF_Msk /*!< TIM3 base time starting from the end of frame */
#define CSI_PRGITR_TIM3EN_Pos (31U)
#define CSI_PRGITR_TIM3EN_Msk (0x1UL << CSI_PRGITR_TIM3EN_Pos) /*!< 0x80000000 */
#define CSI_PRGITR_TIM3EN CSI_PRGITR_TIM3EN_Msk /*!< TIM3 base time enable */
/******************* Bit definition for CSI_WDR register ********************/
#define CSI_WDR_CNT_Pos (0U)
#define CSI_WDR_CNT_Msk (0xFFFFFFFFUL << CSI_WDR_CNT_Pos) /*!< 0xFFFFFFFF */
#define CSI_WDR_CNT CSI_WDR_CNT_Msk /*!< Watchdog counter */
/******************* Bit definition for CSI_IER0 register *******************/
#define CSI_IER0_LB0IE_Pos (0U)
#define CSI_IER0_LB0IE_Msk (0x1UL << CSI_IER0_LB0IE_Pos) /*!< 0x00000001 */
#define CSI_IER0_LB0IE CSI_IER0_LB0IE_Msk /*!< Line byte counter 0 interrupt enable */
#define CSI_IER0_LB1IE_Pos (1U)
#define CSI_IER0_LB1IE_Msk (0x1UL << CSI_IER0_LB1IE_Pos) /*!< 0x00000002 */
#define CSI_IER0_LB1IE CSI_IER0_LB1IE_Msk /*!< Line byte counter 1 interrupt enable */
#define CSI_IER0_LB2IE_Pos (2U)
#define CSI_IER0_LB2IE_Msk (0x1UL << CSI_IER0_LB2IE_Pos) /*!< 0x00000004 */
#define CSI_IER0_LB2IE CSI_IER0_LB2IE_Msk /*!< Line byte counter 2 interrupt enable */
#define CSI_IER0_LB3IE_Pos (3U)
#define CSI_IER0_LB3IE_Msk (0x1UL << CSI_IER0_LB3IE_Pos) /*!< 0x00000008 */
#define CSI_IER0_LB3IE CSI_IER0_LB3IE_Msk /*!< Line byte counter 3 interrupt enable */
#define CSI_IER0_TIM0IE_Pos (4U)
#define CSI_IER0_TIM0IE_Msk (0x1UL << CSI_IER0_TIM0IE_Pos) /*!< 0x00000010 */
#define CSI_IER0_TIM0IE CSI_IER0_TIM0IE_Msk /*!< Timer 0 interrupt enable */
#define CSI_IER0_TIM1IE_Pos (5U)
#define CSI_IER0_TIM1IE_Msk (0x1UL << CSI_IER0_TIM1IE_Pos) /*!< 0x00000020 */
#define CSI_IER0_TIM1IE CSI_IER0_TIM1IE_Msk /*!< Timer 1 interrupt enable */
#define CSI_IER0_TIM2IE_Pos (6U)
#define CSI_IER0_TIM2IE_Msk (0x1UL << CSI_IER0_TIM2IE_Pos) /*!< 0x00000040 */
#define CSI_IER0_TIM2IE CSI_IER0_TIM2IE_Msk /*!< Timer 2 interrupt enable */
#define CSI_IER0_TIM3IE_Pos (7U)
#define CSI_IER0_TIM3IE_Msk (0x1UL << CSI_IER0_TIM3IE_Pos) /*!< 0x00000080 */
#define CSI_IER0_TIM3IE CSI_IER0_TIM3IE_Msk /*!< Timer 3 interrupt enable */
#define CSI_IER0_SOF0IE_Pos (8U)
#define CSI_IER0_SOF0IE_Msk (0x1UL << CSI_IER0_SOF0IE_Pos) /*!< 0x00000100 */
#define CSI_IER0_SOF0IE CSI_IER0_SOF0IE_Msk /*!< Start of frame for virtual channel 0 interrupt enable */
#define CSI_IER0_SOF1IE_Pos (9U)
#define CSI_IER0_SOF1IE_Msk (0x1UL << CSI_IER0_SOF1IE_Pos) /*!< 0x00000200 */
#define CSI_IER0_SOF1IE CSI_IER0_SOF1IE_Msk /*!< Start of frame for virtual channel 1 interrupt enable */
#define CSI_IER0_SOF2IE_Pos (10U)
#define CSI_IER0_SOF2IE_Msk (0x1UL << CSI_IER0_SOF2IE_Pos) /*!< 0x00000400 */
#define CSI_IER0_SOF2IE CSI_IER0_SOF2IE_Msk /*!< Start of frame for virtual channel 2 interrupt enable */
#define CSI_IER0_SOF3IE_Pos (11U)
#define CSI_IER0_SOF3IE_Msk (0x1UL << CSI_IER0_SOF3IE_Pos) /*!< 0x00000800 */
#define CSI_IER0_SOF3IE CSI_IER0_SOF3IE_Msk /*!< Start of frame for virtual channel 3 interrupt enable */
#define CSI_IER0_EOF0IE_Pos (12U)
#define CSI_IER0_EOF0IE_Msk (0x1UL << CSI_IER0_EOF0IE_Pos) /*!< 0x00001000 */
#define CSI_IER0_EOF0IE CSI_IER0_EOF0IE_Msk /*!< End of frame for virtual channel 0 interrupt enable */
#define CSI_IER0_EOF1IE_Pos (13U)
#define CSI_IER0_EOF1IE_Msk (0x1UL << CSI_IER0_EOF1IE_Pos) /*!< 0x00002000 */
#define CSI_IER0_EOF1IE CSI_IER0_EOF1IE_Msk /*!< End of frame for virtual channel 1 interrupt enable */
#define CSI_IER0_EOF2IE_Pos (14U)
#define CSI_IER0_EOF2IE_Msk (0x1UL << CSI_IER0_EOF2IE_Pos) /*!< 0x00004000 */
#define CSI_IER0_EOF2IE CSI_IER0_EOF2IE_Msk /*!< End of frame for virtual channel 2 interrupt enable */
#define CSI_IER0_EOF3IE_Pos (15U)
#define CSI_IER0_EOF3IE_Msk (0x1UL << CSI_IER0_EOF3IE_Pos) /*!< 0x00008000 */
#define CSI_IER0_EOF3IE CSI_IER0_EOF3IE_Msk /*!< End of frame for virtual channel 3 interrupt enable */
#define CSI_IER0_SPKTIE_Pos (16U)
#define CSI_IER0_SPKTIE_Msk (0x1UL << CSI_IER0_SPKTIE_Pos) /*!< 0x00010000 */
#define CSI_IER0_SPKTIE CSI_IER0_SPKTIE_Msk /*!< Short packet interrupt enable */
#define CSI_IER0_CCFIFOFIE_Pos (21U)
#define CSI_IER0_CCFIFOFIE_Msk (0x1UL << CSI_IER0_CCFIFOFIE_Pos) /*!< 0x00200000 */
#define CSI_IER0_CCFIFOFIE CSI_IER0_CCFIFOFIE_Msk /*!< Clock changer FIFO full interrupt enable */
#define CSI_IER0_CRCERRIE_Pos (24U)
#define CSI_IER0_CRCERRIE_Msk (0x1UL << CSI_IER0_CRCERRIE_Pos) /*!< 0x01000000 */
#define CSI_IER0_CRCERRIE CSI_IER0_CRCERRIE_Msk /*!< CRC error interrupt enable */
#define CSI_IER0_ECCERRIE_Pos (25U)
#define CSI_IER0_ECCERRIE_Msk (0x1UL << CSI_IER0_ECCERRIE_Pos) /*!< 0x02000000 */
#define CSI_IER0_ECCERRIE CSI_IER0_ECCERRIE_Msk /*!< ECC error interrupt enable */
#define CSI_IER0_CECCERRIE_Pos (26U)
#define CSI_IER0_CECCERRIE_Msk (0x1UL << CSI_IER0_CECCERRIE_Pos) /*!< 0x04000000 */
#define CSI_IER0_CECCERRIE CSI_IER0_CECCERRIE_Msk /*!< Corrected ECC error interrupt enable */
#define CSI_IER0_IDERRIE_Pos (27U)
#define CSI_IER0_IDERRIE_Msk (0x1UL << CSI_IER0_IDERRIE_Pos) /*!< 0x08000000 */
#define CSI_IER0_IDERRIE CSI_IER0_IDERRIE_Msk /*!< Data type ID error interrupt enable */
#define CSI_IER0_SPKTERRIE_Pos (28U)
#define CSI_IER0_SPKTERRIE_Msk (0x1UL << CSI_IER0_SPKTERRIE_Pos) /*!< 0x10000000 */
#define CSI_IER0_SPKTERRIE CSI_IER0_SPKTERRIE_Msk /*!< Short packet error interrupt enable */
#define CSI_IER0_WDERRIE_Pos (29U)
#define CSI_IER0_WDERRIE_Msk (0x1UL << CSI_IER0_WDERRIE_Pos) /*!< 0x20000000 */
#define CSI_IER0_WDERRIE CSI_IER0_WDERRIE_Msk /*!< Watchdog error interrupt enable */
#define CSI_IER0_SYNCERRIE_Pos (30U)
#define CSI_IER0_SYNCERRIE_Msk (0x1UL << CSI_IER0_SYNCERRIE_Pos) /*!< 0x40000000 */
#define CSI_IER0_SYNCERRIE CSI_IER0_SYNCERRIE_Msk /*!< Invalid synchronization error interrupt enable */
/******************* Bit definition for CSI_IER1 register *******************/
#define CSI_IER1_ESOTDL0IE_Pos (0U)
#define CSI_IER1_ESOTDL0IE_Msk (0x1UL << CSI_IER1_ESOTDL0IE_Pos) /*!< 0x00000001 */
#define CSI_IER1_ESOTDL0IE CSI_IER1_ESOTDL0IE_Msk /*!< Start of transmission error interrupt enable on lane 0 */
#define CSI_IER1_ESOTSYNCDL0IE_Pos (1U)
#define CSI_IER1_ESOTSYNCDL0IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL0IE_Pos) /*!< 0x00000002 */
#define CSI_IER1_ESOTSYNCDL0IE CSI_IER1_ESOTSYNCDL0IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 0 */
#define CSI_IER1_EESCDL0IE_Pos (2U)
#define CSI_IER1_EESCDL0IE_Msk (0x1UL << CSI_IER1_EESCDL0IE_Pos) /*!< 0x00000004 */
#define CSI_IER1_EESCDL0IE CSI_IER1_EESCDL0IE_Msk /*!< D-PHY_RX lane 0 escape entry error interrupt enable */
#define CSI_IER1_ESYNCESCDL0IE_Pos (3U)
#define CSI_IER1_ESYNCESCDL0IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL0IE_Pos) /*!< 0x00000008 */
#define CSI_IER1_ESYNCESCDL0IE CSI_IER1_ESYNCESCDL0IE_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error interrupt enable */
#define CSI_IER1_ECTRLDL0IE_Pos (4U)
#define CSI_IER1_ECTRLDL0IE_Msk (0x1UL << CSI_IER1_ECTRLDL0IE_Pos) /*!< 0x00000010 */
#define CSI_IER1_ECTRLDL0IE CSI_IER1_ECTRLDL0IE_Msk /*!< D-PHY_RX lane 0 control error interrupt enable */
#define CSI_IER1_ESOTDL1IE_Pos (8U)
#define CSI_IER1_ESOTDL1IE_Msk (0x1UL << CSI_IER1_ESOTDL1IE_Pos) /*!< 0x00000100 */
#define CSI_IER1_ESOTDL1IE CSI_IER1_ESOTDL1IE_Msk /*!< Start of transmission error interrupt enable on lane 1 */
#define CSI_IER1_ESOTSYNCDL1IE_Pos (9U)
#define CSI_IER1_ESOTSYNCDL1IE_Msk (0x1UL << CSI_IER1_ESOTSYNCDL1IE_Pos) /*!< 0x00000200 */
#define CSI_IER1_ESOTSYNCDL1IE CSI_IER1_ESOTSYNCDL1IE_Msk /*!< Start of transmission synchronization interrupt error enable on lane 1 */
#define CSI_IER1_EESCDL1IE_Pos (10U)
#define CSI_IER1_EESCDL1IE_Msk (0x1UL << CSI_IER1_EESCDL1IE_Pos) /*!< 0x00000400 */
#define CSI_IER1_EESCDL1IE CSI_IER1_EESCDL1IE_Msk /*!< D-PHY_RX lane 1 escape entry error interrupt enable */
#define CSI_IER1_ESYNCESCDL1IE_Pos (11U)
#define CSI_IER1_ESYNCESCDL1IE_Msk (0x1UL << CSI_IER1_ESYNCESCDL1IE_Pos) /*!< 0x00000800 */
#define CSI_IER1_ESYNCESCDL1IE CSI_IER1_ESYNCESCDL1IE_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error interrupt enable */
#define CSI_IER1_ECTRLDL1IE_Pos (12U)
#define CSI_IER1_ECTRLDL1IE_Msk (0x1UL << CSI_IER1_ECTRLDL1IE_Pos) /*!< 0x00001000 */
#define CSI_IER1_ECTRLDL1IE CSI_IER1_ECTRLDL1IE_Msk /*!< D-PHY_RX lane 1 control error interrupt enable */
/******************* Bit definition for CSI_SR0 register ********************/
#define CSI_SR0_LB0F_Pos (0U)
#define CSI_SR0_LB0F_Msk (0x1UL << CSI_SR0_LB0F_Pos) /*!< 0x00000001 */
#define CSI_SR0_LB0F CSI_SR0_LB0F_Msk /*!< Line byte counter 0 flag */
#define CSI_SR0_LB1F_Pos (1U)
#define CSI_SR0_LB1F_Msk (0x1UL << CSI_SR0_LB1F_Pos) /*!< 0x00000002 */
#define CSI_SR0_LB1F CSI_SR0_LB1F_Msk /*!< Line byte counter 1 flag */
#define CSI_SR0_LB2F_Pos (2U)
#define CSI_SR0_LB2F_Msk (0x1UL << CSI_SR0_LB2F_Pos) /*!< 0x00000004 */
#define CSI_SR0_LB2F CSI_SR0_LB2F_Msk /*!< Line byte counter 2 flag */
#define CSI_SR0_LB3F_Pos (3U)
#define CSI_SR0_LB3F_Msk (0x1UL << CSI_SR0_LB3F_Pos) /*!< 0x00000008 */
#define CSI_SR0_LB3F CSI_SR0_LB3F_Msk /*!< Line byte counter 3 flag */
#define CSI_SR0_TIM0F_Pos (4U)
#define CSI_SR0_TIM0F_Msk (0x1UL << CSI_SR0_TIM0F_Pos) /*!< 0x00000010 */
#define CSI_SR0_TIM0F CSI_SR0_TIM0F_Msk /*!< Timer 0 flag */
#define CSI_SR0_TIM1F_Pos (5U)
#define CSI_SR0_TIM1F_Msk (0x1UL << CSI_SR0_TIM1F_Pos) /*!< 0x00000020 */
#define CSI_SR0_TIM1F CSI_SR0_TIM1F_Msk /*!< Timer 1 flag */
#define CSI_SR0_TIM2F_Pos (6U)
#define CSI_SR0_TIM2F_Msk (0x1UL << CSI_SR0_TIM2F_Pos) /*!< 0x00000040 */
#define CSI_SR0_TIM2F CSI_SR0_TIM2F_Msk /*!< Timer 2 flag */
#define CSI_SR0_TIM3F_Pos (7U)
#define CSI_SR0_TIM3F_Msk (0x1UL << CSI_SR0_TIM3F_Pos) /*!< 0x00000080 */
#define CSI_SR0_TIM3F CSI_SR0_TIM3F_Msk /*!< Timer 3 flag */
#define CSI_SR0_SOF0F_Pos (8U)
#define CSI_SR0_SOF0F_Msk (0x1UL << CSI_SR0_SOF0F_Pos) /*!< 0x00000100 */
#define CSI_SR0_SOF0F CSI_SR0_SOF0F_Msk /*!< Start of frame flag for virtual channel 0 */
#define CSI_SR0_SOF1F_Pos (9U)
#define CSI_SR0_SOF1F_Msk (0x1UL << CSI_SR0_SOF1F_Pos) /*!< 0x00000200 */
#define CSI_SR0_SOF1F CSI_SR0_SOF1F_Msk /*!< Start of frame flag for virtual channel 1 */
#define CSI_SR0_SOF2F_Pos (10U)
#define CSI_SR0_SOF2F_Msk (0x1UL << CSI_SR0_SOF2F_Pos) /*!< 0x00000400 */
#define CSI_SR0_SOF2F CSI_SR0_SOF2F_Msk /*!< Start of frame flag for virtual channel 2 */
#define CSI_SR0_SOF3F_Pos (11U)
#define CSI_SR0_SOF3F_Msk (0x1UL << CSI_SR0_SOF3F_Pos) /*!< 0x00000800 */
#define CSI_SR0_SOF3F CSI_SR0_SOF3F_Msk /*!< Start of frame flag for virtual channel 3 */
#define CSI_SR0_EOF0F_Pos (12U)
#define CSI_SR0_EOF0F_Msk (0x1UL << CSI_SR0_EOF0F_Pos) /*!< 0x00001000 */
#define CSI_SR0_EOF0F CSI_SR0_EOF0F_Msk /*!< End of frame flag for virtual channel 0 */
#define CSI_SR0_EOF1F_Pos (13U)
#define CSI_SR0_EOF1F_Msk (0x1UL << CSI_SR0_EOF1F_Pos) /*!< 0x00002000 */
#define CSI_SR0_EOF1F CSI_SR0_EOF1F_Msk /*!< End of frame flag for virtual channel 1 */
#define CSI_SR0_EOF2F_Pos (14U)
#define CSI_SR0_EOF2F_Msk (0x1UL << CSI_SR0_EOF2F_Pos) /*!< 0x00004000 */
#define CSI_SR0_EOF2F CSI_SR0_EOF2F_Msk /*!< End of frame flag for virtual channel 2 */
#define CSI_SR0_EOF3F_Pos (15U)
#define CSI_SR0_EOF3F_Msk (0x1UL << CSI_SR0_EOF3F_Pos) /*!< 0x00008000 */
#define CSI_SR0_EOF3F CSI_SR0_EOF3F_Msk /*!< End of frame flag for virtual channel 3 */
#define CSI_SR0_SPKTF_Pos (16U)
#define CSI_SR0_SPKTF_Msk (0x1UL << CSI_SR0_SPKTF_Pos) /*!< 0x00010000 */
#define CSI_SR0_SPKTF CSI_SR0_SPKTF_Msk /*!< Short packet flag */
#define CSI_SR0_VC0STATEF_Pos (17U)
#define CSI_SR0_VC0STATEF_Msk (0x1UL << CSI_SR0_VC0STATEF_Pos) /*!< 0x00020000 */
#define CSI_SR0_VC0STATEF CSI_SR0_VC0STATEF_Msk /*!< Virtual channel 0 state flag */
#define CSI_SR0_VC1STATEF_Pos (18U)
#define CSI_SR0_VC1STATEF_Msk (0x1UL << CSI_SR0_VC1STATEF_Pos) /*!< 0x00040000 */
#define CSI_SR0_VC1STATEF CSI_SR0_VC1STATEF_Msk /*!< Virtual channel 1 state flag */
#define CSI_SR0_VC2STATEF_Pos (19U)
#define CSI_SR0_VC2STATEF_Msk (0x1UL << CSI_SR0_VC2STATEF_Pos) /*!< 0x00080000 */
#define CSI_SR0_VC2STATEF CSI_SR0_VC2STATEF_Msk /*!< Virtual channel 2 state flag */
#define CSI_SR0_VC3STATEF_Pos (20U)
#define CSI_SR0_VC3STATEF_Msk (0x1UL << CSI_SR0_VC3STATEF_Pos) /*!< 0x00100000 */
#define CSI_SR0_VC3STATEF CSI_SR0_VC3STATEF_Msk /*!< Virtual channel 3 state flag */
#define CSI_SR0_CCFIFOFF_Pos (21U)
#define CSI_SR0_CCFIFOFF_Msk (0x1UL << CSI_SR0_CCFIFOFF_Pos) /*!< 0x00200000 */
#define CSI_SR0_CCFIFOFF CSI_SR0_CCFIFOFF_Msk /*!< Clock changer FIFO full flag */
#define CSI_SR0_CRCERRF_Pos (24U)
#define CSI_SR0_CRCERRF_Msk (0x1UL << CSI_SR0_CRCERRF_Pos) /*!< 0x01000000 */
#define CSI_SR0_CRCERRF CSI_SR0_CRCERRF_Msk /*!< CRC error flag */
#define CSI_SR0_ECCERRF_Pos (25U)
#define CSI_SR0_ECCERRF_Msk (0x1UL << CSI_SR0_ECCERRF_Pos) /*!< 0x02000000 */
#define CSI_SR0_ECCERRF CSI_SR0_ECCERRF_Msk /*!< ECC error flag */
#define CSI_SR0_CECCERRF_Pos (26U)
#define CSI_SR0_CECCERRF_Msk (0x1UL << CSI_SR0_CECCERRF_Pos) /*!< 0x04000000 */
#define CSI_SR0_CECCERRF CSI_SR0_CECCERRF_Msk /*!< Corrected ECC error flag */
#define CSI_SR0_IDERRF_Pos (27U)
#define CSI_SR0_IDERRF_Msk (0x1UL << CSI_SR0_IDERRF_Pos) /*!< 0x08000000 */
#define CSI_SR0_IDERRF CSI_SR0_IDERRF_Msk /*!< Data type ID error flag */
#define CSI_SR0_SPKTERRF_Pos (28U)
#define CSI_SR0_SPKTERRF_Msk (0x1UL << CSI_SR0_SPKTERRF_Pos) /*!< 0x10000000 */
#define CSI_SR0_SPKTERRF CSI_SR0_SPKTERRF_Msk /*!< Short packet error flag */
#define CSI_SR0_WDERRF_Pos (29U)
#define CSI_SR0_WDERRF_Msk (0x1UL << CSI_SR0_WDERRF_Pos) /*!< 0x20000000 */
#define CSI_SR0_WDERRF CSI_SR0_WDERRF_Msk /*!< Watchdog error flag */
#define CSI_SR0_SYNCERRF_Pos (30U)
#define CSI_SR0_SYNCERRF_Msk (0x1UL << CSI_SR0_SYNCERRF_Pos) /*!< 0x40000000 */
#define CSI_SR0_SYNCERRF CSI_SR0_SYNCERRF_Msk /*!< Invalid synchronization error flag */
/******************* Bit definition for CSI_SR1 register ********************/
#define CSI_SR1_ESOTDL0F_Pos (0U)
#define CSI_SR1_ESOTDL0F_Msk (0x1UL << CSI_SR1_ESOTDL0F_Pos) /*!< 0x00000001 */
#define CSI_SR1_ESOTDL0F CSI_SR1_ESOTDL0F_Msk /*!< Start of transmission error flag on lane 0 */
#define CSI_SR1_ESOTSYNCDL0F_Pos (1U)
#define CSI_SR1_ESOTSYNCDL0F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL0F_Pos) /*!< 0x00000002 */
#define CSI_SR1_ESOTSYNCDL0F CSI_SR1_ESOTSYNCDL0F_Msk /*!< Start of transmission synchronization error flag on lane 0 */
#define CSI_SR1_EESCDL0F_Pos (2U)
#define CSI_SR1_EESCDL0F_Msk (0x1UL << CSI_SR1_EESCDL0F_Pos) /*!< 0x00000004 */
#define CSI_SR1_EESCDL0F CSI_SR1_EESCDL0F_Msk /*!< D-PHY_RX lane 0 escape entry error flag */
#define CSI_SR1_ESYNCESCDL0F_Pos (3U)
#define CSI_SR1_ESYNCESCDL0F_Msk (0x1UL << CSI_SR1_ESYNCESCDL0F_Pos) /*!< 0x00000008 */
#define CSI_SR1_ESYNCESCDL0F CSI_SR1_ESYNCESCDL0F_Msk /*!< D-PHY_RX lane 0 low power data transmission synchronization error flag */
#define CSI_SR1_ECTRLDL0F_Pos (4U)
#define CSI_SR1_ECTRLDL0F_Msk (0x1UL << CSI_SR1_ECTRLDL0F_Pos) /*!< 0x00000010 */
#define CSI_SR1_ECTRLDL0F CSI_SR1_ECTRLDL0F_Msk /*!< D-PHY_RX lane 0 control error flag */
#define CSI_SR1_ESOTDL1F_Pos (8U)
#define CSI_SR1_ESOTDL1F_Msk (0x1UL << CSI_SR1_ESOTDL1F_Pos) /*!< 0x00000100 */
#define CSI_SR1_ESOTDL1F CSI_SR1_ESOTDL1F_Msk /*!< Start of transmission error flag on lane 1 */
#define CSI_SR1_ESOTSYNCDL1F_Pos (9U)
#define CSI_SR1_ESOTSYNCDL1F_Msk (0x1UL << CSI_SR1_ESOTSYNCDL1F_Pos) /*!< 0x00000200 */
#define CSI_SR1_ESOTSYNCDL1F CSI_SR1_ESOTSYNCDL1F_Msk /*!< Start of transmission synchronization error flag on lane 1 */
#define CSI_SR1_EESCDL1F_Pos (10U)
#define CSI_SR1_EESCDL1F_Msk (0x1UL << CSI_SR1_EESCDL1F_Pos) /*!< 0x00000400 */
#define CSI_SR1_EESCDL1F CSI_SR1_EESCDL1F_Msk /*!< D-PHY_RX lane 1 escape entry error flag */
#define CSI_SR1_ESYNCESCDL1F_Pos (11U)
#define CSI_SR1_ESYNCESCDL1F_Msk (0x1UL << CSI_SR1_ESYNCESCDL1F_Pos) /*!< 0x00000800 */
#define CSI_SR1_ESYNCESCDL1F CSI_SR1_ESYNCESCDL1F_Msk /*!< D-PHY_RX lane 1 low power data transmission synchronization error flag */
#define CSI_SR1_ECTRLDL1F_Pos (12U)
#define CSI_SR1_ECTRLDL1F_Msk (0x1UL << CSI_SR1_ECTRLDL1F_Pos) /*!< 0x00001000 */
#define CSI_SR1_ECTRLDL1F CSI_SR1_ECTRLDL1F_Msk /*!< D-PHY_RX lane 1 control error flag */
#define CSI_SR1_ACTDL0F_Pos (16U)
#define CSI_SR1_ACTDL0F_Msk (0x1UL << CSI_SR1_ACTDL0F_Pos) /*!< 0x00010000 */
#define CSI_SR1_ACTDL0F CSI_SR1_ACTDL0F_Msk /*!< D-PHY_RX lane 0 High speed reception active */
#define CSI_SR1_SYNCDL0F_Pos (17U)
#define CSI_SR1_SYNCDL0F_Msk (0x1UL << CSI_SR1_SYNCDL0F_Pos) /*!< 0x00020000 */
#define CSI_SR1_SYNCDL0F CSI_SR1_SYNCDL0F_Msk /*!< D-PHY_RX lane 0 receiver synchronization observed */
#define CSI_SR1_SKCALDL0F_Pos (18U)
#define CSI_SR1_SKCALDL0F_Msk (0x1UL << CSI_SR1_SKCALDL0F_Pos) /*!< 0x00040000 */
#define CSI_SR1_SKCALDL0F CSI_SR1_SKCALDL0F_Msk /*!< D-PHY_RX lane 0 High speed skew calibration */
#define CSI_SR1_STOPDL0F_Pos (19U)
#define CSI_SR1_STOPDL0F_Msk (0x1UL << CSI_SR1_STOPDL0F_Pos) /*!< 0x00080000 */
#define CSI_SR1_STOPDL0F CSI_SR1_STOPDL0F_Msk /*!< D-PHY_RX receiver data lane 0 in stop state */
#define CSI_SR1_ULPNDL0F_Pos (20U)
#define CSI_SR1_ULPNDL0F_Msk (0x1UL << CSI_SR1_ULPNDL0F_Pos) /*!< 0x00100000 */
#define CSI_SR1_ULPNDL0F CSI_SR1_ULPNDL0F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 00 */
#define CSI_SR1_ACTDL1F_Pos (22U)
#define CSI_SR1_ACTDL1F_Msk (0x1UL << CSI_SR1_ACTDL1F_Pos) /*!< 0x00400000 */
#define CSI_SR1_ACTDL1F CSI_SR1_ACTDL1F_Msk /*!< D-PHY_RX lane 1 High speed reception active */
#define CSI_SR1_SYNCDL1F_Pos (23U)
#define CSI_SR1_SYNCDL1F_Msk (0x1UL << CSI_SR1_SYNCDL1F_Pos) /*!< 0x00800000 */
#define CSI_SR1_SYNCDL1F CSI_SR1_SYNCDL1F_Msk /*!< D-PHY_RX lane 1 receiver synchronization observed */
#define CSI_SR1_SKCALDL1F_Pos (24U)
#define CSI_SR1_SKCALDL1F_Msk (0x1UL << CSI_SR1_SKCALDL1F_Pos) /*!< 0x01000000 */
#define CSI_SR1_SKCALDL1F CSI_SR1_SKCALDL1F_Msk /*!< D-PHY_RX lane 1 High speed skew calibration */
#define CSI_SR1_STOPDL1F_Pos (25U)
#define CSI_SR1_STOPDL1F_Msk (0x1UL << CSI_SR1_STOPDL1F_Pos) /*!< 0x02000000 */
#define CSI_SR1_STOPDL1F CSI_SR1_STOPDL1F_Msk /*!< D-PHY_RX receiver data lane 1 in stop state */
#define CSI_SR1_ULPNDL1F_Pos (26U)
#define CSI_SR1_ULPNDL1F_Msk (0x1UL << CSI_SR1_ULPNDL1F_Pos) /*!< 0x04000000 */
#define CSI_SR1_ULPNDL1F CSI_SR1_ULPNDL1F_Msk /*!< D-PHY_RX receiver Ultra low power state (not) Active on data lane 1 */
#define CSI_SR1_STOPCLF_Pos (28U)
#define CSI_SR1_STOPCLF_Msk (0x1UL << CSI_SR1_STOPCLF_Pos) /*!< 0x10000000 */
#define CSI_SR1_STOPCLF CSI_SR1_STOPCLF_Msk /*!< D-PHY_RX receiver in stop state for the clock lane */
#define CSI_SR1_ULPNACTF_Pos (29U)
#define CSI_SR1_ULPNACTF_Msk (0x1UL << CSI_SR1_ULPNACTF_Pos) /*!< 0x20000000 */
#define CSI_SR1_ULPNACTF CSI_SR1_ULPNACTF_Msk /*!< D-PHY_RX receiver ULP state (not) active */
#define CSI_SR1_ULPNCLF_Pos (30U)
#define CSI_SR1_ULPNCLF_Msk (0x1UL << CSI_SR1_ULPNCLF_Pos) /*!< 0x40000000 */
#define CSI_SR1_ULPNCLF CSI_SR1_ULPNCLF_Msk /*!< D-PHY_RX receiver Ultra-Low power state (not) on clock lane */
#define CSI_SR1_ACTCLF_Pos (31U)
#define CSI_SR1_ACTCLF_Msk (0x1UL << CSI_SR1_ACTCLF_Pos) /*!< 0x80000000 */
#define CSI_SR1_ACTCLF CSI_SR1_ACTCLF_Msk /*!< D-PHY_RX receiver clock active flag */
/******************* Bit definition for CSI_FCR0 register *******************/
#define CSI_FCR0_CLB0F_Pos (0U)
#define CSI_FCR0_CLB0F_Msk (0x1UL << CSI_FCR0_CLB0F_Pos) /*!< 0x00000001 */
#define CSI_FCR0_CLB0F CSI_FCR0_CLB0F_Msk /*!< Clear Line byte counter 0 flag */
#define CSI_FCR0_CLB1F_Pos (1U)
#define CSI_FCR0_CLB1F_Msk (0x1UL << CSI_FCR0_CLB1F_Pos) /*!< 0x00000002 */
#define CSI_FCR0_CLB1F CSI_FCR0_CLB1F_Msk /*!< Clear Line byte counter 1 flag */
#define CSI_FCR0_CLB2F_Pos (2U)
#define CSI_FCR0_CLB2F_Msk (0x1UL << CSI_FCR0_CLB2F_Pos) /*!< 0x00000004 */
#define CSI_FCR0_CLB2F CSI_FCR0_CLB2F_Msk /*!< Clear Line byte counter 2 flag */
#define CSI_FCR0_CLB3F_Pos (3U)
#define CSI_FCR0_CLB3F_Msk (0x1UL << CSI_FCR0_CLB3F_Pos) /*!< 0x00000008 */
#define CSI_FCR0_CLB3F CSI_FCR0_CLB3F_Msk /*!< Clear Line byte counter 3 flag */
#define CSI_FCR0_CTIM0F_Pos (4U)
#define CSI_FCR0_CTIM0F_Msk (0x1UL << CSI_FCR0_CTIM0F_Pos) /*!< 0x00000010 */
#define CSI_FCR0_CTIM0F CSI_FCR0_CTIM0F_Msk /*!< Clear Timer 0 flag */
#define CSI_FCR0_CTIM1F_Pos (5U)
#define CSI_FCR0_CTIM1F_Msk (0x1UL << CSI_FCR0_CTIM1F_Pos) /*!< 0x00000020 */
#define CSI_FCR0_CTIM1F CSI_FCR0_CTIM1F_Msk /*!< Clear Timer 1 flag */
#define CSI_FCR0_CTIM2F_Pos (6U)
#define CSI_FCR0_CTIM2F_Msk (0x1UL << CSI_FCR0_CTIM2F_Pos) /*!< 0x00000040 */
#define CSI_FCR0_CTIM2F CSI_FCR0_CTIM2F_Msk /*!< Clear Timer 2 flag */
#define CSI_FCR0_CTIM3F_Pos (7U)
#define CSI_FCR0_CTIM3F_Msk (0x1UL << CSI_FCR0_CTIM3F_Pos) /*!< 0x00000080 */
#define CSI_FCR0_CTIM3F CSI_FCR0_CTIM3F_Msk /*!< Clear Timer 3 flag */
#define CSI_FCR0_CSOF0F_Pos (8U)
#define CSI_FCR0_CSOF0F_Msk (0x1UL << CSI_FCR0_CSOF0F_Pos) /*!< 0x00000100 */
#define CSI_FCR0_CSOF0F CSI_FCR0_CSOF0F_Msk /*!< Clear Start of frame flag for virtual channel 0 */
#define CSI_FCR0_CSOF1F_Pos (9U)
#define CSI_FCR0_CSOF1F_Msk (0x1UL << CSI_FCR0_CSOF1F_Pos) /*!< 0x00000200 */
#define CSI_FCR0_CSOF1F CSI_FCR0_CSOF1F_Msk /*!< Clear Start of frame flag for virtual channel 1 */
#define CSI_FCR0_CSOF2F_Pos (10U)
#define CSI_FCR0_CSOF2F_Msk (0x1UL << CSI_FCR0_CSOF2F_Pos) /*!< 0x00000400 */
#define CSI_FCR0_CSOF2F CSI_FCR0_CSOF2F_Msk /*!< Clear Start of frame flag for virtual channel 2 */
#define CSI_FCR0_CSOF3F_Pos (11U)
#define CSI_FCR0_CSOF3F_Msk (0x1UL << CSI_FCR0_CSOF3F_Pos) /*!< 0x00000800 */
#define CSI_FCR0_CSOF3F CSI_FCR0_CSOF3F_Msk /*!< Clear Start of frame flag for virtual channel 3 */
#define CSI_FCR0_CEOF0F_Pos (12U)
#define CSI_FCR0_CEOF0F_Msk (0x1UL << CSI_FCR0_CEOF0F_Pos) /*!< 0x00001000 */
#define CSI_FCR0_CEOF0F CSI_FCR0_CEOF0F_Msk /*!< Clear End of frame flag for virtual channel 0 */
#define CSI_FCR0_CEOF1F_Pos (13U)
#define CSI_FCR0_CEOF1F_Msk (0x1UL << CSI_FCR0_CEOF1F_Pos) /*!< 0x00002000 */
#define CSI_FCR0_CEOF1F CSI_FCR0_CEOF1F_Msk /*!< Clear End of frame flag for virtual channel 1 */
#define CSI_FCR0_CEOF2F_Pos (14U)
#define CSI_FCR0_CEOF2F_Msk (0x1UL << CSI_FCR0_CEOF2F_Pos) /*!< 0x00004000 */
#define CSI_FCR0_CEOF2F CSI_FCR0_CEOF2F_Msk /*!< Clear End of frame flag for virtual channel 2 */
#define CSI_FCR0_CEOF3F_Pos (15U)
#define CSI_FCR0_CEOF3F_Msk (0x1UL << CSI_FCR0_CEOF3F_Pos) /*!< 0x00008000 */
#define CSI_FCR0_CEOF3F CSI_FCR0_CEOF3F_Msk /*!< Clear End of frame flag for virtual channel 3 */
#define CSI_FCR0_CSPKTF_Pos (16U)
#define CSI_FCR0_CSPKTF_Msk (0x1UL << CSI_FCR0_CSPKTF_Pos) /*!< 0x00010000 */
#define CSI_FCR0_CSPKTF CSI_FCR0_CSPKTF_Msk /*!< Clear Short packet flag */
#define CSI_FCR0_CCCFIFOFF_Pos (21U)
#define CSI_FCR0_CCCFIFOFF_Msk (0x1UL << CSI_FCR0_CCCFIFOFF_Pos) /*!< 0x00200000 */
#define CSI_FCR0_CCCFIFOFF CSI_FCR0_CCCFIFOFF_Msk /*!< Clear Clock changer FIFO full flag */
#define CSI_FCR0_CCRCERRF_Pos (24U)
#define CSI_FCR0_CCRCERRF_Msk (0x1UL << CSI_FCR0_CCRCERRF_Pos) /*!< 0x01000000 */
#define CSI_FCR0_CCRCERRF CSI_FCR0_CCRCERRF_Msk /*!< Clear CRC error flag */
#define CSI_FCR0_CECCERRF_Pos (25U)
#define CSI_FCR0_CECCERRF_Msk (0x1UL << CSI_FCR0_CECCERRF_Pos) /*!< 0x02000000 */
#define CSI_FCR0_CECCERRF CSI_FCR0_CECCERRF_Msk /*!< Clear ECC error flag */
#define CSI_FCR0_CCECCERRF_Pos (26U)
#define CSI_FCR0_CCECCERRF_Msk (0x1UL << CSI_FCR0_CCECCERRF_Pos) /*!< 0x04000000 */
#define CSI_FCR0_CCECCERRF CSI_FCR0_CCECCERRF_Msk /*!< Clear Corrected ECC error flag */
#define CSI_FCR0_CIDERRF_Pos (27U)
#define CSI_FCR0_CIDERRF_Msk (0x1UL << CSI_FCR0_CIDERRF_Pos) /*!< 0x08000000 */
#define CSI_FCR0_CIDERRF CSI_FCR0_CIDERRF_Msk /*!< Clear Data type ID error flag */
#define CSI_FCR0_CSPKTERRF_Pos (28U)
#define CSI_FCR0_CSPKTERRF_Msk (0x1UL << CSI_FCR0_CSPKTERRF_Pos) /*!< 0x10000000 */
#define CSI_FCR0_CSPKTERRF CSI_FCR0_CSPKTERRF_Msk /*!< Clear Short packet error flag */
#define CSI_FCR0_CWDERRF_Pos (29U)
#define CSI_FCR0_CWDERRF_Msk (0x1UL << CSI_FCR0_CWDERRF_Pos) /*!< 0x20000000 */
#define CSI_FCR0_CWDERRF CSI_FCR0_CWDERRF_Msk /*!< Clear Watchdog error flag */
#define CSI_FCR0_CSYNCERRF_Pos (30U)
#define CSI_FCR0_CSYNCERRF_Msk (0x1UL << CSI_FCR0_CSYNCERRF_Pos) /*!< 0x40000000 */
#define CSI_FCR0_CSYNCERRF CSI_FCR0_CSYNCERRF_Msk /*!< Clear Invalid synchronization error flag */
/******************* Bit definition for CSI_FCR1 register *******************/
#define CSI_FCR1_CESOTDL0F_Pos (0U)
#define CSI_FCR1_CESOTDL0F_Msk (0x1UL << CSI_FCR1_CESOTDL0F_Pos) /*!< 0x00000001 */
#define CSI_FCR1_CESOTDL0F CSI_FCR1_CESOTDL0F_Msk /*!< Clear Start of transmission error flag on lane 0 */
#define CSI_FCR1_CESOTSYNCDL0F_Pos (1U)
#define CSI_FCR1_CESOTSYNCDL0F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL0F_Pos) /*!< 0x00000002 */
#define CSI_FCR1_CESOTSYNCDL0F CSI_FCR1_CESOTSYNCDL0F_Msk /*!< Clear Start of transmission synchronization error flag on lane 0 */
#define CSI_FCR1_CEESCDL0F_Pos (2U)
#define CSI_FCR1_CEESCDL0F_Msk (0x1UL << CSI_FCR1_CEESCDL0F_Pos) /*!< 0x00000004 */
#define CSI_FCR1_CEESCDL0F CSI_FCR1_CEESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 escape entry error flag */
#define CSI_FCR1_CESYNCESCDL0F_Pos (3U)
#define CSI_FCR1_CESYNCESCDL0F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL0F_Pos) /*!< 0x00000008 */
#define CSI_FCR1_CESYNCESCDL0F CSI_FCR1_CESYNCESCDL0F_Msk /*!< Clear D-PHY_RX lane 0 low power data transmission synchronization error flag */
#define CSI_FCR1_CECTRLDL0F_Pos (4U)
#define CSI_FCR1_CECTRLDL0F_Msk (0x1UL << CSI_FCR1_CECTRLDL0F_Pos) /*!< 0x00000010 */
#define CSI_FCR1_CECTRLDL0F CSI_FCR1_CECTRLDL0F_Msk /*!< Clear D-PHY_RX lane 0 control error flag */
#define CSI_FCR1_CESOTDL1F_Pos (8U)
#define CSI_FCR1_CESOTDL1F_Msk (0x1UL << CSI_FCR1_CESOTDL1F_Pos) /*!< 0x00000100 */
#define CSI_FCR1_CESOTDL1F CSI_FCR1_CESOTDL1F_Msk /*!< Clear Start of transmission error flag on lane 1 */
#define CSI_FCR1_CESOTSYNCDL1F_Pos (9U)
#define CSI_FCR1_CESOTSYNCDL1F_Msk (0x1UL << CSI_FCR1_CESOTSYNCDL1F_Pos) /*!< 0x00000200 */
#define CSI_FCR1_CESOTSYNCDL1F CSI_FCR1_CESOTSYNCDL1F_Msk /*!< Clear Start of transmission synchronization error flag on lane 1 */
#define CSI_FCR1_CEESCDL1F_Pos (10U)
#define CSI_FCR1_CEESCDL1F_Msk (0x1UL << CSI_FCR1_CEESCDL1F_Pos) /*!< 0x00000400 */
#define CSI_FCR1_CEESCDL1F CSI_FCR1_CEESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 escape entry error flag */
#define CSI_FCR1_CESYNCESCDL1F_Pos (11U)
#define CSI_FCR1_CESYNCESCDL1F_Msk (0x1UL << CSI_FCR1_CESYNCESCDL1F_Pos) /*!< 0x00000800 */
#define CSI_FCR1_CESYNCESCDL1F CSI_FCR1_CESYNCESCDL1F_Msk /*!< Clear D-PHY_RX lane 1 low power data transmission synchronization error flag */
#define CSI_FCR1_CECTRLDL1F_Pos (12U)
#define CSI_FCR1_CECTRLDL1F_Msk (0x1UL << CSI_FCR1_CECTRLDL1F_Pos) /*!< 0x00001000 */
#define CSI_FCR1_CECTRLDL1F CSI_FCR1_CECTRLDL1F_Msk /*!< Clear D-PHY_RX lane 1 control error flag */
/****************** Bit definition for CSI_SPDFR register *******************/
#define CSI_SPDFR_DATAFIELD_Pos (0U)
#define CSI_SPDFR_DATAFIELD_Msk (0xFFFFUL << CSI_SPDFR_DATAFIELD_Pos) /*!< 0x0000FFFF */
#define CSI_SPDFR_DATAFIELD CSI_SPDFR_DATAFIELD_Msk /*!< Data field */
#define CSI_SPDFR_DATATYPE_Pos (16U)
#define CSI_SPDFR_DATATYPE_Msk (0x3FUL << CSI_SPDFR_DATATYPE_Pos) /*!< 0x003F0000 */
#define CSI_SPDFR_DATATYPE CSI_SPDFR_DATATYPE_Msk /*!< Data type class */
#define CSI_SPDFR_VCHANNEL_Pos (22U)
#define CSI_SPDFR_VCHANNEL_Msk (0x3UL << CSI_SPDFR_VCHANNEL_Pos) /*!< 0x00C00000 */
#define CSI_SPDFR_VCHANNEL CSI_SPDFR_VCHANNEL_Msk /*!< Virtual channel */
/******************* Bit definition for CSI_ERR1 register *******************/
#define CSI_ERR1_CRCDTERR_Pos (0U)
#define CSI_ERR1_CRCDTERR_Msk (0x3FUL << CSI_ERR1_CRCDTERR_Pos) /*!< 0x0000003F */
#define CSI_ERR1_CRCDTERR CSI_ERR1_CRCDTERR_Msk /*!< Data type having a CRC error */
#define CSI_ERR1_CRCVCERR_Pos (6U)
#define CSI_ERR1_CRCVCERR_Msk (0x3UL << CSI_ERR1_CRCVCERR_Pos) /*!< 0x000000C0 */
#define CSI_ERR1_CRCVCERR CSI_ERR1_CRCVCERR_Msk /*!< Virtual channel having a CRC error */
#define CSI_ERR1_CECCDTERR_Pos (8U)
#define CSI_ERR1_CECCDTERR_Msk (0x3FUL << CSI_ERR1_CECCDTERR_Pos) /*!< 0x00003F00 */
#define CSI_ERR1_CECCDTERR CSI_ERR1_CECCDTERR_Msk /*!< Data type having a corrected ECC error */
#define CSI_ERR1_CECCVCERR_Pos (14U)
#define CSI_ERR1_CECCVCERR_Msk (0x3UL << CSI_ERR1_CECCVCERR_Pos) /*!< 0x0000C000 */
#define CSI_ERR1_CECCVCERR CSI_ERR1_CECCVCERR_Msk /*!< Virtual channel having a corrected ECC error */
#define CSI_ERR1_IDDTERR_Pos (16U)
#define CSI_ERR1_IDDTERR_Msk (0x3FUL << CSI_ERR1_IDDTERR_Pos) /*!< 0x003F0000 */
#define CSI_ERR1_IDDTERR CSI_ERR1_IDDTERR_Msk /*!< Data type in error */
#define CSI_ERR1_IDVCERR_Pos (22U)
#define CSI_ERR1_IDVCERR_Msk (0x3UL << CSI_ERR1_IDVCERR_Pos) /*!< 0x00C00000 */
#define CSI_ERR1_IDVCERR CSI_ERR1_IDVCERR_Msk /*!< Virtual channel having ID error */
/******************* Bit definition for CSI_ERR2 register *******************/
#define CSI_ERR2_SPKTDTERR_Pos (0U)
#define CSI_ERR2_SPKTDTERR_Msk (0x3FUL << CSI_ERR2_SPKTDTERR_Pos) /*!< 0x0000003F */
#define CSI_ERR2_SPKTDTERR CSI_ERR2_SPKTDTERR_Msk /*!< Data type having a short packet error */
#define CSI_ERR2_SPKTVCERR_Pos (6U)
#define CSI_ERR2_SPKTVCERR_Msk (0x3UL << CSI_ERR2_SPKTVCERR_Pos) /*!< 0x000000C0 */
#define CSI_ERR2_SPKTVCERR CSI_ERR2_SPKTVCERR_Msk /*!< Virtual channel having a short packet error */
#define CSI_ERR2_WDVCERR_Pos (16U)
#define CSI_ERR2_WDVCERR_Msk (0x3UL << CSI_ERR2_WDVCERR_Pos) /*!< 0x00030000 */
#define CSI_ERR2_WDVCERR CSI_ERR2_WDVCERR_Msk /*!< Virtual channel having a watchdog error */
#define CSI_ERR2_SYNCVCERR_Pos (18U)
#define CSI_ERR2_SYNCVCERR_Msk (0x3UL << CSI_ERR2_SYNCVCERR_Pos) /*!< 0x000C0000 */
#define CSI_ERR2_SYNCVCERR CSI_ERR2_SYNCVCERR_Msk /*!< Virtual channel having synchronization error */
/******************* Bit definition for CSI_PRCR register *******************/
#define CSI_PRCR_PEN_Pos (1U)
#define CSI_PRCR_PEN_Msk (0x1UL << CSI_PRCR_PEN_Pos) /*!< 0x00000002 */
#define CSI_PRCR_PEN CSI_PRCR_PEN_Msk /*!< When set to 0, this bit places the digital section of the D-PHY in the reset state */
/******************* Bit definition for CSI_PMCR register *******************/
#define CSI_PMCR_FRXMDL0_Pos (0U)
#define CSI_PMCR_FRXMDL0_Msk (0x1UL << CSI_PMCR_FRXMDL0_Pos) /*!< 0x00000001 */
#define CSI_PMCR_FRXMDL0 CSI_PMCR_FRXMDL0_Msk /*!< Force to Rx Mode the Data Lane 0 */
#define CSI_PMCR_FRXMDL1_Pos (1U)
#define CSI_PMCR_FRXMDL1_Msk (0x1UL << CSI_PMCR_FRXMDL1_Pos) /*!< 0x00000002 */
#define CSI_PMCR_FRXMDL1 CSI_PMCR_FRXMDL1_Msk /*!< Force to Rx Mode the Data Lane 1 */
#define CSI_PMCR_FTXSMDL0_Pos (2U)
#define CSI_PMCR_FTXSMDL0_Msk (0x1UL << CSI_PMCR_FTXSMDL0_Pos) /*!< 0x00000004 */
#define CSI_PMCR_FTXSMDL0 CSI_PMCR_FTXSMDL0_Msk /*!< Force to Tx Stop Mode the Data Lane 0 */
#define CSI_PMCR_DTDL_Pos (4U)
#define CSI_PMCR_DTDL_Msk (0x1UL << CSI_PMCR_DTDL_Pos) /*!< 0x00000010 */
#define CSI_PMCR_DTDL CSI_PMCR_DTDL_Msk /*!< Disable Turn-around Data Lane 0 */
#define CSI_PMCR_RTDL0_Pos (8U)
#define CSI_PMCR_RTDL0_Msk (0x1UL << CSI_PMCR_RTDL0_Pos) /*!< 0x00000100 */
#define CSI_PMCR_RTDL0 CSI_PMCR_RTDL0_Msk /*!< Turn-around Request Data Lane 0 */
#define CSI_PMCR_TUESDL0_Pos (12U)
#define CSI_PMCR_TUESDL0_Msk (0x1UL << CSI_PMCR_TUESDL0_Pos) /*!< 0x00001000 */
#define CSI_PMCR_TUESDL0 CSI_PMCR_TUESDL0_Msk /*!< Tx ULP Escape-mode Data Lane 0 */
#define CSI_PMCR_TUEXDL0_Pos (16U)
#define CSI_PMCR_TUEXDL0_Msk (0x1UL << CSI_PMCR_TUEXDL0_Pos) /*!< 0x00010000 */
#define CSI_PMCR_TUEXDL0 CSI_PMCR_TUEXDL0_Msk /*!< Tx ULP Exit-sequence Data Lane 0 */
/******************* Bit definition for CSI_PFCR register *******************/
#define CSI_PFCR_CCFR_Pos (0U)
#define CSI_PFCR_CCFR_Msk (0x3FUL << CSI_PFCR_CCFR_Pos) /*!< 0x0000003F */
#define CSI_PFCR_CCFR CSI_PFCR_CCFR_Msk /*!< Configuration Clock Frequency Range selection */
#define CSI_PFCR_HSFR_Pos (8U)
#define CSI_PFCR_HSFR_Msk (0x7FUL << CSI_PFCR_HSFR_Pos) /*!< 0x00007F00 */
#define CSI_PFCR_HSFR CSI_PFCR_HSFR_Msk /*!< PHY-high-speed Frequency Range selection */
#define CSI_PFCR_DLD_Pos (16U)
#define CSI_PFCR_DLD_Msk (0x1UL << CSI_PFCR_DLD_Pos) /*!< 0x00010000 */
#define CSI_PFCR_DLD CSI_PFCR_DLD_Msk /*!< Data Lane Direction of lane0 */
/****************** Bit definition for CSI_PTCR0 register *******************/
#define CSI_PTCR0_TCKEN_Pos (0U)
#define CSI_PTCR0_TCKEN_Msk (0x1UL << CSI_PTCR0_TCKEN_Pos) /*!< 0x00000001 */
#define CSI_PTCR0_TCKEN CSI_PTCR0_TCKEN_Msk /*!< Test-interface Clock Enable for the TDI bus into the PHY */
#define CSI_PTCR0_TRSEN_Pos (1U)
#define CSI_PTCR0_TRSEN_Msk (0x1UL << CSI_PTCR0_TRSEN_Pos) /*!< 0x00000002 */
#define CSI_PTCR0_TRSEN CSI_PTCR0_TRSEN_Msk /*!< Test-interface Reset Enable for the TDI bus into the PHY */
/****************** Bit definition for CSI_PTCR1 register *******************/
#define CSI_PTCR1_TDI_Pos (0U)
#define CSI_PTCR1_TDI_Msk (0xFFUL << CSI_PTCR1_TDI_Pos) /*!< 0x000000FF */
#define CSI_PTCR1_TDI CSI_PTCR1_TDI_Msk /*!< Test-interface Data In */
#define CSI_PTCR1_TWM_Pos (16U)
#define CSI_PTCR1_TWM_Msk (0x1UL << CSI_PTCR1_TWM_Pos) /*!< 0x00010000 */
#define CSI_PTCR1_TWM CSI_PTCR1_TWM_Msk /*!< Test-interface Write Mode selector */
/******************* Bit definition for CSI_PTSR register *******************/
#define CSI_PTSR_TDO_Pos (0U)
#define CSI_PTSR_TDO_Msk (0xFFUL << CSI_PTSR_TDO_Pos) /*!< 0x000000FF */
#define CSI_PTSR_TDO CSI_PTSR_TDO_Msk /*!< CSI PHY test interface data output bus for read-back and internal probing functionalities */
/*********************************************************************************/
/* */
/* DBGMCU */
/* */
/*********************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register ****************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device ID */
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< Revision ID */
/******************** Bit definition for DBGMCU_CR register ********************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Allow debug in Sleep mode */
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Allow debug in Stop mode */
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Allow debug in Standby mode */
#define DBGMCU_CR_DBGCLKEN_Pos (20U)
#define DBGMCU_CR_DBGCLKEN_Msk (0x1UL << DBGMCU_CR_DBGCLKEN_Pos) /*!< 0x00100000 */
#define DBGMCU_CR_DBGCLKEN DBGMCU_CR_DBGCLKEN_Msk /*!< Debug clock enable through software */
#define DBGMCU_CR_TRACECLKEN_Pos (21U)
#define DBGMCU_CR_TRACECLKEN_Msk (0x1UL << DBGMCU_CR_TRACECLKEN_Pos) /*!< 0x00200000 */
#define DBGMCU_CR_TRACECLKEN DBGMCU_CR_TRACECLKEN_Msk /*!< TPIU export clock enable through software */
#define DBGMCU_CR_DBTRGOEN_Pos (28U)
#define DBGMCU_CR_DBTRGOEN_Msk (0x1UL << DBGMCU_CR_DBTRGOEN_Pos) /*!< 0x10000000 */
#define DBGMCU_CR_DBTRGOEN DBGMCU_CR_DBTRGOEN_Msk /*!< DBTRGIO connection control */
#define DBGMCU_CR_HLT_TSGEN_EN_Pos (31U)
#define DBGMCU_CR_HLT_TSGEN_EN_Msk (0x1UL << DBGMCU_CR_HLT_TSGEN_EN_Pos) /*!< 0x80000000 */
#define DBGMCU_CR_HLT_TSGEN_EN DBGMCU_CR_HLT_TSGEN_EN_Msk /*!< TSGEN halt enable */
/******************** Bit definition for DBGMCU_APB1LFZ1 register ***************/
#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_APB1LFZ1_DBG_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP_Msk /*!< TIM2 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_APB1LFZ1_DBG_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP_Msk /*!< TIM3 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_APB1LFZ1_DBG_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP_Msk /*!< TIM4 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos (3U)
#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_APB1LFZ1_DBG_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP_Msk /*!< TIM5 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB1LFZ1_DBG_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP_Msk /*!< TIM6 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
#define DBGMCU_APB1LFZ1_DBG_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP_Msk /*!< TIM7 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos (6U)
#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
#define DBGMCU_APB1LFZ1_DBG_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP_Msk /*!< TIM12 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos (7U)
#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
#define DBGMCU_APB1LFZ1_DBG_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP_Msk /*!< TIM13 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos (8U)
#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
#define DBGMCU_APB1LFZ1_DBG_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP_Msk /*!< TIM14 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos (9U)
#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */
#define DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP_Msk /*!< LPTIM1 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos (11U)
#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Pos) /*!< 0x00000800 */
#define DBGMCU_APB1LFZ1_DBG_WWDG1_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP_Msk /*!< WWDG1 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos (12U)
#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Pos) /*!< 0x00001000 */
#define DBGMCU_APB1LFZ1_DBG_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP_Msk /*!< TIM10 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos (13U)
#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Pos) /*!< 0x00002000 */
#define DBGMCU_APB1LFZ1_DBG_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP_Msk /*!< TIM11 stop in debug */
#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */
#define DBGMCU_APB1LFZ1_DBG_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout stop in debug */
#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */
#define DBGMCU_APB1LFZ1_DBG_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout stop in debug */
#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos (23U)
#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */
#define DBGMCU_APB1LFZ1_DBG_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout stop in debug */
#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos (24U)
#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Pos) /*!< 0x01000000 */
#define DBGMCU_APB1LFZ1_DBG_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP_Msk /*!< I3C1 SMBUS timeout stop in debug */
#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos (25U)
#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Pos) /*!< 0x00008000 */
#define DBGMCU_APB1LFZ1_DBG_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP_Msk /*!< I3C2 SMBUS timeout stop in debug */
/******************** Bit definition for DBGMCU_APB1HFZ1 register ***************/
#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos (8U)
#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Pos) /*!< 0x00000100 */
#define DBGMCU_APB1HFZ1_DBG_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP_Msk /*!< FDCAN stop in debug */
/******************** Bit definition for DBGMCU_APB2FZ1 register ***************/
#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos (0U)
#define DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_APB2FZ1_DBG_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP_Msk /*!< TIM1 stop in debug */
#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos (1U)
#define DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_APB2FZ1_DBG_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP_Msk /*!< TIM8 stop in debug */
#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos (15U)
#define DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM18_STOP_Pos) /*!< 0x00008000 */
#define DBGMCU_APB2FZ1_DBG_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP_Msk /*!< TIM18 stop in debug */
#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */
#define DBGMCU_APB2FZ1_DBG_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP_Msk /*!< TIM15 stop in debug */
#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
#define DBGMCU_APB2FZ1_DBG_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP_Msk /*!< TIM16 stop in debug */
#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
#define DBGMCU_APB2FZ1_DBG_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP_Msk /*!< TIM17 stop in debug */
#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos (19U)
#define DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM9_STOP_Pos) /*!< 0x00080000 */
#define DBGMCU_APB2FZ1_DBG_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP_Msk /*!< TIM9 stop in debug */
/******************** Bit definition for DBGMCU_APB4FZ1 register ***************/
#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos (8U)
#define DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_STOP_Pos) /*!< 0x00000100 */
#define DBGMCU_APB4FZ1_DBG_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP_Msk /*!< I2C4 stop in debug */
#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos (9U)
#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x00000200 */
#define DBGMCU_APB4FZ1_DBG_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP_Msk /*!< LPTIM2 stop in debug */
#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos (10U)
#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Pos) /*!< 0x00000400 */
#define DBGMCU_APB4FZ1_DBG_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP_Msk /*!< LPTIM3 stop in debug */
#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos (11U)
#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Pos) /*!< 0x00000800 */
#define DBGMCU_APB4FZ1_DBG_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP_Msk /*!< LPTIM4 stop in debug */
#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos (12U)
#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Pos) /*!< 0x00001000 */
#define DBGMCU_APB4FZ1_DBG_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP_Msk /*!< LPTIM5 stop in debug */
#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos (16U)
#define DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_STOP_Pos) /*!< 0x00010000 */
#define DBGMCU_APB4FZ1_DBG_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP_Msk /*!< RTC stop in debug */
#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos (18U)
#define DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00040000 */
#define DBGMCU_APB4FZ1_DBG_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP_Msk /*!< IWDG stop in debug */
/******************** Bit definition for DBGMCU_APB5FZ1 register ***************/
#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos (4U)
#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk (0x1UL << DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_APB5FZ1_DBG_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP_Msk /*!< GFXTIM stop in debug */
/******************** Bit definition for DBGMCU_AHB1FZ1 register ***************/
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos (0U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP_Msk /*!< GPDMA1_CH0 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos (1U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP_Msk /*!< GPDMA1_CH1 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos (2U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP_Msk /*!< GPDMA1_CH2 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos (3U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP_Msk /*!< GPDMA1_CH3 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos (4U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP_Msk /*!< GPDMA1_CH4 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos (5U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP_Msk /*!< GPDMA1_CH5 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos (6U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP_Msk /*!< GPDMA1_CH6 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos (7U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP_Msk /*!< GPDMA1_CH7 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos (8U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP_Msk /*!< GPDMA1_CH8 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos (9U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP_Msk /*!< GPDMA1_CH9 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos (10U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP_Msk /*!< GPDMA1_CH10 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos (11U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP_Msk /*!< GPDMA1_CH11 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos (12U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP_Msk /*!< GPDMA1_CH12 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos (13U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP_Msk /*!< GPDMA1_CH13 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos (14U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP_Msk /*!< GPDMA1_CH14 suspend in debug */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos (15U)
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */
#define DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP_Msk /*!< GPDMA1_CH15 suspend in debug */
/******************** Bit definition for DBGMCU_AHB5FZ1 register ***************/
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos (0U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Pos) /*!< 0x00000001 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP_Msk /*!< HPDMA1_CH0 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos (1U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Pos) /*!< 0x00000002 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP_Msk /*!< HPDMA1_CH1 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos (2U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Pos) /*!< 0x00000004 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP_Msk /*!< HPDMA1_CH2 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos (3U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Pos) /*!< 0x00000008 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP_Msk /*!< HPDMA1_CH3 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos (4U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Pos) /*!< 0x00000010 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP_Msk /*!< HPDMA1_CH4 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos (5U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Pos) /*!< 0x00000020 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP_Msk /*!< HPDMA1_CH5 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos (6U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Pos) /*!< 0x00000040 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP_Msk /*!< HPDMA1_CH6 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos (7U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Pos) /*!< 0x00000080 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP_Msk /*!< HPDMA1_CH7 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos (8U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Pos) /*!< 0x00000100 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP_Msk /*!< HPDMA1_CH8 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos (9U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Pos) /*!< 0x00000200 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP_Msk /*!< HPDMA1_CH9 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos (10U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Pos) /*!< 0x00000400 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP_Msk /*!< HPDMA1_CH10 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos (11U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Pos) /*!< 0x00000800 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP_Msk /*!< HPDMA1_CH11 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos (12U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Pos) /*!< 0x00001000 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP_Msk /*!< HPDMA1_CH12 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos (13U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Pos) /*!< 0x00002000 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP_Msk /*!< HPDMA1_CH13 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos (14U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Pos) /*!< 0x00004000 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP_Msk /*!< HPDMA1_CH14 suspend in debug */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos (15U)
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk (0x1UL << DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Pos) /*!< 0x00008000 */
#define DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP_Msk /*!< HPDMA1_CH15 suspend in debug */
#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos (16U)
#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk (0x1UL << DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Pos) /*!< 0x00010000 */
#define DBGMCU_AHB5FZ1_NPU_DBG_FREEZE DBGMCU_AHB5FZ1_NPU_DBG_FREEZE_Msk /*!< NPU stop in debug mode */
/******************** Bit definition for DBGMCU_SR register ***************/
#define DBGMCU_SR_AP0_PRESENT_Pos (0U)
#define DBGMCU_SR_AP0_PRESENT_Msk (0x1UL << DBGMCU_SR_AP0_PRESENT_Pos) /*!< 0x00000001 */
#define DBGMCU_SR_AP0_PRESENT DBGMCU_SR_AP0_PRESENT_Msk /*!< Access point 0 presence */
#define DBGMCU_SR_AP1_PRESENT_Pos (1U)
#define DBGMCU_SR_AP1_PRESENT_Msk (0x1UL << DBGMCU_SR_AP1_PRESENT_Pos) /*!< 0x00000002 */
#define DBGMCU_SR_AP1_PRESENT DBGMCU_SR_AP1_PRESENT_Msk /*!< Access point 1 presence */
#define DBGMCU_SR_AP0_ENABLE_Pos (16U)
#define DBGMCU_SR_AP0_ENABLE_Msk (0x1UL << DBGMCU_SR_AP0_ENABLE_Pos) /*!< 0x00010000 */
#define DBGMCU_SR_AP0_ENABLE DBGMCU_SR_AP0_ENABLE_Msk /*!< Access point 0 enable */
#define DBGMCU_SR_AP1_ENABLE_Pos (17U)
#define DBGMCU_SR_AP1_ENABLE_Msk (0x1UL << DBGMCU_SR_AP1_ENABLE_Pos) /*!< 0x00020000 */
#define DBGMCU_SR_AP1_ENABLE DBGMCU_SR_AP1_ENABLE_Msk /*!< Access point 1 enable */
/****************** Bit definition for DBGMCU_DBG_AUTH_HOST register **********************/
#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos (0U)
#define DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_HOST_MESSAGE_Pos) /*!< 0xFFFFFFFF */
#define DBGMCU_DBG_AUTH_HOST_MESSAGE DBGMCU_DBG_AUTH_HOST_MESSAGE_Msk /*!< Message[31:0] */
/****************** Bit definition for DBGMCU_DBG_AUTH_DEV register ***********/
#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos (0U)
#define DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk (0xFFFFFFFFUL << DBGMCU_DBG_AUTH_DEV_MESSAGE_Pos) /*!< 0xFFFFFFFF */
#define DBGMCU_DBG_AUTH_DEV_MESSAGE DBGMCU_DBG_AUTH_DEV_MESSAGE_Msk /*!< Message[31:0] */
/******************** Bit definition for DBGMCU_DBG_AUTH_ACK register ***************/
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos (0U)
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_HOST_ACK_Pos) /*!< 0x00000001 */
#define DBGMCU_DBG_AUTH_ACK_HOST_ACK DBGMCU_DBG_AUTH_ACK_HOST_ACK_Msk /*!< Access status to DBG_AUTH_HOST register */
#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos (1U)
#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk (0x1UL << DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Pos) /*!< 0x00000002 */
#define DBGMCU_DBG_AUTH_ACK_DEVICE_ACK DBGMCU_DBG_AUTH_ACK_DEVICE_ACK_Msk /*!< Access status to DBG_AUTH_DEV register */
/******************************************************************************/
/* */
/* DCMI */
/* */
/******************************************************************************/
/******************** Bits definition for DCMI_CR register ******************/
#define DCMI_CR_CAPTURE_Pos (0U)
#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
#define DCMI_CR_CM_Pos (1U)
#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
#define DCMI_CR_CM DCMI_CR_CM_Msk
#define DCMI_CR_CROP_Pos (2U)
#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
#define DCMI_CR_CROP DCMI_CR_CROP_Msk
#define DCMI_CR_JPEG_Pos (3U)
#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
#define DCMI_CR_ESS_Pos (4U)
#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
#define DCMI_CR_ESS DCMI_CR_ESS_Msk
#define DCMI_CR_PCKPOL_Pos (5U)
#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
#define DCMI_CR_HSPOL_Pos (6U)
#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
#define DCMI_CR_VSPOL_Pos (7U)
#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
#define DCMI_CR_FCRC_Pos (8U)
#define DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) /*!< 0x00000300 */
#define DCMI_CR_FCRC DCMI_CR_FCRC_Msk /*!< DCMI Frame capture rate control FCRC[1:0] */
#define DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) /*!< 0x00000100 */
#define DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) /*!< 0x00000200 */
#define DCMI_CR_EDM_Pos (10U)
#define DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) /*!< 0x00000C00 */
#define DCMI_CR_EDM DCMI_CR_EDM_Msk /*!< DCMI Extended data mode EDM[1:0] */
#define DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) /*!< 0x00000400 */
#define DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) /*!< 0x00000800 */
#define DCMI_CR_ENABLE_Pos (14U)
#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
#define DCMI_CR_BSM_Pos (16U)
#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
#define DCMI_CR_BSM DCMI_CR_BSM_Msk
#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
#define DCMI_CR_OEBS_Pos (18U)
#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
#define DCMI_CR_LSM_Pos (19U)
#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
#define DCMI_CR_LSM DCMI_CR_LSM_Msk
#define DCMI_CR_OELS_Pos (20U)
#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
#define DCMI_CR_OELS DCMI_CR_OELS_Msk
#define DCMI_CR_PSDM_Pos (31U)
#define DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) /*!< 0x00000000 */
#define DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/
/******************** Bits definition for DCMI_SR register ******************/
#define DCMI_SR_HSYNC_Pos (0U)
#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
#define DCMI_SR_VSYNC_Pos (1U)
#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
#define DCMI_SR_FNE_Pos (2U)
#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
#define DCMI_SR_FNE DCMI_SR_FNE_Msk
/******************** Bits definition for DCMI_RIS register ****************/
#define DCMI_RIS_FRAME_RIS_Pos (0U)
#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
#define DCMI_RIS_OVR_RIS_Pos (1U)
#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
#define DCMI_RIS_ERR_RIS_Pos (2U)
#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
#define DCMI_RIS_VSYNC_RIS_Pos (3U)
#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
#define DCMI_RIS_LINE_RIS_Pos (4U)
#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
/******************** Bits definition for DCMI_IER register *****************/
#define DCMI_IER_FRAME_IE_Pos (0U)
#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
#define DCMI_IER_OVR_IE_Pos (1U)
#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
#define DCMI_IER_ERR_IE_Pos (2U)
#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
#define DCMI_IER_VSYNC_IE_Pos (3U)
#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
#define DCMI_IER_LINE_IE_Pos (4U)
#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
/******************** Bits definition for DCMI_MIS register *****************/
#define DCMI_MIS_FRAME_MIS_Pos (0U)
#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
#define DCMI_MIS_OVR_MIS_Pos (1U)
#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
#define DCMI_MIS_ERR_MIS_Pos (2U)
#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
#define DCMI_MIS_VSYNC_MIS_Pos (3U)
#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
#define DCMI_MIS_LINE_MIS_Pos (4U)
#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
/******************** Bits definition for DCMI_ICR register *****************/
#define DCMI_ICR_FRAME_ISC_Pos (0U)
#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
#define DCMI_ICR_OVR_ISC_Pos (1U)
#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
#define DCMI_ICR_ERR_ISC_Pos (2U)
#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
#define DCMI_ICR_VSYNC_ISC_Pos (3U)
#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
#define DCMI_ICR_LINE_ISC_Pos (4U)
#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
/******************** Bits definition for DCMI_ESCR register ******************/
#define DCMI_ESCR_FSC_Pos (0U)
#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
#define DCMI_ESCR_LSC_Pos (8U)
#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
#define DCMI_ESCR_LEC_Pos (16U)
#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
#define DCMI_ESCR_FEC_Pos (24U)
#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
/******************** Bits definition for DCMI_ESUR register ******************/
#define DCMI_ESUR_FSU_Pos (0U)
#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
#define DCMI_ESUR_LSU_Pos (8U)
#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
#define DCMI_ESUR_LEU_Pos (16U)
#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
#define DCMI_ESUR_FEU_Pos (24U)
#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
/******************** Bits definition for DCMI_CWSTRT register ******************/
#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
#define DCMI_CWSTRT_VST_Pos (16U)
#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
/******************** Bits definition for DCMI_CWSIZE register ******************/
#define DCMI_CWSIZE_CAPCNT_Pos (0U)
#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
#define DCMI_CWSIZE_VLINE_Pos (16U)
#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
/******************** Bits definition for DCMI_DR register ******************/
#define DCMI_DR_BYTE0_Pos (0U)
#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
#define DCMI_DR_BYTE1_Pos (8U)
#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
#define DCMI_DR_BYTE2_Pos (16U)
#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
#define DCMI_DR_BYTE3_Pos (24U)
#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
/******************************************************************************/
/* */
/* DCMIPP */
/* */
/******************************************************************************/
/***************** Bit definition for DCMIPP_IPGR1 register *****************/
#define DCMIPP_IPGR1_MEMORYPAGE_Pos (0U)
#define DCMIPP_IPGR1_MEMORYPAGE_Msk (0x7UL << DCMIPP_IPGR1_MEMORYPAGE_Pos) /*!< 0x00000007 */
#define DCMIPP_IPGR1_MEMORYPAGE DCMIPP_IPGR1_MEMORYPAGE_Msk /*!< Memory page size, as power of 2 of 64-byte units: */
#define DCMIPP_IPGR1_QOS_MODE_Pos (24U)
#define DCMIPP_IPGR1_QOS_MODE_Msk (0x1UL << DCMIPP_IPGR1_QOS_MODE_Pos) /*!< 0x01000000 */
#define DCMIPP_IPGR1_QOS_MODE DCMIPP_IPGR1_QOS_MODE_Msk /*!< Quality of service */
/***************** Bit definition for DCMIPP_IPGR2 register *****************/
#define DCMIPP_IPGR2_PSTART_Pos (0U)
#define DCMIPP_IPGR2_PSTART_Msk (0x1UL << DCMIPP_IPGR2_PSTART_Pos) /*!< 0x00000001 */
#define DCMIPP_IPGR2_PSTART DCMIPP_IPGR2_PSTART_Msk /*!< Request to lock the IP-Plug, to allow reconfiguration */
/***************** Bit definition for DCMIPP_IPGR3 register *****************/
#define DCMIPP_IPGR3_IDLE_Pos (0U)
#define DCMIPP_IPGR3_IDLE_Msk (0x1UL << DCMIPP_IPGR3_IDLE_Pos) /*!< 0x00000001 */
#define DCMIPP_IPGR3_IDLE DCMIPP_IPGR3_IDLE_Msk /*!< Status of IP-Plug */
/***************** Bit definition for DCMIPP_IPGR8 register *****************/
#define DCMIPP_IPGR8_DID_Pos (0U)
#define DCMIPP_IPGR8_DID_Msk (0x3FUL << DCMIPP_IPGR8_DID_Pos) /*!< 0x0000003F */
#define DCMIPP_IPGR8_DID DCMIPP_IPGR8_DID_Msk /*!< Division identifier (0x14) */
#define DCMIPP_IPGR8_REVID_Pos (8U)
#define DCMIPP_IPGR8_REVID_Msk (0x1FUL << DCMIPP_IPGR8_REVID_Pos) /*!< 0x00001F00 */
#define DCMIPP_IPGR8_REVID DCMIPP_IPGR8_REVID_Msk /*!< Revision identifier (0x03) */
#define DCMIPP_IPGR8_ARCHIID_Pos (16U)
#define DCMIPP_IPGR8_ARCHIID_Msk (0x1FUL << DCMIPP_IPGR8_ARCHIID_Pos) /*!< 0x001F0000 */
#define DCMIPP_IPGR8_ARCHIID DCMIPP_IPGR8_ARCHIID_Msk /*!< Architecture identifier (0x04) */
#define DCMIPP_IPGR8_IPPID_Pos (24U)
#define DCMIPP_IPGR8_IPPID_Msk (0xFFUL << DCMIPP_IPGR8_IPPID_Pos) /*!< 0xFF000000 */
#define DCMIPP_IPGR8_IPPID DCMIPP_IPGR8_IPPID_Msk /*!< IP identifier (0xAA) */
/**************** Bit definition for DCMIPP_IPC1R1 register *****************/
#define DCMIPP_IPC1R1_TRAFFIC_Pos (0U)
#define DCMIPP_IPC1R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC1R1_TRAFFIC_Pos) /*!< 0x00000007 */
#define DCMIPP_IPC1R1_TRAFFIC DCMIPP_IPC1R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */
#define DCMIPP_IPC1R1_OTR_Pos (8U)
#define DCMIPP_IPC1R1_OTR_Msk (0xFUL << DCMIPP_IPC1R1_OTR_Pos) /*!< 0x00000F00 */
#define DCMIPP_IPC1R1_OTR DCMIPP_IPC1R1_OTR_Msk /*!< max outstanding transactions: */
/**************** Bit definition for DCMIPP_IPC1R2 register *****************/
#define DCMIPP_IPC1R2_WLRU_Pos (16U)
#define DCMIPP_IPC1R2_WLRU_Msk (0xFUL << DCMIPP_IPC1R2_WLRU_Pos) /*!< 0x000F0000 */
#define DCMIPP_IPC1R2_WLRU DCMIPP_IPC1R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */
/**************** Bit definition for DCMIPP_IPC1R3 register *****************/
#define DCMIPP_IPC1R3_DPREGSTART_Pos (0U)
#define DCMIPP_IPC1R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGSTART_Pos) /*!< 0x000003FF */
#define DCMIPP_IPC1R3_DPREGSTART DCMIPP_IPC1R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
#define DCMIPP_IPC1R3_DPREGEND_Pos (16U)
#define DCMIPP_IPC1R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC1R3_DPREGEND_Pos) /*!< 0x03FF0000 */
#define DCMIPP_IPC1R3_DPREGEND DCMIPP_IPC1R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */
/**************** Bit definition for DCMIPP_IPC2R1 register *****************/
#define DCMIPP_IPC2R1_TRAFFIC_Pos (0U)
#define DCMIPP_IPC2R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC2R1_TRAFFIC_Pos) /*!< 0x00000007 */
#define DCMIPP_IPC2R1_TRAFFIC DCMIPP_IPC2R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */
#define DCMIPP_IPC2R1_OTR_Pos (8U)
#define DCMIPP_IPC2R1_OTR_Msk (0xFUL << DCMIPP_IPC2R1_OTR_Pos) /*!< 0x00000F00 */
#define DCMIPP_IPC2R1_OTR DCMIPP_IPC2R1_OTR_Msk /*!< max outstanding transactions: */
/**************** Bit definition for DCMIPP_IPC2R2 register *****************/
#define DCMIPP_IPC2R2_WLRU_Pos (16U)
#define DCMIPP_IPC2R2_WLRU_Msk (0xFUL << DCMIPP_IPC2R2_WLRU_Pos) /*!< 0x000F0000 */
#define DCMIPP_IPC2R2_WLRU DCMIPP_IPC2R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */
/**************** Bit definition for DCMIPP_IPC2R3 register *****************/
#define DCMIPP_IPC2R3_DPREGSTART_Pos (0U)
#define DCMIPP_IPC2R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGSTART_Pos) /*!< 0x000003FF */
#define DCMIPP_IPC2R3_DPREGSTART DCMIPP_IPC2R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
#define DCMIPP_IPC2R3_DPREGEND_Pos (16U)
#define DCMIPP_IPC2R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC2R3_DPREGEND_Pos) /*!< 0x03FF0000 */
#define DCMIPP_IPC2R3_DPREGEND DCMIPP_IPC2R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */
/**************** Bit definition for DCMIPP_IPC3R1 register *****************/
#define DCMIPP_IPC3R1_TRAFFIC_Pos (0U)
#define DCMIPP_IPC3R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC3R1_TRAFFIC_Pos) /*!< 0x00000007 */
#define DCMIPP_IPC3R1_TRAFFIC DCMIPP_IPC3R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */
#define DCMIPP_IPC3R1_OTR_Pos (8U)
#define DCMIPP_IPC3R1_OTR_Msk (0xFUL << DCMIPP_IPC3R1_OTR_Pos) /*!< 0x00000F00 */
#define DCMIPP_IPC3R1_OTR DCMIPP_IPC3R1_OTR_Msk /*!< max outstanding transactions: */
/**************** Bit definition for DCMIPP_IPC3R2 register *****************/
#define DCMIPP_IPC3R2_WLRU_Pos (16U)
#define DCMIPP_IPC3R2_WLRU_Msk (0xFUL << DCMIPP_IPC3R2_WLRU_Pos) /*!< 0x000F0000 */
#define DCMIPP_IPC3R2_WLRU DCMIPP_IPC3R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */
/**************** Bit definition for DCMIPP_IPC3R3 register *****************/
#define DCMIPP_IPC3R3_DPREGSTART_Pos (0U)
#define DCMIPP_IPC3R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGSTART_Pos) /*!< 0x000003FF */
#define DCMIPP_IPC3R3_DPREGSTART DCMIPP_IPC3R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
#define DCMIPP_IPC3R3_DPREGEND_Pos (16U)
#define DCMIPP_IPC3R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC3R3_DPREGEND_Pos) /*!< 0x03FF0000 */
#define DCMIPP_IPC3R3_DPREGEND DCMIPP_IPC3R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */
/**************** Bit definition for DCMIPP_IPC4R1 register *****************/
#define DCMIPP_IPC4R1_TRAFFIC_Pos (0U)
#define DCMIPP_IPC4R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC4R1_TRAFFIC_Pos) /*!< 0x00000007 */
#define DCMIPP_IPC4R1_TRAFFIC DCMIPP_IPC4R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */
#define DCMIPP_IPC4R1_OTR_Pos (8U)
#define DCMIPP_IPC4R1_OTR_Msk (0xFUL << DCMIPP_IPC4R1_OTR_Pos) /*!< 0x00000F00 */
#define DCMIPP_IPC4R1_OTR DCMIPP_IPC4R1_OTR_Msk /*!< max outstanding transactions: */
/**************** Bit definition for DCMIPP_IPC4R2 register *****************/
#define DCMIPP_IPC4R2_WLRU_Pos (16U)
#define DCMIPP_IPC4R2_WLRU_Msk (0xFUL << DCMIPP_IPC4R2_WLRU_Pos) /*!< 0x000F0000 */
#define DCMIPP_IPC4R2_WLRU DCMIPP_IPC4R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */
/**************** Bit definition for DCMIPP_IPC4R3 register *****************/
#define DCMIPP_IPC4R3_DPREGSTART_Pos (0U)
#define DCMIPP_IPC4R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGSTART_Pos) /*!< 0x000003FF */
#define DCMIPP_IPC4R3_DPREGSTART DCMIPP_IPC4R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
#define DCMIPP_IPC4R3_DPREGEND_Pos (16U)
#define DCMIPP_IPC4R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC4R3_DPREGEND_Pos) /*!< 0x03FF0000 */
#define DCMIPP_IPC4R3_DPREGEND DCMIPP_IPC4R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */
/**************** Bit definition for DCMIPP_IPC5R1 register *****************/
#define DCMIPP_IPC5R1_TRAFFIC_Pos (0U)
#define DCMIPP_IPC5R1_TRAFFIC_Msk (0x7UL << DCMIPP_IPC5R1_TRAFFIC_Pos) /*!< 0x00000007 */
#define DCMIPP_IPC5R1_TRAFFIC DCMIPP_IPC5R1_TRAFFIC_Msk /*!< Burst size as power of 2 of 8 bytes units */
#define DCMIPP_IPC5R1_OTR_Pos (8U)
#define DCMIPP_IPC5R1_OTR_Msk (0xFUL << DCMIPP_IPC5R1_OTR_Pos) /*!< 0x00000F00 */
#define DCMIPP_IPC5R1_OTR DCMIPP_IPC5R1_OTR_Msk /*!< max outstanding transactions: */
/**************** Bit definition for DCMIPP_IPC5R2 register *****************/
#define DCMIPP_IPC5R2_WLRU_Pos (16U)
#define DCMIPP_IPC5R2_WLRU_Msk (0xFUL << DCMIPP_IPC5R2_WLRU_Pos) /*!< 0x000F0000 */
#define DCMIPP_IPC5R2_WLRU DCMIPP_IPC5R2_WLRU_Msk /*!< Ratio for WLRU[3:0] arbitration: */
/**************** Bit definition for DCMIPP_IPC5R3 register *****************/
#define DCMIPP_IPC5R3_DPREGSTART_Pos (0U)
#define DCMIPP_IPC5R3_DPREGSTART_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGSTART_Pos) /*!< 0x000003FF */
#define DCMIPP_IPC5R3_DPREGSTART DCMIPP_IPC5R3_DPREGSTART_Msk /*!< Start word (AXI width = 64 bits) of the FIFO of this client */
#define DCMIPP_IPC5R3_DPREGEND_Pos (16U)
#define DCMIPP_IPC5R3_DPREGEND_Msk (0x3FFUL << DCMIPP_IPC5R3_DPREGEND_Pos) /*!< 0x03FF0000 */
#define DCMIPP_IPC5R3_DPREGEND DCMIPP_IPC5R3_DPREGEND_Msk /*!< End word (AXI width = 64 bits) of the FIFO of this client */
/*************** Bit definition for DCMIPP_PRHWCFGR register ****************/
/***************** Bit definition for DCMIPP_PRCR register ******************/
#define DCMIPP_PRCR_ESS_Pos (4U)
#define DCMIPP_PRCR_ESS_Msk (0x1UL << DCMIPP_PRCR_ESS_Pos) /*!< 0x00000010 */
#define DCMIPP_PRCR_ESS DCMIPP_PRCR_ESS_Msk /*!< Embedded synchronization select */
#define DCMIPP_PRCR_PCKPOL_Pos (5U)
#define DCMIPP_PRCR_PCKPOL_Msk (0x1UL << DCMIPP_PRCR_PCKPOL_Pos) /*!< 0x00000020 */
#define DCMIPP_PRCR_PCKPOL DCMIPP_PRCR_PCKPOL_Msk /*!< Pixel clock polarity */
#define DCMIPP_PRCR_HSPOL_Pos (6U)
#define DCMIPP_PRCR_HSPOL_Msk (0x1UL << DCMIPP_PRCR_HSPOL_Pos) /*!< 0x00000040 */
#define DCMIPP_PRCR_HSPOL DCMIPP_PRCR_HSPOL_Msk /*!< Horizontal synchronization polarity */
#define DCMIPP_PRCR_VSPOL_Pos (7U)
#define DCMIPP_PRCR_VSPOL_Msk (0x1UL << DCMIPP_PRCR_VSPOL_Pos) /*!< 0x00000080 */
#define DCMIPP_PRCR_VSPOL DCMIPP_PRCR_VSPOL_Msk /*!< Vertical synchronization polarity */
#define DCMIPP_PRCR_EDM_Pos (10U)
#define DCMIPP_PRCR_EDM_Msk (0x7UL << DCMIPP_PRCR_EDM_Pos) /*!< 0x00001C00 */
#define DCMIPP_PRCR_EDM DCMIPP_PRCR_EDM_Msk /*!< Extended data mode */
#define DCMIPP_PRCR_ENABLE_Pos (14U)
#define DCMIPP_PRCR_ENABLE_Msk (0x1UL << DCMIPP_PRCR_ENABLE_Pos) /*!< 0x00004000 */
#define DCMIPP_PRCR_ENABLE DCMIPP_PRCR_ENABLE_Msk /*!< Parallel interface enable */
#define DCMIPP_PRCR_FORMAT_Pos (16U)
#define DCMIPP_PRCR_FORMAT_Msk (0xFFUL << DCMIPP_PRCR_FORMAT_Pos) /*!< 0x00FF0000 */
#define DCMIPP_PRCR_FORMAT DCMIPP_PRCR_FORMAT_Msk /*!< Other values: Data is captured and output as-is through the data/dump pipeline only (e */
#define DCMIPP_PRCR_SWAPCYCLES_Pos (25U)
#define DCMIPP_PRCR_SWAPCYCLES_Msk (0x1UL << DCMIPP_PRCR_SWAPCYCLES_Pos) /*!< 0x02000000 */
#define DCMIPP_PRCR_SWAPCYCLES DCMIPP_PRCR_SWAPCYCLES_Msk /*!< Swap data from cycle 0 vs */
#define DCMIPP_PRCR_SWAPBITS_Pos (26U)
#define DCMIPP_PRCR_SWAPBITS_Msk (0x1UL << DCMIPP_PRCR_SWAPBITS_Pos) /*!< 0x04000000 */
#define DCMIPP_PRCR_SWAPBITS DCMIPP_PRCR_SWAPBITS_Msk /*!< Swap LSB vs */
/**************** Bit definition for DCMIPP_PRESCR register *****************/
#define DCMIPP_PRESCR_FSC_Pos (0U)
#define DCMIPP_PRESCR_FSC_Msk (0xFFUL << DCMIPP_PRESCR_FSC_Pos) /*!< 0x000000FF */
#define DCMIPP_PRESCR_FSC DCMIPP_PRESCR_FSC_Msk /*!< Frame start delimiter code */
#define DCMIPP_PRESCR_LSC_Pos (8U)
#define DCMIPP_PRESCR_LSC_Msk (0xFFUL << DCMIPP_PRESCR_LSC_Pos) /*!< 0x0000FF00 */
#define DCMIPP_PRESCR_LSC DCMIPP_PRESCR_LSC_Msk /*!< Line start delimiter code */
#define DCMIPP_PRESCR_LEC_Pos (16U)
#define DCMIPP_PRESCR_LEC_Msk (0xFFUL << DCMIPP_PRESCR_LEC_Pos) /*!< 0x00FF0000 */
#define DCMIPP_PRESCR_LEC DCMIPP_PRESCR_LEC_Msk /*!< Line end delimiter code */
#define DCMIPP_PRESCR_FEC_Pos (24U)
#define DCMIPP_PRESCR_FEC_Msk (0xFFUL << DCMIPP_PRESCR_FEC_Pos) /*!< 0xFF000000 */
#define DCMIPP_PRESCR_FEC DCMIPP_PRESCR_FEC_Msk /*!< Frame end delimiter code */
/**************** Bit definition for DCMIPP_PRESUR register *****************/
#define DCMIPP_PRESUR_FSU_Pos (0U)
#define DCMIPP_PRESUR_FSU_Msk (0xFFUL << DCMIPP_PRESUR_FSU_Pos) /*!< 0x000000FF */
#define DCMIPP_PRESUR_FSU DCMIPP_PRESUR_FSU_Msk /*!< Frame start delimiter unmask */
#define DCMIPP_PRESUR_LSU_Pos (8U)
#define DCMIPP_PRESUR_LSU_Msk (0xFFUL << DCMIPP_PRESUR_LSU_Pos) /*!< 0x0000FF00 */
#define DCMIPP_PRESUR_LSU DCMIPP_PRESUR_LSU_Msk /*!< Line start delimiter unmask */
#define DCMIPP_PRESUR_LEU_Pos (16U)
#define DCMIPP_PRESUR_LEU_Msk (0xFFUL << DCMIPP_PRESUR_LEU_Pos) /*!< 0x00FF0000 */
#define DCMIPP_PRESUR_LEU DCMIPP_PRESUR_LEU_Msk /*!< Line end delimiter unmask */
#define DCMIPP_PRESUR_FEU_Pos (24U)
#define DCMIPP_PRESUR_FEU_Msk (0xFFUL << DCMIPP_PRESUR_FEU_Pos) /*!< 0xFF000000 */
#define DCMIPP_PRESUR_FEU DCMIPP_PRESUR_FEU_Msk /*!< Frame end delimiter unmask */
/***************** Bit definition for DCMIPP_PRIER register *****************/
#define DCMIPP_PRIER_ERRIE_Pos (6U)
#define DCMIPP_PRIER_ERRIE_Msk (0x1UL << DCMIPP_PRIER_ERRIE_Pos) /*!< 0x00000040 */
#define DCMIPP_PRIER_ERRIE DCMIPP_PRIER_ERRIE_Msk /*!< Synchronization error interrupt enable */
/***************** Bit definition for DCMIPP_PRSR register ******************/
#define DCMIPP_PRSR_ERRF_Pos (6U)
#define DCMIPP_PRSR_ERRF_Msk (0x1UL << DCMIPP_PRSR_ERRF_Pos) /*!< 0x00000040 */
#define DCMIPP_PRSR_ERRF DCMIPP_PRSR_ERRF_Msk /*!< Synchronization error raw interrupt status */
#define DCMIPP_PRSR_HSYNC_Pos (16U)
#define DCMIPP_PRSR_HSYNC_Msk (0x1UL << DCMIPP_PRSR_HSYNC_Pos) /*!< 0x00010000 */
#define DCMIPP_PRSR_HSYNC DCMIPP_PRSR_HSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity if the ENABLE bit is */
#define DCMIPP_PRSR_VSYNC_Pos (17U)
#define DCMIPP_PRSR_VSYNC_Msk (0x1UL << DCMIPP_PRSR_VSYNC_Pos) /*!< 0x00020000 */
#define DCMIPP_PRSR_VSYNC DCMIPP_PRSR_VSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity if the ENABLE bit is */
/***************** Bit definition for DCMIPP_PRFCR register *****************/
#define DCMIPP_PRFCR_CERRF_Pos (6U)
#define DCMIPP_PRFCR_CERRF_Msk (0x1UL << DCMIPP_PRFCR_CERRF_Pos) /*!< 0x00000040 */
#define DCMIPP_PRFCR_CERRF DCMIPP_PRFCR_CERRF_Msk /*!< Synchronization error interrupt status clear */
/***************** Bit definition for DCMIPP_CMCR register ******************/
#define DCMIPP_CMCR_INSEL_Pos (0U)
#define DCMIPP_CMCR_INSEL_Msk (0x1UL << DCMIPP_CMCR_INSEL_Pos) /*!< 0x00000001 */
#define DCMIPP_CMCR_INSEL DCMIPP_CMCR_INSEL_Msk /*!< input selection */
#define DCMIPP_CMCR_PSFC_Pos (1U)
#define DCMIPP_CMCR_PSFC_Msk (0x3UL << DCMIPP_CMCR_PSFC_Pos) /*!< 0x00000006 */
#define DCMIPP_CMCR_PSFC DCMIPP_CMCR_PSFC_Msk /*!< Pipe selection for the frame counter */
#define DCMIPP_CMCR_CFC_Pos (4U)
#define DCMIPP_CMCR_CFC_Msk (0x1UL << DCMIPP_CMCR_CFC_Pos) /*!< 0x00000010 */
#define DCMIPP_CMCR_CFC DCMIPP_CMCR_CFC_Msk /*!< Clear frame counter */
#define DCMIPP_CMCR_SWAPRB_Pos (7U)
#define DCMIPP_CMCR_SWAPRB_Msk (0x1UL << DCMIPP_CMCR_SWAPRB_Pos) /*!< 0x00000080 */
#define DCMIPP_CMCR_SWAPRB DCMIPP_CMCR_SWAPRB_Msk /*!< Swap R/U and B/V */
/**************** Bit definition for DCMIPP_CMFRCR register *****************/
#define DCMIPP_CMFRCR_FRMCNT_Pos (0U)
#define DCMIPP_CMFRCR_FRMCNT_Msk (0xFFFFFFFFUL << DCMIPP_CMFRCR_FRMCNT_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_CMFRCR_FRMCNT DCMIPP_CMFRCR_FRMCNT_Msk /*!< Frame counter, read-only, loops around */
/***************** Bit definition for DCMIPP_CMIER register *****************/
#define DCMIPP_CMIER_ATXERRIE_Pos (5U)
#define DCMIPP_CMIER_ATXERRIE_Msk (0x1UL << DCMIPP_CMIER_ATXERRIE_Pos) /*!< 0x00000020 */
#define DCMIPP_CMIER_ATXERRIE DCMIPP_CMIER_ATXERRIE_Msk /*!< AXI Transfer error interrupt enable for IPPLUG */
#define DCMIPP_CMIER_PRERRIE_Pos (6U)
#define DCMIPP_CMIER_PRERRIE_Msk (0x1UL << DCMIPP_CMIER_PRERRIE_Pos) /*!< 0x00000040 */
#define DCMIPP_CMIER_PRERRIE DCMIPP_CMIER_PRERRIE_Msk /*!< limit interrupt enable for the Parallel Interface */
#define DCMIPP_CMIER_P0LINEIE_Pos (8U)
#define DCMIPP_CMIER_P0LINEIE_Msk (0x1UL << DCMIPP_CMIER_P0LINEIE_Pos) /*!< 0x00000100 */
#define DCMIPP_CMIER_P0LINEIE DCMIPP_CMIER_P0LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0FRAMEIE_Pos (9U)
#define DCMIPP_CMIER_P0FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P0FRAMEIE_Pos) /*!< 0x00000200 */
#define DCMIPP_CMIER_P0FRAMEIE DCMIPP_CMIER_P0FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0VSYNCIE_Pos (10U)
#define DCMIPP_CMIER_P0VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P0VSYNCIE_Pos) /*!< 0x00000400 */
#define DCMIPP_CMIER_P0VSYNCIE DCMIPP_CMIER_P0VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0LIMITIE_Pos (14U)
#define DCMIPP_CMIER_P0LIMITIE_Msk (0x1UL << DCMIPP_CMIER_P0LIMITIE_Pos) /*!< 0x00004000 */
#define DCMIPP_CMIER_P0LIMITIE DCMIPP_CMIER_P0LIMITIE_Msk /*!< limit interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P0OVRIE_Pos (15U)
#define DCMIPP_CMIER_P0OVRIE_Msk (0x1UL << DCMIPP_CMIER_P0OVRIE_Pos) /*!< 0x00008000 */
#define DCMIPP_CMIER_P0OVRIE DCMIPP_CMIER_P0OVRIE_Msk /*!< Overrun interrupt enable for the Pipe0 */
#define DCMIPP_CMIER_P1LINEIE_Pos (16U)
#define DCMIPP_CMIER_P1LINEIE_Msk (0x1UL << DCMIPP_CMIER_P1LINEIE_Pos) /*!< 0x00010000 */
#define DCMIPP_CMIER_P1LINEIE DCMIPP_CMIER_P1LINEIE_Msk /*!< multi-Line Capture complete interrupt status clear for the Pipe1 */
#define DCMIPP_CMIER_P1FRAMEIE_Pos (17U)
#define DCMIPP_CMIER_P1FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P1FRAMEIE_Pos) /*!< 0x00020000 */
#define DCMIPP_CMIER_P1FRAMEIE DCMIPP_CMIER_P1FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe1 */
#define DCMIPP_CMIER_P1VSYNCIE_Pos (18U)
#define DCMIPP_CMIER_P1VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P1VSYNCIE_Pos) /*!< 0x00040000 */
#define DCMIPP_CMIER_P1VSYNCIE DCMIPP_CMIER_P1VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe1 */
#define DCMIPP_CMIER_P1OVRIE_Pos (23U)
#define DCMIPP_CMIER_P1OVRIE_Msk (0x1UL << DCMIPP_CMIER_P1OVRIE_Pos) /*!< 0x00800000 */
#define DCMIPP_CMIER_P1OVRIE DCMIPP_CMIER_P1OVRIE_Msk /*!< Overrun interrupt enable for the Pipe1 */
#define DCMIPP_CMIER_P2LINEIE_Pos (24U)
#define DCMIPP_CMIER_P2LINEIE_Msk (0x1UL << DCMIPP_CMIER_P2LINEIE_Pos) /*!< 0x01000000 */
#define DCMIPP_CMIER_P2LINEIE DCMIPP_CMIER_P2LINEIE_Msk /*!< multi-Line Capture complete interrupt enable for the Pipe2 */
#define DCMIPP_CMIER_P2FRAMEIE_Pos (25U)
#define DCMIPP_CMIER_P2FRAMEIE_Msk (0x1UL << DCMIPP_CMIER_P2FRAMEIE_Pos) /*!< 0x02000000 */
#define DCMIPP_CMIER_P2FRAMEIE DCMIPP_CMIER_P2FRAMEIE_Msk /*!< Frame Capture complete interrupt enable for the Pipe2 */
#define DCMIPP_CMIER_P2VSYNCIE_Pos (26U)
#define DCMIPP_CMIER_P2VSYNCIE_Msk (0x1UL << DCMIPP_CMIER_P2VSYNCIE_Pos) /*!< 0x04000000 */
#define DCMIPP_CMIER_P2VSYNCIE DCMIPP_CMIER_P2VSYNCIE_Msk /*!< Vertical sync interrupt enable for the Pipe2 */
#define DCMIPP_CMIER_P2OVRIE_Pos (31U)
#define DCMIPP_CMIER_P2OVRIE_Msk (0x1UL << DCMIPP_CMIER_P2OVRIE_Pos) /*!< 0x80000000 */
#define DCMIPP_CMIER_P2OVRIE DCMIPP_CMIER_P2OVRIE_Msk /*!< Overrun interrupt status enable for the Pipe2 */
/***************** Bit definition for DCMIPP_CMSR1 register *****************/
#define DCMIPP_CMSR1_PRHSYNC_Pos (0U)
#define DCMIPP_CMSR1_PRHSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRHSYNC_Pos) /*!< 0x00000001 */
#define DCMIPP_CMSR1_PRHSYNC DCMIPP_CMSR1_PRHSYNC_Msk /*!< This bit gives the state of the HSYNC pin with the correct programmed polarity on the parallel inte */
#define DCMIPP_CMSR1_PRVSYNC_Pos (1U)
#define DCMIPP_CMSR1_PRVSYNC_Msk (0x1UL << DCMIPP_CMSR1_PRVSYNC_Pos) /*!< 0x00000002 */
#define DCMIPP_CMSR1_PRVSYNC DCMIPP_CMSR1_PRVSYNC_Msk /*!< This bit gives the state of the VSYNC pin with the correct programmed polarity on the parallel inte */
#define DCMIPP_CMSR1_P0LSTLINE_Pos (8U)
#define DCMIPP_CMSR1_P0LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P0LSTLINE_Pos) /*!< 0x00000100 */
#define DCMIPP_CMSR1_P0LSTLINE DCMIPP_CMSR1_P0LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe0 */
#define DCMIPP_CMSR1_P0LSTFRM_Pos (9U)
#define DCMIPP_CMSR1_P0LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P0LSTFRM_Pos) /*!< 0x00000200 */
#define DCMIPP_CMSR1_P0LSTFRM DCMIPP_CMSR1_P0LSTFRM_Msk /*!< Last frame LSB bit, sampled at Frame capture complete event for Pipe0 */
#define DCMIPP_CMSR1_P0CPTACT_Pos (15U)
#define DCMIPP_CMSR1_P0CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P0CPTACT_Pos) /*!< 0x00008000 */
#define DCMIPP_CMSR1_P0CPTACT DCMIPP_CMSR1_P0CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe0 */
#define DCMIPP_CMSR1_P1LSTLINE_Pos (16U)
#define DCMIPP_CMSR1_P1LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P1LSTLINE_Pos) /*!< 0x00010000 */
#define DCMIPP_CMSR1_P1LSTLINE DCMIPP_CMSR1_P1LSTLINE_Msk /*!< Last Line LSB bit, sampled at Frame capture complete event for Pipe1 */
#define DCMIPP_CMSR1_P1LSTFRM_Pos (17U)
#define DCMIPP_CMSR1_P1LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P1LSTFRM_Pos) /*!< 0x00020000 */
#define DCMIPP_CMSR1_P1LSTFRM DCMIPP_CMSR1_P1LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe1 */
#define DCMIPP_CMSR1_P1CPTACT_Pos (23U)
#define DCMIPP_CMSR1_P1CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P1CPTACT_Pos) /*!< 0x00800000 */
#define DCMIPP_CMSR1_P1CPTACT DCMIPP_CMSR1_P1CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe1 */
#define DCMIPP_CMSR1_P2LSTLINE_Pos (24U)
#define DCMIPP_CMSR1_P2LSTLINE_Msk (0x1UL << DCMIPP_CMSR1_P2LSTLINE_Pos) /*!< 0x01000000 */
#define DCMIPP_CMSR1_P2LSTLINE DCMIPP_CMSR1_P2LSTLINE_Msk /*!< Last line LSB bit, sampled at Frame capture complete event for Pipe2 */
#define DCMIPP_CMSR1_P2LSTFRM_Pos (25U)
#define DCMIPP_CMSR1_P2LSTFRM_Msk (0x1UL << DCMIPP_CMSR1_P2LSTFRM_Pos) /*!< 0x02000000 */
#define DCMIPP_CMSR1_P2LSTFRM DCMIPP_CMSR1_P2LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event for Pipe2 */
#define DCMIPP_CMSR1_P2CPTACT_Pos (31U)
#define DCMIPP_CMSR1_P2CPTACT_Msk (0x1UL << DCMIPP_CMSR1_P2CPTACT_Pos) /*!< 0x80000000 */
#define DCMIPP_CMSR1_P2CPTACT DCMIPP_CMSR1_P2CPTACT_Msk /*!< Active frame capture (active from start-of-frame to frame complete) for Pipe2 */
/***************** Bit definition for DCMIPP_CMSR2 register *****************/
#define DCMIPP_CMSR2_ATXERRF_Pos (5U)
#define DCMIPP_CMSR2_ATXERRF_Msk (0x1UL << DCMIPP_CMSR2_ATXERRF_Pos) /*!< 0x00000020 */
#define DCMIPP_CMSR2_ATXERRF DCMIPP_CMSR2_ATXERRF_Msk /*!< AXI transfer error interrupt status flag for the IPPLUG */
#define DCMIPP_CMSR2_PRERRF_Pos (6U)
#define DCMIPP_CMSR2_PRERRF_Msk (0x1UL << DCMIPP_CMSR2_PRERRF_Pos) /*!< 0x00000040 */
#define DCMIPP_CMSR2_PRERRF DCMIPP_CMSR2_PRERRF_Msk /*!< Synchronization error raw interrupt status for the parallel interface */
#define DCMIPP_CMSR2_P0LINEF_Pos (8U)
#define DCMIPP_CMSR2_P0LINEF_Msk (0x1UL << DCMIPP_CMSR2_P0LINEF_Pos) /*!< 0x00000100 */
#define DCMIPP_CMSR2_P0LINEF DCMIPP_CMSR2_P0LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe0 */
#define DCMIPP_CMSR2_P0FRAMEF_Pos (9U)
#define DCMIPP_CMSR2_P0FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P0FRAMEF_Pos) /*!< 0x00000200 */
#define DCMIPP_CMSR2_P0FRAMEF DCMIPP_CMSR2_P0FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe0 */
#define DCMIPP_CMSR2_P0VSYNCF_Pos (10U)
#define DCMIPP_CMSR2_P0VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P0VSYNCF_Pos) /*!< 0x00000400 */
#define DCMIPP_CMSR2_P0VSYNCF DCMIPP_CMSR2_P0VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe0 */
#define DCMIPP_CMSR2_P0LIMITF_Pos (14U)
#define DCMIPP_CMSR2_P0LIMITF_Msk (0x1UL << DCMIPP_CMSR2_P0LIMITF_Pos) /*!< 0x00004000 */
#define DCMIPP_CMSR2_P0LIMITF DCMIPP_CMSR2_P0LIMITF_Msk /*!< Limit raw interrupt status for Pipe0 */
#define DCMIPP_CMSR2_P0OVRF_Pos (15U)
#define DCMIPP_CMSR2_P0OVRF_Msk (0x1UL << DCMIPP_CMSR2_P0OVRF_Pos) /*!< 0x00008000 */
#define DCMIPP_CMSR2_P0OVRF DCMIPP_CMSR2_P0OVRF_Msk /*!< Overrun raw interrupt status for Pipe0 */
#define DCMIPP_CMSR2_P1LINEF_Pos (16U)
#define DCMIPP_CMSR2_P1LINEF_Msk (0x1UL << DCMIPP_CMSR2_P1LINEF_Pos) /*!< 0x00010000 */
#define DCMIPP_CMSR2_P1LINEF DCMIPP_CMSR2_P1LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe1 */
#define DCMIPP_CMSR2_P1FRAMEF_Pos (17U)
#define DCMIPP_CMSR2_P1FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P1FRAMEF_Pos) /*!< 0x00020000 */
#define DCMIPP_CMSR2_P1FRAMEF DCMIPP_CMSR2_P1FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe1 */
#define DCMIPP_CMSR2_P1VSYNCF_Pos (18U)
#define DCMIPP_CMSR2_P1VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P1VSYNCF_Pos) /*!< 0x00040000 */
#define DCMIPP_CMSR2_P1VSYNCF DCMIPP_CMSR2_P1VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe1 */
#define DCMIPP_CMSR2_P1OVRF_Pos (23U)
#define DCMIPP_CMSR2_P1OVRF_Msk (0x1UL << DCMIPP_CMSR2_P1OVRF_Pos) /*!< 0x00800000 */
#define DCMIPP_CMSR2_P1OVRF DCMIPP_CMSR2_P1OVRF_Msk /*!< Overrun raw interrupt status for Pipe1 */
#define DCMIPP_CMSR2_P2LINEF_Pos (24U)
#define DCMIPP_CMSR2_P2LINEF_Msk (0x1UL << DCMIPP_CMSR2_P2LINEF_Pos) /*!< 0x01000000 */
#define DCMIPP_CMSR2_P2LINEF DCMIPP_CMSR2_P2LINEF_Msk /*!< Multi-line capture completed raw interrupt status for Pipe2 */
#define DCMIPP_CMSR2_P2FRAMEF_Pos (25U)
#define DCMIPP_CMSR2_P2FRAMEF_Msk (0x1UL << DCMIPP_CMSR2_P2FRAMEF_Pos) /*!< 0x02000000 */
#define DCMIPP_CMSR2_P2FRAMEF DCMIPP_CMSR2_P2FRAMEF_Msk /*!< Frame capture completed raw interrupt status for Pipe2 */
#define DCMIPP_CMSR2_P2VSYNCF_Pos (26U)
#define DCMIPP_CMSR2_P2VSYNCF_Msk (0x1UL << DCMIPP_CMSR2_P2VSYNCF_Pos) /*!< 0x04000000 */
#define DCMIPP_CMSR2_P2VSYNCF DCMIPP_CMSR2_P2VSYNCF_Msk /*!< VSYNC raw interrupt status for Pipe2 */
#define DCMIPP_CMSR2_P2OVRF_Pos (31U)
#define DCMIPP_CMSR2_P2OVRF_Msk (0x1UL << DCMIPP_CMSR2_P2OVRF_Pos) /*!< 0x80000000 */
#define DCMIPP_CMSR2_P2OVRF DCMIPP_CMSR2_P2OVRF_Msk /*!< Overrun raw interrupt status for Pipe2 */
/***************** Bit definition for DCMIPP_CMFCR register *****************/
#define DCMIPP_CMFCR_CATXERRF_Pos (5U)
#define DCMIPP_CMFCR_CATXERRF_Msk (0x1UL << DCMIPP_CMFCR_CATXERRF_Pos) /*!< 0x00000020 */
#define DCMIPP_CMFCR_CATXERRF DCMIPP_CMFCR_CATXERRF_Msk /*!< AXI Transfer error interrupt status clear */
#define DCMIPP_CMFCR_CPRERRF_Pos (6U)
#define DCMIPP_CMFCR_CPRERRF_Msk (0x1UL << DCMIPP_CMFCR_CPRERRF_Pos) /*!< 0x00000040 */
#define DCMIPP_CMFCR_CPRERRF DCMIPP_CMFCR_CPRERRF_Msk /*!< Synchronization error interrupt status clear */
#define DCMIPP_CMFCR_CP0LINEF_Pos (8U)
#define DCMIPP_CMFCR_CP0LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP0LINEF_Pos) /*!< 0x00000100 */
#define DCMIPP_CMFCR_CP0LINEF DCMIPP_CMFCR_CP0LINEF_Msk /*!< Multi-line capture complete interrupt status clear */
#define DCMIPP_CMFCR_CP0FRAMEF_Pos (9U)
#define DCMIPP_CMFCR_CP0FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP0FRAMEF_Pos) /*!< 0x00000200 */
#define DCMIPP_CMFCR_CP0FRAMEF DCMIPP_CMFCR_CP0FRAMEF_Msk /*!< Frame capture complete interrupt status clear */
#define DCMIPP_CMFCR_CP0VSYNCF_Pos (10U)
#define DCMIPP_CMFCR_CP0VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP0VSYNCF_Pos) /*!< 0x00000400 */
#define DCMIPP_CMFCR_CP0VSYNCF DCMIPP_CMFCR_CP0VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */
#define DCMIPP_CMFCR_CP0LIMITF_Pos (14U)
#define DCMIPP_CMFCR_CP0LIMITF_Msk (0x1UL << DCMIPP_CMFCR_CP0LIMITF_Pos) /*!< 0x00004000 */
#define DCMIPP_CMFCR_CP0LIMITF DCMIPP_CMFCR_CP0LIMITF_Msk /*!< limit interrupt status clear */
#define DCMIPP_CMFCR_CP0OVRF_Pos (15U)
#define DCMIPP_CMFCR_CP0OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP0OVRF_Pos) /*!< 0x00008000 */
#define DCMIPP_CMFCR_CP0OVRF DCMIPP_CMFCR_CP0OVRF_Msk /*!< Overrun interrupt status clear */
#define DCMIPP_CMFCR_CP1LINEF_Pos (16U)
#define DCMIPP_CMFCR_CP1LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP1LINEF_Pos) /*!< 0x00010000 */
#define DCMIPP_CMFCR_CP1LINEF DCMIPP_CMFCR_CP1LINEF_Msk /*!< Multi-line capture complete interrupt status clear */
#define DCMIPP_CMFCR_CP1FRAMEF_Pos (17U)
#define DCMIPP_CMFCR_CP1FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP1FRAMEF_Pos) /*!< 0x00020000 */
#define DCMIPP_CMFCR_CP1FRAMEF DCMIPP_CMFCR_CP1FRAMEF_Msk /*!< Frame capture complete interrupt status clear */
#define DCMIPP_CMFCR_CP1VSYNCF_Pos (18U)
#define DCMIPP_CMFCR_CP1VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP1VSYNCF_Pos) /*!< 0x00040000 */
#define DCMIPP_CMFCR_CP1VSYNCF DCMIPP_CMFCR_CP1VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */
#define DCMIPP_CMFCR_CP1OVRF_Pos (23U)
#define DCMIPP_CMFCR_CP1OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP1OVRF_Pos) /*!< 0x00800000 */
#define DCMIPP_CMFCR_CP1OVRF DCMIPP_CMFCR_CP1OVRF_Msk /*!< Overrun interrupt status clear */
#define DCMIPP_CMFCR_CP2LINEF_Pos (24U)
#define DCMIPP_CMFCR_CP2LINEF_Msk (0x1UL << DCMIPP_CMFCR_CP2LINEF_Pos) /*!< 0x01000000 */
#define DCMIPP_CMFCR_CP2LINEF DCMIPP_CMFCR_CP2LINEF_Msk /*!< Multi-line capture complete interrupt status clear */
#define DCMIPP_CMFCR_CP2FRAMEF_Pos (25U)
#define DCMIPP_CMFCR_CP2FRAMEF_Msk (0x1UL << DCMIPP_CMFCR_CP2FRAMEF_Pos) /*!< 0x02000000 */
#define DCMIPP_CMFCR_CP2FRAMEF DCMIPP_CMFCR_CP2FRAMEF_Msk /*!< Frame capture complete interrupt status clear */
#define DCMIPP_CMFCR_CP2VSYNCF_Pos (26U)
#define DCMIPP_CMFCR_CP2VSYNCF_Msk (0x1UL << DCMIPP_CMFCR_CP2VSYNCF_Pos) /*!< 0x04000000 */
#define DCMIPP_CMFCR_CP2VSYNCF DCMIPP_CMFCR_CP2VSYNCF_Msk /*!< Vertical synchronization interrupt status clear */
#define DCMIPP_CMFCR_CP2OVRF_Pos (31U)
#define DCMIPP_CMFCR_CP2OVRF_Msk (0x1UL << DCMIPP_CMFCR_CP2OVRF_Pos) /*!< 0x80000000 */
#define DCMIPP_CMFCR_CP2OVRF DCMIPP_CMFCR_CP2OVRF_Msk /*!< Overrun interrupt status clear */
/**************** Bit definition for DCMIPP_P0FSCR register *****************/
#define DCMIPP_P0FSCR_DTIDA_Pos (0U)
#define DCMIPP_P0FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDA_Pos) /*!< 0x0000003F */
#define DCMIPP_P0FSCR_DTIDA DCMIPP_P0FSCR_DTIDA_Msk /*!< Data type selection ID A */
#define DCMIPP_P0FSCR_DTIDB_Pos (8U)
#define DCMIPP_P0FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0FSCR_DTIDB_Pos) /*!< 0x00003F00 */
#define DCMIPP_P0FSCR_DTIDB DCMIPP_P0FSCR_DTIDB_Msk /*!< Data type selection ID B */
#define DCMIPP_P0FSCR_DTMODE_Pos (16U)
#define DCMIPP_P0FSCR_DTMODE_Msk (0x3UL << DCMIPP_P0FSCR_DTMODE_Pos) /*!< 0x00030000 */
#define DCMIPP_P0FSCR_DTMODE DCMIPP_P0FSCR_DTMODE_Msk /*!< Flow selection mode */
#define DCMIPP_P0FSCR_VC_Pos (19U)
#define DCMIPP_P0FSCR_VC_Msk (0x3UL << DCMIPP_P0FSCR_VC_Pos) /*!< 0x00180000 */
#define DCMIPP_P0FSCR_VC DCMIPP_P0FSCR_VC_Msk /*!< Flow selection mode */
#define DCMIPP_P0FSCR_PIPEN_Pos (31U)
#define DCMIPP_P0FSCR_PIPEN_Msk (0x1UL << DCMIPP_P0FSCR_PIPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P0FSCR_PIPEN DCMIPP_P0FSCR_PIPEN_Msk /*!< Activation of PipeN */
/**************** Bit definition for DCMIPP_P0FCTCR register ****************/
#define DCMIPP_P0FCTCR_FRATE_Pos (0U)
#define DCMIPP_P0FCTCR_FRATE_Msk (0x3UL << DCMIPP_P0FCTCR_FRATE_Pos) /*!< 0x00000003 */
#define DCMIPP_P0FCTCR_FRATE DCMIPP_P0FCTCR_FRATE_Msk /*!< Frame capture rate control */
#define DCMIPP_P0FCTCR_CPTMODE_Pos (2U)
#define DCMIPP_P0FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0FCTCR_CPTMODE_Pos) /*!< 0x00000004 */
#define DCMIPP_P0FCTCR_CPTMODE DCMIPP_P0FCTCR_CPTMODE_Msk /*!< Capture mode */
#define DCMIPP_P0FCTCR_CPTREQ_Pos (3U)
#define DCMIPP_P0FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0FCTCR_CPTREQ_Pos) /*!< 0x00000008 */
#define DCMIPP_P0FCTCR_CPTREQ DCMIPP_P0FCTCR_CPTREQ_Msk /*!< Capture requested */
/**************** Bit definition for DCMIPP_P0SCSTR register ****************/
#define DCMIPP_P0SCSTR_HSTART_Pos (0U)
#define DCMIPP_P0SCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P0SCSTR_HSTART DCMIPP_P0SCSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 words wide */
#define DCMIPP_P0SCSTR_VSTART_Pos (16U)
#define DCMIPP_P0SCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0SCSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P0SCSTR_VSTART DCMIPP_P0SCSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */
/**************** Bit definition for DCMIPP_P0SCSZR register ****************/
#define DCMIPP_P0SCSZR_HSIZE_Pos (0U)
#define DCMIPP_P0SCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P0SCSZR_HSIZE DCMIPP_P0SCSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 word wide (data 32-bit) */
#define DCMIPP_P0SCSZR_VSIZE_Pos (16U)
#define DCMIPP_P0SCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0SCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P0SCSZR_VSIZE DCMIPP_P0SCSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P0SCSZR_POSNEG_Pos (30U)
#define DCMIPP_P0SCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0SCSZR_POSNEG_Pos) /*!< 0x40000000 */
#define DCMIPP_P0SCSZR_POSNEG DCMIPP_P0SCSZR_POSNEG_Msk /*!< This bit is set and cleared by software */
#define DCMIPP_P0SCSZR_ENABLE_Pos (31U)
#define DCMIPP_P0SCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0SCSZR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P0SCSZR_ENABLE DCMIPP_P0SCSZR_ENABLE_Msk /*!< This bit is set and cleared by software */
/*************** Bit definition for DCMIPP_P0DCCNTR register ****************/
#define DCMIPP_P0DCCNTR_CNT_Pos (0U)
#define DCMIPP_P0DCCNTR_CNT_Msk (0x3FFFFFFUL << DCMIPP_P0DCCNTR_CNT_Pos) /*!< 0x03FFFFFF */
#define DCMIPP_P0DCCNTR_CNT DCMIPP_P0DCCNTR_CNT_Msk /*!< Number of data dumped during the frame */
/*************** Bit definition for DCMIPP_P0DCLMTR register ****************/
#define DCMIPP_P0DCLMTR_LIMIT_Pos (0U)
#define DCMIPP_P0DCLMTR_LIMIT_Msk (0xFFFFFFUL << DCMIPP_P0DCLMTR_LIMIT_Pos) /*!< 0x00FFFFFF */
#define DCMIPP_P0DCLMTR_LIMIT DCMIPP_P0DCLMTR_LIMIT_Msk /*!< Maximum number of 32-bit data that can be dumped during a frame, after the crop 2D operation */
#define DCMIPP_P0DCLMTR_ENABLE_Pos (31U)
#define DCMIPP_P0DCLMTR_ENABLE_Msk (0x1UL << DCMIPP_P0DCLMTR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P0DCLMTR_ENABLE DCMIPP_P0DCLMTR_ENABLE_Msk /*!< */
/**************** Bit definition for DCMIPP_P0PPCR register *****************/
#define DCMIPP_P0PPCR_SWAPYUV_Pos (0U)
#define DCMIPP_P0PPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0PPCR_SWAPYUV_Pos) /*!< 0x00000001 */
#define DCMIPP_P0PPCR_SWAPYUV DCMIPP_P0PPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */
#define DCMIPP_P0PPCR_PAD_Pos (5U)
#define DCMIPP_P0PPCR_PAD_Msk (0x1UL << DCMIPP_P0PPCR_PAD_Pos) /*!< 0x00000020 */
#define DCMIPP_P0PPCR_PAD DCMIPP_P0PPCR_PAD_Msk /*!< Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
#define DCMIPP_P0PPCR_HEADEREN_Pos (6U)
#define DCMIPP_P0PPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0PPCR_HEADEREN_Pos) /*!< 0x00000040 */
#define DCMIPP_P0PPCR_HEADEREN DCMIPP_P0PPCR_HEADEREN_Msk /*!< CSI header dump enable */
#define DCMIPP_P0PPCR_BSM_Pos (7U)
#define DCMIPP_P0PPCR_BSM_Msk (0x3UL << DCMIPP_P0PPCR_BSM_Pos) /*!< 0x00000180 */
#define DCMIPP_P0PPCR_BSM DCMIPP_P0PPCR_BSM_Msk /*!< Byte select mode */
#define DCMIPP_P0PPCR_OEBS_Pos (9U)
#define DCMIPP_P0PPCR_OEBS_Msk (0x1UL << DCMIPP_P0PPCR_OEBS_Pos) /*!< 0x00000200 */
#define DCMIPP_P0PPCR_OEBS DCMIPP_P0PPCR_OEBS_Msk /*!< Odd/even byte select (byte select start) */
#define DCMIPP_P0PPCR_LSM_Pos (10U)
#define DCMIPP_P0PPCR_LSM_Msk (0x1UL << DCMIPP_P0PPCR_LSM_Pos) /*!< 0x00000400 */
#define DCMIPP_P0PPCR_LSM DCMIPP_P0PPCR_LSM_Msk /*!< Line select mode */
#define DCMIPP_P0PPCR_OELS_Pos (11U)
#define DCMIPP_P0PPCR_OELS_Msk (0x1UL << DCMIPP_P0PPCR_OELS_Pos) /*!< 0x00000800 */
#define DCMIPP_P0PPCR_OELS DCMIPP_P0PPCR_OELS_Msk /*!< Odd/even line select (line select start) */
#define DCMIPP_P0PPCR_LINEMULT_Pos (13U)
#define DCMIPP_P0PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0PPCR_LINEMULT_Pos) /*!< 0x0000E000 */
#define DCMIPP_P0PPCR_LINEMULT DCMIPP_P0PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */
#define DCMIPP_P0PPCR_DBM_Pos (16U)
#define DCMIPP_P0PPCR_DBM_Msk (0x1UL << DCMIPP_P0PPCR_DBM_Pos) /*!< 0x00010000 */
#define DCMIPP_P0PPCR_DBM DCMIPP_P0PPCR_DBM_Msk /*!< Double buffer mode */
/*************** Bit definition for DCMIPP_P0PPM0AR1 register ***************/
#define DCMIPP_P0PPM0AR1_M0A_Pos (0U)
#define DCMIPP_P0PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P0PPM0AR1_M0A DCMIPP_P0PPM0AR1_M0A_Msk /*!< Memory0 address */
/*************** Bit definition for DCMIPP_P0PPM0AR2 register ***************/
#define DCMIPP_P0PPM0AR2_M0A_Pos (0U)
#define DCMIPP_P0PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P0PPM0AR2_M0A DCMIPP_P0PPM0AR2_M0A_Msk /*!< Memory0 address */
/***************** Bit definition for DCMIPP_P0IER register *****************/
#define DCMIPP_P0IER_LINEIE_Pos (0U)
#define DCMIPP_P0IER_LINEIE_Msk (0x1UL << DCMIPP_P0IER_LINEIE_Pos) /*!< 0x00000001 */
#define DCMIPP_P0IER_LINEIE DCMIPP_P0IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */
#define DCMIPP_P0IER_FRAMEIE_Pos (1U)
#define DCMIPP_P0IER_FRAMEIE_Msk (0x1UL << DCMIPP_P0IER_FRAMEIE_Pos) /*!< 0x00000002 */
#define DCMIPP_P0IER_FRAMEIE DCMIPP_P0IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */
#define DCMIPP_P0IER_VSYNCIE_Pos (2U)
#define DCMIPP_P0IER_VSYNCIE_Msk (0x1UL << DCMIPP_P0IER_VSYNCIE_Pos) /*!< 0x00000004 */
#define DCMIPP_P0IER_VSYNCIE DCMIPP_P0IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */
#define DCMIPP_P0IER_LIMITIE_Pos (6U)
#define DCMIPP_P0IER_LIMITIE_Msk (0x1UL << DCMIPP_P0IER_LIMITIE_Pos) /*!< 0x00000040 */
#define DCMIPP_P0IER_LIMITIE DCMIPP_P0IER_LIMITIE_Msk /*!< Limit interrupt enable */
#define DCMIPP_P0IER_OVRIE_Pos (7U)
#define DCMIPP_P0IER_OVRIE_Msk (0x1UL << DCMIPP_P0IER_OVRIE_Pos) /*!< 0x00000080 */
#define DCMIPP_P0IER_OVRIE DCMIPP_P0IER_OVRIE_Msk /*!< Overrun interrupt enable */
/***************** Bit definition for DCMIPP_P0SR register ******************/
#define DCMIPP_P0SR_LINEF_Pos (0U)
#define DCMIPP_P0SR_LINEF_Msk (0x1UL << DCMIPP_P0SR_LINEF_Pos) /*!< 0x00000001 */
#define DCMIPP_P0SR_LINEF DCMIPP_P0SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */
#define DCMIPP_P0SR_FRAMEF_Pos (1U)
#define DCMIPP_P0SR_FRAMEF_Msk (0x1UL << DCMIPP_P0SR_FRAMEF_Pos) /*!< 0x00000002 */
#define DCMIPP_P0SR_FRAMEF DCMIPP_P0SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */
#define DCMIPP_P0SR_VSYNCF_Pos (2U)
#define DCMIPP_P0SR_VSYNCF_Msk (0x1UL << DCMIPP_P0SR_VSYNCF_Pos) /*!< 0x00000004 */
#define DCMIPP_P0SR_VSYNCF DCMIPP_P0SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */
#define DCMIPP_P0SR_LIMITF_Pos (6U)
#define DCMIPP_P0SR_LIMITF_Msk (0x1UL << DCMIPP_P0SR_LIMITF_Pos) /*!< 0x00000040 */
#define DCMIPP_P0SR_LIMITF DCMIPP_P0SR_LIMITF_Msk /*!< Limit raw interrupt status */
#define DCMIPP_P0SR_OVRF_Pos (7U)
#define DCMIPP_P0SR_OVRF_Msk (0x1UL << DCMIPP_P0SR_OVRF_Pos) /*!< 0x00000080 */
#define DCMIPP_P0SR_OVRF DCMIPP_P0SR_OVRF_Msk /*!< Overrun raw interrupt status */
#define DCMIPP_P0SR_LSTLINE_Pos (16U)
#define DCMIPP_P0SR_LSTLINE_Msk (0x1UL << DCMIPP_P0SR_LSTLINE_Pos) /*!< 0x00010000 */
#define DCMIPP_P0SR_LSTLINE DCMIPP_P0SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */
#define DCMIPP_P0SR_LSTFRM_Pos (17U)
#define DCMIPP_P0SR_LSTFRM_Msk (0x1UL << DCMIPP_P0SR_LSTFRM_Pos) /*!< 0x00020000 */
#define DCMIPP_P0SR_LSTFRM DCMIPP_P0SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */
#define DCMIPP_P0SR_CPTACT_Pos (23U)
#define DCMIPP_P0SR_CPTACT_Msk (0x1UL << DCMIPP_P0SR_CPTACT_Pos) /*!< 0x00800000 */
#define DCMIPP_P0SR_CPTACT DCMIPP_P0SR_CPTACT_Msk /*!< Capture immediate status */
/***************** Bit definition for DCMIPP_P0FCR register *****************/
#define DCMIPP_P0FCR_CLINEF_Pos (0U)
#define DCMIPP_P0FCR_CLINEF_Msk (0x1UL << DCMIPP_P0FCR_CLINEF_Pos) /*!< 0x00000001 */
#define DCMIPP_P0FCR_CLINEF DCMIPP_P0FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */
#define DCMIPP_P0FCR_CFRAMEF_Pos (1U)
#define DCMIPP_P0FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P0FCR_CFRAMEF_Pos) /*!< 0x00000002 */
#define DCMIPP_P0FCR_CFRAMEF DCMIPP_P0FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */
#define DCMIPP_P0FCR_CVSYNCF_Pos (2U)
#define DCMIPP_P0FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P0FCR_CVSYNCF_Pos) /*!< 0x00000004 */
#define DCMIPP_P0FCR_CVSYNCF DCMIPP_P0FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */
#define DCMIPP_P0FCR_CLIMITF_Pos (6U)
#define DCMIPP_P0FCR_CLIMITF_Msk (0x1UL << DCMIPP_P0FCR_CLIMITF_Pos) /*!< 0x00000040 */
#define DCMIPP_P0FCR_CLIMITF DCMIPP_P0FCR_CLIMITF_Msk /*!< limit interrupt status clear */
#define DCMIPP_P0FCR_COVRF_Pos (7U)
#define DCMIPP_P0FCR_COVRF_Msk (0x1UL << DCMIPP_P0FCR_COVRF_Pos) /*!< 0x00000080 */
#define DCMIPP_P0FCR_COVRF DCMIPP_P0FCR_COVRF_Msk /*!< Overrun interrupt status clear */
/**************** Bit definition for DCMIPP_P0CFSCR register ****************/
#define DCMIPP_P0CFSCR_DTIDA_Pos (0U)
#define DCMIPP_P0CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDA_Pos) /*!< 0x0000003F */
#define DCMIPP_P0CFSCR_DTIDA DCMIPP_P0CFSCR_DTIDA_Msk /*!< Current Data type selection ID A */
#define DCMIPP_P0CFSCR_DTIDB_Pos (8U)
#define DCMIPP_P0CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P0CFSCR_DTIDB_Pos) /*!< 0x00003F00 */
#define DCMIPP_P0CFSCR_DTIDB DCMIPP_P0CFSCR_DTIDB_Msk /*!< Current Data type selection ID B */
#define DCMIPP_P0CFSCR_DTMODE_Pos (16U)
#define DCMIPP_P0CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P0CFSCR_DTMODE_Pos) /*!< 0x00030000 */
#define DCMIPP_P0CFSCR_DTMODE DCMIPP_P0CFSCR_DTMODE_Msk /*!< Flow selection mode */
#define DCMIPP_P0CFSCR_VC_Pos (19U)
#define DCMIPP_P0CFSCR_VC_Msk (0x3UL << DCMIPP_P0CFSCR_VC_Pos) /*!< 0x00180000 */
#define DCMIPP_P0CFSCR_VC DCMIPP_P0CFSCR_VC_Msk /*!< Current flow selection mode */
#define DCMIPP_P0CFSCR_PIPEN_Pos (31U)
#define DCMIPP_P0CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P0CFSCR_PIPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P0CFSCR_PIPEN DCMIPP_P0CFSCR_PIPEN_Msk /*!< Current activation of PipeN */
/*************** Bit definition for DCMIPP_P0CFCTCR register ****************/
#define DCMIPP_P0CFCTCR_FRATE_Pos (0U)
#define DCMIPP_P0CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P0CFCTCR_FRATE_Pos) /*!< 0x00000003 */
#define DCMIPP_P0CFCTCR_FRATE DCMIPP_P0CFCTCR_FRATE_Msk /*!< Frame capture rate control */
#define DCMIPP_P0CFCTCR_CPTMODE_Pos (2U)
#define DCMIPP_P0CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */
#define DCMIPP_P0CFCTCR_CPTMODE DCMIPP_P0CFCTCR_CPTMODE_Msk /*!< Capture mode */
#define DCMIPP_P0CFCTCR_CPTREQ_Pos (3U)
#define DCMIPP_P0CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P0CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */
#define DCMIPP_P0CFCTCR_CPTREQ DCMIPP_P0CFCTCR_CPTREQ_Msk /*!< Capture requested */
/*************** Bit definition for DCMIPP_P0CSCSTR register ****************/
#define DCMIPP_P0CSCSTR_HSTART_Pos (0U)
#define DCMIPP_P0CSCSTR_HSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P0CSCSTR_HSTART DCMIPP_P0CSCSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 words wide */
#define DCMIPP_P0CSCSTR_VSTART_Pos (16U)
#define DCMIPP_P0CSCSTR_VSTART_Msk (0xFFFUL << DCMIPP_P0CSCSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P0CSCSTR_VSTART DCMIPP_P0CSCSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */
/*************** Bit definition for DCMIPP_P0CSCSZR register ****************/
#define DCMIPP_P0CSCSZR_HSIZE_Pos (0U)
#define DCMIPP_P0CSCSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P0CSCSZR_HSIZE DCMIPP_P0CSCSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 word wide (data 32-bit) */
#define DCMIPP_P0CSCSZR_VSIZE_Pos (16U)
#define DCMIPP_P0CSCSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P0CSCSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P0CSCSZR_VSIZE DCMIPP_P0CSCSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P0CSCSZR_POSNEG_Pos (30U)
#define DCMIPP_P0CSCSZR_POSNEG_Msk (0x1UL << DCMIPP_P0CSCSZR_POSNEG_Pos) /*!< 0x40000000 */
#define DCMIPP_P0CSCSZR_POSNEG DCMIPP_P0CSCSZR_POSNEG_Msk /*!< Current value of the POSNEG bit */
#define DCMIPP_P0CSCSZR_ENABLE_Pos (31U)
#define DCMIPP_P0CSCSZR_ENABLE_Msk (0x1UL << DCMIPP_P0CSCSZR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P0CSCSZR_ENABLE DCMIPP_P0CSCSZR_ENABLE_Msk /*!< Current value of the ENABLE bit */
/**************** Bit definition for DCMIPP_P0CPPCR register ****************/
#define DCMIPP_P0CPPCR_SWAPYUV_Pos (0U)
#define DCMIPP_P0CPPCR_SWAPYUV_Msk (0x1UL << DCMIPP_P0CPPCR_SWAPYUV_Pos) /*!< 0x00000001 */
#define DCMIPP_P0CPPCR_SWAPYUV DCMIPP_P0CPPCR_SWAPYUV_Msk /*!< SwapY vs UV bits, when the YUV mode is active */
#define DCMIPP_P0CPPCR_PAD_Pos (5U)
#define DCMIPP_P0CPPCR_PAD_Msk (0x1UL << DCMIPP_P0CPPCR_PAD_Pos) /*!< 0x00000020 */
#define DCMIPP_P0CPPCR_PAD DCMIPP_P0CPPCR_PAD_Msk /*!< Current Pad mode for monochrome and raw Bayer 10/12/14 bpp: MSB vs */
#define DCMIPP_P0CPPCR_HEADEREN_Pos (6U)
#define DCMIPP_P0CPPCR_HEADEREN_Msk (0x1UL << DCMIPP_P0CPPCR_HEADEREN_Pos) /*!< 0x00000040 */
#define DCMIPP_P0CPPCR_HEADEREN DCMIPP_P0CPPCR_HEADEREN_Msk /*!< Current CSI header dump enable */
#define DCMIPP_P0CPPCR_BSM_Pos (7U)
#define DCMIPP_P0CPPCR_BSM_Msk (0x3UL << DCMIPP_P0CPPCR_BSM_Pos) /*!< 0x00000180 */
#define DCMIPP_P0CPPCR_BSM DCMIPP_P0CPPCR_BSM_Msk /*!< Current Byte select mode */
#define DCMIPP_P0CPPCR_OEBS_Pos (9U)
#define DCMIPP_P0CPPCR_OEBS_Msk (0x1UL << DCMIPP_P0CPPCR_OEBS_Pos) /*!< 0x00000200 */
#define DCMIPP_P0CPPCR_OEBS DCMIPP_P0CPPCR_OEBS_Msk /*!< Current odd/even byte select (Byte select start) */
#define DCMIPP_P0CPPCR_LSM_Pos (10U)
#define DCMIPP_P0CPPCR_LSM_Msk (0x1UL << DCMIPP_P0CPPCR_LSM_Pos) /*!< 0x00000400 */
#define DCMIPP_P0CPPCR_LSM DCMIPP_P0CPPCR_LSM_Msk /*!< Current Line select mode */
#define DCMIPP_P0CPPCR_OELS_Pos (11U)
#define DCMIPP_P0CPPCR_OELS_Msk (0x1UL << DCMIPP_P0CPPCR_OELS_Pos) /*!< 0x00000800 */
#define DCMIPP_P0CPPCR_OELS DCMIPP_P0CPPCR_OELS_Msk /*!< Current odd/even line select (Line select start) */
#define DCMIPP_P0CPPCR_LINEMULT_Pos (13U)
#define DCMIPP_P0CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */
#define DCMIPP_P0CPPCR_LINEMULT DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Current amount of capture completed lines for LINE Event and Interrupt */
#define DCMIPP_P0CPPCR_DBM_Pos (16U)
#define DCMIPP_P0CPPCR_DBM_Msk (0x1UL << DCMIPP_P0CPPCR_LINEMULT_Pos) /*!< 0x00010000 */
#define DCMIPP_P0CPPCR_DBM DCMIPP_P0CPPCR_LINEMULT_Msk /*!< Double buffer mode */
/************** Bit definition for DCMIPP_P0CPPM0AR1 register ***************/
#define DCMIPP_P0CPPM0AR1_M0A_Pos (0U)
#define DCMIPP_P0CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P0CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P0CPPM0AR1_M0A DCMIPP_P0CPPM0AR1_M0A_Msk /*!< Memory0 address */
/**************** Bit definition for DCMIPP_P1FSCR register *****************/
#define DCMIPP_P1FSCR_DTIDA_Pos (0U)
#define DCMIPP_P1FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDA_Pos) /*!< 0x0000003F */
#define DCMIPP_P1FSCR_DTIDA DCMIPP_P1FSCR_DTIDA_Msk /*!< Data type ID A */
#define DCMIPP_P1FSCR_DTIDB_Pos (8U)
#define DCMIPP_P1FSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1FSCR_DTIDB_Pos) /*!< 0x00003F00 */
#define DCMIPP_P1FSCR_DTIDB DCMIPP_P1FSCR_DTIDB_Msk /*!< Data type ID B */
#define DCMIPP_P1FSCR_DTMODE_Pos (16U)
#define DCMIPP_P1FSCR_DTMODE_Msk (0x3UL << DCMIPP_P1FSCR_DTMODE_Pos) /*!< 0x00030000 */
#define DCMIPP_P1FSCR_DTMODE DCMIPP_P1FSCR_DTMODE_Msk /*!< Flow selection mode */
#define DCMIPP_P1FSCR_PIPEDIFF_Pos (18U)
#define DCMIPP_P1FSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1FSCR_PIPEDIFF_Pos) /*!< 0x00040000 */
#define DCMIPP_P1FSCR_PIPEDIFF DCMIPP_P1FSCR_PIPEDIFF_Msk /*!< Differentiates Pipe2 vs */
#define DCMIPP_P1FSCR_VC_Pos (19U)
#define DCMIPP_P1FSCR_VC_Msk (0x3UL << DCMIPP_P1FSCR_VC_Pos) /*!< 0x00180000 */
#define DCMIPP_P1FSCR_VC DCMIPP_P1FSCR_VC_Msk /*!< Flow selection mode */
#define DCMIPP_P1FSCR_FDTF_Pos (24U)
#define DCMIPP_P1FSCR_FDTF_Msk (0x3FUL << DCMIPP_P1FSCR_FDTF_Pos) /*!< 0x3F000000 */
#define DCMIPP_P1FSCR_FDTF DCMIPP_P1FSCR_FDTF_Msk /*!< Force Data type format */
#define DCMIPP_P1FSCR_FDTFEN_Pos (30U)
#define DCMIPP_P1FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1FSCR_FDTFEN_Pos) /*!< 0x40000000 */
#define DCMIPP_P1FSCR_FDTFEN DCMIPP_P1FSCR_FDTFEN_Msk /*!< Force Data type format enable */
#define DCMIPP_P1FSCR_PIPEN_Pos (31U)
#define DCMIPP_P1FSCR_PIPEN_Msk (0x1UL << DCMIPP_P1FSCR_PIPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P1FSCR_PIPEN DCMIPP_P1FSCR_PIPEN_Msk /*!< Activation of PipeN */
/**************** Bit definition for DCMIPP_P1SRCR register *****************/
#define DCMIPP_P1SRCR_LASTLINE_Pos (0U)
#define DCMIPP_P1SRCR_LASTLINE_Msk (0xFFFUL << DCMIPP_P1SRCR_LASTLINE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1SRCR_LASTLINE DCMIPP_P1SRCR_LASTLINE_Msk /*!< Number of the last line to be kept when CROPEN = 1 */
#define DCMIPP_P1SRCR_FIRSTLINEDEL_Pos (12U)
#define DCMIPP_P1SRCR_FIRSTLINEDEL_Msk (0x7UL << DCMIPP_P1SRCR_FIRSTLINEDEL_Pos) /*!< 0x00007000 */
#define DCMIPP_P1SRCR_FIRSTLINEDEL DCMIPP_P1SRCR_FIRSTLINEDEL_Msk /*!< Number of lines to be deleted when CROPEN = 1 */
#define DCMIPP_P1SRCR_CROPEN_Pos (15U)
#define DCMIPP_P1SRCR_CROPEN_Msk (0x1UL << DCMIPP_P1SRCR_CROPEN_Pos) /*!< 0x00008000 */
#define DCMIPP_P1SRCR_CROPEN DCMIPP_P1SRCR_CROPEN_Msk /*!< Crop line enable */
/**************** Bit definition for DCMIPP_P1BPRCR register ****************/
#define DCMIPP_P1BPRCR_ENABLE_Pos (0U)
#define DCMIPP_P1BPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1BPRCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1BPRCR_ENABLE DCMIPP_P1BPRCR_ENABLE_Msk /*!< Bad pixel detection must be enabled only for raw Bayer flows, as it corrupts RGB flows */
#define DCMIPP_P1BPRCR_STRENGTH_Pos (1U)
#define DCMIPP_P1BPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1BPRCR_STRENGTH_Pos) /*!< 0x0000000E */
#define DCMIPP_P1BPRCR_STRENGTH DCMIPP_P1BPRCR_STRENGTH_Msk /*!< Strength (aggressivity) of the bad pixel detection: */
/**************** Bit definition for DCMIPP_P1BPRSR register ****************/
#define DCMIPP_P1BPRSR_BADCNT_Pos (0U)
#define DCMIPP_P1BPRSR_BADCNT_Msk (0xFFFUL << DCMIPP_P1BPRSR_BADCNT_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1BPRSR_BADCNT DCMIPP_P1BPRSR_BADCNT_Msk /*!< Amount of detected bad pixels */
/**************** Bit definition for DCMIPP_P1DECR register *****************/
#define DCMIPP_P1DECR_ENABLE_Pos (0U)
#define DCMIPP_P1DECR_ENABLE_Msk (0x1UL << DCMIPP_P1DECR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1DECR_ENABLE DCMIPP_P1DECR_ENABLE_Msk /*!< */
#define DCMIPP_P1DECR_HDEC_Pos (1U)
#define DCMIPP_P1DECR_HDEC_Msk (0x3UL << DCMIPP_P1DECR_HDEC_Pos) /*!< 0x00000006 */
#define DCMIPP_P1DECR_HDEC DCMIPP_P1DECR_HDEC_Msk /*!< Horizontal decimation ratio */
#define DCMIPP_P1DECR_VDEC_Pos (3U)
#define DCMIPP_P1DECR_VDEC_Msk (0x3UL << DCMIPP_P1DECR_VDEC_Pos) /*!< 0x00000018 */
#define DCMIPP_P1DECR_VDEC DCMIPP_P1DECR_VDEC_Msk /*!< Vertical decimation ratio */
/**************** Bit definition for DCMIPP_P1BLCCR register ****************/
#define DCMIPP_P1BLCCR_ENABLE_Pos (0U)
#define DCMIPP_P1BLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1BLCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1BLCCR_ENABLE DCMIPP_P1BLCCR_ENABLE_Msk /*!< Black level calibration */
#define DCMIPP_P1BLCCR_BLCB_Pos (8U)
#define DCMIPP_P1BLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCB_Pos) /*!< 0x0000FF00 */
#define DCMIPP_P1BLCCR_BLCB DCMIPP_P1BLCCR_BLCB_Msk /*!< Black level calibration - Blue */
#define DCMIPP_P1BLCCR_BLCG_Pos (16U)
#define DCMIPP_P1BLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCG_Pos) /*!< 0x00FF0000 */
#define DCMIPP_P1BLCCR_BLCG DCMIPP_P1BLCCR_BLCG_Msk /*!< Black level calibration - Green */
#define DCMIPP_P1BLCCR_BLCR_Pos (24U)
#define DCMIPP_P1BLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1BLCCR_BLCR_Pos) /*!< 0xFF000000 */
#define DCMIPP_P1BLCCR_BLCR DCMIPP_P1BLCCR_BLCR_Msk /*!< Black level calibration - Red */
/**************** Bit definition for DCMIPP_P1EXCR1 register ****************/
#define DCMIPP_P1EXCR1_ENABLE_Pos (0U)
#define DCMIPP_P1EXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1EXCR1_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1EXCR1_ENABLE DCMIPP_P1EXCR1_ENABLE_Msk /*!< Exposure control (multiplication and shift) of all red, green and blue */
#define DCMIPP_P1EXCR1_MULTR_Pos (20U)
#define DCMIPP_P1EXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1EXCR1_MULTR_Pos) /*!< 0x0FF00000 */
#define DCMIPP_P1EXCR1_MULTR DCMIPP_P1EXCR1_MULTR_Msk /*!< Exposure multiplier - Red */
#define DCMIPP_P1EXCR1_SHFR_Pos (28U)
#define DCMIPP_P1EXCR1_SHFR_Msk (0x7UL << DCMIPP_P1EXCR1_SHFR_Pos) /*!< 0x70000000 */
#define DCMIPP_P1EXCR1_SHFR DCMIPP_P1EXCR1_SHFR_Msk /*!< Exposure shift - Red */
/**************** Bit definition for DCMIPP_P1EXCR2 register ****************/
#define DCMIPP_P1EXCR2_MULTB_Pos (4U)
#define DCMIPP_P1EXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTB_Pos) /*!< 0x00000FF0 */
#define DCMIPP_P1EXCR2_MULTB DCMIPP_P1EXCR2_MULTB_Msk /*!< Exposure multiplier - Blue */
#define DCMIPP_P1EXCR2_SHFB_Pos (12U)
#define DCMIPP_P1EXCR2_SHFB_Msk (0x7UL << DCMIPP_P1EXCR2_SHFB_Pos) /*!< 0x00007000 */
#define DCMIPP_P1EXCR2_SHFB DCMIPP_P1EXCR2_SHFB_Msk /*!< Exposure shift - Blue */
#define DCMIPP_P1EXCR2_MULTG_Pos (20U)
#define DCMIPP_P1EXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1EXCR2_MULTG_Pos) /*!< 0x0FF00000 */
#define DCMIPP_P1EXCR2_MULTG DCMIPP_P1EXCR2_MULTG_Msk /*!< Exposure multiplier - Green */
#define DCMIPP_P1EXCR2_SHFG_Pos (28U)
#define DCMIPP_P1EXCR2_SHFG_Msk (0x7UL << DCMIPP_P1EXCR2_SHFG_Pos) /*!< 0x70000000 */
#define DCMIPP_P1EXCR2_SHFG DCMIPP_P1EXCR2_SHFG_Msk /*!< Exposure shift - Green */
/**************** Bit definition for DCMIPP_P1ST1CR register ****************/
#define DCMIPP_P1ST1CR_ENABLE_Pos (0U)
#define DCMIPP_P1ST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST1CR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1ST1CR_ENABLE DCMIPP_P1ST1CR_ENABLE_Msk /*!< */
#define DCMIPP_P1ST1CR_BINS_Pos (2U)
#define DCMIPP_P1ST1CR_BINS_Msk (0x3UL << DCMIPP_P1ST1CR_BINS_Pos) /*!< 0x0000000C */
#define DCMIPP_P1ST1CR_BINS DCMIPP_P1ST1CR_BINS_Msk /*!< Bin definition */
#define DCMIPP_P1ST1CR_SRC_Pos (4U)
#define DCMIPP_P1ST1CR_SRC_Msk (0x7UL << DCMIPP_P1ST1CR_SRC_Pos) /*!< 0x00000070 */
#define DCMIPP_P1ST1CR_SRC DCMIPP_P1ST1CR_SRC_Msk /*!< Statistics source */
#define DCMIPP_P1ST1CR_MODE_Pos (7U)
#define DCMIPP_P1ST1CR_MODE_Msk (0x1UL << DCMIPP_P1ST1CR_MODE_Pos) /*!< 0x00000080 */
#define DCMIPP_P1ST1CR_MODE DCMIPP_P1ST1CR_MODE_Msk /*!< Statistics mode */
/**************** Bit definition for DCMIPP_P1ST2CR register ****************/
#define DCMIPP_P1ST2CR_ENABLE_Pos (0U)
#define DCMIPP_P1ST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST2CR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1ST2CR_ENABLE DCMIPP_P1ST2CR_ENABLE_Msk /*!< */
#define DCMIPP_P1ST2CR_BINS_Pos (2U)
#define DCMIPP_P1ST2CR_BINS_Msk (0x3UL << DCMIPP_P1ST2CR_BINS_Pos) /*!< 0x0000000C */
#define DCMIPP_P1ST2CR_BINS DCMIPP_P1ST2CR_BINS_Msk /*!< Bin definition */
#define DCMIPP_P1ST2CR_SRC_Pos (4U)
#define DCMIPP_P1ST2CR_SRC_Msk (0x7UL << DCMIPP_P1ST2CR_SRC_Pos) /*!< 0x00000070 */
#define DCMIPP_P1ST2CR_SRC DCMIPP_P1ST2CR_SRC_Msk /*!< Statistics source */
#define DCMIPP_P1ST2CR_MODE_Pos (7U)
#define DCMIPP_P1ST2CR_MODE_Msk (0x1UL << DCMIPP_P1ST2CR_MODE_Pos) /*!< 0x00000080 */
#define DCMIPP_P1ST2CR_MODE DCMIPP_P1ST2CR_MODE_Msk /*!< Statistics mode */
/**************** Bit definition for DCMIPP_P1ST3CR register ****************/
#define DCMIPP_P1ST3CR_ENABLE_Pos (0U)
#define DCMIPP_P1ST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1ST3CR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1ST3CR_ENABLE DCMIPP_P1ST3CR_ENABLE_Msk /*!< */
#define DCMIPP_P1ST3CR_BINS_Pos (2U)
#define DCMIPP_P1ST3CR_BINS_Msk (0x3UL << DCMIPP_P1ST3CR_BINS_Pos) /*!< 0x0000000C */
#define DCMIPP_P1ST3CR_BINS DCMIPP_P1ST3CR_BINS_Msk /*!< Bin definition */
#define DCMIPP_P1ST3CR_SRC_Pos (4U)
#define DCMIPP_P1ST3CR_SRC_Msk (0x7UL << DCMIPP_P1ST3CR_SRC_Pos) /*!< 0x00000070 */
#define DCMIPP_P1ST3CR_SRC DCMIPP_P1ST3CR_SRC_Msk /*!< Statistics source */
#define DCMIPP_P1ST3CR_MODE_Pos (7U)
#define DCMIPP_P1ST3CR_MODE_Msk (0x1UL << DCMIPP_P1ST3CR_MODE_Pos) /*!< 0x00000080 */
#define DCMIPP_P1ST3CR_MODE DCMIPP_P1ST3CR_MODE_Msk /*!< Statistics mode */
/**************** Bit definition for DCMIPP_P1STSTR register ****************/
#define DCMIPP_P1STSTR_HSTART_Pos (0U)
#define DCMIPP_P1STSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1STSTR_HSTART DCMIPP_P1STSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */
#define DCMIPP_P1STSTR_VSTART_Pos (16U)
#define DCMIPP_P1STSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1STSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1STSTR_VSTART DCMIPP_P1STSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */
/**************** Bit definition for DCMIPP_P1STSZR register ****************/
#define DCMIPP_P1STSZR_HSIZE_Pos (0U)
#define DCMIPP_P1STSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1STSZR_HSIZE DCMIPP_P1STSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P1STSZR_VSIZE_Pos (16U)
#define DCMIPP_P1STSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1STSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1STSZR_VSIZE DCMIPP_P1STSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P1STSZR_CROPEN_Pos (31U)
#define DCMIPP_P1STSZR_CROPEN_Msk (0x1UL << DCMIPP_P1STSZR_CROPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P1STSZR_CROPEN DCMIPP_P1STSZR_CROPEN_Msk /*!< */
/**************** Bit definition for DCMIPP_P1ST1SR register ****************/
#define DCMIPP_P1ST1SR_ACCU_Pos (0U)
#define DCMIPP_P1ST1SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST1SR_ACCU_Pos) /*!< 0x00FFFFFF */
#define DCMIPP_P1ST1SR_ACCU DCMIPP_P1ST1SR_ACCU_Msk /*!< Accumulation result, divided by 256 */
/**************** Bit definition for DCMIPP_P1ST2SR register ****************/
#define DCMIPP_P1ST2SR_ACCU_Pos (0U)
#define DCMIPP_P1ST2SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST2SR_ACCU_Pos) /*!< 0x00FFFFFF */
#define DCMIPP_P1ST2SR_ACCU DCMIPP_P1ST2SR_ACCU_Msk /*!< accumulation result, divided by 256 */
/**************** Bit definition for DCMIPP_P1ST3SR register ****************/
#define DCMIPP_P1ST3SR_ACCU_Pos (0U)
#define DCMIPP_P1ST3SR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1ST3SR_ACCU_Pos) /*!< 0x00FFFFFF */
#define DCMIPP_P1ST3SR_ACCU DCMIPP_P1ST3SR_ACCU_Msk /*!< accumulation result, divided by 256 */
/**************** Bit definition for DCMIPP_P1DMCR register *****************/
#define DCMIPP_P1DMCR_ENABLE_Pos (0U)
#define DCMIPP_P1DMCR_ENABLE_Msk (0x1UL << DCMIPP_P1DMCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1DMCR_ENABLE DCMIPP_P1DMCR_ENABLE_Msk /*!< */
#define DCMIPP_P1DMCR_TYPE_Pos (1U)
#define DCMIPP_P1DMCR_TYPE_Msk (0x3UL << DCMIPP_P1DMCR_TYPE_Pos) /*!< 0x00000006 */
#define DCMIPP_P1DMCR_TYPE DCMIPP_P1DMCR_TYPE_Msk /*!< Raw Bayer type */
#define DCMIPP_P1DMCR_PEAK_Pos (16U)
#define DCMIPP_P1DMCR_PEAK_Msk (0x7UL << DCMIPP_P1DMCR_PEAK_Pos) /*!< 0x00070000 */
#define DCMIPP_P1DMCR_PEAK DCMIPP_P1DMCR_PEAK_Msk /*!< Strength of the peak detection */
#define DCMIPP_P1DMCR_LINEV_Pos (20U)
#define DCMIPP_P1DMCR_LINEV_Msk (0x7UL << DCMIPP_P1DMCR_LINEV_Pos) /*!< 0x00700000 */
#define DCMIPP_P1DMCR_LINEV DCMIPP_P1DMCR_LINEV_Msk /*!< Strength of the vertical line detection */
#define DCMIPP_P1DMCR_LINEH_Pos (24U)
#define DCMIPP_P1DMCR_LINEH_Msk (0x7UL << DCMIPP_P1DMCR_LINEH_Pos) /*!< 0x07000000 */
#define DCMIPP_P1DMCR_LINEH DCMIPP_P1DMCR_LINEH_Msk /*!< Strength of the horizontal line detection */
#define DCMIPP_P1DMCR_EDGE_Pos (28U)
#define DCMIPP_P1DMCR_EDGE_Msk (0x7UL << DCMIPP_P1DMCR_EDGE_Pos) /*!< 0x70000000 */
#define DCMIPP_P1DMCR_EDGE DCMIPP_P1DMCR_EDGE_Msk /*!< Strength of the edge detection */
/**************** Bit definition for DCMIPP_P1CCCR register *****************/
#define DCMIPP_P1CCCR_ENABLE_Pos (0U)
#define DCMIPP_P1CCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CCCR_ENABLE DCMIPP_P1CCCR_ENABLE_Msk /*!< */
#define DCMIPP_P1CCCR_TYPE_Pos (1U)
#define DCMIPP_P1CCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCR_TYPE_Pos) /*!< 0x00000002 */
#define DCMIPP_P1CCCR_TYPE DCMIPP_P1CCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */
#define DCMIPP_P1CCCR_CLAMP_Pos (2U)
#define DCMIPP_P1CCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCR_CLAMP_Pos) /*!< 0x00000004 */
#define DCMIPP_P1CCCR_CLAMP DCMIPP_P1CCCR_CLAMP_Msk /*!< Clamp the output samples */
/**************** Bit definition for DCMIPP_P1CCRR1 register ****************/
#define DCMIPP_P1CCRR1_RR_Pos (0U)
#define DCMIPP_P1CCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCRR1_RR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCRR1_RR DCMIPP_P1CCRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */
#define DCMIPP_P1CCRR1_RG_Pos (16U)
#define DCMIPP_P1CCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCRR1_RG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1CCRR1_RG DCMIPP_P1CCRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */
/**************** Bit definition for DCMIPP_P1CCRR2 register ****************/
#define DCMIPP_P1CCRR2_RB_Pos (0U)
#define DCMIPP_P1CCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCRR2_RB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCRR2_RB DCMIPP_P1CCRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */
#define DCMIPP_P1CCRR2_RA_Pos (16U)
#define DCMIPP_P1CCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCRR2_RA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1CCRR2_RA DCMIPP_P1CCRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */
/**************** Bit definition for DCMIPP_P1CCGR1 register ****************/
#define DCMIPP_P1CCGR1_GR_Pos (0U)
#define DCMIPP_P1CCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCGR1_GR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCGR1_GR DCMIPP_P1CCGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */
#define DCMIPP_P1CCGR1_GG_Pos (16U)
#define DCMIPP_P1CCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCGR1_GG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1CCGR1_GG DCMIPP_P1CCGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */
/**************** Bit definition for DCMIPP_P1CCGR2 register ****************/
#define DCMIPP_P1CCGR2_GB_Pos (0U)
#define DCMIPP_P1CCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCGR2_GB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCGR2_GB DCMIPP_P1CCGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */
#define DCMIPP_P1CCGR2_GA_Pos (16U)
#define DCMIPP_P1CCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCGR2_GA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1CCGR2_GA DCMIPP_P1CCGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */
/**************** Bit definition for DCMIPP_P1CCBR1 register ****************/
#define DCMIPP_P1CCBR1_BR_Pos (0U)
#define DCMIPP_P1CCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCBR1_BR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCBR1_BR DCMIPP_P1CCBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */
#define DCMIPP_P1CCBR1_BG_Pos (16U)
#define DCMIPP_P1CCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCBR1_BG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1CCBR1_BG DCMIPP_P1CCBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */
/**************** Bit definition for DCMIPP_P1CCBR2 register ****************/
#define DCMIPP_P1CCBR2_BB_Pos (0U)
#define DCMIPP_P1CCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCBR2_BB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCBR2_BB DCMIPP_P1CCBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */
#define DCMIPP_P1CCBR2_BA_Pos (16U)
#define DCMIPP_P1CCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCBR2_BA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1CCBR2_BA DCMIPP_P1CCBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */
/**************** Bit definition for DCMIPP_P1CTCR1 register ****************/
#define DCMIPP_P1CTCR1_ENABLE_Pos (0U)
#define DCMIPP_P1CTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CTCR1_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CTCR1_ENABLE DCMIPP_P1CTCR1_ENABLE_Msk /*!< */
#define DCMIPP_P1CTCR1_LUM0_Pos (9U)
#define DCMIPP_P1CTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CTCR1_LUM0_Pos) /*!< 0x00007E00 */
#define DCMIPP_P1CTCR1_LUM0 DCMIPP_P1CTCR1_LUM0_Msk /*!< Luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
/**************** Bit definition for DCMIPP_P1CTCR2 register ****************/
#define DCMIPP_P1CTCR2_LUM4_Pos (1U)
#define DCMIPP_P1CTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM4_Pos) /*!< 0x0000007E */
#define DCMIPP_P1CTCR2_LUM4 DCMIPP_P1CTCR2_LUM4_Msk /*!< Luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CTCR2_LUM3_Pos (9U)
#define DCMIPP_P1CTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM3_Pos) /*!< 0x00007E00 */
#define DCMIPP_P1CTCR2_LUM3 DCMIPP_P1CTCR2_LUM3_Msk /*!< Luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CTCR2_LUM2_Pos (17U)
#define DCMIPP_P1CTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM2_Pos) /*!< 0x007E0000 */
#define DCMIPP_P1CTCR2_LUM2 DCMIPP_P1CTCR2_LUM2_Msk /*!< Luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CTCR2_LUM1_Pos (25U)
#define DCMIPP_P1CTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CTCR2_LUM1_Pos) /*!< 0x7E000000 */
#define DCMIPP_P1CTCR2_LUM1 DCMIPP_P1CTCR2_LUM1_Msk /*!< Luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
/**************** Bit definition for DCMIPP_P1CTCR3 register ****************/
#define DCMIPP_P1CTCR3_LUM8_Pos (1U)
#define DCMIPP_P1CTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM8_Pos) /*!< 0x0000007E */
#define DCMIPP_P1CTCR3_LUM8 DCMIPP_P1CTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CTCR3_LUM7_Pos (9U)
#define DCMIPP_P1CTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM7_Pos) /*!< 0x00007E00 */
#define DCMIPP_P1CTCR3_LUM7 DCMIPP_P1CTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CTCR3_LUM6_Pos (17U)
#define DCMIPP_P1CTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM6_Pos) /*!< 0x007E0000 */
#define DCMIPP_P1CTCR3_LUM6 DCMIPP_P1CTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CTCR3_LUM5_Pos (25U)
#define DCMIPP_P1CTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CTCR3_LUM5_Pos) /*!< 0x7E000000 */
#define DCMIPP_P1CTCR3_LUM5 DCMIPP_P1CTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
/**************** Bit definition for DCMIPP_P1FCTCR register ****************/
#define DCMIPP_P1FCTCR_FRATE_Pos (0U)
#define DCMIPP_P1FCTCR_FRATE_Msk (0x3UL << DCMIPP_P1FCTCR_FRATE_Pos) /*!< 0x00000003 */
#define DCMIPP_P1FCTCR_FRATE DCMIPP_P1FCTCR_FRATE_Msk /*!< Frame capture rate control */
#define DCMIPP_P1FCTCR_CPTMODE_Pos (2U)
#define DCMIPP_P1FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1FCTCR_CPTMODE_Pos) /*!< 0x00000004 */
#define DCMIPP_P1FCTCR_CPTMODE DCMIPP_P1FCTCR_CPTMODE_Msk /*!< Capture mode */
#define DCMIPP_P1FCTCR_CPTREQ_Pos (3U)
#define DCMIPP_P1FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1FCTCR_CPTREQ_Pos) /*!< 0x00000008 */
#define DCMIPP_P1FCTCR_CPTREQ DCMIPP_P1FCTCR_CPTREQ_Msk /*!< Capture requested */
/**************** Bit definition for DCMIPP_P1CRSTR register ****************/
#define DCMIPP_P1CRSTR_HSTART_Pos (0U)
#define DCMIPP_P1CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1CRSTR_HSTART DCMIPP_P1CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */
#define DCMIPP_P1CRSTR_VSTART_Pos (16U)
#define DCMIPP_P1CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1CRSTR_VSTART DCMIPP_P1CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */
/**************** Bit definition for DCMIPP_P1CRSZR register ****************/
#define DCMIPP_P1CRSZR_HSIZE_Pos (0U)
#define DCMIPP_P1CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1CRSZR_HSIZE DCMIPP_P1CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P1CRSZR_VSIZE_Pos (16U)
#define DCMIPP_P1CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1CRSZR_VSIZE DCMIPP_P1CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P1CRSZR_ENABLE_Pos (31U)
#define DCMIPP_P1CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CRSZR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P1CRSZR_ENABLE DCMIPP_P1CRSZR_ENABLE_Msk /*!< */
/**************** Bit definition for DCMIPP_P1DCCR register *****************/
#define DCMIPP_P1DCCR_ENABLE_Pos (0U)
#define DCMIPP_P1DCCR_ENABLE_Msk (0x1UL << DCMIPP_P1DCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1DCCR_ENABLE DCMIPP_P1DCCR_ENABLE_Msk /*!< Decimation enable */
#define DCMIPP_P1DCCR_HDEC_Pos (1U)
#define DCMIPP_P1DCCR_HDEC_Msk (0x3UL << DCMIPP_P1DCCR_HDEC_Pos) /*!< 0x00000006 */
#define DCMIPP_P1DCCR_HDEC DCMIPP_P1DCCR_HDEC_Msk /*!< Horizontal decimation ratio */
#define DCMIPP_P1DCCR_VDEC_Pos (3U)
#define DCMIPP_P1DCCR_VDEC_Msk (0x3UL << DCMIPP_P1DCCR_VDEC_Pos) /*!< 0x00000018 */
#define DCMIPP_P1DCCR_VDEC DCMIPP_P1DCCR_VDEC_Msk /*!< Vertical decimation ratio */
/**************** Bit definition for DCMIPP_P1DSCR register *****************/
#define DCMIPP_P1DSCR_HDIV_Pos (0U)
#define DCMIPP_P1DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_HDIV_Pos) /*!< 0x000003FF */
#define DCMIPP_P1DSCR_HDIV DCMIPP_P1DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P1DSCR_VDIV_Pos (16U)
#define DCMIPP_P1DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1DSCR_VDIV_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1DSCR_VDIV DCMIPP_P1DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P1DSCR_ENABLE_Pos (31U)
#define DCMIPP_P1DSCR_ENABLE_Msk (0x1UL << DCMIPP_P1DSCR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P1DSCR_ENABLE DCMIPP_P1DSCR_ENABLE_Msk /*!< Downscaler Enable */
/*************** Bit definition for DCMIPP_P1DSRTIOR register ***************/
#define DCMIPP_P1DSRTIOR_HRATIO_Pos (0U)
#define DCMIPP_P1DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */
#define DCMIPP_P1DSRTIOR_HRATIO DCMIPP_P1DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
#define DCMIPP_P1DSRTIOR_VRATIO_Pos (16U)
#define DCMIPP_P1DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */
#define DCMIPP_P1DSRTIOR_VRATIO DCMIPP_P1DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
/**************** Bit definition for DCMIPP_P1DSSZR register ****************/
#define DCMIPP_P1DSSZR_HSIZE_Pos (0U)
#define DCMIPP_P1DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1DSSZR_HSIZE DCMIPP_P1DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P1DSSZR_VSIZE_Pos (16U)
#define DCMIPP_P1DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1DSSZR_VSIZE DCMIPP_P1DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */
/*************** Bit definition for DCMIPP_P1CMRICR register ***************/
#define DCMIPP_P1CMRICR_ROILSZ_Pos (0U)
#define DCMIPP_P1CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P1CMRICR_ROILSZ_Pos) /*!< 0x00000003 */
#define DCMIPP_P1CMRICR_ROILSZ DCMIPP_P1CMRICR_ROILSZ_Msk /*!< Region of interest line size width */
#define DCMIPP_P1CMRICR_ROI1EN_Pos (16U)
#define DCMIPP_P1CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI1EN_Pos) /*!< 0x00010000 */
#define DCMIPP_P1CMRICR_ROI1EN DCMIPP_P1CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */
#define DCMIPP_P1CMRICR_ROI2EN_Pos (17U)
#define DCMIPP_P1CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI2EN_Pos) /*!< 0x00020000 */
#define DCMIPP_P1CMRICR_ROI2EN DCMIPP_P1CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */
#define DCMIPP_P1CMRICR_ROI3EN_Pos (18U)
#define DCMIPP_P1CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI3EN_Pos) /*!< 0x00040000 */
#define DCMIPP_P1CMRICR_ROI3EN DCMIPP_P1CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */
#define DCMIPP_P1CMRICR_ROI4EN_Pos (19U)
#define DCMIPP_P1CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI4EN_Pos) /*!< 0x00080000 */
#define DCMIPP_P1CMRICR_ROI4EN DCMIPP_P1CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */
#define DCMIPP_P1CMRICR_ROI5EN_Pos (20U)
#define DCMIPP_P1CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI5EN_Pos) /*!< 0x00100000 */
#define DCMIPP_P1CMRICR_ROI5EN DCMIPP_P1CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */
#define DCMIPP_P1CMRICR_ROI6EN_Pos (21U)
#define DCMIPP_P1CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI6EN_Pos) /*!< 0x00200000 */
#define DCMIPP_P1CMRICR_ROI6EN DCMIPP_P1CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */
#define DCMIPP_P1CMRICR_ROI7EN_Pos (22U)
#define DCMIPP_P1CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI7EN_Pos) /*!< 0x00400000 */
#define DCMIPP_P1CMRICR_ROI7EN DCMIPP_P1CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */
#define DCMIPP_P1CMRICR_ROI8EN_Pos (23U)
#define DCMIPP_P1CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P1CMRICR_ROI8EN_Pos) /*!< 0x00800000 */
#define DCMIPP_P1CMRICR_ROI8EN DCMIPP_P1CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */
/*************** Bit definition for DCMIPP_P1RIxCR1 register ***************/
#define DCMIPP_P1RIxCR1_HSTART_Pos (0U)
#define DCMIPP_P1RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1RIxCR1_HSTART DCMIPP_P1RIxCR1_HSTART_Msk /*!< Horizontal start */
#define DCMIPP_P1RIxCR1_CLB_Pos (12U)
#define DCMIPP_P1RIxCR1_CLB_Msk (0x3UL << DCMIPP_P1RIxCR1_CLB_Pos) /*!< 0x00003000 */
#define DCMIPP_P1RIxCR1_CLB DCMIPP_P1RIxCR1_CLB_Msk /*!< Color line blue */
#define DCMIPP_P1RIxCR1_CLG_Pos (14U)
#define DCMIPP_P1RIxCR1_CLG_Msk (0x3UL << DCMIPP_P1RIxCR1_CLG_Pos) /*!< 0x0000C000 */
#define DCMIPP_P1RIxCR1_CLG DCMIPP_P1RIxCR1_CLG_Msk /*!< Color line green */
#define DCMIPP_P1RIxCR1_VSTART_Pos (16U)
#define DCMIPP_P1RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P1RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1RIxCR1_VSTART DCMIPP_P1RIxCR1_VSTART_Msk /*!< Vertical start */
#define DCMIPP_P1RIxCR1_CLR_Pos (28U)
#define DCMIPP_P1RIxCR1_CLR_Msk (0x3UL << DCMIPP_P1RIxCR1_CLR_Pos) /*!< 0x30000000 */
#define DCMIPP_P1RIxCR1_CLR DCMIPP_P1RIxCR1_CLR_Msk /*!< Color line red */
/*************** Bit definition for DCMIPP_P1RIxCR2 register ***************/
#define DCMIPP_P1RIxCR2_VSIZE_Pos (0U)
#define DCMIPP_P1RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1RIxCR2_VSIZE DCMIPP_P1RIxCR2_VSIZE_Msk /*!< Vertical Size */
#define DCMIPP_P1RIxCR2_HSIZE_Pos (16U)
#define DCMIPP_P1RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P1RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */
#define DCMIPP_P1RIxCR2_HSIZE DCMIPP_P1RIxCR2_HSIZE_Msk /*!< Horizontal Size */
/**************** Bit definition for DCMIPP_P1GMCR register *****************/
#define DCMIPP_P1GMCR_ENABLE_Pos (0U)
#define DCMIPP_P1GMCR_ENABLE_Msk (0x1UL << DCMIPP_P1GMCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1GMCR_ENABLE DCMIPP_P1GMCR_ENABLE_Msk /*!< Gamma enable*/
/**************** Bit definition for DCMIPP_P1YUVCR register ****************/
#define DCMIPP_P1YUVCR_ENABLE_Pos (0U)
#define DCMIPP_P1YUVCR_ENABLE_Msk (0x1UL << DCMIPP_P1YUVCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1YUVCR_ENABLE DCMIPP_P1YUVCR_ENABLE_Msk /*!< */
#define DCMIPP_P1YUVCR_TYPE_Pos (1U)
#define DCMIPP_P1YUVCR_TYPE_Msk (0x1UL << DCMIPP_P1YUVCR_TYPE_Pos) /*!< 0x00000002 */
#define DCMIPP_P1YUVCR_TYPE DCMIPP_P1YUVCR_TYPE_Msk /*!< Output samples type used while CLAMP is activated */
#define DCMIPP_P1YUVCR_CLAMP_Pos (2U)
#define DCMIPP_P1YUVCR_CLAMP_Msk (0x1UL << DCMIPP_P1YUVCR_CLAMP_Pos) /*!< 0x00000004 */
#define DCMIPP_P1YUVCR_CLAMP DCMIPP_P1YUVCR_CLAMP_Msk /*!< Clamp the output samples */
/*************** Bit definition for DCMIPP_P1YUVRR1 register ****************/
#define DCMIPP_P1YUVRR1_RR_Pos (0U)
#define DCMIPP_P1YUVRR1_RR_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1YUVRR1_RR DCMIPP_P1YUVRR1_RR_Msk /*!< Coefficient row 1 column 1 of the matrix */
#define DCMIPP_P1YUVRR1_RG_Pos (16U)
#define DCMIPP_P1YUVRR1_RG_Msk (0x7FFUL << DCMIPP_P1YUVRR1_RG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1YUVRR1_RG DCMIPP_P1YUVRR1_RG_Msk /*!< Coefficient row 1 column 2 of the matrix */
/*************** Bit definition for DCMIPP_P1YUVRR2 register ****************/
#define DCMIPP_P1YUVRR2_RB_Pos (0U)
#define DCMIPP_P1YUVRR2_RB_Msk (0x7FFUL << DCMIPP_P1YUVRR2_RB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1YUVRR2_RB DCMIPP_P1YUVRR2_RB_Msk /*!< Coefficient row 1 column 3 of the matrix */
#define DCMIPP_P1YUVRR2_RA_Pos (16U)
#define DCMIPP_P1YUVRR2_RA_Msk (0x3FFUL << DCMIPP_P1YUVRR2_RA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1YUVRR2_RA DCMIPP_P1YUVRR2_RA_Msk /*!< Coefficient row 1 of the added column (signed integer value) */
/*************** Bit definition for DCMIPP_P1YUVGR1 register ****************/
#define DCMIPP_P1YUVGR1_GR_Pos (0U)
#define DCMIPP_P1YUVGR1_GR_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1YUVGR1_GR DCMIPP_P1YUVGR1_GR_Msk /*!< Coefficient row 2 column 1 of the matrix */
#define DCMIPP_P1YUVGR1_GG_Pos (16U)
#define DCMIPP_P1YUVGR1_GG_Msk (0x7FFUL << DCMIPP_P1YUVGR1_GG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1YUVGR1_GG DCMIPP_P1YUVGR1_GG_Msk /*!< Coefficient row 2 column 2 of the matrix */
/*************** Bit definition for DCMIPP_P1YUVGR2 register ****************/
#define DCMIPP_P1YUVGR2_GB_Pos (0U)
#define DCMIPP_P1YUVGR2_GB_Msk (0x7FFUL << DCMIPP_P1YUVGR2_GB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1YUVGR2_GB DCMIPP_P1YUVGR2_GB_Msk /*!< Coefficient row 2 column 3 of the matrix */
#define DCMIPP_P1YUVGR2_GA_Pos (16U)
#define DCMIPP_P1YUVGR2_GA_Msk (0x3FFUL << DCMIPP_P1YUVGR2_GA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1YUVGR2_GA DCMIPP_P1YUVGR2_GA_Msk /*!< Coefficient row 2 of the added column (signed integer value) */
/*************** Bit definition for DCMIPP_P1YUVBR1 register ****************/
#define DCMIPP_P1YUVBR1_BR_Pos (0U)
#define DCMIPP_P1YUVBR1_BR_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1YUVBR1_BR DCMIPP_P1YUVBR1_BR_Msk /*!< Coefficient row 3 column 1 of the matrix */
#define DCMIPP_P1YUVBR1_BG_Pos (16U)
#define DCMIPP_P1YUVBR1_BG_Msk (0x7FFUL << DCMIPP_P1YUVBR1_BG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1YUVBR1_BG DCMIPP_P1YUVBR1_BG_Msk /*!< Coefficient row 3 column 2 of the matrix */
/*************** Bit definition for DCMIPP_P1YUVBR2 register ****************/
#define DCMIPP_P1YUVBR2_BB_Pos (0U)
#define DCMIPP_P1YUVBR2_BB_Msk (0x7FFUL << DCMIPP_P1YUVBR2_BB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1YUVBR2_BB DCMIPP_P1YUVBR2_BB_Msk /*!< Coefficient row 3 column 3 of the matrix */
#define DCMIPP_P1YUVBR2_BA_Pos (16U)
#define DCMIPP_P1YUVBR2_BA_Msk (0x3FFUL << DCMIPP_P1YUVBR2_BA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1YUVBR2_BA DCMIPP_P1YUVBR2_BA_Msk /*!< Coefficient row 3 of the added column (signed integer value) */
/**************** Bit definition for DCMIPP_P1PPCR register *****************/
#define DCMIPP_P1PPCR_FORMAT_Pos (0U)
#define DCMIPP_P1PPCR_FORMAT_Msk (0xFUL << DCMIPP_P1PPCR_FORMAT_Pos) /*!< 0x0000000F */
#define DCMIPP_P1PPCR_FORMAT DCMIPP_P1PPCR_FORMAT_Msk /*!< Memory format */
#define DCMIPP_P1PPCR_SWAPRB_Pos (4U)
#define DCMIPP_P1PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1PPCR_SWAPRB_Pos) /*!< 0x00000010 */
#define DCMIPP_P1PPCR_SWAPRB DCMIPP_P1PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
#define DCMIPP_P1PPCR_LINEMULT_Pos (13U)
#define DCMIPP_P1PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1PPCR_LINEMULT_Pos) /*!< 0x0000E000 */
#define DCMIPP_P1PPCR_LINEMULT DCMIPP_P1PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */
#define DCMIPP_P1PPCR_DBM_Pos (16U)
#define DCMIPP_P1PPCR_DBM_Msk (0x1UL << DCMIPP_P1PPCR_DBM_Pos) /*!< 0x00010000 */
#define DCMIPP_P1PPCR_DBM DCMIPP_P1PPCR_DBM_Msk /*!< Double buffer mode */
#define DCMIPP_P1PPCR_LMAWM_Pos (17U)
#define DCMIPP_P1PPCR_LMAWM_Msk (0x7UL << DCMIPP_P1PPCR_LMAWM_Pos) /*!< 0x000E0000 */
#define DCMIPP_P1PPCR_LMAWM DCMIPP_P1PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */
#define DCMIPP_P1PPCR_LMAWE_Pos (20U)
#define DCMIPP_P1PPCR_LMAWE_Msk (0x1UL << DCMIPP_P1PPCR_LMAWE_Pos) /*!< 0x00100000 */
#define DCMIPP_P1PPCR_LMAWE DCMIPP_P1PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */
/*************** Bit definition for DCMIPP_P1PPM0AR1 register ***************/
#define DCMIPP_P1PPM0AR1_M0A_Pos (0U)
#define DCMIPP_P1PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1PPM0AR1_M0A DCMIPP_P1PPM0AR1_M0A_Msk /*!< Memory0 address register 1*/
/*************** Bit definition for DCMIPP_P1PPM0AR2 register ***************/
#define DCMIPP_P1PPM0AR2_M0A_Pos (0U)
#define DCMIPP_P1PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1PPM0AR2_M0A DCMIPP_P1PPM0AR2_M0A_Msk /*!< Memory0 address register 2 */
/*************** Bit definition for DCMIPP_P1PPM0PR register ****************/
#define DCMIPP_P1PPM0PR_PITCH_Pos (0U)
#define DCMIPP_P1PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM0PR_PITCH_Pos) /*!< 0x00007FFF */
#define DCMIPP_P1PPM0PR_PITCH DCMIPP_P1PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */
/*************** Bit definition for DCMIPP_P1PPM1AR1 register ***************/
#define DCMIPP_P1PPM1AR1_M1A_Pos (0U)
#define DCMIPP_P1PPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1PPM1AR1_M1A DCMIPP_P1PPM1AR1_M1A_Msk /*!< Memory1 address */
/*************** Bit definition for DCMIPP_P1PPM1AR2 register ***************/
#define DCMIPP_P1PPM1AR2_M1A_Pos (0U)
#define DCMIPP_P1PPM1AR2_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM1AR2_M1A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1PPM1AR2_M1A DCMIPP_P1PPM1AR2_M1A_Msk /*!< Memory1 address */
/*************** Bit definition for DCMIPP_P1PPM1PR register ****************/
#define DCMIPP_P1PPM1PR_PITCH_Pos (0U)
#define DCMIPP_P1PPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1PPM1PR_PITCH_Pos) /*!< 0x00007FFF */
#define DCMIPP_P1PPM1PR_PITCH DCMIPP_P1PPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */
/*************** Bit definition for DCMIPP_P1STM1AR register ****************/
#define DCMIPP_P1STM1AR_M1A_Pos (0U)
#define DCMIPP_P1STM1AR_M1A_Msk (0x7FFFUL << DCMIPP_P1STM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1STM1AR_M1A DCMIPP_P1STM1AR_M1A_Msk /*!< status Memory1 address register */
/*************** Bit definition for DCMIPP_P1PPM2AR1 register ***************/
#define DCMIPP_P1PPM2AR1_M2A_Pos (0U)
#define DCMIPP_P1PPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1PPM2AR1_M2A DCMIPP_P1PPM2AR1_M2A_Msk /*!< Memory2 address register 1*/
/*************** Bit definition for DCMIPP_P1PPM2AR2 register ***************/
#define DCMIPP_P1PPM2AR2_M2A_Pos (0U)
#define DCMIPP_P1PPM2AR2_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1PPM2AR2_M2A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1PPM2AR2_M2A DCMIPP_P1PPM2AR2_M2A_Msk /*!< Memory2 address register 2 */
/*************** Bit definition for DCMIPP_P1STM2AR register ****************/
#define DCMIPP_P1STM2AR_M2A_Pos (0U)
#define DCMIPP_P1STM2AR_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1STM2AR_M2A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1STM2AR_M2A DCMIPP_P1STM2AR_M2A_Msk /*!< status Memory2 address register */
/***************** Bit definition for DCMIPP_P1IER register *****************/
#define DCMIPP_P1IER_LINEIE_Pos (0U)
#define DCMIPP_P1IER_LINEIE_Msk (0x1UL << DCMIPP_P1IER_LINEIE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1IER_LINEIE DCMIPP_P1IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */
#define DCMIPP_P1IER_FRAMEIE_Pos (1U)
#define DCMIPP_P1IER_FRAMEIE_Msk (0x1UL << DCMIPP_P1IER_FRAMEIE_Pos) /*!< 0x00000002 */
#define DCMIPP_P1IER_FRAMEIE DCMIPP_P1IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */
#define DCMIPP_P1IER_VSYNCIE_Pos (2U)
#define DCMIPP_P1IER_VSYNCIE_Msk (0x1UL << DCMIPP_P1IER_VSYNCIE_Pos) /*!< 0x00000004 */
#define DCMIPP_P1IER_VSYNCIE DCMIPP_P1IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */
#define DCMIPP_P1IER_OVRIE_Pos (7U)
#define DCMIPP_P1IER_OVRIE_Msk (0x1UL << DCMIPP_P1IER_OVRIE_Pos) /*!< 0x00000080 */
#define DCMIPP_P1IER_OVRIE DCMIPP_P1IER_OVRIE_Msk /*!< Overrun interrupt enable */
/***************** Bit definition for DCMIPP_P1SR register ******************/
#define DCMIPP_P1SR_LINEF_Pos (0U)
#define DCMIPP_P1SR_LINEF_Msk (0x1UL << DCMIPP_P1SR_LINEF_Pos) /*!< 0x00000001 */
#define DCMIPP_P1SR_LINEF DCMIPP_P1SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */
#define DCMIPP_P1SR_FRAMEF_Pos (1U)
#define DCMIPP_P1SR_FRAMEF_Msk (0x1UL << DCMIPP_P1SR_FRAMEF_Pos) /*!< 0x00000002 */
#define DCMIPP_P1SR_FRAMEF DCMIPP_P1SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */
#define DCMIPP_P1SR_VSYNCF_Pos (2U)
#define DCMIPP_P1SR_VSYNCF_Msk (0x1UL << DCMIPP_P1SR_VSYNCF_Pos) /*!< 0x00000004 */
#define DCMIPP_P1SR_VSYNCF DCMIPP_P1SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */
#define DCMIPP_P1SR_OVRF_Pos (7U)
#define DCMIPP_P1SR_OVRF_Msk (0x1UL << DCMIPP_P1SR_OVRF_Pos) /*!< 0x00000080 */
#define DCMIPP_P1SR_OVRF DCMIPP_P1SR_OVRF_Msk /*!< Overrun raw interrupt status */
#define DCMIPP_P1SR_LSTLINE_Pos (16U)
#define DCMIPP_P1SR_LSTLINE_Msk (0x1UL << DCMIPP_P1SR_LSTLINE_Pos) /*!< 0x00010000 */
#define DCMIPP_P1SR_LSTLINE DCMIPP_P1SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */
#define DCMIPP_P1SR_LSTFRM_Pos (17U)
#define DCMIPP_P1SR_LSTFRM_Msk (0x1UL << DCMIPP_P1SR_LSTFRM_Pos) /*!< 0x00020000 */
#define DCMIPP_P1SR_LSTFRM DCMIPP_P1SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */
#define DCMIPP_P1SR_CPTACT_Pos (23U)
#define DCMIPP_P1SR_CPTACT_Msk (0x1UL << DCMIPP_P1SR_CPTACT_Pos) /*!< 0x00800000 */
#define DCMIPP_P1SR_CPTACT DCMIPP_P1SR_CPTACT_Msk /*!< Capture immediate status */
/***************** Bit definition for DCMIPP_P1FCR register *****************/
#define DCMIPP_P1FCR_CLINEF_Pos (0U)
#define DCMIPP_P1FCR_CLINEF_Msk (0x1UL << DCMIPP_P1FCR_CLINEF_Pos) /*!< 0x00000001 */
#define DCMIPP_P1FCR_CLINEF DCMIPP_P1FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */
#define DCMIPP_P1FCR_CFRAMEF_Pos (1U)
#define DCMIPP_P1FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P1FCR_CFRAMEF_Pos) /*!< 0x00000002 */
#define DCMIPP_P1FCR_CFRAMEF DCMIPP_P1FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */
#define DCMIPP_P1FCR_CVSYNCF_Pos (2U)
#define DCMIPP_P1FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P1FCR_CVSYNCF_Pos) /*!< 0x00000004 */
#define DCMIPP_P1FCR_CVSYNCF DCMIPP_P1FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */
#define DCMIPP_P1FCR_COVRF_Pos (7U)
#define DCMIPP_P1FCR_COVRF_Msk (0x1UL << DCMIPP_P1FCR_COVRF_Pos) /*!< 0x00000080 */
#define DCMIPP_P1FCR_COVRF DCMIPP_P1FCR_COVRF_Msk /*!< Overrun interrupt status clear */
/**************** Bit definition for DCMIPP_P1CFSCR register ****************/
#define DCMIPP_P1CFSCR_DTIDA_Pos (0U)
#define DCMIPP_P1CFSCR_DTIDA_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDA_Pos) /*!< 0x0000003F */
#define DCMIPP_P1CFSCR_DTIDA DCMIPP_P1CFSCR_DTIDA_Msk /*!< Current Data type ID A */
#define DCMIPP_P1CFSCR_DTIDB_Pos (8U)
#define DCMIPP_P1CFSCR_DTIDB_Msk (0x3FUL << DCMIPP_P1CFSCR_DTIDB_Pos) /*!< 0x00003F00 */
#define DCMIPP_P1CFSCR_DTIDB DCMIPP_P1CFSCR_DTIDB_Msk /*!< Current Data type ID B */
#define DCMIPP_P1CFSCR_DTMODE_Pos (16U)
#define DCMIPP_P1CFSCR_DTMODE_Msk (0x3UL << DCMIPP_P1CFSCR_DTMODE_Pos) /*!< 0x00030000 */
#define DCMIPP_P1CFSCR_DTMODE DCMIPP_P1CFSCR_DTMODE_Msk /*!< Flow selection mode */
#define DCMIPP_P1CFSCR_PIPEDIFF_Pos (18U)
#define DCMIPP_P1CFSCR_PIPEDIFF_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEDIFF_Pos) /*!< 0x00040000 */
#define DCMIPP_P1CFSCR_PIPEDIFF DCMIPP_P1CFSCR_PIPEDIFF_Msk /*!< Current differentiates Pipe2 vs */
#define DCMIPP_P1CFSCR_VC_Pos (19U)
#define DCMIPP_P1CFSCR_VC_Msk (0x3UL << DCMIPP_P1CFSCR_VC_Pos) /*!< 0x00180000 */
#define DCMIPP_P1CFSCR_VC DCMIPP_P1CFSCR_VC_Msk /*!< Current flow selection mode */
#define DCMIPP_P1CFSCR_FDTF_Pos (24U)
#define DCMIPP_P1CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P1CFSCR_FDTF_Pos) /*!< 0x3F000000 */
#define DCMIPP_P1CFSCR_FDTF DCMIPP_P1CFSCR_FDTF_Msk /*!< Current force Data type format */
#define DCMIPP_P1CFSCR_FDTFEN_Pos (30U)
#define DCMIPP_P1CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P1CFSCR_FDTFEN_Pos) /*!< 0x40000000 */
#define DCMIPP_P1CFSCR_FDTFEN DCMIPP_P1CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */
#define DCMIPP_P1CFSCR_PIPEN_Pos (31U)
#define DCMIPP_P1CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P1CFSCR_PIPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P1CFSCR_PIPEN DCMIPP_P1CFSCR_PIPEN_Msk /*!< Current activation of PipeN */
/*************** Bit definition for DCMIPP_P1CBPRCR register ****************/
#define DCMIPP_P1CBPRCR_ENABLE_Pos (0U)
#define DCMIPP_P1CBPRCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBPRCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CBPRCR_ENABLE DCMIPP_P1CBPRCR_ENABLE_Msk /*!< Current status of enable bit */
#define DCMIPP_P1CBPRCR_STRENGTH_Pos (1U)
#define DCMIPP_P1CBPRCR_STRENGTH_Msk (0x7UL << DCMIPP_P1CBPRCR_STRENGTH_Pos) /*!< 0x0000000E */
#define DCMIPP_P1CBPRCR_STRENGTH DCMIPP_P1CBPRCR_STRENGTH_Msk /*!< Current strength (aggressivity) of the bad pixel detection: */
/*************** Bit definition for DCMIPP_P1CBLCCR register ****************/
#define DCMIPP_P1CBLCCR_ENABLE_Pos (0U)
#define DCMIPP_P1CBLCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CBLCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CBLCCR_ENABLE DCMIPP_P1CBLCCR_ENABLE_Msk /*!< For current black level calibration */
#define DCMIPP_P1CBLCCR_BLCB_Pos (8U)
#define DCMIPP_P1CBLCCR_BLCB_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCB_Pos) /*!< 0x0000FF00 */
#define DCMIPP_P1CBLCCR_BLCB DCMIPP_P1CBLCCR_BLCB_Msk /*!< Current black level calibration - Blue */
#define DCMIPP_P1CBLCCR_BLCG_Pos (16U)
#define DCMIPP_P1CBLCCR_BLCG_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCG_Pos) /*!< 0x00FF0000 */
#define DCMIPP_P1CBLCCR_BLCG DCMIPP_P1CBLCCR_BLCG_Msk /*!< Current black level calibration - Green */
#define DCMIPP_P1CBLCCR_BLCR_Pos (24U)
#define DCMIPP_P1CBLCCR_BLCR_Msk (0xFFUL << DCMIPP_P1CBLCCR_BLCR_Pos) /*!< 0xFF000000 */
#define DCMIPP_P1CBLCCR_BLCR DCMIPP_P1CBLCCR_BLCR_Msk /*!< Current black level calibration - Red */
/*************** Bit definition for DCMIPP_P1CEXCR1 register ****************/
#define DCMIPP_P1CEXCR1_ENABLE_Pos (0U)
#define DCMIPP_P1CEXCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CEXCR1_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CEXCR1_ENABLE DCMIPP_P1CEXCR1_ENABLE_Msk /*!< for exposure control (multiplication and shift) */
#define DCMIPP_P1CEXCR1_MULTR_Pos (20U)
#define DCMIPP_P1CEXCR1_MULTR_Msk (0xFFUL << DCMIPP_P1CEXCR1_MULTR_Pos) /*!< 0x0FF00000 */
#define DCMIPP_P1CEXCR1_MULTR DCMIPP_P1CEXCR1_MULTR_Msk /*!< Current exposure multiplier - Red */
#define DCMIPP_P1CEXCR1_SHFR_Pos (28U)
#define DCMIPP_P1CEXCR1_SHFR_Msk (0x7UL << DCMIPP_P1CEXCR1_SHFR_Pos) /*!< 0x70000000 */
#define DCMIPP_P1CEXCR1_SHFR DCMIPP_P1CEXCR1_SHFR_Msk /*!< Current exposure shift - Red */
/*************** Bit definition for DCMIPP_P1CEXCR2 register ****************/
#define DCMIPP_P1CEXCR2_MULTB_Pos (4U)
#define DCMIPP_P1CEXCR2_MULTB_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTB_Pos) /*!< 0x00000FF0 */
#define DCMIPP_P1CEXCR2_MULTB DCMIPP_P1CEXCR2_MULTB_Msk /*!< Current exposure multiplier - Blue */
#define DCMIPP_P1CEXCR2_SHFB_Pos (12U)
#define DCMIPP_P1CEXCR2_SHFB_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFB_Pos) /*!< 0x00007000 */
#define DCMIPP_P1CEXCR2_SHFB DCMIPP_P1CEXCR2_SHFB_Msk /*!< Current exposure shift - Blue */
#define DCMIPP_P1CEXCR2_MULTG_Pos (20U)
#define DCMIPP_P1CEXCR2_MULTG_Msk (0xFFUL << DCMIPP_P1CEXCR2_MULTG_Pos) /*!< 0x0FF00000 */
#define DCMIPP_P1CEXCR2_MULTG DCMIPP_P1CEXCR2_MULTG_Msk /*!< Current exposure multiplier - Green */
#define DCMIPP_P1CEXCR2_SHFG_Pos (28U)
#define DCMIPP_P1CEXCR2_SHFG_Msk (0x7UL << DCMIPP_P1CEXCR2_SHFG_Pos) /*!< 0x70000000 */
#define DCMIPP_P1CEXCR2_SHFG DCMIPP_P1CEXCR2_SHFG_Msk /*!< Current exposure shift - Green */
/*************** Bit definition for DCMIPP_P1CST1CR register ****************/
#define DCMIPP_P1CST1CR_ENABLE_Pos (0U)
#define DCMIPP_P1CST1CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST1CR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CST1CR_ENABLE DCMIPP_P1CST1CR_ENABLE_Msk /*!< Current enable bit value */
#define DCMIPP_P1CST1CR_BINS_Pos (2U)
#define DCMIPP_P1CST1CR_BINS_Msk (0x3UL << DCMIPP_P1CST1CR_BINS_Pos) /*!< 0x0000000C */
#define DCMIPP_P1CST1CR_BINS DCMIPP_P1CST1CR_BINS_Msk /*!< Current bin definition */
#define DCMIPP_P1CST1CR_SRC_Pos (4U)
#define DCMIPP_P1CST1CR_SRC_Msk (0x7UL << DCMIPP_P1CST1CR_SRC_Pos) /*!< 0x00000070 */
#define DCMIPP_P1CST1CR_SRC DCMIPP_P1CST1CR_SRC_Msk /*!< Current source of statistics */
#define DCMIPP_P1CST1CR_MODE_Pos (7U)
#define DCMIPP_P1CST1CR_MODE_Msk (0x1UL << DCMIPP_P1CST1CR_MODE_Pos) /*!< 0x00000080 */
#define DCMIPP_P1CST1CR_MODE DCMIPP_P1CST1CR_MODE_Msk /*!< Current statistics mode */
#define DCMIPP_P1CST1CR_ACCU_Pos (8U)
#define DCMIPP_P1CST1CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST1CR_ACCU_Pos) /*!< 0xFFFFFF00 */
#define DCMIPP_P1CST1CR_ACCU DCMIPP_P1CST1CR_ACCU_Msk /*!< Current accumulation result, divided by 256 */
/*************** Bit definition for DCMIPP_P1CST2CR register ****************/
#define DCMIPP_P1CST2CR_ENABLE_Pos (0U)
#define DCMIPP_P1CST2CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST2CR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CST2CR_ENABLE DCMIPP_P1CST2CR_ENABLE_Msk /*!< */
#define DCMIPP_P1CST2CR_BINS_Pos (2U)
#define DCMIPP_P1CST2CR_BINS_Msk (0x3UL << DCMIPP_P1CST2CR_BINS_Pos) /*!< 0x0000000C */
#define DCMIPP_P1CST2CR_BINS DCMIPP_P1CST2CR_BINS_Msk /*!< Bin definition */
#define DCMIPP_P1CST2CR_SRC_Pos (4U)
#define DCMIPP_P1CST2CR_SRC_Msk (0x7UL << DCMIPP_P1CST2CR_SRC_Pos) /*!< 0x00000070 */
#define DCMIPP_P1CST2CR_SRC DCMIPP_P1CST2CR_SRC_Msk /*!< source of stat */
#define DCMIPP_P1CST2CR_MODE_Pos (7U)
#define DCMIPP_P1CST2CR_MODE_Msk (0x1UL << DCMIPP_P1CST2CR_MODE_Pos) /*!< 0x00000080 */
#define DCMIPP_P1CST2CR_MODE DCMIPP_P1CST2CR_MODE_Msk /*!< statistics mode */
#define DCMIPP_P1CST2CR_ACCU_Pos (8U)
#define DCMIPP_P1CST2CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST2CR_ACCU_Pos) /*!< 0xFFFFFF00 */
#define DCMIPP_P1CST2CR_ACCU DCMIPP_P1CST2CR_ACCU_Msk /*!< Accumulation result, divided by 256 */
/*************** Bit definition for DCMIPP_P1CST3CR register ****************/
#define DCMIPP_P1CST3CR_ENABLE_Pos (0U)
#define DCMIPP_P1CST3CR_ENABLE_Msk (0x1UL << DCMIPP_P1CST3CR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CST3CR_ENABLE DCMIPP_P1CST3CR_ENABLE_Msk /*!< */
#define DCMIPP_P1CST3CR_BINS_Pos (2U)
#define DCMIPP_P1CST3CR_BINS_Msk (0x3UL << DCMIPP_P1CST3CR_BINS_Pos) /*!< 0x0000000C */
#define DCMIPP_P1CST3CR_BINS DCMIPP_P1CST3CR_BINS_Msk /*!< Bin definition */
#define DCMIPP_P1CST3CR_SRC_Pos (4U)
#define DCMIPP_P1CST3CR_SRC_Msk (0x7UL << DCMIPP_P1CST3CR_SRC_Pos) /*!< 0x00000070 */
#define DCMIPP_P1CST3CR_SRC DCMIPP_P1CST3CR_SRC_Msk /*!< Statistics source */
#define DCMIPP_P1CST3CR_MODE_Pos (7U)
#define DCMIPP_P1CST3CR_MODE_Msk (0x1UL << DCMIPP_P1CST3CR_MODE_Pos) /*!< 0x00000080 */
#define DCMIPP_P1CST3CR_MODE DCMIPP_P1CST3CR_MODE_Msk /*!< Statistics mode */
#define DCMIPP_P1CST3CR_ACCU_Pos (8U)
#define DCMIPP_P1CST3CR_ACCU_Msk (0xFFFFFFUL << DCMIPP_P1CST3CR_ACCU_Pos) /*!< 0xFFFFFF00 */
#define DCMIPP_P1CST3CR_ACCU DCMIPP_P1CST3CR_ACCU_Msk /*!< Accumulation result, divided by 256 */
/*************** Bit definition for DCMIPP_P1CSTSTR register ****************/
#define DCMIPP_P1CSTSTR_HSTART_Pos (0U)
#define DCMIPP_P1CSTSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1CSTSTR_HSTART DCMIPP_P1CSTSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */
#define DCMIPP_P1CSTSTR_VSTART_Pos (16U)
#define DCMIPP_P1CSTSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CSTSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1CSTSTR_VSTART DCMIPP_P1CSTSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */
/*************** Bit definition for DCMIPP_P1CSTSZR register ****************/
#define DCMIPP_P1CSTSZR_HSIZE_Pos (0U)
#define DCMIPP_P1CSTSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1CSTSZR_HSIZE DCMIPP_P1CSTSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P1CSTSZR_VSIZE_Pos (16U)
#define DCMIPP_P1CSTSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CSTSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1CSTSZR_VSIZE DCMIPP_P1CSTSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P1CSTSZR_CROPEN_Pos (31U)
#define DCMIPP_P1CSTSZR_CROPEN_Msk (0x1UL << DCMIPP_P1CSTSZR_CROPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P1CSTSZR_CROPEN DCMIPP_P1CSTSZR_CROPEN_Msk /*!< Current CROPEN bit value */
/**************** Bit definition for DCMIPP_P1CCCCR register ****************/
#define DCMIPP_P1CCCCR_ENABLE_Pos (0U)
#define DCMIPP_P1CCCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CCCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CCCCR_ENABLE DCMIPP_P1CCCCR_ENABLE_Msk /*!< This bit indicates the current value applied */
#define DCMIPP_P1CCCCR_TYPE_Pos (1U)
#define DCMIPP_P1CCCCR_TYPE_Msk (0x1UL << DCMIPP_P1CCCCR_TYPE_Pos) /*!< 0x00000002 */
#define DCMIPP_P1CCCCR_TYPE DCMIPP_P1CCCCR_TYPE_Msk /*!< output samples type used while CLAMP is activated */
#define DCMIPP_P1CCCCR_CLAMP_Pos (2U)
#define DCMIPP_P1CCCCR_CLAMP_Msk (0x1UL << DCMIPP_P1CCCCR_CLAMP_Pos) /*!< 0x00000004 */
#define DCMIPP_P1CCCCR_CLAMP DCMIPP_P1CCCCR_CLAMP_Msk /*!< Clamp the output samples */
/*************** Bit definition for DCMIPP_P1CCCRR1 register ****************/
#define DCMIPP_P1CCCRR1_RR_Pos (0U)
#define DCMIPP_P1CCCRR1_RR_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCCRR1_RR DCMIPP_P1CCCRR1_RR_Msk /*!< Current coefficient row 1 column 1 of the matrix */
#define DCMIPP_P1CCCRR1_RG_Pos (16U)
#define DCMIPP_P1CCCRR1_RG_Msk (0x7FFUL << DCMIPP_P1CCCRR1_RG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1CCCRR1_RG DCMIPP_P1CCCRR1_RG_Msk /*!< Current coefficient row 1 column 2 of the matrix */
/*************** Bit definition for DCMIPP_P1CCCRR2 register ****************/
#define DCMIPP_P1CCCRR2_RB_Pos (0U)
#define DCMIPP_P1CCCRR2_RB_Msk (0x7FFUL << DCMIPP_P1CCCRR2_RB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCCRR2_RB DCMIPP_P1CCCRR2_RB_Msk /*!< Current coefficient row 1 column 3 of the matrix */
#define DCMIPP_P1CCCRR2_RA_Pos (16U)
#define DCMIPP_P1CCCRR2_RA_Msk (0x3FFUL << DCMIPP_P1CCCRR2_RA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1CCCRR2_RA DCMIPP_P1CCCRR2_RA_Msk /*!< Current coefficient row 1 of the added column (signed integer value) */
/*************** Bit definition for DCMIPP_P1CCCGR1 register ****************/
#define DCMIPP_P1CCCGR1_GR_Pos (0U)
#define DCMIPP_P1CCCGR1_GR_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCCGR1_GR DCMIPP_P1CCCGR1_GR_Msk /*!< Current coefficient row 2 column 1 of the matrix */
#define DCMIPP_P1CCCGR1_GG_Pos (16U)
#define DCMIPP_P1CCCGR1_GG_Msk (0x7FFUL << DCMIPP_P1CCCGR1_GG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1CCCGR1_GG DCMIPP_P1CCCGR1_GG_Msk /*!< Current coefficient row 2 column 2 of the matrix */
/*************** Bit definition for DCMIPP_P1CCCGR2 register ****************/
#define DCMIPP_P1CCCGR2_GB_Pos (0U)
#define DCMIPP_P1CCCGR2_GB_Msk (0x7FFUL << DCMIPP_P1CCCGR2_GB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCCGR2_GB DCMIPP_P1CCCGR2_GB_Msk /*!< Current coefficient row 2 column 3 of the matrix */
#define DCMIPP_P1CCCGR2_GA_Pos (16U)
#define DCMIPP_P1CCCGR2_GA_Msk (0x3FFUL << DCMIPP_P1CCCGR2_GA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1CCCGR2_GA DCMIPP_P1CCCGR2_GA_Msk /*!< Current coefficient row 2 of the added column (signed integer value) */
/*************** Bit definition for DCMIPP_P1CCCBR1 register ****************/
#define DCMIPP_P1CCCBR1_BR_Pos (0U)
#define DCMIPP_P1CCCBR1_BR_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BR_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCCBR1_BR DCMIPP_P1CCCBR1_BR_Msk /*!< Current coefficient row 3 column 1 of the matrix */
#define DCMIPP_P1CCCBR1_BG_Pos (16U)
#define DCMIPP_P1CCCBR1_BG_Msk (0x7FFUL << DCMIPP_P1CCCBR1_BG_Pos) /*!< 0x07FF0000 */
#define DCMIPP_P1CCCBR1_BG DCMIPP_P1CCCBR1_BG_Msk /*!< Current coefficient row 3 column 2 of the matrix */
/*************** Bit definition for DCMIPP_P1CCCBR2 register ****************/
#define DCMIPP_P1CCCBR2_BB_Pos (0U)
#define DCMIPP_P1CCCBR2_BB_Msk (0x7FFUL << DCMIPP_P1CCCBR2_BB_Pos) /*!< 0x000007FF */
#define DCMIPP_P1CCCBR2_BB DCMIPP_P1CCCBR2_BB_Msk /*!< Current coefficient row 3 column 3 of the matrix */
#define DCMIPP_P1CCCBR2_BA_Pos (16U)
#define DCMIPP_P1CCCBR2_BA_Msk (0x3FFUL << DCMIPP_P1CCCBR2_BA_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1CCCBR2_BA DCMIPP_P1CCCBR2_BA_Msk /*!< Current coefficient row 3 of the added column (signed integer value) */
/*************** Bit definition for DCMIPP_P1CCTCR1 register ****************/
#define DCMIPP_P1CCTCR1_ENABLE_Pos (0U)
#define DCMIPP_P1CCTCR1_ENABLE_Msk (0x1UL << DCMIPP_P1CCTCR1_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CCTCR1_ENABLE DCMIPP_P1CCTCR1_ENABLE_Msk /*!< Current ENABLE bit value */
#define DCMIPP_P1CCTCR1_LUM0_Pos (9U)
#define DCMIPP_P1CCTCR1_LUM0_Msk (0x3FUL << DCMIPP_P1CCTCR1_LUM0_Pos) /*!< 0x00007E00 */
#define DCMIPP_P1CCTCR1_LUM0 DCMIPP_P1CCTCR1_LUM0_Msk /*!< Current luminance increase for input luminance of 0 (increase is idle with LUMx = 16) */
/*************** Bit definition for DCMIPP_P1CCTCR2 register ****************/
#define DCMIPP_P1CCTCR2_LUM4_Pos (1U)
#define DCMIPP_P1CCTCR2_LUM4_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM4_Pos) /*!< 0x0000007E */
#define DCMIPP_P1CCTCR2_LUM4 DCMIPP_P1CCTCR2_LUM4_Msk /*!< Current luminance increase for input luminance of 128 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CCTCR2_LUM3_Pos (9U)
#define DCMIPP_P1CCTCR2_LUM3_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM3_Pos) /*!< 0x00007E00 */
#define DCMIPP_P1CCTCR2_LUM3 DCMIPP_P1CCTCR2_LUM3_Msk /*!< Current luminance increase for input luminance of 96 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CCTCR2_LUM2_Pos (17U)
#define DCMIPP_P1CCTCR2_LUM2_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM2_Pos) /*!< 0x007E0000 */
#define DCMIPP_P1CCTCR2_LUM2 DCMIPP_P1CCTCR2_LUM2_Msk /*!< Current luminance increase for input luminance of 64 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CCTCR2_LUM1_Pos (25U)
#define DCMIPP_P1CCTCR2_LUM1_Msk (0x3FUL << DCMIPP_P1CCTCR2_LUM1_Pos) /*!< 0x7E000000 */
#define DCMIPP_P1CCTCR2_LUM1 DCMIPP_P1CCTCR2_LUM1_Msk /*!< Current luminance increase for input luminance of 32 (increase is idle with LUMx = 16) */
/*************** Bit definition for DCMIPP_P1CCTCR3 register ****************/
#define DCMIPP_P1CCTCR3_LUM8_Pos (1U)
#define DCMIPP_P1CCTCR3_LUM8_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM8_Pos) /*!< 0x0000007E */
#define DCMIPP_P1CCTCR3_LUM8 DCMIPP_P1CCTCR3_LUM8_Msk /*!< Luminance increase for input luminance of 256 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CCTCR3_LUM7_Pos (9U)
#define DCMIPP_P1CCTCR3_LUM7_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM7_Pos) /*!< 0x00007E00 */
#define DCMIPP_P1CCTCR3_LUM7 DCMIPP_P1CCTCR3_LUM7_Msk /*!< Luminance increase for input luminance of 224 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CCTCR3_LUM6_Pos (17U)
#define DCMIPP_P1CCTCR3_LUM6_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM6_Pos) /*!< 0x007E0000 */
#define DCMIPP_P1CCTCR3_LUM6 DCMIPP_P1CCTCR3_LUM6_Msk /*!< Luminance increase for input luminance of 192 (increase is idle with LUMx = 16) */
#define DCMIPP_P1CCTCR3_LUM5_Pos (25U)
#define DCMIPP_P1CCTCR3_LUM5_Msk (0x3FUL << DCMIPP_P1CCTCR3_LUM5_Pos) /*!< 0x7E000000 */
#define DCMIPP_P1CCTCR3_LUM5 DCMIPP_P1CCTCR3_LUM5_Msk /*!< Luminance increase for input luminance of 160 (increase is idle with LUMx = 16) */
/*************** Bit definition for DCMIPP_P1CFCTCR register ****************/
#define DCMIPP_P1CFCTCR_FRATE_Pos (0U)
#define DCMIPP_P1CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P1CFCTCR_FRATE_Pos) /*!< 0x00000003 */
#define DCMIPP_P1CFCTCR_FRATE DCMIPP_P1CFCTCR_FRATE_Msk /*!< Frame capture rate control */
#define DCMIPP_P1CFCTCR_CPTMODE_Pos (2U)
#define DCMIPP_P1CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */
#define DCMIPP_P1CFCTCR_CPTMODE DCMIPP_P1CFCTCR_CPTMODE_Msk /*!< Capture mode */
#define DCMIPP_P1CFCTCR_CPTREQ_Pos (3U)
#define DCMIPP_P1CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P1CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */
#define DCMIPP_P1CFCTCR_CPTREQ DCMIPP_P1CFCTCR_CPTREQ_Msk /*!< Capture requested */
/*************** Bit definition for DCMIPP_P1CCRSTR register ****************/
#define DCMIPP_P1CCRSTR_HSTART_Pos (0U)
#define DCMIPP_P1CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1CCRSTR_HSTART DCMIPP_P1CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */
#define DCMIPP_P1CCRSTR_VSTART_Pos (16U)
#define DCMIPP_P1CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P1CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1CCRSTR_VSTART DCMIPP_P1CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */
/*************** Bit definition for DCMIPP_P1CCRSZR register ****************/
#define DCMIPP_P1CCRSZR_HSIZE_Pos (0U)
#define DCMIPP_P1CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1CCRSZR_HSIZE DCMIPP_P1CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P1CCRSZR_VSIZE_Pos (16U)
#define DCMIPP_P1CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1CCRSZR_VSIZE DCMIPP_P1CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P1CCRSZR_ENABLE_Pos (31U)
#define DCMIPP_P1CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P1CCRSZR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P1CCRSZR_ENABLE DCMIPP_P1CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */
/**************** Bit definition for DCMIPP_P1CDCCR register *****************/
#define DCMIPP_P1CDCCR_ENABLE_Pos (0U)
#define DCMIPP_P1CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P1CDCCR_ENABLE DCMIPP_P1CDCCR_ENABLE_Msk /*!< Decimation enable */
#define DCMIPP_P1CDCCR_HDEC_Pos (1U)
#define DCMIPP_P1CDCCR_HDEC_Msk (0x3UL << DCMIPP_P1CDCCR_HDEC_Pos) /*!< 0x00000006 */
#define DCMIPP_P1CDCCR_HDEC DCMIPP_P1CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */
#define DCMIPP_P1CDCCR_VDEC_Pos (3U)
#define DCMIPP_P1CDCCR_VDEC_Msk (0x3UL << DCMIPP_P1CDCCR_VDEC_Pos) /*!< 0x00000018 */
#define DCMIPP_P1CDCCR_VDEC DCMIPP_P1CDCCR_VDEC_Msk /*!< Vertical decimation ratio */
/**************** Bit definition for DCMIPP_P1CDSCR register ****************/
#define DCMIPP_P1CDSCR_HDIV_Pos (0U)
#define DCMIPP_P1CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_HDIV_Pos) /*!< 0x000003FF */
#define DCMIPP_P1CDSCR_HDIV DCMIPP_P1CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P1CDSCR_VDIV_Pos (16U)
#define DCMIPP_P1CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P1CDSCR_VDIV_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P1CDSCR_VDIV DCMIPP_P1CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P1CDSCR_ENABLE_Pos (31U)
#define DCMIPP_P1CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P1CDSCR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P1CDSCR_ENABLE DCMIPP_P1CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */
/************** Bit definition for DCMIPP_P1CDSRTIOR register ***************/
#define DCMIPP_P1CDSRTIOR_HRATIO_Pos (0U)
#define DCMIPP_P1CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */
#define DCMIPP_P1CDSRTIOR_HRATIO DCMIPP_P1CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
#define DCMIPP_P1CDSRTIOR_VRATIO_Pos (16U)
#define DCMIPP_P1CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P1CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */
#define DCMIPP_P1CDSRTIOR_VRATIO DCMIPP_P1CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
/*************** Bit definition for DCMIPP_P1CDSSZR register ****************/
#define DCMIPP_P1CDSSZR_HSIZE_Pos (0U)
#define DCMIPP_P1CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P1CDSSZR_HSIZE DCMIPP_P1CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P1CDSSZR_VSIZE_Pos (16U)
#define DCMIPP_P1CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P1CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P1CDSSZR_VSIZE DCMIPP_P1CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */
/**************** Bit definition for DCMIPP_P1CPPCR register ****************/
#define DCMIPP_P1CPPCR_FORMAT_Pos (0U)
#define DCMIPP_P1CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P1CPPCR_FORMAT_Pos) /*!< 0x0000000F */
#define DCMIPP_P1CPPCR_FORMAT DCMIPP_P1CPPCR_FORMAT_Msk /*!< Memory format */
#define DCMIPP_P1CPPCR_SWAPRB_Pos (4U)
#define DCMIPP_P1CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P1CPPCR_SWAPRB_Pos) /*!< 0x00000010 */
#define DCMIPP_P1CPPCR_SWAPRB DCMIPP_P1CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and U-vs-V components if YUV */
#define DCMIPP_P1CPPCR_LINEMULT_Pos (13U)
#define DCMIPP_P1CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P1CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */
#define DCMIPP_P1CPPCR_LINEMULT DCMIPP_P1CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */
/************** Bit definition for DCMIPP_P1CPPM0AR1 register ***************/
#define DCMIPP_P1CPPM0AR1_M0A_Pos (0U)
#define DCMIPP_P1CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1CPPM0AR1_M0A DCMIPP_P1CPPM0AR1_M0A_Msk /*!< Memory0 address */
/*************** Bit definition for DCMIPP_P1CPPM0PR register ***************/
#define DCMIPP_P1CPPM0PR_PITCH_Pos (0U)
#define DCMIPP_P1CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */
#define DCMIPP_P1CPPM0PR_PITCH DCMIPP_P1CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */
/************** Bit definition for DCMIPP_P1CPPM1AR1 register ***************/
#define DCMIPP_P1CPPM1AR1_M1A_Pos (0U)
#define DCMIPP_P1CPPM1AR1_M1A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM1AR1_M1A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1CPPM1AR1_M1A DCMIPP_P1CPPM1AR1_M1A_Msk /*!< Memory1 address */
/*************** Bit definition for DCMIPP_P1CPPM1PR register ***************/
#define DCMIPP_P1CPPM1PR_PITCH_Pos (0U)
#define DCMIPP_P1CPPM1PR_PITCH_Msk (0x7FFFUL << DCMIPP_P1CPPM1PR_PITCH_Pos) /*!< 0x00007FFF */
#define DCMIPP_P1CPPM1PR_PITCH DCMIPP_P1CPPM1PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */
/************** Bit definition for DCMIPP_P1CPPM2AR1 register ***************/
#define DCMIPP_P1CPPM2AR1_M2A_Pos (0U)
#define DCMIPP_P1CPPM2AR1_M2A_Msk (0xFFFFFFFFUL << DCMIPP_P1CPPM2AR1_M2A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P1CPPM2AR1_M2A DCMIPP_P1CPPM2AR1_M2A_Msk /*!< Memory 2 address */
/**************** Bit definition for DCMIPP_P2FSCR register *****************/
#define DCMIPP_P2FSCR_DTIDA_Pos (0U)
#define DCMIPP_P2FSCR_DTIDA_Msk (0x3FUL << DCMIPP_P2FSCR_DTIDA_Pos) /*!< 0x0000003F */
#define DCMIPP_P2FSCR_DTIDA DCMIPP_P2FSCR_DTIDA_Msk /*!< Data type ID */
#define DCMIPP_P2FSCR_VC_Pos (19U)
#define DCMIPP_P2FSCR_VC_Msk (0x3UL << DCMIPP_P2FSCR_VC_Pos) /*!< 0x00180000 */
#define DCMIPP_P2FSCR_VC DCMIPP_P2FSCR_VC_Msk /*!< Flow selection mode */
#define DCMIPP_P2FSCR_FDTF_Pos (24U)
#define DCMIPP_P2FSCR_FDTF_Msk (0x3FUL << DCMIPP_P2FSCR_FDTF_Pos) /*!< 0x3F000000 */
#define DCMIPP_P2FSCR_FDTF DCMIPP_P2FSCR_FDTF_Msk /*!< Force Data type format */
#define DCMIPP_P2FSCR_FDTFEN_Pos (30U)
#define DCMIPP_P2FSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2FSCR_FDTFEN_Pos) /*!< 0x40000000 */
#define DCMIPP_P2FSCR_FDTFEN DCMIPP_P2FSCR_FDTFEN_Msk /*!< Force Data type format enable */
#define DCMIPP_P2FSCR_PIPEN_Pos (31U)
#define DCMIPP_P2FSCR_PIPEN_Msk (0x1UL << DCMIPP_P2FSCR_PIPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P2FSCR_PIPEN DCMIPP_P2FSCR_PIPEN_Msk /*!< Activation of PipeN */
/**************** Bit definition for DCMIPP_P2FCTCR register ****************/
#define DCMIPP_P2FCTCR_FRATE_Pos (0U)
#define DCMIPP_P2FCTCR_FRATE_Msk (0x3UL << DCMIPP_P2FCTCR_FRATE_Pos) /*!< 0x00000003 */
#define DCMIPP_P2FCTCR_FRATE DCMIPP_P2FCTCR_FRATE_Msk /*!< Frame capture rate control */
#define DCMIPP_P2FCTCR_CPTMODE_Pos (2U)
#define DCMIPP_P2FCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2FCTCR_CPTMODE_Pos) /*!< 0x00000004 */
#define DCMIPP_P2FCTCR_CPTMODE DCMIPP_P2FCTCR_CPTMODE_Msk /*!< Capture mode */
#define DCMIPP_P2FCTCR_CPTREQ_Pos (3U)
#define DCMIPP_P2FCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2FCTCR_CPTREQ_Pos) /*!< 0x00000008 */
#define DCMIPP_P2FCTCR_CPTREQ DCMIPP_P2FCTCR_CPTREQ_Msk /*!< Capture requested */
/**************** Bit definition for DCMIPP_P2CRSTR register ****************/
#define DCMIPP_P2CRSTR_HSTART_Pos (0U)
#define DCMIPP_P2CRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2CRSTR_HSTART DCMIPP_P2CRSTR_HSTART_Msk /*!< Horizontal start, from 0 to 4094 pixels wide */
#define DCMIPP_P2CRSTR_VSTART_Pos (16U)
#define DCMIPP_P2CRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CRSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P2CRSTR_VSTART DCMIPP_P2CRSTR_VSTART_Msk /*!< Vertical start, from 0 to 4094 pixels high */
/**************** Bit definition for DCMIPP_P2CRSZR register ****************/
#define DCMIPP_P2CRSZR_HSIZE_Pos (0U)
#define DCMIPP_P2CRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2CRSZR_HSIZE DCMIPP_P2CRSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P2CRSZR_VSIZE_Pos (16U)
#define DCMIPP_P2CRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P2CRSZR_VSIZE DCMIPP_P2CRSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P2CRSZR_ENABLE_Pos (31U)
#define DCMIPP_P2CRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CRSZR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P2CRSZR_ENABLE DCMIPP_P2CRSZR_ENABLE_Msk /*!< */
/**************** Bit definition for DCMIPP_P2DCCR register *****************/
#define DCMIPP_P2DCCR_ENABLE_Pos (0U)
#define DCMIPP_P2DCCR_ENABLE_Msk (0x1UL << DCMIPP_P2DCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P2DCCR_ENABLE DCMIPP_P2DCCR_ENABLE_Msk /*!< Decimation enable */
#define DCMIPP_P2DCCR_HDEC_Pos (1U)
#define DCMIPP_P2DCCR_HDEC_Msk (0x3UL << DCMIPP_P2DCCR_HDEC_Pos) /*!< 0x00000006 */
#define DCMIPP_P2DCCR_HDEC DCMIPP_P2DCCR_HDEC_Msk /*!< Horizontal decimation ratio */
#define DCMIPP_P2DCCR_VDEC_Pos (3U)
#define DCMIPP_P2DCCR_VDEC_Msk (0x3UL << DCMIPP_P2DCCR_VDEC_Pos) /*!< 0x00000018 */
#define DCMIPP_P2DCCR_VDEC DCMIPP_P2DCCR_VDEC_Msk /*!< Vertical decimation ratio */
/**************** Bit definition for DCMIPP_P2DSCR register *****************/
#define DCMIPP_P2DSCR_HDIV_Pos (0U)
#define DCMIPP_P2DSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_HDIV_Pos) /*!< 0x000003FF */
#define DCMIPP_P2DSCR_HDIV DCMIPP_P2DSCR_HDIV_Msk /*!< Horizontal division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P2DSCR_VDIV_Pos (16U)
#define DCMIPP_P2DSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2DSCR_VDIV_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P2DSCR_VDIV DCMIPP_P2DSCR_VDIV_Msk /*!< Vertical division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P2DSCR_ENABLE_Pos (31U)
#define DCMIPP_P2DSCR_ENABLE_Msk (0x1UL << DCMIPP_P2DSCR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P2DSCR_ENABLE DCMIPP_P2DSCR_ENABLE_Msk /*!< */
/*************** Bit definition for DCMIPP_P2DSRTIOR register ***************/
#define DCMIPP_P2DSRTIOR_HRATIO_Pos (0U)
#define DCMIPP_P2DSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */
#define DCMIPP_P2DSRTIOR_HRATIO DCMIPP_P2DSRTIOR_HRATIO_Msk /*!< Horizontal ratio, from 8192 (1x) to 65535 (8x) */
#define DCMIPP_P2DSRTIOR_VRATIO_Pos (16U)
#define DCMIPP_P2DSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2DSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */
#define DCMIPP_P2DSRTIOR_VRATIO DCMIPP_P2DSRTIOR_VRATIO_Msk /*!< Vertical ratio, from 8192 (1x) to 65535 (8x) */
/**************** Bit definition for DCMIPP_P2DSSZR register ****************/
#define DCMIPP_P2DSSZR_HSIZE_Pos (0U)
#define DCMIPP_P2DSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2DSSZR_HSIZE DCMIPP_P2DSSZR_HSIZE_Msk /*!< Horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P2DSSZR_VSIZE_Pos (16U)
#define DCMIPP_P2DSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2DSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P2DSSZR_VSIZE DCMIPP_P2DSSZR_VSIZE_Msk /*!< Vertical size, from 0 to 4094 pixels high */
/**************** Bit definition for DCMIPP_P2GMCR register *****************/
#define DCMIPP_P2GMCR_ENABLE_Pos (0U)
#define DCMIPP_P2GMCR_ENABLE_Msk (0x1UL << DCMIPP_P2GMCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P2GMCR_ENABLE DCMIPP_P2GMCR_ENABLE_Msk /*!< */
/*************** Bit definition for DCMIPP_P2CMRICR register ***************/
#define DCMIPP_P2CMRICR_ROILSZ_Pos (0U)
#define DCMIPP_P2CMRICR_ROILSZ_Msk (0x3UL << DCMIPP_P2CMRICR_ROILSZ_Pos) /*!< 0x00000003 */
#define DCMIPP_P2CMRICR_ROILSZ DCMIPP_P2CMRICR_ROILSZ_Msk /*!< Region of interest line size width */
#define DCMIPP_P2CMRICR_ROI1EN_Pos (16U)
#define DCMIPP_P2CMRICR_ROI1EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI1EN_Pos) /*!< 0x00010000 */
#define DCMIPP_P2CMRICR_ROI1EN DCMIPP_P2CMRICR_ROI1EN_Msk /*!< Region Of Interest 1 Enable */
#define DCMIPP_P2CMRICR_ROI2EN_Pos (17U)
#define DCMIPP_P2CMRICR_ROI2EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI2EN_Pos) /*!< 0x00020000 */
#define DCMIPP_P2CMRICR_ROI2EN DCMIPP_P2CMRICR_ROI2EN_Msk /*!< Region Of Interest 2 Enable */
#define DCMIPP_P2CMRICR_ROI3EN_Pos (18U)
#define DCMIPP_P2CMRICR_ROI3EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI3EN_Pos) /*!< 0x00040000 */
#define DCMIPP_P2CMRICR_ROI3EN DCMIPP_P2CMRICR_ROI3EN_Msk /*!< Region Of Interest 3 Enable */
#define DCMIPP_P2CMRICR_ROI4EN_Pos (19U)
#define DCMIPP_P2CMRICR_ROI4EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI4EN_Pos) /*!< 0x00080000 */
#define DCMIPP_P2CMRICR_ROI4EN DCMIPP_P2CMRICR_ROI4EN_Msk /*!< Region Of Interest 4 Enable */
#define DCMIPP_P2CMRICR_ROI5EN_Pos (20U)
#define DCMIPP_P2CMRICR_ROI5EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI5EN_Pos) /*!< 0x00100000 */
#define DCMIPP_P2CMRICR_ROI5EN DCMIPP_P2CMRICR_ROI5EN_Msk /*!< Region Of Interest 5 Enable */
#define DCMIPP_P2CMRICR_ROI6EN_Pos (21U)
#define DCMIPP_P2CMRICR_ROI6EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI6EN_Pos) /*!< 0x00200000 */
#define DCMIPP_P2CMRICR_ROI6EN DCMIPP_P2CMRICR_ROI6EN_Msk /*!< Region Of Interest 6 Enable */
#define DCMIPP_P2CMRICR_ROI7EN_Pos (22U)
#define DCMIPP_P2CMRICR_ROI7EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI7EN_Pos) /*!< 0x00400000 */
#define DCMIPP_P2CMRICR_ROI7EN DCMIPP_P2CMRICR_ROI7EN_Msk /*!< Region Of Interest 7 Enable */
#define DCMIPP_P2CMRICR_ROI8EN_Pos (23U)
#define DCMIPP_P2CMRICR_ROI8EN_Msk (0x1UL << DCMIPP_P2CMRICR_ROI8EN_Pos) /*!< 0x00800000 */
#define DCMIPP_P2CMRICR_ROI8EN DCMIPP_P2CMRICR_ROI8EN_Msk /*!< Region Of Interest 8 Enable */
/*************** Bit definition for DCMIPP_P2RIxCR1 register ***************/
#define DCMIPP_P2RIxCR1_HSTART_Pos (0U)
#define DCMIPP_P2RIxCR1_HSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2RIxCR1_HSTART DCMIPP_P2RIxCR1_HSTART_Msk /*!< Horizontal start */
#define DCMIPP_P2RIxCR1_CLB_Pos (12U)
#define DCMIPP_P2RIxCR1_CLB_Msk (0x3UL << DCMIPP_P2RIxCR1_CLB_Pos) /*!< 0x00003000 */
#define DCMIPP_P2RIxCR1_CLB DCMIPP_P2RIxCR1_CLB_Msk /*!< Color line blue */
#define DCMIPP_P2RIxCR1_CLG_Pos (14U)
#define DCMIPP_P2RIxCR1_CLG_Msk (0x3UL << DCMIPP_P2RIxCR1_CLG_Pos) /*!< 0x0000C000 */
#define DCMIPP_P2RIxCR1_CLG DCMIPP_P2RIxCR1_CLG_Msk /*!< Color line green */
#define DCMIPP_P2RIxCR1_VSTART_Pos (16U)
#define DCMIPP_P2RIxCR1_VSTART_Msk (0xFFFUL << DCMIPP_P2RIxCR1_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P2RIxCR1_VSTART DCMIPP_P2RIxCR1_VSTART_Msk /*!< Vertical start */
#define DCMIPP_P2RIxCR1_CLR_Pos (28U)
#define DCMIPP_P2RIxCR1_CLR_Msk (0x3UL << DCMIPP_P2RIxCR1_CLR_Pos) /*!< 0x30000000 */
#define DCMIPP_P2RIxCR1_CLR DCMIPP_P2RIxCR1_CLR_Msk /*!< Color line red */
/*************** Bit definition for DCMIPP_P2RIxCR2 register ***************/
#define DCMIPP_P2RIxCR2_VSIZE_Pos (0U)
#define DCMIPP_P2RIxCR2_VSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_VSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2RIxCR2_VSIZE DCMIPP_P2RIxCR2_VSIZE_Msk /*!< Vertical Size */
#define DCMIPP_P2RIxCR2_HSIZE_Pos (16U)
#define DCMIPP_P2RIxCR2_HSIZE_Msk (0xFFFUL << DCMIPP_P2RIxCR2_HSIZE_Pos) /*!< 0x07FF8000 */
#define DCMIPP_P2RIxCR2_HSIZE DCMIPP_P2RIxCR2_HSIZE_Msk /*!< Horizontal Size */
/**************** Bit definition for DCMIPP_P2PPCR register *****************/
#define DCMIPP_P2PPCR_FORMAT_Pos (0U)
#define DCMIPP_P2PPCR_FORMAT_Msk (0xFUL << DCMIPP_P2PPCR_FORMAT_Pos) /*!< 0x0000000F */
#define DCMIPP_P2PPCR_FORMAT DCMIPP_P2PPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */
#define DCMIPP_P2PPCR_SWAPRB_Pos (4U)
#define DCMIPP_P2PPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2PPCR_SWAPRB_Pos) /*!< 0x00000010 */
#define DCMIPP_P2PPCR_SWAPRB DCMIPP_P2PPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
#define DCMIPP_P2PPCR_LINEMULT_Pos (13U)
#define DCMIPP_P2PPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2PPCR_LINEMULT_Pos) /*!< 0x0000E000 */
#define DCMIPP_P2PPCR_LINEMULT DCMIPP_P2PPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */
#define DCMIPP_P2PPCR_DBM_Pos (16U)
#define DCMIPP_P2PPCR_DBM_Msk (0x1UL << DCMIPP_P2PPCR_DBM_Pos) /*!< 0x00010000 */
#define DCMIPP_P2PPCR_DBM DCMIPP_P2PPCR_DBM_Msk /*!< Double buffer mode */
#define DCMIPP_P2PPCR_LMAWM_Pos (17U)
#define DCMIPP_P2PPCR_LMAWM_Msk (0x7UL << DCMIPP_P2PPCR_LMAWM_Pos) /*!< 0x000E0000 */
#define DCMIPP_P2PPCR_LMAWM DCMIPP_P2PPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */
#define DCMIPP_P2PPCR_LMAWE_Pos (20U)
#define DCMIPP_P2PPCR_LMAWE_Msk (0x7UL << DCMIPP_P2PPCR_LMAWE_Pos) /*!< 0x00100000 */
#define DCMIPP_P2PPCR_LMAWE DCMIPP_P2PPCR_LMAWE_Msk /*!< Line multi address wrapping enable */
/*************** Bit definition for DCMIPP_P2PPM0AR1 register ***************/
#define DCMIPP_P2PPM0AR1_M0A_Pos (0U)
#define DCMIPP_P2PPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P2PPM0AR1_M0A DCMIPP_P2PPM0AR1_M0A_Msk /*!< Memory0 address register 1 */
/*************** Bit definition for DCMIPP_P2PPM0AR2 register ***************/
#define DCMIPP_P2PPM0AR2_M0A_Pos (0U)
#define DCMIPP_P2PPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2PPM0AR2_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P2PPM0AR2_M0A DCMIPP_P2PPM0AR2_M0A_Msk /*!< Memory0 address register 2*/
/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/
#define DCMIPP_P2PPM0PR_PITCH_Pos (0U)
#define DCMIPP_P2PPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2PPM0PR_PITCH_Pos) /*!< 0x00007FFF */
#define DCMIPP_P2PPM0PR_PITCH DCMIPP_P2PPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */
/*************** Bit definition for DCMIPP_P2PPM0PR register ****************/
#define DCMIPP_P2STM0AR_Pos (0U)
#define DCMIPP_P2STM0AR_Msk (0xFFFFFFFFUL << DCMIPP_P2STM0AR_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P2STM0AR DCMIPP_P2STM0AR_Msk /*!< Pipe2 status Memory0 address register */
/***************** Bit definition for DCMIPP_P2IER register *****************/
#define DCMIPP_P2IER_LINEIE_Pos (0U)
#define DCMIPP_P2IER_LINEIE_Msk (0x1UL << DCMIPP_P2IER_LINEIE_Pos) /*!< 0x00000001 */
#define DCMIPP_P2IER_LINEIE DCMIPP_P2IER_LINEIE_Msk /*!< Multi-line capture completed interrupt enable */
#define DCMIPP_P2IER_FRAMEIE_Pos (1U)
#define DCMIPP_P2IER_FRAMEIE_Msk (0x1UL << DCMIPP_P2IER_FRAMEIE_Pos) /*!< 0x00000002 */
#define DCMIPP_P2IER_FRAMEIE DCMIPP_P2IER_FRAMEIE_Msk /*!< Frame capture completed interrupt enable */
#define DCMIPP_P2IER_VSYNCIE_Pos (2U)
#define DCMIPP_P2IER_VSYNCIE_Msk (0x1UL << DCMIPP_P2IER_VSYNCIE_Pos) /*!< 0x00000004 */
#define DCMIPP_P2IER_VSYNCIE DCMIPP_P2IER_VSYNCIE_Msk /*!< VSYNC interrupt enable */
#define DCMIPP_P2IER_OVRIE_Pos (7U)
#define DCMIPP_P2IER_OVRIE_Msk (0x1UL << DCMIPP_P2IER_OVRIE_Pos) /*!< 0x00000080 */
#define DCMIPP_P2IER_OVRIE DCMIPP_P2IER_OVRIE_Msk /*!< Overrun interrupt enable */
/***************** Bit definition for DCMIPP_P2SR register ******************/
#define DCMIPP_P2SR_LINEF_Pos (0U)
#define DCMIPP_P2SR_LINEF_Msk (0x1UL << DCMIPP_P2SR_LINEF_Pos) /*!< 0x00000001 */
#define DCMIPP_P2SR_LINEF DCMIPP_P2SR_LINEF_Msk /*!< Multi-line capture completed raw interrupt status */
#define DCMIPP_P2SR_FRAMEF_Pos (1U)
#define DCMIPP_P2SR_FRAMEF_Msk (0x1UL << DCMIPP_P2SR_FRAMEF_Pos) /*!< 0x00000002 */
#define DCMIPP_P2SR_FRAMEF DCMIPP_P2SR_FRAMEF_Msk /*!< Frame capture completed raw interrupt status */
#define DCMIPP_P2SR_VSYNCF_Pos (2U)
#define DCMIPP_P2SR_VSYNCF_Msk (0x1UL << DCMIPP_P2SR_VSYNCF_Pos) /*!< 0x00000004 */
#define DCMIPP_P2SR_VSYNCF DCMIPP_P2SR_VSYNCF_Msk /*!< VSYNC raw interrupt status */
#define DCMIPP_P2SR_OVRF_Pos (7U)
#define DCMIPP_P2SR_OVRF_Msk (0x1UL << DCMIPP_P2SR_OVRF_Pos) /*!< 0x00000080 */
#define DCMIPP_P2SR_OVRF DCMIPP_P2SR_OVRF_Msk /*!< Overrun raw interrupt status */
#define DCMIPP_P2SR_LSTLINE_Pos (16U)
#define DCMIPP_P2SR_LSTLINE_Msk (0x1UL << DCMIPP_P2SR_LSTLINE_Pos) /*!< 0x00010000 */
#define DCMIPP_P2SR_LSTLINE DCMIPP_P2SR_LSTLINE_Msk /*!< Last line LSB bit, sampled at frame capture complete event */
#define DCMIPP_P2SR_LSTFRM_Pos (17U)
#define DCMIPP_P2SR_LSTFRM_Msk (0x1UL << DCMIPP_P2SR_LSTFRM_Pos) /*!< 0x00020000 */
#define DCMIPP_P2SR_LSTFRM DCMIPP_P2SR_LSTFRM_Msk /*!< Last frame LSB bit, sampled at frame capture complete event */
#define DCMIPP_P2SR_CPTACT_Pos (23U)
#define DCMIPP_P2SR_CPTACT_Msk (0x1UL << DCMIPP_P2SR_CPTACT_Pos) /*!< 0x00800000 */
#define DCMIPP_P2SR_CPTACT DCMIPP_P2SR_CPTACT_Msk /*!< Capture immediate status */
/***************** Bit definition for DCMIPP_P2FCR register *****************/
#define DCMIPP_P2FCR_CLINEF_Pos (0U)
#define DCMIPP_P2FCR_CLINEF_Msk (0x1UL << DCMIPP_P2FCR_CLINEF_Pos) /*!< 0x00000001 */
#define DCMIPP_P2FCR_CLINEF DCMIPP_P2FCR_CLINEF_Msk /*!< Multi-line capture complete interrupt status clear */
#define DCMIPP_P2FCR_CFRAMEF_Pos (1U)
#define DCMIPP_P2FCR_CFRAMEF_Msk (0x1UL << DCMIPP_P2FCR_CFRAMEF_Pos) /*!< 0x00000002 */
#define DCMIPP_P2FCR_CFRAMEF DCMIPP_P2FCR_CFRAMEF_Msk /*!< Frame capture complete interrupt status clear */
#define DCMIPP_P2FCR_CVSYNCF_Pos (2U)
#define DCMIPP_P2FCR_CVSYNCF_Msk (0x1UL << DCMIPP_P2FCR_CVSYNCF_Pos) /*!< 0x00000004 */
#define DCMIPP_P2FCR_CVSYNCF DCMIPP_P2FCR_CVSYNCF_Msk /*!< Vertical synchronization interrupt status clear */
#define DCMIPP_P2FCR_COVRF_Pos (7U)
#define DCMIPP_P2FCR_COVRF_Msk (0x1UL << DCMIPP_P2FCR_COVRF_Pos) /*!< 0x00000080 */
#define DCMIPP_P2FCR_COVRF DCMIPP_P2FCR_COVRF_Msk /*!< Overrun interrupt status clear */
/**************** Bit definition for DCMIPP_P2CFSCR register ****************/
#define DCMIPP_P2CFSCR_DTID_Pos (0U)
#define DCMIPP_P2CFSCR_DTID_Msk (0x3FUL << DCMIPP_P2CFSCR_DTID_Pos) /*!< 0x0000003F */
#define DCMIPP_P2CFSCR_DTID DCMIPP_P2CFSCR_DTID_Msk /*!< Current Data type ID */
#define DCMIPP_P2CFSCR_VC_Pos (19U)
#define DCMIPP_P2CFSCR_VC_Msk (0x3UL << DCMIPP_P2CFSCR_VC_Pos) /*!< 0x00180000 */
#define DCMIPP_P2CFSCR_VC DCMIPP_P2CFSCR_VC_Msk /*!< Current flow selection mode */
#define DCMIPP_P2CFSCR_FDTF_Pos (24U)
#define DCMIPP_P2CFSCR_FDTF_Msk (0x3FUL << DCMIPP_P2CFSCR_FDTF_Pos) /*!< 0x3F000000 */
#define DCMIPP_P2CFSCR_FDTF DCMIPP_P2CFSCR_FDTF_Msk /*!< Current force Data type format */
#define DCMIPP_P2CFSCR_FDTFEN_Pos (30U)
#define DCMIPP_P2CFSCR_FDTFEN_Msk (0x1UL << DCMIPP_P2CFSCR_FDTFEN_Pos) /*!< 0x40000000 */
#define DCMIPP_P2CFSCR_FDTFEN DCMIPP_P2CFSCR_FDTFEN_Msk /*!< Current force Data type format enable */
#define DCMIPP_P2CFSCR_PIPEN_Pos (31U)
#define DCMIPP_P2CFSCR_PIPEN_Msk (0x1UL << DCMIPP_P2CFSCR_PIPEN_Pos) /*!< 0x80000000 */
#define DCMIPP_P2CFSCR_PIPEN DCMIPP_P2CFSCR_PIPEN_Msk /*!< Current activation of PipeN */
/*************** Bit definition for DCMIPP_P2CFCTCR register ****************/
#define DCMIPP_P2CFCTCR_FRATE_Pos (0U)
#define DCMIPP_P2CFCTCR_FRATE_Msk (0x3UL << DCMIPP_P2CFCTCR_FRATE_Pos) /*!< 0x00000003 */
#define DCMIPP_P2CFCTCR_FRATE DCMIPP_P2CFCTCR_FRATE_Msk /*!< Frame capture rate control */
#define DCMIPP_P2CFCTCR_CPTMODE_Pos (2U)
#define DCMIPP_P2CFCTCR_CPTMODE_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTMODE_Pos) /*!< 0x00000004 */
#define DCMIPP_P2CFCTCR_CPTMODE DCMIPP_P2CFCTCR_CPTMODE_Msk /*!< Capture mode */
#define DCMIPP_P2CFCTCR_CPTREQ_Pos (3U)
#define DCMIPP_P2CFCTCR_CPTREQ_Msk (0x1UL << DCMIPP_P2CFCTCR_CPTREQ_Pos) /*!< 0x00000008 */
#define DCMIPP_P2CFCTCR_CPTREQ DCMIPP_P2CFCTCR_CPTREQ_Msk /*!< Capture requested */
/*************** Bit definition for DCMIPP_P2CCRSTR register ****************/
#define DCMIPP_P2CCRSTR_HSTART_Pos (0U)
#define DCMIPP_P2CCRSTR_HSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_HSTART_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2CCRSTR_HSTART DCMIPP_P2CCRSTR_HSTART_Msk /*!< Current horizontal start, from 0 to 4094 pixels wide */
#define DCMIPP_P2CCRSTR_VSTART_Pos (16U)
#define DCMIPP_P2CCRSTR_VSTART_Msk (0xFFFUL << DCMIPP_P2CCRSTR_VSTART_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P2CCRSTR_VSTART DCMIPP_P2CCRSTR_VSTART_Msk /*!< Current vertical start, from 0 to 4094 pixels high */
/*************** Bit definition for DCMIPP_P2CCRSZR register ****************/
#define DCMIPP_P2CCRSZR_HSIZE_Pos (0U)
#define DCMIPP_P2CCRSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2CCRSZR_HSIZE DCMIPP_P2CCRSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P2CCRSZR_VSIZE_Pos (16U)
#define DCMIPP_P2CCRSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CCRSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P2CCRSZR_VSIZE DCMIPP_P2CCRSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */
#define DCMIPP_P2CCRSZR_ENABLE_Pos (31U)
#define DCMIPP_P2CCRSZR_ENABLE_Msk (0x1UL << DCMIPP_P2CCRSZR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P2CCRSZR_ENABLE DCMIPP_P2CCRSZR_ENABLE_Msk /*!< Current ENABLE bit value */
/**************** Bit definition for DCMIPP_P2CDCCR register *****************/
#define DCMIPP_P2CDCCR_ENABLE_Pos (0U)
#define DCMIPP_P2CDCCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDCCR_ENABLE_Pos) /*!< 0x00000001 */
#define DCMIPP_P2CDCCR_ENABLE DCMIPP_P2CDCCR_ENABLE_Msk /*!< Decimation enable */
#define DCMIPP_P2CDCCR_HDEC_Pos (1U)
#define DCMIPP_P2CDCCR_HDEC_Msk (0x3UL << DCMIPP_P2CDCCR_HDEC_Pos) /*!< 0x00000006 */
#define DCMIPP_P2CDCCR_HDEC DCMIPP_P2CDCCR_HDEC_Msk /*!< Horizontal decimation ratio */
#define DCMIPP_P2CDCCR_VDEC_Pos (3U)
#define DCMIPP_P2CDCCR_VDEC_Msk (0x3UL << DCMIPP_P2CDCCR_VDEC_Pos) /*!< 0x00000018 */
#define DCMIPP_P2CDCCR_VDEC DCMIPP_P2CDCCR_VDEC_Msk /*!< Vertical decimation ratio */
/**************** Bit definition for DCMIPP_P2CDSCR register ****************/
#define DCMIPP_P2CDSCR_HDIV_Pos (0U)
#define DCMIPP_P2CDSCR_HDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_HDIV_Pos) /*!< 0x000003FF */
#define DCMIPP_P2CDSCR_HDIV DCMIPP_P2CDSCR_HDIV_Msk /*!< Current horizontal division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P2CDSCR_VDIV_Pos (16U)
#define DCMIPP_P2CDSCR_VDIV_Msk (0x3FFUL << DCMIPP_P2CDSCR_VDIV_Pos) /*!< 0x03FF0000 */
#define DCMIPP_P2CDSCR_VDIV DCMIPP_P2CDSCR_VDIV_Msk /*!< Current vertical division factor, from 128 (8x) to 1023 (1x) */
#define DCMIPP_P2CDSCR_ENABLE_Pos (31U)
#define DCMIPP_P2CDSCR_ENABLE_Msk (0x1UL << DCMIPP_P2CDSCR_ENABLE_Pos) /*!< 0x80000000 */
#define DCMIPP_P2CDSCR_ENABLE DCMIPP_P2CDSCR_ENABLE_Msk /*!< Current value of the bit ENABLE */
/************** Bit definition for DCMIPP_P2CDSRTIOR register ***************/
#define DCMIPP_P2CDSRTIOR_HRATIO_Pos (0U)
#define DCMIPP_P2CDSRTIOR_HRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_HRATIO_Pos) /*!< 0x0000FFFF */
#define DCMIPP_P2CDSRTIOR_HRATIO DCMIPP_P2CDSRTIOR_HRATIO_Msk /*!< Current horizontal ratio, from 8192 (1x) to 65535 (8x) */
#define DCMIPP_P2CDSRTIOR_VRATIO_Pos (16U)
#define DCMIPP_P2CDSRTIOR_VRATIO_Msk (0xFFFFUL << DCMIPP_P2CDSRTIOR_VRATIO_Pos) /*!< 0xFFFF0000 */
#define DCMIPP_P2CDSRTIOR_VRATIO DCMIPP_P2CDSRTIOR_VRATIO_Msk /*!< Current vertical ratio, from 8192 (1x) to 65535 (8x) */
/*************** Bit definition for DCMIPP_P2CDSSZR register ****************/
#define DCMIPP_P2CDSSZR_HSIZE_Pos (0U)
#define DCMIPP_P2CDSSZR_HSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_HSIZE_Pos) /*!< 0x00000FFF */
#define DCMIPP_P2CDSSZR_HSIZE DCMIPP_P2CDSSZR_HSIZE_Msk /*!< Current horizontal size, from 0 to 4094 pixels wide */
#define DCMIPP_P2CDSSZR_VSIZE_Pos (16U)
#define DCMIPP_P2CDSSZR_VSIZE_Msk (0xFFFUL << DCMIPP_P2CDSSZR_VSIZE_Pos) /*!< 0x0FFF0000 */
#define DCMIPP_P2CDSSZR_VSIZE DCMIPP_P2CDSSZR_VSIZE_Msk /*!< Current vertical size, from 0 to 4094 pixels high */
/**************** Bit definition for DCMIPP_P2CPPCR register ****************/
#define DCMIPP_P2CPPCR_FORMAT_Pos (0U)
#define DCMIPP_P2CPPCR_FORMAT_Msk (0xFUL << DCMIPP_P2CPPCR_FORMAT_Pos) /*!< 0x0000000F */
#define DCMIPP_P2CPPCR_FORMAT DCMIPP_P2CPPCR_FORMAT_Msk /*!< Memory format (only coplanar formats are supported in Pipe2) */
#define DCMIPP_P2CPPCR_SWAPRB_Pos (4U)
#define DCMIPP_P2CPPCR_SWAPRB_Msk (0x1UL << DCMIPP_P2CPPCR_SWAPRB_Pos) /*!< 0x00000010 */
#define DCMIPP_P2CPPCR_SWAPRB DCMIPP_P2CPPCR_SWAPRB_Msk /*!< Swaps R-vs-B components if RGB, and if YUV, swaps U-vs-V components */
#define DCMIPP_P2CPPCR_LINEMULT_Pos (13U)
#define DCMIPP_P2CPPCR_LINEMULT_Msk (0x7UL << DCMIPP_P2CPPCR_LINEMULT_Pos) /*!< 0x0000E000 */
#define DCMIPP_P2CPPCR_LINEMULT DCMIPP_P2CPPCR_LINEMULT_Msk /*!< Amount of capture completed lines for LINE Event and Interrupt */
#define DCMIPP_P2CPPCR_DBM_Pos (16U)
#define DCMIPP_P2CPPCR_DBM_Msk (0x1UL << DCMIPP_P2CPPCR_DBM_Pos) /*!< 0x00010000 */
#define DCMIPP_P2CPPCR_DBM DCMIPP_P2CPPCR_DBM_Msk /*!< Double buffer mode */
#define DCMIPP_P2CPPCR_LMAWM_Pos (17U)
#define DCMIPP_P2CPPCR_LMAWM_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWM_Pos) /*!< 0x000E0000 */
#define DCMIPP_P2CPPCR_LMAWM DCMIPP_P2CPPCR_LMAWM_Msk /*!< Line multi address wrapping modulo */
#define DCMIPP_P2CPPCR_LMAWE_Pos (20U)
#define DCMIPP_P2CPPCR_LMAWE_Msk (0x7UL << DCMIPP_P2CPPCR_LMAWE_Pos) /*!< 0x00100000 */
#define DCMIPP_P2CPPCR_LMAWE DCMIPP_P2CPPCR_LMAWE_Msk /*!< Line multi address wrapping enable */
/************** Bit definition for DCMIPP_P2CPPM0AR1 register ***************/
#define DCMIPP_P2CPPM0AR1_M0A_Pos (0U)
#define DCMIPP_P2CPPM0AR1_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P2CPPM0AR1_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address */
/************** Bit definition for DCMIPP_P2CPPM0AR2 register ***************/
#define DCMIPP_P2CPPM0AR2_M0A_Pos (0U)
#define DCMIPP_P2CPPM0AR2_M0A_Msk (0xFFFFFFFFUL << DCMIPP_P2CPPM0AR1_M0A_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_P2CPPM0AR2_M0A DCMIPP_P2CPPM0AR1_M0A_Msk /*!< Memory0 address Register 2 */
/*************** Bit definition for DCMIPP_P2CPPM0PR register ***************/
#define DCMIPP_P2CPPM0PR_PITCH_Pos (0U)
#define DCMIPP_P2CPPM0PR_PITCH_Msk (0x7FFFUL << DCMIPP_P2CPPM0PR_PITCH_Pos) /*!< 0x00007FFF */
#define DCMIPP_P2CPPM0PR_PITCH DCMIPP_P2CPPM0PR_PITCH_Msk /*!< Number of bytes between the address of two consecutive lines */
/**************** Bit definition for DCMIPP_HWCFGR2 register ****************/
#define DCMIPP_HWCFGR2_VPFT_Pos (0U)
#define DCMIPP_HWCFGR2_VPFT_Msk (0x7U << DCMIPP_HWCFGR2_VPFT_Pos) /*!< 0x00000007 */
#define DCMIPP_HWCFGR2_VPFT DCMIPP_HWCFGR2_VPFT_Msk /*!< Virtual pipe function */
#define DCMIPP_HWCFGR2_DBMFT_Pos (4U)
#define DCMIPP_HWCFGR2_DBMFT_Msk (0x1U << DCMIPP_HWCFGR2_DBMFT_Pos) /*!< 0x00000010 */
#define DCMIPP_HWCFGR2_DBMFT DCMIPP_HWCFGR2_DBMFT_Msk /*!< Double buffer mode featured */
#define DCMIPP_HWCFGR2_PROCCLK_Pos (8U)
#define DCMIPP_HWCFGR2_PROCCLK_Msk (0x1U << DCMIPP_HWCFGR2_PROCCLK_Pos) /*!< 0x00000100 */
#define DCMIPP_HWCFGR2_PROCCLK DCMIPP_HWCFGR2_PROCCLK_Msk /*!< Processing clock linked to AXI clock featured */
#define DCMIPP_HWCFGR2_ADDMOD_Pos (12U)
#define DCMIPP_HWCFGR2_ADDMOD_Msk (0x1U << DCMIPP_HWCFGR2_ADDMOD_Pos) /*!< 0x00001000 */
#define DCMIPP_HWCFGR2_ADDMOD DCMIPP_HWCFGR2_ADDMOD_Msk /*!< Address modulo computation to access a small buffer in streaming featured */
#define DCMIPP_HWCFGR2_DEC1_Pos (16U)
#define DCMIPP_HWCFGR2_DEC1_Msk (0x1U << DCMIPP_HWCFGR2_DEC1_Pos) /*!< 0x00010000 */
#define DCMIPP_HWCFGR2_DEC1 DCMIPP_HWCFGR2_DEC1_Msk /*!< Decimation on Pipe1 before downsize */
#define DCMIPP_HWCFGR2_DEC2_Pos (17U)
#define DCMIPP_HWCFGR2_DEC2_Msk (0x1U << DCMIPP_HWCFGR2_DEC2_Pos) /*!< 0x00020000 */
#define DCMIPP_HWCFGR2_DEC2 DCMIPP_HWCFGR2_DEC2_Msk /*!< Decimation on Pipe2 before downsize */
#define DCMIPP_HWCFGR2_MCU_Pos (20U)
#define DCMIPP_HWCFGR2_MCU_Msk (0x1U << DCMIPP_HWCFGR2_MCU_Pos) /*!< 0x00100000 */
#define DCMIPP_HWCFGR2_MCU DCMIPP_HWCFGR2_MCU_Msk /*!< Macroblock unit as pixel format */
#define DCMIPP_HWCFGR2_TPG_Pos (24U)
#define DCMIPP_HWCFGR2_TPG_Msk (0x1U << DCMIPP_HWCFGR2_TPG_Pos) /*!< 0x01000000 */
#define DCMIPP_HWCFGR2_TPG DCMIPP_HWCFGR2_TPG_Msk /*!< Test Pattern Generator */
#define DCMIPP_HWCFGR2_STV_Pos (28U)
#define DCMIPP_HWCFGR2_STV_Msk (0x1U << DCMIPP_HWCFGR2_STV_Pos) /*!< 0x10000000 */
#define DCMIPP_HWCFGR2_STV DCMIPP_HWCFGR2_STV_Msk /*!< Statistic Version */
/**************** Bit definition for DCMIPP_HWCFGR1 register ****************/
#define DCMIPP_HWCFGR1_CSIFT_Pos (0U)
#define DCMIPP_HWCFGR1_CSIFT_Msk (0x1U << DCMIPP_HWCFGR1_CSIFT_Pos) /*!< 0x00000001 */
#define DCMIPP_HWCFGR1_CSIFT DCMIPP_HWCFGR1_CSIFT_Msk /*!< CSI2 host protocol compliant */
#define DCMIPP_HWCFGR1_PIPENB_Pos (4U)
#define DCMIPP_HWCFGR1_PIPENB_Msk (0x3U << DCMIPP_HWCFGR1_PIPENB_Pos) /*!< 0x00000030 */
#define DCMIPP_HWCFGR1_PIPENB DCMIPP_HWCFGR1_PIPENB_Msk /*!< Number of pipes */
#define DCMIPP_HWCFGR1_IPPLUGCFG_Pos (8U)
#define DCMIPP_HWCFGR1_IPPLUGCFG_Msk (0x1U << DCMIPP_HWCFGR1_IPPLUGCFG_Pos) /*!< 0x00000100 */
#define DCMIPP_HWCFGR1_IPPLUGCFG DCMIPP_HWCFGR1_IPPLUGCFG_Msk /*!< IP-Plug configuration */
#define DCMIPP_HWCFGR1_DSP1FT_Pos (12U)
#define DCMIPP_HWCFGR1_DSP1FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP1FT_Pos) /*!< 0x00001000 */
#define DCMIPP_HWCFGR1_DSP1FT DCMIPP_HWCFGR1_DSP1FT_Msk /*!< Down-sampling feature for the pixel Pipe1 */
#define DCMIPP_HWCFGR1_DSP2FT_Pos (13U)
#define DCMIPP_HWCFGR1_DSP2FT_Msk (0x1U << DCMIPP_HWCFGR1_DSP2FT_Pos) /*!< 0x00002000 */
#define DCMIPP_HWCFGR1_DSP2FT DCMIPP_HWCFGR1_DSP2FT_Msk /*!< Down-sampling feature for the pixel Pipe2 */
#define DCMIPP_HWCFGR1_RB2RGB_Pos (16U)
#define DCMIPP_HWCFGR1_RB2RGB_Msk (0x1U << DCMIPP_HWCFGR1_RB2RGB_Pos) /*!< 0x00010000 */
#define DCMIPP_HWCFGR1_RB2RGB DCMIPP_HWCFGR1_RB2RGB_Msk /*!< Raw Bayer to RGB feature (demosaicer) */
#define DCMIPP_HWCFGR1_PLANARFT_Pos (20U)
#define DCMIPP_HWCFGR1_PLANARFT_Msk (0x3U << DCMIPP_HWCFGR1_PLANARFT_Pos) /*!< 0x00300000 */
#define DCMIPP_HWCFGR1_PLANARFT DCMIPP_HWCFGR1_PLANARFT_Msk /*!< Buffer features for Pipe1 */
#define DCMIPP_HWCFGR1_ROI1NB_Pos (24U)
#define DCMIPP_HWCFGR1_ROI1NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI1NB_Pos) /*!< 0x0F000000 */
#define DCMIPP_HWCFGR1_ROI1NB DCMIPP_HWCFGR1_ROI1NB_Msk /*!< Number of ROIs for Pipe1 */
#define DCMIPP_HWCFGR1_ROI2NB_Pos (28U)
#define DCMIPP_HWCFGR1_ROI2NB_Msk (0xFU << DCMIPP_HWCFGR1_ROI2NB_Pos) /*!< 0xF0000000 */
#define DCMIPP_HWCFGR1_ROI2NB DCMIPP_HWCFGR1_ROI2NB_Msk /*!< Number of ROIs for Pipe2 */
/***************** Bit definition for DCMIPP_VERR register ******************/
#define DCMIPP_VERR_MINREV_Pos (0U)
#define DCMIPP_VERR_MINREV_Msk (0xFU << DCMIPP_VERR_MINREV_Pos) /*!< 0x0000000F */
#define DCMIPP_VERR_MINREV DCMIPP_VERR_MINREV_Msk /*!< DCMIPP minor revision */
#define DCMIPP_VERR_MAJREV_Pos (4U)
#define DCMIPP_VERR_MAJREV_Msk (0xFU << DCMIPP_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define DCMIPP_VERR_MAJREV DCMIPP_VERR_MAJREV_Msk /*!< DCMIPP major revision */
/***************** Bit definition for DCMIPP_IPIDR register *****************/
#define DCMIPP_IPIDR_IDR_Pos (0U)
#define DCMIPP_IPIDR_IDR_Msk (0xFFFFFFFFU << DCMIPP_IPIDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_IPIDR_IDR DCMIPP_IPIDR_IDR_Msk /*!< Parallel camera interface (DCMI) and optional pixel processing (PP) */
/***************** Bit definition for DCMIPP_SIDR register ******************/
#define DCMIPP_SIDR_SID_Pos (0U)
#define DCMIPP_SIDR_SID_Msk (0xFFFFFFFFU << DCMIPP_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define DCMIPP_SIDR_SID DCMIPP_SIDR_SID_Msk /*!< 4-Kbyte decoding space */
/******************************************************************************/
/* */
/* Delay Block Interface (DLYB) */
/* */
/******************************************************************************/
/******************* Bit definition for DLYB_CR register ********************/
#define DLYB_CR_DEN_Pos (0U)
#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
#define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
#define DLYB_CR_SEN_Pos (1U)
#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
#define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
/******************* Bit definition for DLYB_CFGR register ********************/
#define DLYB_CFGR_SEL_Pos (0U)
#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
#define DLYB_CFGR_UNIT_Pos (8U)
#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
#define DLYB_CFGR_LNG_Pos (16U)
#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
#define DLYB_CFGR_LNGF_Pos (31U)
#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_SECCFGR register ****************/
#define DMA_SECCFGR_SEC0_Pos (0U)
#define DMA_SECCFGR_SEC0_Msk (0x1UL << DMA_SECCFGR_SEC0_Pos) /*!< 0x00000001 */
#define DMA_SECCFGR_SEC0 DMA_SECCFGR_SEC0_Msk /*!< Secure State of Channel 0 */
#define DMA_SECCFGR_SEC1_Pos (1U)
#define DMA_SECCFGR_SEC1_Msk (0x1UL << DMA_SECCFGR_SEC1_Pos) /*!< 0x00000002 */
#define DMA_SECCFGR_SEC1 DMA_SECCFGR_SEC1_Msk /*!< Secure State of Channel 1 */
#define DMA_SECCFGR_SEC2_Pos (2U)
#define DMA_SECCFGR_SEC2_Msk (0x1UL << DMA_SECCFGR_SEC2_Pos) /*!< 0x00000004 */
#define DMA_SECCFGR_SEC2 DMA_SECCFGR_SEC2_Msk /*!< Secure State of Channel 2 */
#define DMA_SECCFGR_SEC3_Pos (3U)
#define DMA_SECCFGR_SEC3_Msk (0x1UL << DMA_SECCFGR_SEC3_Pos) /*!< 0x00000008 */
#define DMA_SECCFGR_SEC3 DMA_SECCFGR_SEC3_Msk /*!< Secure State of Channel 3 */
#define DMA_SECCFGR_SEC4_Pos (4U)
#define DMA_SECCFGR_SEC4_Msk (0x1UL << DMA_SECCFGR_SEC4_Pos) /*!< 0x00000010 */
#define DMA_SECCFGR_SEC4 DMA_SECCFGR_SEC4_Msk /*!< Secure State of Channel 4 */
#define DMA_SECCFGR_SEC5_Pos (5U)
#define DMA_SECCFGR_SEC5_Msk (0x1UL << DMA_SECCFGR_SEC5_Pos) /*!< 0x00000020 */
#define DMA_SECCFGR_SEC5 DMA_SECCFGR_SEC5_Msk /*!< Secure State of Channel 5 */
#define DMA_SECCFGR_SEC6_Pos (6U)
#define DMA_SECCFGR_SEC6_Msk (0x1UL << DMA_SECCFGR_SEC6_Pos) /*!< 0x00000040 */
#define DMA_SECCFGR_SEC6 DMA_SECCFGR_SEC6_Msk /*!< Secure State of Channel 6 */
#define DMA_SECCFGR_SEC7_Pos (7U)
#define DMA_SECCFGR_SEC7_Msk (0x1UL << DMA_SECCFGR_SEC7_Pos) /*!< 0x00000080 */
#define DMA_SECCFGR_SEC7 DMA_SECCFGR_SEC7_Msk /*!< Secure State of Channel 7 */
#define DMA_SECCFGR_SEC8_Pos (8U)
#define DMA_SECCFGR_SEC8_Msk (0x1UL << DMA_SECCFGR_SEC8_Pos) /*!< 0x00000100 */
#define DMA_SECCFGR_SEC8 DMA_SECCFGR_SEC8_Msk /*!< Secure State of Channel 8 */
#define DMA_SECCFGR_SEC9_Pos (9U)
#define DMA_SECCFGR_SEC9_Msk (0x1UL << DMA_SECCFGR_SEC9_Pos) /*!< 0x00000200 */
#define DMA_SECCFGR_SEC9 DMA_SECCFGR_SEC9_Msk /*!< Secure State of Channel 9 */
#define DMA_SECCFGR_SEC10_Pos (10U)
#define DMA_SECCFGR_SEC10_Msk (0x1UL << DMA_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
#define DMA_SECCFGR_SEC10 DMA_SECCFGR_SEC10_Msk /*!< Secure State of Channel 10 */
#define DMA_SECCFGR_SEC11_Pos (11U)
#define DMA_SECCFGR_SEC11_Msk (0x1UL << DMA_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define DMA_SECCFGR_SEC11 DMA_SECCFGR_SEC11_Msk /*!< Secure State of Channel 11 */
#define DMA_SECCFGR_SEC12_Pos (12U)
#define DMA_SECCFGR_SEC12_Msk (0x1UL << DMA_SECCFGR_SEC12_Pos) /*!< 0x00001000 */
#define DMA_SECCFGR_SEC12 DMA_SECCFGR_SEC12_Msk /*!< Secure State of Channel 12 */
#define DMA_SECCFGR_SEC13_Pos (13U)
#define DMA_SECCFGR_SEC13_Msk (0x1UL << DMA_SECCFGR_SEC13_Pos) /*!< 0x00002000 */
#define DMA_SECCFGR_SEC13 DMA_SECCFGR_SEC13_Msk /*!< Secure State of Channel 13 */
#define DMA_SECCFGR_SEC14_Pos (14U)
#define DMA_SECCFGR_SEC14_Msk (0x1UL << DMA_SECCFGR_SEC14_Pos) /*!< 0x00004000 */
#define DMA_SECCFGR_SEC14 DMA_SECCFGR_SEC14_Msk /*!< Secure State of Channel 14 */
#define DMA_SECCFGR_SEC15_Pos (15U)
#define DMA_SECCFGR_SEC15_Msk (0x1UL << DMA_SECCFGR_SEC15_Pos) /*!< 0x00008000 */
#define DMA_SECCFGR_SEC15 DMA_SECCFGR_SEC14_Msk /*!< Secure State of Channel 15 */
/******************* Bit definition for DMA_PRIVCFGR register ****************/
#define DMA_PRIVCFGR_PRIV0_Pos (0U)
#define DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */
#define DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk /*!< Privileged State of Channel 0 */
#define DMA_PRIVCFGR_PRIV1_Pos (1U)
#define DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */
#define DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk /*!< Privileged State of Channel 1 */
#define DMA_PRIVCFGR_PRIV2_Pos (2U)
#define DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */
#define DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk /*!< Privileged State of Channel 2 */
#define DMA_PRIVCFGR_PRIV3_Pos (3U)
#define DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */
#define DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk /*!< Privileged State of Channel 3 */
#define DMA_PRIVCFGR_PRIV4_Pos (4U)
#define DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */
#define DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk /*!< Privileged State of Channel 4 */
#define DMA_PRIVCFGR_PRIV5_Pos (5U)
#define DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */
#define DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk /*!< Privileged State of Channel 5 */
#define DMA_PRIVCFGR_PRIV6_Pos (6U)
#define DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */
#define DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk /*!< Privileged State of Channel 6 */
#define DMA_PRIVCFGR_PRIV7_Pos (7U)
#define DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */
#define DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk /*!< Privileged State of Channel 7 */
#define DMA_PRIVCFGR_PRIV8_Pos (8U)
#define DMA_PRIVCFGR_PRIV8_Msk (0x1UL << DMA_PRIVCFGR_PRIV8_Pos) /*!< 0x00000100 */
#define DMA_PRIVCFGR_PRIV8 DMA_PRIVCFGR_PRIV8_Msk /*!< Privileged State of Channel 8 */
#define DMA_PRIVCFGR_PRIV9_Pos (9U)
#define DMA_PRIVCFGR_PRIV9_Msk (0x1UL << DMA_PRIVCFGR_PRIV9_Pos) /*!< 0x00000200 */
#define DMA_PRIVCFGR_PRIV9 DMA_PRIVCFGR_PRIV9_Msk /*!< Privileged State of Channel 9 */
#define DMA_PRIVCFGR_PRIV10_Pos (10U)
#define DMA_PRIVCFGR_PRIV10_Msk (0x1UL << DMA_PRIVCFGR_PRIV10_Pos) /*!< 0x00000400 */
#define DMA_PRIVCFGR_PRIV10 DMA_PRIVCFGR_PRIV10_Msk /*!< Privileged State of Channel 10 */
#define DMA_PRIVCFGR_PRIV11_Pos (11U)
#define DMA_PRIVCFGR_PRIV11_Msk (0x1UL << DMA_PRIVCFGR_PRIV11_Pos) /*!< 0x00000800 */
#define DMA_PRIVCFGR_PRIV11 DMA_PRIVCFGR_PRIV11_Msk /*!< Privileged State of Channel 11 */
#define DMA_PRIVCFGR_PRIV12_Pos (12U)
#define DMA_PRIVCFGR_PRIV12_Msk (0x1UL << DMA_PRIVCFGR_PRIV12_Pos) /*!< 0x00001000 */
#define DMA_PRIVCFGR_PRIV12 DMA_PRIVCFGR_PRIV12_Msk /*!< Privileged State of Channel 12 */
#define DMA_PRIVCFGR_PRIV13_Pos (13U)
#define DMA_PRIVCFGR_PRIV13_Msk (0x1UL << DMA_PRIVCFGR_PRIV13_Pos) /*!< 0x00002000 */
#define DMA_PRIVCFGR_PRIV13 DMA_PRIVCFGR_PRIV13_Msk /*!< Privileged State of Channel 13 */
#define DMA_PRIVCFGR_PRIV14_Pos (14U)
#define DMA_PRIVCFGR_PRIV14_Msk (0x1UL << DMA_PRIVCFGR_PRIV14_Pos) /*!< 0x00004000 */
#define DMA_PRIVCFGR_PRIV14 DMA_PRIVCFGR_PRIV14_Msk /*!< Privileged State of Channel 14 */
#define DMA_PRIVCFGR_PRIV15_Pos (15U)
#define DMA_PRIVCFGR_PRIV15_Msk (0x1UL << DMA_PRIVCFGR_PRIV15_Pos) /*!< 0x00008000 */
#define DMA_PRIVCFGR_PRIV15 DMA_PRIVCFGR_PRIV15_Msk /*!< Privileged State of Channel 15 */
/******************* Bit definition for DMA_RCFGLOCKR register ****************/
#define DMA_RCFGLOCKR_LOCK0_Pos (0U)
#define DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) /*!< 0x00000001 */
#define DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk /*!< Lock the configuration of Channel 0 */
#define DMA_RCFGLOCKR_LOCK1_Pos (1U)
#define DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) /*!< 0x00000002 */
#define DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk /*!< Lock the configuration of Channel 1 */
#define DMA_RCFGLOCKR_LOCK2_Pos (2U)
#define DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) /*!< 0x00000004 */
#define DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk /*!< Lock the configuration of Channel 2 */
#define DMA_RCFGLOCKR_LOCK3_Pos (3U)
#define DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) /*!< 0x00000008 */
#define DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk /*!< Lock the configuration of Channel 3 */
#define DMA_RCFGLOCKR_LOCK4_Pos (4U)
#define DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) /*!< 0x00000010 */
#define DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk /*!< Lock the configuration of Channel 4 */
#define DMA_RCFGLOCKR_LOCK5_Pos (5U)
#define DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) /*!< 0x00000020 */
#define DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk /*!< Lock the configuration of Channel 5 */
#define DMA_RCFGLOCKR_LOCK6_Pos (6U)
#define DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) /*!< 0x00000040 */
#define DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk /*!< Lock the configuration of Channel 6 */
#define DMA_RCFGLOCKR_LOCK7_Pos (7U)
#define DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) /*!< 0x00000080 */
#define DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk /*!< Lock the configuration of Channel 7 */
#define DMA_RCFGLOCKR_LOCK8_Pos (8U)
#define DMA_RCFGLOCKR_LOCK8_Msk (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos) /*!< 0x00000100 */
#define DMA_RCFGLOCKR_LOCK8 DMA_RCFGLOCKR_LOCK8_Msk /*!< Lock the configuration of Channel 8 */
#define DMA_RCFGLOCKR_LOCK9_Pos (9U)
#define DMA_RCFGLOCKR_LOCK9_Msk (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos) /*!< 0x00000200 */
#define DMA_RCFGLOCKR_LOCK9 DMA_RCFGLOCKR_LOCK9_Msk /*!< Lock the configuration of Channel 9 */
#define DMA_RCFGLOCKR_LOCK10_Pos (10U)
#define DMA_RCFGLOCKR_LOCK10_Msk (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos) /*!< 0x00000400 */
#define DMA_RCFGLOCKR_LOCK10 DMA_RCFGLOCKR_LOCK10_Msk /*!< Lock the configuration of Channel 10 */
#define DMA_RCFGLOCKR_LOCK11_Pos (11U)
#define DMA_RCFGLOCKR_LOCK11_Msk (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos) /*!< 0x00000800 */
#define DMA_RCFGLOCKR_LOCK11 DMA_RCFGLOCKR_LOCK11_Msk /*!< Lock the configuration of Channel 11 */
#define DMA_RCFGLOCKR_LOCK12_Pos (12U)
#define DMA_RCFGLOCKR_LOCK12_Msk (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos) /*!< 0x00001000 */
#define DMA_RCFGLOCKR_LOCK12 DMA_RCFGLOCKR_LOCK12_Msk /*!< Lock the configuration of Channel 12 */
#define DMA_RCFGLOCKR_LOCK13_Pos (13U)
#define DMA_RCFGLOCKR_LOCK13_Msk (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos) /*!< 0x00002000 */
#define DMA_RCFGLOCKR_LOCK13 DMA_RCFGLOCKR_LOCK13_Msk /*!< Lock the configuration of Channel 13 */
#define DMA_RCFGLOCKR_LOCK14_Pos (14U)
#define DMA_RCFGLOCKR_LOCK14_Msk (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos) /*!< 0x00004000 */
#define DMA_RCFGLOCKR_LOCK14 DMA_RCFGLOCKR_LOCK14_Msk /*!< Lock the configuration of Channel 14 */
#define DMA_RCFGLOCKR_LOCK15_Pos (15U)
#define DMA_RCFGLOCKR_LOCK15_Msk (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos) /*!< 0x00008000 */
#define DMA_RCFGLOCKR_LOCK15 DMA_RCFGLOCKR_LOCK15_Msk /*!< Lock the configuration of Channel 15 */
/******************* Bit definition for DMA_MISR register ****************/
#define DMA_MISR_MIS0_Pos (0U)
#define DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) /*!< 0x00000001 */
#define DMA_MISR_MIS0 DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */
#define DMA_MISR_MIS1_Pos (1U)
#define DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) /*!< 0x00000002 */
#define DMA_MISR_MIS1 DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */
#define DMA_MISR_MIS2_Pos (2U)
#define DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) /*!< 0x00000004 */
#define DMA_MISR_MIS2 DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */
#define DMA_MISR_MIS3_Pos (3U)
#define DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) /*!< 0x00000008 */
#define DMA_MISR_MIS3 DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */
#define DMA_MISR_MIS4_Pos (4U)
#define DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) /*!< 0x00000010 */
#define DMA_MISR_MIS4 DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */
#define DMA_MISR_MIS5_Pos (5U)
#define DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) /*!< 0x00000020 */
#define DMA_MISR_MIS5 DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */
#define DMA_MISR_MIS6_Pos (6U)
#define DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) /*!< 0x00000040 */
#define DMA_MISR_MIS6 DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */
#define DMA_MISR_MIS7_Pos (7U)
#define DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) /*!< 0x00000080 */
#define DMA_MISR_MIS7 DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */
#define DMA_MISR_MIS8_Pos (8U)
#define DMA_MISR_MIS8_Msk (0x1UL << DMA_MISR_MIS8_Pos) /*!< 0x00000100 */
#define DMA_MISR_MIS8 DMA_MISR_MIS8_Msk /*!< Masked Interrupt State of Non-Secure Channel 8 */
#define DMA_MISR_MIS9_Pos (9U)
#define DMA_MISR_MIS9_Msk (0x1UL << DMA_MISR_MIS9_Pos) /*!< 0x00000200 */
#define DMA_MISR_MIS9 DMA_MISR_MIS9_Msk /*!< Masked Interrupt State of Non-Secure Channel 9 */
#define DMA_MISR_MIS10_Pos (10U)
#define DMA_MISR_MIS10_Msk (0x1UL << DMA_MISR_MIS10_Pos) /*!< 0x00000400 */
#define DMA_MISR_MIS10 DMA_MISR_MIS10_Msk /*!< Masked Interrupt State of Non-Secure Channel 10 */
#define DMA_MISR_MIS11_Pos (11U)
#define DMA_MISR_MIS11_Msk (0x1UL << DMA_MISR_MIS11_Pos) /*!< 0x00000800 */
#define DMA_MISR_MIS11 DMA_MISR_MIS11_Msk /*!< Masked Interrupt State of Non-Secure Channel 11 */
#define DMA_MISR_MIS12_Pos (12U)
#define DMA_MISR_MIS12_Msk (0x1UL << DMA_MISR_MIS12_Pos) /*!< 0x00001000 */
#define DMA_MISR_MIS12 DMA_MISR_MIS12_Msk /*!< Masked Interrupt State of Non-Secure Channel 12 */
#define DMA_MISR_MIS13_Pos (13U)
#define DMA_MISR_MIS13_Msk (0x1UL << DMA_MISR_MIS13_Pos) /*!< 0x00002000 */
#define DMA_MISR_MIS13 DMA_MISR_MIS13_Msk /*!< Masked Interrupt State of Non-Secure Channel 13 */
#define DMA_MISR_MIS14_Pos (14U)
#define DMA_MISR_MIS14_Msk (0x1UL << DMA_MISR_MIS14_Pos) /*!< 0x00004000 */
#define DMA_MISR_MIS14 DMA_MISR_MIS14_Msk /*!< Masked Interrupt State of Non-Secure Channel 14 */
#define DMA_MISR_MIS15_Pos (15U)
#define DMA_MISR_MIS15_Msk (0x1UL << DMA_MISR_MIS15_Pos) /*!< 0x00008000 */
#define DMA_MISR_MIS15 DMA_MISR_MIS14_Msk /*!< Masked Interrupt State of Non-Secure Channel 15 */
/******************* Bit definition for DMA_SMISR register ****************/
#define DMA_SMISR_MIS0_Pos (0U)
#define DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) /*!< 0x00000001 */
#define DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk /*!< Masked Interrupt State of Secure Channel 0 */
#define DMA_SMISR_MIS1_Pos (1U)
#define DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) /*!< 0x00000002 */
#define DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk /*!< Masked Interrupt State of Secure Channel 1 */
#define DMA_SMISR_MIS2_Pos (2U)
#define DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) /*!< 0x00000004 */
#define DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk /*!< Masked Interrupt State of Secure Channel 2 */
#define DMA_SMISR_MIS3_Pos (3U)
#define DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) /*!< 0x00000008 */
#define DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk /*!< Masked Interrupt State of Secure Channel 3 */
#define DMA_SMISR_MIS4_Pos (4U)
#define DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) /*!< 0x00000010 */
#define DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk /*!< Masked Interrupt State of Secure Channel 4 */
#define DMA_SMISR_MIS5_Pos (5U)
#define DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) /*!< 0x00000020 */
#define DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk /*!< Masked Interrupt State of Secure Channel 5 */
#define DMA_SMISR_MIS6_Pos (6U)
#define DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) /*!< 0x00000040 */
#define DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk /*!< Masked Interrupt State of Secure Channel 6 */
#define DMA_SMISR_MIS7_Pos (7U)
#define DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) /*!< 0x00000080 */
#define DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk /*!< Masked Interrupt State of Secure Channel 7 */
#define DMA_SMISR_MIS8_Pos (8U)
#define DMA_SMISR_MIS8_Msk (0x1UL << DMA_SMISR_MIS8_Pos) /*!< 0x00000100 */
#define DMA_SMISR_MIS8 DMA_SMISR_MIS8_Msk /*!< Masked Interrupt State of Secure Channel 8 */
#define DMA_SMISR_MIS9_Pos (9U)
#define DMA_SMISR_MIS9_Msk (0x1UL << DMA_SMISR_MIS9_Pos) /*!< 0x00000200 */
#define DMA_SMISR_MIS9 DMA_SMISR_MIS9_Msk /*!< Masked Interrupt State of Secure Channel 9 */
#define DMA_SMISR_MIS10_Pos (10U)
#define DMA_SMISR_MIS10_Msk (0x1UL << DMA_SMISR_MIS10_Pos) /*!< 0x00000400 */
#define DMA_SMISR_MIS10 DMA_SMISR_MIS10_Msk /*!< Masked Interrupt State of Secure Channel 10 */
#define DMA_SMISR_MIS11_Pos (11U)
#define DMA_SMISR_MIS11_Msk (0x1UL << DMA_SMISR_MIS11_Pos) /*!< 0x00000800 */
#define DMA_SMISR_MIS11 DMA_SMISR_MIS11_Msk /*!< Masked Interrupt State of Secure Channel 11 */
#define DMA_SMISR_MIS12_Pos (12U)
#define DMA_SMISR_MIS12_Msk (0x1UL << DMA_SMISR_MIS12_Pos) /*!< 0x00001000 */
#define DMA_SMISR_MIS12 DMA_SMISR_MIS12_Msk /*!< Masked Interrupt State of Secure Channel 12 */
#define DMA_SMISR_MIS13_Pos (13U)
#define DMA_SMISR_MIS13_Msk (0x1UL << DMA_SMISR_MIS13_Pos) /*!< 0x00002000 */
#define DMA_SMISR_MIS13 DMA_SMISR_MIS13_Msk /*!< Masked Interrupt State of Secure Channel 13 */
#define DMA_SMISR_MIS14_Pos (14U)
#define DMA_SMISR_MIS14_Msk (0x1UL << DMA_SMISR_MIS14_Pos) /*!< 0x00004000 */
#define DMA_SMISR_MIS14 DMA_SMISR_MIS14_Msk /*!< Masked Interrupt State of Secure Channel 14 */
#define DMA_SMISR_MIS15_Pos (15U)
#define DMA_SMISR_MIS15_Msk (0x1UL << DMA_SMISR_MIS15_Pos) /*!< 0x00008000 */
#define DMA_SMISR_MIS15 DMA_SMISR_MIS14_Msk /*!< Masked Interrupt State of Secure Channel 15 */
/******************* Bit definition for DMA_CLBAR register ****************/
#define DMA_CLBAR_LBA_Pos (16U)
#define DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) /*!< 0xFFFF0000 */
#define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-list Base Address of DMA channel x */
/******************* Bit definition for DMA_CCIDCFGR register *******************/
#define DMA_CCIDCFGR_CFEN_Pos (0U)
#define DMA_CCIDCFGR_CFEN_Msk (0x1UL << DMA_CCIDCFGR_CFEN_Pos) /*!< 0x00000001 */
#define DMA_CCIDCFGR_CFEN DMA_CCIDCFGR_CFEN_Msk /*!< CID filtering enable of the channel x */
#define DMA_CCIDCFGR_SCID_Pos (4U)
#define DMA_CCIDCFGR_SCID_Msk (0x7UL << DMA_CCIDCFGR_SCID_Pos) /*!< 0x00000070 */
#define DMA_CCIDCFGR_SCID DMA_CCIDCFGR_SCID_Msk /*!< select a static CID to the channel x */
/******************* Bit definition for DMA_CFCR register *******************/
#define DMA_CFCR_TCF_Pos (8U)
#define DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) /*!< 0x00000100 */
#define DMA_CFCR_TCF DMA_CFCR_TCF_Msk /*!< Transfer complete flag clear */
#define DMA_CFCR_HTF_Pos (9U)
#define DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) /*!< 0x00000200 */
#define DMA_CFCR_HTF DMA_CFCR_HTF_Msk /*!< Half transfer complete flag clear */
#define DMA_CFCR_DTEF_Pos (10U)
#define DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) /*!< 0x00000400 */
#define DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk /*!< Data transfer error flag clear */
#define DMA_CFCR_ULEF_Pos (11U)
#define DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) /*!< 0x00000800 */
#define DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag clear */
#define DMA_CFCR_USEF_Pos (12U)
#define DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) /*!< 0x00001000 */
#define DMA_CFCR_USEF DMA_CFCR_USEF_Msk /*!< User setting error flag clear */
#define DMA_CFCR_SUSPF_Pos (13U)
#define DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) /*!< 0x00002000 */
#define DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk /*!< Completed suspension flag clear */
#define DMA_CFCR_TOF_Pos (14U)
#define DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) /*!< 0x00004000 */
#define DMA_CFCR_TOF DMA_CFCR_TOF_Msk /*!< Trigger overrun clear flag */
/******************* Bit definition for DMA_CSR register *******************/
#define DMA_CSR_IDLEF_Pos (0U)
#define DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) /*!< 0x00000001 */
#define DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk /*!< Idle flag */
#define DMA_CSR_TCF_Pos (8U)
#define DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) /*!< 0x00000100 */
#define DMA_CSR_TCF DMA_CSR_TCF_Msk /*!< Transfer complete flag */
#define DMA_CSR_HTF_Pos (9U)
#define DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) /*!< 0x00000200 */
#define DMA_CSR_HTF DMA_CSR_HTF_Msk /*!< Half transfer complete flag */
#define DMA_CSR_DTEF_Pos (10U)
#define DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) /*!< 0x00000400 */
#define DMA_CSR_DTEF DMA_CSR_DTEF_Msk /*!< Data transfer error flag */
#define DMA_CSR_ULEF_Pos (11U)
#define DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) /*!< 0x00000800 */
#define DMA_CSR_ULEF DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag */
#define DMA_CSR_USEF_Pos (12U)
#define DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) /*!< 0x00001000 */
#define DMA_CSR_USEF DMA_CSR_USEF_Msk /*!< User setting error flag */
#define DMA_CSR_SUSPF_Pos (13U)
#define DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) /*!< 0x00002000 */
#define DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk /*!< User setting error flag */
#define DMA_CSR_TOF_Pos (14U)
#define DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) /*!< 0x00004000 */
#define DMA_CSR_TOF DMA_CSR_TOF_Msk /*!< Trigger overrun flag */
#define DMA_CSR_FIFOL_Pos (16U)
#define DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) /*!< 0x00FF0000 */
#define DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk /*!< Monitored FIFO level in bytes */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_RESET_Pos (1U)
#define DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) /*!< 0x00000002 */
#define DMA_CCR_RESET DMA_CCR_RESET_Msk /*!< Channel reset */
#define DMA_CCR_SUSP_Pos (2U)
#define DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) /*!< 0x00000004 */
#define DMA_CCR_SUSP DMA_CCR_SUSP_Msk /*!< Channel suspend */
#define DMA_CCR_TCIE_Pos (8U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000100 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (9U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000200 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half transfer complete interrupt enable */
#define DMA_CCR_DTEIE_Pos (10U)
#define DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) /*!< 0x00000400 */
#define DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk /*!< Data transfer error interrupt enable */
#define DMA_CCR_ULEIE_Pos (11U)
#define DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) /*!< 0x00000800 */
#define DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk /*!< Update linked-list item error interrupt enable */
#define DMA_CCR_USEIE_Pos (12U)
#define DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) /*!< 0x00001000 */
#define DMA_CCR_USEIE DMA_CCR_USEIE_Msk /*!< User setting error interrupt enable */
#define DMA_CCR_SUSPIE_Pos (13U)
#define DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) /*!< 0x00002000 */
#define DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk /*!< Completed suspension interrupt enable */
#define DMA_CCR_TOIE_Pos (14U)
#define DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) /*!< 0x00004000 */
#define DMA_CCR_TOIE DMA_CCR_TOIE_Msk /*!< Trigger overrun interrupt enable */
#define DMA_CCR_LSM_Pos (16U)
#define DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) /*!< 0x00010000 */
#define DMA_CCR_LSM DMA_CCR_LSM_Msk /*!< Link step mode */
#define DMA_CCR_LAP_Pos (17U)
#define DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) /*!< 0x00020000 */
#define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-list allocated port */
#define DMA_CCR_PRIO_Pos (22U)
#define DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) /*!< 0x00C00000 */
#define DMA_CCR_PRIO DMA_CCR_PRIO_Msk /*!< Priority level */
#define DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) /*!< 0x00400000 */
#define DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) /*!< 0x00800000 */
/******************* Bit definition for DMA_CTR1 register *******************/
#define DMA_CTR1_SDW_LOG2_Pos (0U)
#define DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) /*!< 0x00000003 */
#define DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk /*!< Binary logarithm of the source data width of a burst */
#define DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 0 */
#define DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) /*!< Bit 1 */
#define DMA_CTR1_SINC_Pos (3U)
#define DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) /*!< 0x00000008 */
#define DMA_CTR1_SINC DMA_CTR1_SINC_Msk /*!< Source incrementing burst */
#define DMA_CTR1_SBL_1_Pos (4U)
#define DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) /*!< 0x000003F0 */
#define DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk /*!< Source burst length minus 1 */
#define DMA_CTR1_PAM_Pos (11U)
#define DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) /*!< 0x0001800 */
#define DMA_CTR1_PAM DMA_CTR1_PAM_Msk /*!< Padding / alignment mode */
#define DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) /*!< Bit 0 */
#define DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) /*!< Bit 1 */
#define DMA_CTR1_SBX_Pos (13U)
#define DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) /*!< 0x00002000 */
#define DMA_CTR1_SBX DMA_CTR1_SBX_Msk /*!< Source byte exchange within the unaligned half-word of each source word */
#define DMA_CTR1_SAP_Pos (14U)
#define DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) /*!< 0x00004000 */
#define DMA_CTR1_SAP DMA_CTR1_SAP_Msk /*!< Source allocated port */
#define DMA_CTR1_SSEC_Pos (15U)
#define DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) /*!< 0x00008000 */
#define DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk /*!< Security attribute of the DMA transfer from the source */
#define DMA_CTR1_DDW_LOG2_Pos (16U)
#define DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) /*!< 0x00030000 */
#define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary logarithm of the destination data width of a burst */
#define DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 0 */
#define DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) /*!< Bit 1 */
#define DMA_CTR1_DINC_Pos (19U)
#define DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) /*!< 0x00080000 */
#define DMA_CTR1_DINC DMA_CTR1_DINC_Msk /*!< Destination incrementing burst */
#define DMA_CTR1_DBL_1_Pos (20U)
#define DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) /*!< 0x03F00000 */
#define DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk /*!< Destination burst length minus 1 */
#define DMA_CTR1_DBX_Pos (26U)
#define DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) /*!< 0x04000000 */
#define DMA_CTR1_DBX DMA_CTR1_DBX_Msk /*!< Destination byte exchange */
#define DMA_CTR1_DHX_Pos (27U)
#define DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) /*!< 0x08000000 */
#define DMA_CTR1_DHX DMA_CTR1_DHX_Msk /*!< Destination half-word exchange */
#define DMA_CTR1_DWX_Pos (28U)
#define DMA_CTR1_DWX_Msk (0x1UL << DMA_CTR1_DWX_Pos) /*!< 0x10000000 */
#define DMA_CTR1_DWX DMA_CTR1_DWX_Msk /*!< Destination word-word exchange */
#define DMA_CTR1_DAP_Pos (30U)
#define DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) /*!< 0x40000000 */
#define DMA_CTR1_DAP DMA_CTR1_DAP_Msk /*!< Destination allocated port */
#define DMA_CTR1_DSEC_Pos (31U)
#define DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) /*!< 0x80000000 */
#define DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk /*!< Security attribute of the DMA transfer from the destination */
/****************** Bit definition for DMA_CTR2 register *******************/
#define DMA_CTR2_REQSEL_Pos (0U)
#define DMA_CTR2_REQSEL_Msk (0xFFUL << DMA_CTR2_REQSEL_Pos) /*!< 0x000000FF */
#define DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk /*!< DMA hardware request selection */
#define DMA_CTR2_SWREQ_Pos (9U)
#define DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) /*!< 0x00000200 */
#define DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk /*!< Software request */
#define DMA_CTR2_DREQ_Pos (10U)
#define DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) /*!< 0x00000400 */
#define DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk /*!< Destination hardware request */
#define DMA_CTR2_BREQ_Pos (11U)
#define DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) /*!< 0x00000800 */
#define DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk /*!< Block hardware request */
#define DMA_CTR2_PFREQ_Pos (12U)
#define DMA_CTR2_PFREQ_Msk (0x1UL << DMA_CTR2_PFREQ_Pos) /*!< 0x00001000 */
#define DMA_CTR2_PFREQ DMA_CTR2_PFREQ_Msk /*!< Hardware request in peripheral flow control mode */
#define DMA_CTR2_TRIGM_Pos (14U)
#define DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) /*!< 0x0000C000 */
#define DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk /*!< Trigger mode */
#define DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 0 */
#define DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) /*!< Bit 1 */
#define DMA_CTR2_TRIGSEL_Pos (16U)
#define DMA_CTR2_TRIGSEL_Msk (0x7FUL << DMA_CTR2_TRIGSEL_Pos) /*!< 0x007F0000 */
#define DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk /*!< Trigger event input selection */
#define DMA_CTR2_TRIGPOL_Pos (24U)
#define DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) /*!< 0x03000000 */
#define DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk /*!< Trigger event polarity */
#define DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 0 */
#define DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) /*!< Bit 1 */
#define DMA_CTR2_TCEM_Pos (30U)
#define DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) /*!< 0xC0000000 */
#define DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk /*!< Transfer complete event mode */
#define DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) /*!< Bit 0 */
#define DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) /*!< Bit 1 */
/****************** Bit definition for DMA_CBR1 register *******************/
#define DMA_CBR1_BNDT_Pos (0U)
#define DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) /*!< 0x0000FFFF */
#define DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk /*!< Block number of data bytes to transfer from the source */
#define DMA_CBR1_BRC_Pos (16U)
#define DMA_CBR1_BRC_Msk (0x7FFUL << DMA_CBR1_BRC_Pos) /*!< 0x07FF0000 */
#define DMA_CBR1_BRC DMA_CBR1_BRC_Msk /*!< Block repeat counter */
#define DMA_CBR1_SDEC_Pos (28U)
#define DMA_CBR1_SDEC_Msk (0x1UL << DMA_CBR1_SDEC_Pos) /*!< 0x10000000 */
#define DMA_CBR1_SDEC DMA_CBR1_SDEC_Msk /*!< Source address decrement */
#define DMA_CBR1_DDEC_Pos (29U)
#define DMA_CBR1_DDEC_Msk (0x1UL << DMA_CBR1_DDEC_Pos) /*!< 0x20000000 */
#define DMA_CBR1_DDEC DMA_CBR1_DDEC_Msk /*!< Destination address decrement */
#define DMA_CBR1_BRSDEC_Pos (30U)
#define DMA_CBR1_BRSDEC_Msk (0x1UL << DMA_CBR1_BRSDEC_Pos) /*!< 0x40000000 */
#define DMA_CBR1_BRSDEC DMA_CBR1_BRSDEC_Msk /*!< Block repeat source address decrement */
#define DMA_CBR1_BRDDEC_Pos (31U)
#define DMA_CBR1_BRDDEC_Msk (0x1UL << DMA_CBR1_BRDDEC_Pos) /*!< 0x80000000 */
#define DMA_CBR1_BRDDEC DMA_CBR1_BRDDEC_Msk /*!< Block repeat destination address decrement */
/****************** Bit definition for DMA_CSAR register ********************/
#define DMA_CSAR_SA_Pos (0U)
#define DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CSAR_SA DMA_CSAR_SA_Msk /*!< Source Address */
/****************** Bit definition for DMA_CDAR register *******************/
#define DMA_CDAR_DA_Pos (0U)
#define DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CDAR_DA DMA_CDAR_DA_Msk /*!< Destination address */
/****************** Bit definition for DMA_CTR3 register *******************/
#define DMA_CTR3_SAO_Pos (0U)
#define DMA_CTR3_SAO_Msk (0x1FFFUL << DMA_CTR3_SAO_Pos) /*!< 0x00001FFF */
#define DMA_CTR3_SAO DMA_CTR3_SAO_Msk /*!< Source address offset increment */
#define DMA_CTR3_DAO_Pos (16U)
#define DMA_CTR3_DAO_Msk (0x1FFFUL << DMA_CTR3_DAO_Pos) /*!< 0x1FFF0000 */
#define DMA_CTR3_DAO DMA_CTR3_DAO_Msk /*!< Destination address offset increment */
/****************** Bit definition for DMA_CBR2 register *******************/
#define DMA_CBR2_BRSAO_Pos (0U)
#define DMA_CBR2_BRSAO_Msk (0xFFFFUL << DMA_CBR2_BRSAO_Pos) /*!< 0x0000FFFF */
#define DMA_CBR2_BRSAO DMA_CBR2_BRSAO_Msk /*!< Block repeated source address offset */
#define DMA_CBR2_BRDAO_Pos (16U)
#define DMA_CBR2_BRDAO_Msk (0xFFFFUL << DMA_CBR2_BRDAO_Pos) /*!< 0xFFFF0000 */
#define DMA_CBR2_BRDAO DMA_CBR2_BRDAO_Msk /*!< Block repeated destination address offset */
/****************** Bit definition for DMA_CLLR register *******************/
#define DMA_CLLR_LA_Pos (2U)
#define DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) /*!< 0x0000FFFC */
#define DMA_CLLR_LA DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
#define DMA_CLLR_ULL_Pos (16U)
#define DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) /*!< 0x00010000 */
#define DMA_CLLR_ULL DMA_CLLR_ULL_Msk /*!< Update link address register from memory */
#define DMA_CLLR_UB2_Pos (25U)
#define DMA_CLLR_UB2_Msk (0x1UL << DMA_CLLR_UB2_Pos) /*!< 0x02000000 */
#define DMA_CLLR_UB2 DMA_CLLR_UB2_Msk /*!< Update block register 2 from memory */
#define DMA_CLLR_UT3_Pos (26U)
#define DMA_CLLR_UT3_Msk (0x1UL << DMA_CLLR_UT3_Pos) /*!< 0x04000000 */
#define DMA_CLLR_UT3 DMA_CLLR_UT3_Msk /*!< Update transfer register 3 from SRAM */
#define DMA_CLLR_UDA_Pos (27U)
#define DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) /*!< 0x08000000 */
#define DMA_CLLR_UDA DMA_CLLR_UDA_Msk /*!< Update destination address register from SRAM */
#define DMA_CLLR_USA_Pos (28U)
#define DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) /*!< 0x10000000 */
#define DMA_CLLR_USA DMA_CLLR_USA_Msk /*!< Update source address register from SRAM */
#define DMA_CLLR_UB1_Pos (29U)
#define DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) /*!< 0x20000000 */
#define DMA_CLLR_UB1 DMA_CLLR_UB1_Msk /*!< Update block register 1 from SRAM */
#define DMA_CLLR_UT2_Pos (30U)
#define DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) /*!< 0x40000000 */
#define DMA_CLLR_UT2 DMA_CLLR_UT2_Msk /*!< Update transfer register 2 from SRAM */
#define DMA_CLLR_UT1_Pos (31U)
#define DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) /*!< 0x80000000 */
#define DMA_CLLR_UT1 DMA_CLLR_UT1_Msk /*!< Update transfer register 1 from SRAM */
/******************************************************************************/
/* */
/* DMA2D Controller (DMA2D) */
/* */
/******************************************************************************/
/******************** Bit definition for DMA2D_CR register ******************/
#define DMA2D_CR_START_Pos (0U)
#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
#define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
#define DMA2D_CR_SUSP_Pos (1U)
#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
#define DMA2D_CR_ABORT_Pos (2U)
#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
#define DMA2D_CR_LOM_Pos (6U)
#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
#define DMA2D_CR_TEIE_Pos (8U)
#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define DMA2D_CR_TCIE_Pos (9U)
#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define DMA2D_CR_TWIE_Pos (10U)
#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
#define DMA2D_CR_CAEIE_Pos (11U)
#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
#define DMA2D_CR_CTCIE_Pos (12U)
#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
#define DMA2D_CR_CEIE_Pos (13U)
#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
#define DMA2D_CR_MODE_Pos (16U)
#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
/******************** Bit definition for DMA2D_ISR register *****************/
#define DMA2D_ISR_TEIF_Pos (0U)
#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
#define DMA2D_ISR_TCIF_Pos (1U)
#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
#define DMA2D_ISR_TWIF_Pos (2U)
#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_ISR_CAEIF_Pos (3U)
#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_ISR_CTCIF_Pos (4U)
#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_ISR_CEIF_Pos (5U)
#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_IFCR register ****************/
#define DMA2D_IFCR_CTEIF_Pos (0U)
#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
#define DMA2D_IFCR_CTCIF_Pos (1U)
#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CTWIF_Pos (2U)
#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
#define DMA2D_IFCR_CAECIF_Pos (3U)
#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
#define DMA2D_IFCR_CCTCIF_Pos (4U)
#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
#define DMA2D_IFCR_CCEIF_Pos (5U)
#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
/******************** Bit definition for DMA2D_FGMAR register ***************/
#define DMA2D_FGMAR_MA_Pos (0U)
#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_FGOR register ****************/
#define DMA2D_FGOR_LO_Pos (0U)
#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_BGMAR register ***************/
#define DMA2D_BGMAR_MA_Pos (0U)
#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_BGOR register ****************/
#define DMA2D_BGOR_LO_Pos (0U)
#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_FGPFCCR register *************/
#define DMA2D_FGPFCCR_CM_Pos (0U)
#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
#define DMA2D_FGPFCCR_CCM_Pos (4U)
#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
#define DMA2D_FGPFCCR_START_Pos (5U)
#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
#define DMA2D_FGPFCCR_CS_Pos (8U)
#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
#define DMA2D_FGPFCCR_AM_Pos (16U)
#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
#define DMA2D_FGPFCCR_CSS_Pos (18U)
#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /*!< Chroma Sub-Sampling */
#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
#define DMA2D_FGPFCCR_AI_Pos (20U)
#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Alpha Inverted */
#define DMA2D_FGPFCCR_RBS_Pos (21U)
#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Red Blue Swap */
#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
/******************** Bit definition for DMA2D_FGCOLR register **************/
#define DMA2D_FGCOLR_BLUE_Pos (0U)
#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
#define DMA2D_FGCOLR_GREEN_Pos (8U)
#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
#define DMA2D_FGCOLR_RED_Pos (16U)
#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
/******************** Bit definition for DMA2D_BGPFCCR register *************/
#define DMA2D_BGPFCCR_CM_Pos (0U)
#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
#define DMA2D_BGPFCCR_CCM_Pos (4U)
#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
#define DMA2D_BGPFCCR_START_Pos (5U)
#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
#define DMA2D_BGPFCCR_CS_Pos (8U)
#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
#define DMA2D_BGPFCCR_AM_Pos (16U)
#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
#define DMA2D_BGPFCCR_AI_Pos (20U)
#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< Alpha Inverted */
#define DMA2D_BGPFCCR_RBS_Pos (21U)
#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Red Blue Swap */
#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< Alpha value */
/******************** Bit definition for DMA2D_BGCOLR register **************/
#define DMA2D_BGCOLR_BLUE_Pos (0U)
#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
#define DMA2D_BGCOLR_GREEN_Pos (8U)
#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
#define DMA2D_BGCOLR_RED_Pos (16U)
#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
/******************** Bit definition for DMA2D_FGCMAR register **************/
#define DMA2D_FGCMAR_MA_Pos (0U)
#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_BGCMAR register **************/
#define DMA2D_BGCMAR_MA_Pos (0U)
#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_OPFCCR register **************/
#define DMA2D_OPFCCR_CM_Pos (0U)
#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
#define DMA2D_OPFCCR_SB_Pos (8U)
#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
#define DMA2D_OPFCCR_AI_Pos (20U)
#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Alpha Inverted */
#define DMA2D_OPFCCR_RBS_Pos (21U)
#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Red Blue Swap */
/******************** Bit definition for DMA2D_OCOLR register ***************/
/*!<Mode_ARGB8888/RGB888 */
#define DMA2D_OCOLR_BLUE_1 (0x000000FFUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_1 (0x0000FF00UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_1 (0x00FF0000UL) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_1 (0xFF000000UL) /*!< Alpha Channel Value */
/*!<Mode_RGB565 */
#define DMA2D_OCOLR_BLUE_2 (0x0000001FUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_2 (0x000007E0UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_2 (0x0000F800UL) /*!< Red Value */
/*!<Mode_ARGB1555 */
#define DMA2D_OCOLR_BLUE_3 (0x0000001FUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_3 (0x000003E0UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_3 (0x00007C00UL) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_3 (0x00008000UL) /*!< Alpha Channel Value */
/*!<Mode_ARGB4444 */
#define DMA2D_OCOLR_BLUE_4 (0x0000000FUL) /*!< Blue Value */
#define DMA2D_OCOLR_GREEN_4 (0x000000F0UL) /*!< Green Value */
#define DMA2D_OCOLR_RED_4 (0x00000F00UL) /*!< Red Value */
#define DMA2D_OCOLR_ALPHA_4 (0x0000F000UL) /*!< Alpha Channel Value */
/******************** Bit definition for DMA2D_OMAR register ****************/
#define DMA2D_OMAR_MA_Pos (0U)
#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
/******************** Bit definition for DMA2D_OOR register *****************/
#define DMA2D_OOR_LO_Pos (0U)
#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
/******************** Bit definition for DMA2D_NLR register *****************/
#define DMA2D_NLR_NL_Pos (0U)
#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
#define DMA2D_NLR_PL_Pos (16U)
#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
/******************** Bit definition for DMA2D_LWR register *****************/
#define DMA2D_LWR_LW_Pos (0U)
#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
/******************** Bit definition for DMA2D_AMTCR register ***************/
#define DMA2D_AMTCR_EN_Pos (0U)
#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
#define DMA2D_AMTCR_DT_Pos (8U)
#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
/******************** Bit definition for DMA2D_FGCLUT register **************/
/******************** Bit definition for DMA2D_BGCLUT register **************/
/******************************************************************************/
/* */
/* Digital Temperature Sensor */
/* */
/******************************************************************************/
/******************* Bit definition for DTS_PVTREG_LOCKR register *****************/
#define DTS_PVTREG_LOCKR_LOCK_Pos (0U)
#define DTS_PVTREG_LOCKR_LOCK_Msk (0xFFFFFFFFUL << DTS_PVTREG_LOCKR_LOCK_Pos) /*!< 0xFFFFFFFF */
#define DTS_PVTREG_LOCKR_LOCK DTS_PVTREG_LOCKR_LOCK_Msk /*!< PVT software lock */
/******************* Bit definition for DTS_PVTLOCK_SR register *****************/
#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos (0U)
#define DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk (0x1UL << DTS_PVTLOCK_SR_SW_LOCK_STATUS_Pos) /*!< 0x00000001 */
#define DTS_PVTLOCK_SR_SW_LOCK_STATUS DTS_PVTLOCK_SR_SW_LOCK_STATUS_Msk /*!< Software lock status */
#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos (1U)
#define DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk (0x1UL << DTS_PVTLOCK_SR_HW_LOCK_STATUS_Pos) /*!< 0x00000002 */
#define DTS_PVTLOCK_SR_HW_LOCK_STATUS DTS_PVTLOCK_SR_HW_LOCK_STATUS_Msk /*!< Hardware lock status */
/******************* Bit definition for DTS_PVTTMR_CR register *****************/
#define DTS_PVTTMR_CR_TMR_DELAY_Pos (0U)
#define DTS_PVTTMR_CR_TMR_DELAY_Msk (0xFFFFUL << DTS_PVTTMR_CR_TMR_DELAY_Pos) /*!< 0x0000FFFF */
#define DTS_PVTTMR_CR_TMR_DELAY DTS_PVTTMR_CR_TMR_DELAY_Msk /*!< Timer delay */
#define DTS_PVTTMR_CR_TMR_RUN_Pos (16U)
#define DTS_PVTTMR_CR_TMR_RUN_Msk (0x1UL << DTS_PVTTMR_CR_TMR_RUN_Pos) /*!< 0x00010000 */
#define DTS_PVTTMR_CR_TMR_RUN DTS_PVTTMR_CR_TMR_RUN_Msk /*!< Enable */
/******************* Bit definition for DTS_PVTTMR_SR register *****************/
#define DTS_PVTTMR_SR_TMR_BUSY_Pos (0U)
#define DTS_PVTTMR_SR_TMR_BUSY_Msk (0x1UL << DTS_PVTTMR_SR_TMR_BUSY_Pos) /*!< 0x00000001 */
#define DTS_PVTTMR_SR_TMR_BUSY DTS_PVTTMR_SR_TMR_BUSY_Msk /*!< Counter busy flag */
#define DTS_PVTTMR_SR_TMR_DONE_Pos (1U)
#define DTS_PVTTMR_SR_TMR_DONE_Msk (0x1UL << DTS_PVTTMR_SR_TMR_DONE_Pos) /*!< 0x00000002 */
#define DTS_PVTTMR_SR_TMR_DONE DTS_PVTTMR_SR_TMR_DONE_Msk /*!< Cnt delay timeout */
/******************* Bit definition for DTS_PVT_IER register *****************/
#define DTS_PVT_IER_TMR_IRQ_ENABLE_Pos (0U)
#define DTS_PVT_IER_TMR_IRQ_ENABLE_Msk (0x1UL << DTS_PVT_IER_TMR_IRQ_ENABLE_Pos) /*!< 0x00000001 */
#define DTS_PVT_IER_TMR_IRQ_ENABLE DTS_PVT_IER_TMR_IRQ_ENABLE_Msk /*!< Timer IRQ enable */
#define DTS_PVT_IER_TS_IRQ_ENABLE_Pos (1U)
#define DTS_PVT_IER_TS_IRQ_ENABLE_Msk (0x1UL << DTS_PVT_IER_TS_IRQ_ENABLE_Pos) /*!< 0x00000002 */
#define DTS_PVT_IER_TS_IRQ_ENABLE DTS_PVT_IER_TS_IRQ_ENABLE_Msk /*!< TS IRQ enable */
/******************* Bit definition for DTS_PVTIRQTRMASKR register *****************/
#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos (0U)
#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk (0x1UL << DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Pos) /*!< 0x00000001 */
#define DTS_PVTIRQTRMASKR_TMR_IRQ_MASK DTS_PVTIRQTRMASKR_TMR_IRQ_MASK_Msk /*!< Timer IRQ mask */
/******************* Bit definition for DTS_TS_MR register *****************/
#define DTS_TS_MR_TS0_IRQ_MASK_Pos (0U)
#define DTS_TS_MR_TS0_IRQ_MASK_Msk (0x1UL << DTS_TS_MR_TS0_IRQ_MASK_Pos) /*!< 0x00000001 */
#define DTS_TS_MR_TS0_IRQ_MASK DTS_TS_MR_TS0_IRQ_MASK_Msk /*!< TS0 IRQ mask */
#define DTS_TS_MR_TS1_IRQ_MASK_Pos (1U)
#define DTS_TS_MR_TS1_IRQ_MASK_Msk (0x1UL << DTS_TS_MR_TS1_IRQ_MASK_Pos) /*!< 0x00000002 */
#define DTS_TS_MR_TS1_IRQ_MASK DTS_TS_MR_TS1_IRQ_MASK_Msk /*!< TS1 IRQ mask */
/******************* Bit definition for DTS_PVTTR_SR register *****************/
#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos (0U)
#define DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk (0x1UL << DTS_PVTTR_SR_TMR_IRQ_STATUS_Pos) /*!< 0x00000001 */
#define DTS_PVTTR_SR_TMR_IRQ_STATUS DTS_PVTTR_SR_TMR_IRQ_STATUS_Msk /*!< Timer IRQ status after masking */
/******************* Bit definition for DTS_TS_ISR register *****************/
#define DTS_TS_ISR_TS0_IRQ_STATUS_Pos (0U)
#define DTS_TS_ISR_TS0_IRQ_STATUS_Msk (0x1UL << DTS_TS_ISR_TS0_IRQ_STATUS_Pos) /*!< 0x00000001 */
#define DTS_TS_ISR_TS0_IRQ_STATUS DTS_TS_ISR_TS0_IRQ_STATUS_Msk /*!< TS0 IRQ status after masking */
#define DTS_TS_ISR_TS1_IRQ_STATUS_Pos (1U)
#define DTS_TS_ISR_TS1_IRQ_STATUS_Msk (0x1UL << DTS_TS_ISR_TS1_IRQ_STATUS_Pos) /*!< 0x00000002 */
#define DTS_TS_ISR_TS1_IRQ_STATUS DTS_TS_ISR_TS1_IRQ_STATUS_Msk /*!< TS1 IRQ status after masking */
/******************* Bit definition for DTS_PVTTMRRAW_ISR register *****************/
#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos (0U)
#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk (0x1UL << DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Pos) /*!< 0x00000001 */
#define DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS DTS_PVTTMRRAW_ISR_TMR_IRQ_RAW_STATUS_Msk /*!< Timer IRQ status before masking */
/******************* Bit definition for DTS_TSRAW_ISR register *****************/
#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos (0U)
#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Msk (0x1UL << DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS_Pos) /*!< 0x00000001 */
#define DTS_TSRAW_ISR_TS0_IRQ_RAW_STATUS DTS_TSRAW_ISR_TS0_RAW_IRQ_STATUS_Msk /*!< TS0 IRQ status before masking */
#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos (1U)
#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk (0x1UL << DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Pos) /*!< 0x00000002 */
#define DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS DTS_TSRAW_ISR_TS1_IRQ_RAW_STATUS_Msk /*!< TS1 IRQ status before masking */
/******************* Bit definition for DTS_TSCCLKSYNTHR register *****************/
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos (0U)
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Pos) /*!< 0x000000FF */
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_LO DTS_TSCCLKSYNTHR_CLK_SYNTH_LO_Msk /*!< Synthesized clk_ts low period */
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos (8U)
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk (0xFFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Pos) /*!< 0x0000FF00 */
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HI DTS_TSCCLKSYNTHR_CLK_SYNTH_HI_Msk /*!< Synthesized clk_ts ghigh period */
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos (16U)
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk (0xFUL << DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Pos) /*!< 0x000F0000 */
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD DTS_TSCCLKSYNTHR_CLK_SYNTH_HOLD_Msk /*!< Hold input or output delay */
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos (24U)
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk (0x1UL << DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Pos) /*!< 0x01000000 */
#define DTS_TSCCLKSYNTHR_CLK_SYNTH_EN DTS_TSCCLKSYNTHR_CLK_SYNTH_EN_Msk /*!< Synthesized enable */
/******************* Bit definition for DTS_TSCSDIFDISABLER register *****************/
#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos (0U)
#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk (0x1UL << DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Pos) /*!< 0x00000001 */
#define DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE DTS_TSCSDIFDISABLER_TS0_SDIF_DISABLE_Msk /*!< TS0 SDIF disable */
#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos (1U)
#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk (0x1UL << DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Pos) /*!< 0x00000002 */
#define DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE DTS_TSCSDIFDISABLER_TS1_SDIF_DISABLE_Msk /*!< TS1 SDIF disable */
/******************* Bit definition for DTS_TSCSDIF_SR register *****************/
#define DTS_TSCSDIF_SR_SDIF_BUSY_Pos (0U)
#define DTS_TSCSDIF_SR_SDIF_BUSY_Msk (0x1UL << DTS_TSCSDIF_SR_SDIF_BUSY_Pos) /*!< 0x00000001 */
#define DTS_TSCSDIF_SR_SDIF_BUSY DTS_TSCSDIF_SR_SDIF_BUSY_Msk /*!< SDIF busy flag */
#define DTS_TSCSDIF_SR_SDIF_LOCK_Pos (1U)
#define DTS_TSCSDIF_SR_SDIF_LOCK_Msk (0x1UL << DTS_TSCSDIF_SR_SDIF_LOCK_Pos) /*!< 0x00000002 */
#define DTS_TSCSDIF_SR_SDIF_LOCK DTS_TSCSDIF_SR_SDIF_LOCK_Msk /*!< SDIF locked flag */
/******************* Bit definition for DTS_TSCSDIF_CR register *****************/
#define DTS_TSCSDIF_CR_SDIF_WDATA_Pos (0U)
#define DTS_TSCSDIF_CR_SDIF_WDATA_Msk (0xFFFFFFUL << DTS_TSCSDIF_CR_SDIF_WDATA_Pos) /*!< 0x00FFFFFF */
#define DTS_TSCSDIF_CR_SDIF_WDATA DTS_TSCSDIF_CR_SDIF_WDATA_Msk /*!< SDIF write data */
#define DTS_TSCSDIF_CR_SDIF_ADDR_Pos (24U)
#define DTS_TSCSDIF_CR_SDIF_ADDR_Msk (0x7UL << DTS_TSCSDIF_CR_SDIF_ADDR_Pos) /*!< 0x07000000 */
#define DTS_TSCSDIF_CR_SDIF_ADDR DTS_TSCSDIF_CR_SDIF_ADDR_Msk /*!< SDIF register address */
#define DTS_TSCSDIF_CR_SDIF_WRN_Pos (27U)
#define DTS_TSCSDIF_CR_SDIF_WRN_Msk (0x1UL << DTS_TSCSDIF_CR_SDIF_WRN_Pos) /*!< 0x08000000 */
#define DTS_TSCSDIF_CR_SDIF_WRN DTS_TSCSDIF_CR_SDIF_WRN_Msk /*!< SDIF write no read control */
#define DTS_TSCSDIF_CR_SDIF_PROG_Pos (31U)
#define DTS_TSCSDIF_CR_SDIF_PROG_Msk (0x1UL << DTS_TSCSDIF_CR_SDIF_PROG_Pos) /*!< 0x80000000 */
#define DTS_TSCSDIF_CR_SDIF_PROG DTS_TSCSDIF_CR_SDIF_PROG_Msk /*!< SDIF program request */
/******************* Bit definition for DTS_TSCSDIFHALTR register *****************/
#define DTS_TSCSDIFHALTR_SDIF_STOP_Pos (0U)
#define DTS_TSCSDIFHALTR_SDIF_STOP_Msk (0x1UL << DTS_TSCSDIFHALTR_SDIF_STOP_Pos) /*!< 0x00000001 */
#define DTS_TSCSDIFHALTR_SDIF_STOP DTS_TSCSDIFHALTR_SDIF_STOP_Msk /*!< SDIF stop */
/******************* Bit definition for DTS_TSCSDIF_CFGR register *****************/
#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos (0U)
#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk (0x3UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos) /*!< 0x00000003 */
#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Msk /*!< SDIF programming inhibit */
#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_0 (0x1UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos) /*!< 0x00000001 */
#define DTS_TSCSDIF_CFGR_SDIF_INHIBIT_1 (0x2UL << DTS_TSCSDIF_CFGR_SDIF_INHIBIT_Pos) /*!< 0x00000002 */
/******************* Bit definition for DTS_TSCSMPL_CR register *****************/
#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos (0U)
#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Pos) /*!< 0x00000001 */
#define DTS_TSCSMPL_CR_SMPL_CTR_DISABLE DTS_TSCSMPL_CR_SMPL_CTR_DISABLE_Msk /*!< Sample counter disable */
#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos (1U)
#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk (0x1UL << DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Pos) /*!< 0x00000002 */
#define DTS_TSCSMPL_CR_SMPL_CTR_HOLD DTS_TSCSMPL_CR_SMPL_CTR_HOLD_Msk /*!< Sample counter hold */
#define DTS_TSCSMPL_CR_SMPL_DISCARD_Pos (2U)
#define DTS_TSCSMPL_CR_SMPL_DISCARD_Msk (0x1UL << DTS_TSCSMPL_CR_SMPL_DISCARD_Pos) /*!< 0x00000004 */
#define DTS_TSCSMPL_CR_SMPL_DISCARD DTS_TSCSMPL_CR_SMPL_DISCARD_Msk /*!< Sample discard */
/******************* Bit definition for DTS_TSCSDIFSMPLCLRR register *****************/
#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos (0U)
#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk (0x1UL << DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Pos) /*!< 0x00000001 */
#define DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR DTS_TSCSDIFSMPLCLRR_SMPL_CNTER_CLEAR_Msk /*!< Sample counter clear */
/******************* Bit definition for DTS_TSCSMPLCNTR register *****************/
#define DTS_TSCSMPLCNTR_SMPL_COUNT_Pos (0U)
#define DTS_TSCSMPLCNTR_SMPL_COUNT_Msk (0xFFFFUL << DTS_TSCSMPLCNTR_SMPL_COUNT_Pos) /*!< 0x0000FFFF */
#define DTS_TSCSMPLCNTR_SMPL_COUNT DTS_TSCSMPLCNTR_SMPL_COUNT_Msk /*!< Sample counter */
/******************* Bit definition for DTS_TS_IER register *****************/
#define DTS_TS_IER_IRQ_EN_FAULT_Pos (0U)
#define DTS_TS_IER_IRQ_EN_FAULT_Msk (0x1UL << DTS_TS_IER_IRQ_EN_FAULT_Pos) /*!< 0x00000001 */
#define DTS_TS_IER_IRQ_EN_FAULT DTS_TS_IER_IRQ_EN_FAULT_Msk /*!< TS Fault IRQ enable */
#define DTS_TS_IER_IRQ_EN_DONE_Pos (1U)
#define DTS_TS_IER_IRQ_EN_DONE_Msk (0x1UL << DTS_TS_IER_IRQ_EN_DONE_Pos) /*!< 0x00000002 */
#define DTS_TS_IER_IRQ_EN_DONE DTS_TS_IER_IRQ_EN_DONE_Msk /*!< TS Sample done IRQ enable */
#define DTS_TS_IER_IRQ_EN_ALARMA_Pos (3U)
#define DTS_TS_IER_IRQ_EN_ALARMA_Msk (0x1UL << DTS_TS_IER_IRQ_EN_ALARMA_Pos) /*!< 0x00000008 */
#define DTS_TS_IER_IRQ_EN_ALARMA DTS_TS_IER_IRQ_EN_ALARMA_Msk /*!< TS Alarm A IRQ enable */
#define DTS_TS_IER_IRQ_EN_ALARMB_Pos (4U)
#define DTS_TS_IER_IRQ_EN_ALARMB_Msk (0x1UL << DTS_TS_IER_IRQ_EN_ALARMB_Pos) /*!< 0x00000010 */
#define DTS_TS_IER_IRQ_EN_ALARMB DTS_TS_IER_IRQ_EN_ALARMB_Msk /*!< TS Alarm B IRQ enable */
/******************* Bit definition for DTS_TS_ISR register *****************/
#define DTS_TS_ISR_IRQ_STATUS_FAULT_Pos (0U)
#define DTS_TS_ISR_IRQ_STATUS_FAULT_Msk (0x1UL << DTS_TS_ISR_IRQ_STATUS_FAULT_Pos) /*!< 0x00000001 */
#define DTS_TS_ISR_IRQ_STATUS_FAULT DTS_TS_ISR_IRQ_STATUS_FAULT_Msk /*!< TS Fault IRQ status */
#define DTS_TS_ISR_IRQ_STATUS_DONE_Pos (1U)
#define DTS_TS_ISR_IRQ_STATUS_DONE_Msk (0x1UL << DTS_TS_ISR_IRQ_STATUS_DONE_Pos) /*!< 0x00000002 */
#define DTS_TS_ISR_IRQ_STATUS_DONE DTS_TS_ISR_IRQ_STATUS_DONE_Msk /*!< TS Sample done IRQ status */
#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos (3U)
#define DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMA_Pos) /*!< 0x00000008 */
#define DTS_TS_ISR_IRQ_STATUS_ALARMA DTS_TS_ISR_IRQ_STATUS_ALARMA_Msk /*!< TS Alarm A IRQ status */
#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos (4U)
#define DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk (0x1UL << DTS_TS_ISR_IRQ_STATUS_ALARMB_Pos) /*!< 0x00000010 */
#define DTS_TS_ISR_IRQ_STATUS_ALARMB DTS_TS_ISR_IRQ_STATUS_ALARMB_Msk /*!< TS Alarm B IRQ status */
/******************* Bit definition for DTS_TS_ICR register *****************/
#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos (0U)
#define DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk (0x1UL << DTS_TS_ICR_IRQ_CLEAR_FAULT_Pos) /*!< 0x00000001 */
#define DTS_TS_ICR_IRQ_CLEAR_FAULT DTS_TS_ICR_IRQ_CLEAR_FAULT_Msk /*!< TS Fault IRQ clear */
#define DTS_TS_ICR_IRQ_CLEAR_DONE_Pos (1U)
#define DTS_TS_ICR_IRQ_CLEAR_DONE_Msk (0x1UL << DTS_TS_ICR_IRQ_CLEAR_DONE_Pos) /*!< 0x00000002 */
#define DTS_TS_ICR_IRQ_CLEAR_DONE DTS_TS_ICR_IRQ_CLEAR_DONE_Msk /*!< TS Sample done IRQ clear */
#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos (3U)
#define DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMA_Pos) /*!< 0x00000008 */
#define DTS_TS_ICR_IRQ_CLEAR_ALARMA DTS_TS_ICR_IRQ_CLEAR_ALARMA_Msk /*!< TS Alarm A IRQ clear */
#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos (4U)
#define DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk (0x1UL << DTS_TS_ICR_IRQ_CLEAR_ALARMB_Pos) /*!< 0x00000010 */
#define DTS_TS_ICR_IRQ_CLEAR_ALARMB DTS_TS_ICR_IRQ_CLEAR_ALARMB_Msk /*!< TS Alarm B IRQ clear */
/******************* Bit definition for DTS_TSIRQTESTR register *****************/
#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos (0U)
#define DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_FAULT_Pos) /*!< 0x00000001 */
#define DTS_TSIRQTESTR_IRQ_TEST_FAULT DTS_TSIRQTESTR_IRQ_TEST_FAULT_Msk /*!< TS Fault IRQ test */
#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos (1U)
#define DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_DONE_Pos) /*!< 0x00000002 */
#define DTS_TSIRQTESTR_IRQ_TEST_DONE DTS_TSIRQTESTR_IRQ_TEST_DONE_Msk /*!< TS Sample done IRQ test */
#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos (3U)
#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Pos) /*!< 0x00000008 */
#define DTS_TSIRQTESTR_IRQ_TEST_ALARMA DTS_TSIRQTESTR_IRQ_TEST_ALARMA_Msk /*!< TS Alarm A IRQ test */
#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos (4U)
#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk (0x1UL << DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Pos) /*!< 0x00000010 */
#define DTS_TSIRQTESTR_IRQ_TEST_ALARMB DTS_TSIRQTESTR_IRQ_TEST_ALARMB_Msk /*!< TS Alarm B IRQ test */
/******************* Bit definition for DTS_TSSDIFRDATAR register *****************/
#define DTS_TSSDIFRDATAR_SDIF_RDATA_Pos (0U)
#define DTS_TSSDIFRDATAR_SDIF_RDATA_Msk (0xFFFFFFUL << DTS_TSSDIFRDATAR_SDIF_RDATA_Pos) /*!< 0x00FFFFFF */
#define DTS_TSSDIFRDATAR_SDIF_RDATA DTS_TSSDIFRDATAR_SDIF_RDATA_Msk /*!< TS SDIF read data */
/******************* Bit definition for DTS_TSSDIFDONER register *****************/
#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos (0U)
#define DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk (0x1UL << DTS_TSSDIFDONER_SDIF_SMPL_DONE_Pos) /*!< 0x00000001 */
#define DTS_TSSDIFDONER_SDIF_SMPL_DONE DTS_TSSDIFDONER_SDIF_SMPL_DONE_Msk /*!< TS Sample done flag */
/******************* Bit definition for DTS_TSSDIFDATAR register *****************/
#define DTS_TSSDIFDATAR_SAMPLE_DATA_Pos (0U)
#define DTS_TSSDIFDATAR_SAMPLE_DATA_Msk (0xFFFFUL << DTS_TSSDIFDATAR_SAMPLE_DATA_Pos) /*!< 0x0000FFFF */
#define DTS_TSSDIFDATAR_SAMPLE_DATA DTS_TSSDIFDATAR_SAMPLE_DATA_Msk /*!< TS Sample data */
#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos (16U)
#define DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk (0x1UL << DTS_TSSDIFDATAR_SAMPLE_TYPE_Pos) /*!< 0x00010000 */
#define DTS_TSSDIFDATAR_SAMPLE_TYPE DTS_TSSDIFDATAR_SAMPLE_TYPE_Msk /*!< TS Sample type */
#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos (17U)
#define DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk (0x1UL << DTS_TSSDIFDATAR_SAMPLE_FAULT_Pos) /*!< 0x00020000 */
#define DTS_TSSDIFDATAR_SAMPLE_FAULT DTS_TSSDIFDATAR_SAMPLE_FAULT_Msk /*!< TS Sample fault */
/******************* Bit definition for DTS_TSALARMA_CFGR register *****************/
#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos (0U)
#define DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk (0xFFFFUL << DTS_TSALARMA_CFGR_HYSTA_THRESH_Pos) /*!< 0x0000FFFF */
#define DTS_TSALARMA_CFGR_HYSTA_THRESH DTS_TSALARMA_CFGR_HYSTA_THRESH_Msk /*!< TS Alarm A hysteresis threshold */
#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos (16U)
#define DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk (0xFFFFUL << DTS_TSALARMA_CFGR_ALARMA_THRESH_Pos) /*!< 0xFFFF0000 */
#define DTS_TSALARMA_CFGR_ALARMA_THRESH DTS_TSALARMA_CFGR_ALARMA_THRESH_Msk /*!< TS Alarm A threshold */
/******************* Bit definition for DTS_TSALARMB_CFGR register *****************/
#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos (0U)
#define DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk (0xFFFFUL << DTS_TSALARMB_CFGR_HYSTB_THRESH_Pos) /*!< 0x0000FFFF */
#define DTS_TSALARMB_CFGR_HYSTB_THRESH DTS_TSALARMB_CFGR_HYSTB_THRESH_Msk /*!< TS Alarm B hysteresis threshold */
#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos (16U)
#define DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk (0xFFFFUL << DTS_TSALARMB_CFGR_ALARMB_THRESH_Pos) /*!< 0xFFFF0000 */
#define DTS_TSALARMB_CFGR_ALARMB_THRESH DTS_TSALARMB_CFGR_ALARMB_THRESH_Msk /*!< TS Alarm B threshold */
/******************* Bit definition for DTS_TSHLSAMPLER register *****************/
#define DTS_TSHLSAMPLER_SMPL_LO_Pos (0U)
#define DTS_TSHLSAMPLER_SMPL_LO_Msk (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_LO_Pos) /*!< 0x0000FFFF */
#define DTS_TSHLSAMPLER_SMPL_LO DTS_TSHLSAMPLER_SMPL_LO_Msk /*!< TS Lowest valid data sample value received */
#define DTS_TSHLSAMPLER_SMPL_HI_Pos (16U)
#define DTS_TSHLSAMPLER_SMPL_HI_Msk (0xFFFFUL << DTS_TSHLSAMPLER_SMPL_HI_Pos) /*!< 0xFFFF0000 */
#define DTS_TSHLSAMPLER_SMPL_HI DTS_TSHLSAMPLER_SMPL_HI_Msk /*!< TS Highest valid data sample value received */
/******************* Bit definition for DTS_TSHILORESETR register *****************/
#define DTS_TSHILORESETR_SMPL_LO_SET_Pos (0U)
#define DTS_TSHILORESETR_SMPL_LO_SET_Msk (0x1UL << DTS_TSHILORESETR_SMPL_LO_SET_Pos) /*!< 0x00000001 */
#define DTS_TSHILORESETR_SMPL_LO_SET DTS_TSHILORESETR_SMPL_LO_SET_Msk /*!< TS Sample Low Set */
#define DTS_TSHILORESETR_SMPL_HI_CLR_Pos (1U)
#define DTS_TSHILORESETR_SMPL_HI_CLR_Msk (0x1UL << DTS_TSHILORESETR_SMPL_HI_CLR_Pos) /*!< 0x00000002 */
#define DTS_TSHILORESETR_SMPL_HI_CLR DTS_TSHILORESETR_SMPL_HI_CLR_Msk /*!< TS Sample high clear 0 */
/******************************************************************************/
/* */
/* Ethernet MAC */
/* */
/******************************************************************************/
/****** Bit definition for Ethernet MAC Configuration Register **************/
#define ETH_MACCR_ARP_Pos (31U)
#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
#define ETH_MACCR_SARC_Pos (28U)
#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
#define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
#define ETH_MACCR_IPC_Pos (27U)
#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
#define ETH_MACCR_IPG_Pos (24U)
#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
#define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
#define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
#define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
#define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
#define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
#define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
#define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
#define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
#define ETH_MACCR_GPSLCE_Pos (23U)
#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
#define ETH_MACCR_S2KP_Pos (22U)
#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
#define ETH_MACCR_CST_Pos (21U)
#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
#define ETH_MACCR_ACS_Pos (20U)
#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
#define ETH_MACCR_WD_Pos (19U)
#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
#define ETH_MACCR_PB_Pos (18U)
#define ETH_MACCR_PB_Msk (0x1UL << ETH_MACCR_PB_Pos) /*!< 0x00040000 */
#define ETH_MACCR_PB ETH_MACCR_PB_Msk /* Packet Burst Enable */
#define ETH_MACCR_JD_Pos (17U)
#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
#define ETH_MACCR_JE_Pos (16U)
#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
#define ETH_MACCR_PS_Pos (15U)
#define ETH_MACCR_PS_Msk (0x1UL << ETH_MACCR_PS_Pos) /*!< 0x00008000 */
#define ETH_MACCR_PS ETH_MACCR_PS_Msk /* Port Select */
#define ETH_MACCR_FES_Pos (14U)
#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* MAC speed */
#define ETH_MACCR_DM_Pos (13U)
#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
#define ETH_MACCR_LM_Pos (12U)
#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
#define ETH_MACCR_ECRSFD_Pos (11U)
#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
#define ETH_MACCR_DO_Pos (10U)
#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
#define ETH_MACCR_DCRS_Pos (9U)
#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
#define ETH_MACCR_DR_Pos (8U)
#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
#define ETH_MACCR_BL_Pos (5U)
#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
#define ETH_MACCR_DC_Pos (4U)
#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
#define ETH_MACCR_PRELEN_Pos (2U)
#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
#define ETH_MACCR_TE_Pos (1U)
#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
#define ETH_MACCR_RE_Pos (0U)
#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
/****** Bit definition for Ethernet MAC Extended Configuration Register ***********/
#define ETH_MACECR_APDIM_Pos (30U)
#define ETH_MACECR_APDIM_Msk (0x1FUL << ETH_MACECR_APDIM_Pos) /*!< 0x40000000 */
#define ETH_MACECR_APDIM ETH_MACECR_APDIM_Msk /* ARP Packet Drop if IP Address Mismatch */
#define ETH_MACECR_EIPG_Pos (25U)
#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
#define ETH_MACECR_EIPGEN_Pos (24U)
#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
#define ETH_MACECR_USP_Pos (18U)
#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
#define ETH_MACECR_SPEN_Pos (17U)
#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
#define ETH_MACECR_DCRCC_Pos (16U)
#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
#define ETH_MACECR_GPSL_Pos (0U)
#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
/************ Bit definition for Ethernet MAC Packet Filter Register ***************/
#define ETH_MACPFR_RA_Pos (31U)
#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
#define ETH_MACPFR_DNTU_Pos (21U)
#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
#define ETH_MACPFR_IPFE_Pos (20U)
#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
#define ETH_MACPFR_VTFE_Pos (16U)
#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
#define ETH_MACPFR_HPF_Pos (10U)
#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
#define ETH_MACPFR_SAF_Pos (9U)
#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
#define ETH_MACPFR_SAIF_Pos (8U)
#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
#define ETH_MACPFR_PCF_Pos (6U)
#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
#define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACPFR_DBF_Pos (5U)
#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
#define ETH_MACPFR_PM_Pos (4U)
#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
#define ETH_MACPFR_DAIF_Pos (3U)
#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
#define ETH_MACPFR_HMC_Pos (2U)
#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
#define ETH_MACPFR_HUC_Pos (1U)
#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
#define ETH_MACPFR_PR_Pos (0U)
#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
/************ Bit definition for Ethernet MAC Watchdog Timeout Register ***************/
#define ETH_MACWTR_PWE_Pos (8U)
#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
#define ETH_MACWTR_WTO_Pos (0U)
#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
#define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
#define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
#define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
#define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
#define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
#define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
#define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
#define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
#define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
#define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
#define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
#define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
#define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
#define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
#define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
/************ Bit definition for Ethernet MAC Hash Table 0 register ***************/
#define ETH_MACHT0R_HTH_Pos (0U)
#define ETH_MACHT0R_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHT0R_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
/************ Bit definition for Ethernet MAC Hash Table 1 register ***************/
#define ETH_MACHT1R_HTL_Pos (0U)
#define ETH_MACHT1R_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACHT1R_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
/************ Bit definition for Ethernet MAC VLAN tag Control register ***************/
#define ETH_MACVTCR_EIVLRXS_Pos (31U)
#define ETH_MACVTCR_EIVLRXS_Msk (0x1UL << ETH_MACVTCR_EIVLRXS_Pos) /*!< 0x80000000 */
#define ETH_MACVTCR_EIVLRXS ETH_MACVTCR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
#define ETH_MACVTCR_EIVLS_Pos (28U)
#define ETH_MACVTCR_EIVLS_Msk (0x3UL << ETH_MACVTCR_EIVLS_Pos) /*!< 0x30000000 */
#define ETH_MACVTCR_EIVLS ETH_MACVTCR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
#define ETH_MACVTCR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos (28U)
#define ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
#define ETH_MACVTCR_EIVLS_STRIPIFPASS ETH_MACVTCR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos (29U)
#define ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTCR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
#define ETH_MACVTCR_EIVLS_STRIPIFFAILS ETH_MACVTCR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos (28U)
#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
#define ETH_MACVTCR_EIVLS_ALWAYSSTRIP ETH_MACVTCR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
#define ETH_MACVTCR_ERIVLT_Pos (27U)
#define ETH_MACVTCR_ERIVLT_Msk (0x1UL << ETH_MACVTCR_ERIVLT_Pos) /*!< 0x08000000 */
#define ETH_MACVTCR_ERIVLT ETH_MACVTCR_ERIVLT_Msk /* Enable Inner VLAN Tag */
#define ETH_MACVTCR_EDVLP_Pos (26U)
#define ETH_MACVTCR_EDVLP_Msk (0x1UL << ETH_MACVTCR_EDVLP_Pos) /*!< 0x04000000 */
#define ETH_MACVTCR_EDVLP ETH_MACVTCR_EDVLP_Msk /* Enable Double VLAN Processing */
#define ETH_MACVTCR_VTHM_Pos (25U)
#define ETH_MACVTCR_VTHM_Msk (0x1UL << ETH_MACVTCR_VTHM_Pos) /*!< 0x02000000 */
#define ETH_MACVTCR_VTHM ETH_MACVTCR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
#define ETH_MACVTCR_EVLRXS_Pos (24U)
#define ETH_MACVTCR_EVLRXS_Msk (0x1UL << ETH_MACVTCR_EVLRXS_Pos) /*!< 0x01000000 */
#define ETH_MACVTCR_EVLRXS ETH_MACVTCR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
#define ETH_MACVTCR_EVLS_Pos (21U)
#define ETH_MACVTCR_EVLS_Msk (0x3UL << ETH_MACVTCR_EVLS_Pos) /*!< 0x00600000 */
#define ETH_MACVTCR_EVLS ETH_MACVTCR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
#define ETH_MACVTCR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
#define ETH_MACVTCR_EVLS_STRIPIFPASS_Pos (21U)
#define ETH_MACVTCR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTCR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
#define ETH_MACVTCR_EVLS_STRIPIFPASS ETH_MACVTCR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos (22U)
#define ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTCR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
#define ETH_MACVTCR_EVLS_STRIPIFFAILS ETH_MACVTCR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos (21U)
#define ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTCR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
#define ETH_MACVTCR_EVLS_ALWAYSSTRIP ETH_MACVTCR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
#define ETH_MACVTCR_DOVLTC_Pos (20U)
#define ETH_MACVTCR_DOVLTC_Msk (0x1UL << ETH_MACVTCR_DOVLTC_Pos) /*!< 0x00100000 */
#define ETH_MACVTCR_DOVLTC ETH_MACVTCR_DOVLTC_Msk /* Disable VLAN Type Check */
#define ETH_MACVTCR_ERSVLM_Pos (19U)
#define ETH_MACVTCR_ERSVLM_Msk (0x1UL << ETH_MACVTCR_ERSVLM_Pos) /*!< 0x00080000 */
#define ETH_MACVTCR_ERSVLM ETH_MACVTCR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
#define ETH_MACVTCR_ESVL_Pos (18U)
#define ETH_MACVTCR_ESVL_Msk (0x1UL << ETH_MACVTCR_ESVL_Pos) /*!< 0x00040000 */
#define ETH_MACVTCR_ESVL ETH_MACVTCR_ESVL_Msk /* Enable S-VLAN */
#define ETH_MACVTCR_VTIM_Pos (17U)
#define ETH_MACVTCR_VTIM_Msk (0x1UL << ETH_MACVTCR_VTIM_Pos) /*!< 0x00020000 */
#define ETH_MACVTCR_VTIM ETH_MACVTCR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
#define ETH_MACVTCR_ETV_Pos (16U)
#define ETH_MACVTCR_ETV_Msk (0x1UL << ETH_MACVTCR_ETV_Pos) /*!< 0x00010000 */
#define ETH_MACVTCR_ETV ETH_MACVTCR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
#define ETH_MACVTCR_OFS_Pos (2U)
#define ETH_MACVTCR_OFS_Msk (0x3UL << ETH_MACVTCR_OFS_Pos) /*!< 0x0000000C */
#define ETH_MACVTCR_OFS ETH_MACVTCR_EVLS_Msk /* Offset */
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER0 ((uint32_t)0x00000000) /* holds MAC VLAN Tag Filter0 content */
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos (2U)
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Pos) /*!< 0x00000004 */
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1 ETH_MACVTCR_OFS_HOLDVLANTAGFILTER1_Msk /* holds MAC VLAN Tag Filter1 content */
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos (3U)
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk (0x1UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Pos) /*!< 0x00000008 */
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2 ETH_MACVTCR_OFS_HOLDVLANTAGFILTER2_Msk /* holds MAC VLAN Tag Filter2 content */
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos (2U)
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk (0x3UL << ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Pos) /*!< 0x0000000C */
#define ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3 ETH_MACVTCR_OFS_HOLDVLANTAGFILTER3_Msk /* holds MAC VLAN Tag Filter3 content */
#define ETH_MACVTCR_CT_Pos (1U)
#define ETH_MACVTCR_CT_Msk (0x1UL << ETH_MACVTCR_CT_Pos) /*!< 0x00000002 */
#define ETH_MACVTCR_CT ETH_MACVTCR_CT_Msk /* Command Type */
#define ETH_MACVTCR_OB_Pos (0U)
#define ETH_MACVTCR_OB_Msk (0x1UL << ETH_MACVTCR_OB_Pos) /*!< 0x00000001 */
#define ETH_MACVTCR_OB ETH_MACVTCR_OB_Msk /* Operation Busy */
/************ Bit definition for Ethernet MAC VLAN tag data register ***************/
#define ETH_MACVTDR_DMACHN_Pos (25U)
#define ETH_MACVTDR_DMACHN_Msk (0x1UL << ETH_MACVTDR_DMACHN_Pos) /*!< 0x02000000 */
#define ETH_MACVTDR_DMACHN ETH_MACVTDR_DMACHN_Msk /* DMA Channel Number */
#define ETH_MACVTDR_DMACHEN_Pos (24U)
#define ETH_MACVTDR_DMACHEN_Msk (0x1UL << ETH_MACVTDR_DMACHEN_Pos) /*!< 0x01000000 */
#define ETH_MACVTDR_DMACHEN ETH_MACVTDR_DMACHEN_Msk /* DMA Channel Number Enable */
#define ETH_MACVTDR_ERIVLT_Pos (20U)
#define ETH_MACVTDR_ERIVLT_Msk (0x1UL << ETH_MACVTDR_ERIVLT_Pos) /*!< 0x00100000 */
#define ETH_MACVTDR_ERIVLT ETH_MACVTDR_ERIVLT_Msk /* Enable Inner VLAN Tag Comparison */
#define ETH_MACVTDR_ERSVLM_Pos (19U)
#define ETH_MACVTDR_ERSVLM_Msk (0x1UL << ETH_MACVTDR_ERSVLM_Pos) /*!< 0x00080000 */
#define ETH_MACVTDR_ERSVLM ETH_MACVTDR_ERSVLM_Msk /* Enable S-VLAN Match for received Frames */
#define ETH_MACVTDR_DOVLTC_Pos (18U)
#define ETH_MACVTDR_DOVLTC_Msk (0x1UL << ETH_MACVTDR_DOVLTC_Pos) /*!< 0x00080000 */
#define ETH_MACVTDR_DOVLTC ETH_MACVTDR_DOVLTC_Msk /* Disable VLAN Type Comparison */
#define ETH_MACVTDR_ETV_Pos (17U)
#define ETH_MACVTDR_ETV_Msk (0x1UL << ETH_MACVTDR_ETV_Pos) /*!< 0x00020000 */
#define ETH_MACVTDR_ETV ETH_MACVTDR_ETV_Msk /* 12-bit or 16-bit VLAN comparison */
#define ETH_MACVTDR_ETV_VLAN16B ((uint32_t)0x00000000) /* 16-bit VLAN */
#define ETH_MACVTDR_ETV_VLAN12B_Pos (17U)
#define ETH_MACVTDR_ETV_VLAN12B_Msk (0x1UL << ETH_MACVTDR_ETV_VLAN12B_Pos) /*!< 0x00020000 */
#define ETH_MACVTDR_ETV_VLAN12B ETH_MACVTDR_ETV_VLAN12B_Msk /* 12-bit VLAN */
#define ETH_MACVTDR_VEN_Pos (16U)
#define ETH_MACVTDR_VEN_Msk (0x1UL << ETH_MACVTDR_VEN_Pos) /*!< 0x00010000 */
#define ETH_MACVTDR_VEN ETH_MACVTDR_VEN_Msk /* VLAN Tag Enable */
#define ETH_MACVTDR_VID_Pos (0U)
#define ETH_MACVTDR_VID_Msk (0xFFFFUL << ETH_MACVTDR_VID_Pos) /*!< 0x0000FFFF */
#define ETH_MACVTDR_VID ETH_MACVTDR_VID_Msk /* VLAN Tag ID */
#define ETH_MACVTDR_VID_12BIT_Msk (0xFFFU << ETH_MACVTDR_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACVTDR_VID_12BIT ETH_MACVTDR_VID_12BIT_Msk /*!< VLAN Tag Identifier field of VLAN tag 12bit */
#define ETH_MACVTDR_VID_16BIT_Msk (0xFFFFU << ETH_MACVTDR_VID_Pos) /*!< 0x0000FFFF */
#define ETH_MACVTDR_VID_16BIT ETH_MACVTDR_VID_16BIT_Msk /*!< VLAN Tag Identifier field of VLAN tag 16bit */
#define ETH_MACVTDR_VID_0 (0x1U << ETH_MACVTDR_VID_Pos) /*!< 0x00000001 */
#define ETH_MACVTDR_VID_1 (0x2U << ETH_MACVTDR_VID_Pos) /*!< 0x00000002 */
#define ETH_MACVTDR_VID_2 (0x4U << ETH_MACVTDR_VID_Pos) /*!< 0x00000004 */
#define ETH_MACVTDR_VID_3 (0x8U << ETH_MACVTDR_VID_Pos) /*!< 0x00000008 */
#define ETH_MACVTDR_VID_4 (0x10U << ETH_MACVTDR_VID_Pos) /*!< 0x00000010 */
#define ETH_MACVTDR_VID_5 (0x20U << ETH_MACVTDR_VID_Pos) /*!< 0x00000020 */
#define ETH_MACVTDR_VID_6 (0x40U << ETH_MACVTDR_VID_Pos) /*!< 0x00000040 */
#define ETH_MACVTDR_VID_7 (0x80U << ETH_MACVTDR_VID_Pos) /*!< 0x00000080 */
#define ETH_MACVTDR_VID_8 (0x100U << ETH_MACVTDR_VID_Pos) /*!< 0x00000100 */
#define ETH_MACVTDR_VID_9 (0x200U << ETH_MACVTDR_VID_Pos) /*!< 0x00000200 */
#define ETH_MACVTDR_VID_10 (0x400U << ETH_MACVTDR_VID_Pos) /*!< 0x00000400 */
#define ETH_MACVTDR_VID_11 (0x800U << ETH_MACVTDR_VID_Pos) /*!< 0x00000800 */
#define ETH_MACVTDR_VID_12 (0x1000U << ETH_MACVTDR_VID_Pos) /*!< 0x00001000 */
#define ETH_MACVTDR_VID_13 (0x2000U << ETH_MACVTDR_VID_Pos) /*!< 0x00002000 */
#define ETH_MACVTDR_VID_14 (0x4000U << ETH_MACVTDR_VID_Pos) /*!< 0x00004000 */
#define ETH_MACVTDR_VID_15 (0x8000U << ETH_MACVTDR_VID_Pos) /*!< 0x00008000 */
/************ Bit definition for Ethernet MAC VLAN Hash Table Register ***************/
#define ETH_MACVHTR_VLHT_Pos (0U)
#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
/************ Bit definition for Ethernet MAC VLAN inclusion Register ***************/
#define ETH_MACVIR_BUSY_Pos (31U)
#define ETH_MACVIR_BUSY_Msk (0x1UL << ETH_MACVIR_BUSY_Pos) /*!< 0x80000000 */
#define ETH_MACVIR_BUSY ETH_MACVIR_BUSY_Msk /* Busy */
#define ETH_MACVIR_RDWR_Pos (30U)
#define ETH_MACVIR_RDWR_Msk (0x1UL << ETH_MACVIR_RDWR_Pos) /*!< 0x40000000 */
#define ETH_MACVIR_RDWR ETH_MACVIR_RDWR_Msk /* Read write control */
#define ETH_MACVIR_ADDR_Pos (24U)
#define ETH_MACVIR_ADDR_Msk (0x1UL << ETH_MACVIR_ADDR_Pos) /*!< 0x01000000 */
#define ETH_MACVIR_ADDR ETH_MACVIR_ADDR_Msk /* Address */
#define ETH_MACVIR_ADDR_VLANINSTXQ0 ((uint32_t)0x00000000) /* VLAN tag for insertion in the Transmit packets from Tx Queue 0 */
#define ETH_MACVIR_ADDR_VLANINSTXQ1_Pos (24U)
#define ETH_MACVIR_ADDR_VLANINSTXQ1_Msk (0x1UL << ETH_MACVIR_ADDR_VLANINSTXQ1_Pos) /*!< 0x01000000 */
#define ETH_MACVIR_ADDR_VLANINSTXQ1 ETH_MACVIR_ADDR_VLANINSTXQ1_Msk /* VLAN tag for insertion in the Transmit packets from Tx Queue 1 */
#define ETH_MACVIR_CBTI_Pos (21U)
#define ETH_MACVIR_CBTI_Msk (0x1UL << ETH_MACVIR_CBTI_Pos) /*!< 0x00200000 */
#define ETH_MACVIR_CBTI ETH_MACVIR_CBTI_Msk /* Channel based tag insertion */
#define ETH_MACVIR_VLTI_Pos (20U)
#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
#define ETH_MACVIR_CSVL_Pos (19U)
#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
#define ETH_MACVIR_VLP_Pos (18U)
#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
#define ETH_MACVIR_VLC_Pos (16U)
#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
#define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define ETH_MACVIR_VLT_Pos (0U)
#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
#define ETH_MACVIR_VLT_UP_Pos (13U)
#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACVIR_VLT_VID_Pos (0U)
#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
/************ Bit definition for Ethernet MAC Inner_VLAN Incl Register ***************/
#define ETH_MACIVIR_VLTI_Pos (20U)
#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
#define ETH_MACIVIR_CSVL_Pos (19U)
#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
#define ETH_MACIVIR_VLP_Pos (18U)
#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
#define ETH_MACIVIR_VLC_Pos (16U)
#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
#define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
#define ETH_MACIVIR_VLT_Pos (0U)
#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
#define ETH_MACIVIR_VLT_UP_Pos (13U)
#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
#define ETH_MACIVIR_VLT_VID_Pos (0U)
#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
/************ Bit definition for Ethernet MAC Tx Queue 0 flow control Register ***************/
#define ETH_MACQ0TXFCR_PT_Pos (16U)
#define ETH_MACQ0TXFCR_PT_Msk (0xFFFFUL << ETH_MACQ0TXFCR_PT_Pos) /*!< 0xFFFF0000 */
#define ETH_MACQ0TXFCR_PT ETH_MACQ0TXFCR_PT_Msk /* Pause Time */
#define ETH_MACQ0TXFCR_DZPQ_Pos (7U)
#define ETH_MACQ0TXFCR_DZPQ_Msk (0x1UL << ETH_MACQ0TXFCR_DZPQ_Pos) /*!< 0x00000080 */
#define ETH_MACQ0TXFCR_DZPQ ETH_MACQ0TXFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
#define ETH_MACQ0TXFCR_PLT_Pos (4U)
#define ETH_MACQ0TXFCR_PLT_Msk (0x7UL << ETH_MACQ0TXFCR_PLT_Pos) /*!< 0x00000070 */
#define ETH_MACQ0TXFCR_PLT ETH_MACQ0TXFCR_PLT_Msk /* Pause Low Threshold */
#define ETH_MACQ0TXFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
#define ETH_MACQ0TXFCR_PLT_MINUS28_Pos (4U)
#define ETH_MACQ0TXFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
#define ETH_MACQ0TXFCR_PLT_MINUS28 ETH_MACQ0TXFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
#define ETH_MACQ0TXFCR_PLT_MINUS36_Pos (5U)
#define ETH_MACQ0TXFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
#define ETH_MACQ0TXFCR_PLT_MINUS36 ETH_MACQ0TXFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
#define ETH_MACQ0TXFCR_PLT_MINUS144_Pos (4U)
#define ETH_MACQ0TXFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACQ0TXFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
#define ETH_MACQ0TXFCR_PLT_MINUS144 ETH_MACQ0TXFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
#define ETH_MACQ0TXFCR_PLT_MINUS256_Pos (6U)
#define ETH_MACQ0TXFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACQ0TXFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
#define ETH_MACQ0TXFCR_PLT_MINUS256 ETH_MACQ0TXFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
#define ETH_MACQ0TXFCR_PLT_MINUS512_Pos (4U)
#define ETH_MACQ0TXFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACQ0TXFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
#define ETH_MACQ0TXFCR_PLT_MINUS512 ETH_MACQ0TXFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
#define ETH_MACQ0TXFCR_TFE_Pos (1U)
#define ETH_MACQ0TXFCR_TFE_Msk (0x1UL << ETH_MACQ0TXFCR_TFE_Pos) /*!< 0x00000002 */
#define ETH_MACQ0TXFCR_TFE ETH_MACQ0TXFCR_TFE_Msk /* Transmit Flow Control Enable */
#define ETH_MACQ0TXFCR_FCB_Pos (0U)
#define ETH_MACQ0TXFCR_FCB_Msk (0x1UL << ETH_MACQ0TXFCR_FCB_Pos) /*!< 0x00000001 */
#define ETH_MACQ0TXFCR_FCB ETH_MACQ0TXFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
/************ Bit definition for Ethernet MAC Rx flow control Register ***************/
#define ETH_MACRXFCR_UP_Pos (1U)
#define ETH_MACRXFCR_UP_Msk (0x1UL << ETH_MACRXFCR_UP_Pos) /*!< 0x00000002 */
#define ETH_MACRXFCR_UP ETH_MACRXFCR_UP_Msk /* Unicast Pause Packet Detect */
#define ETH_MACRXFCR_RFE_Pos (0U)
#define ETH_MACRXFCR_RFE_Msk (0x1UL << ETH_MACRXFCR_RFE_Pos) /*!< 0x00000001 */
#define ETH_MACRXFCR_RFE ETH_MACRXFCR_RFE_Msk /* Receive Flow Control Enable */
/************ Bit definition for Ethernet MAC Rx Queue control Register ***************/
#define ETH_MACRXQCR_VFFQ_Pos (17U)
#define ETH_MACRXQCR_VFFQ_Msk (0x1UL << ETH_MACRXQCR_VFFQ_Pos) /*!< 0x00020000 */
#define ETH_MACRXQCR_VFFQ ETH_MACRXQCR_VFFQ_Msk /* VLAN Tag Filter Fail Packets Queue */
#define ETH_MACRXQCR_VFFQ_Q0 ((uint32_t)0x00000000) /* Queue 0 */
#define ETH_MACRXQCR_VFFQ_Q1_Pos (17U)
#define ETH_MACRXQCR_VFFQ_Q1_Msk (0x1UL << ETH_MACRXQCR_VFFQ_Q1_Pos) /*!< 0x00020000 */
#define ETH_MACRXQCR_VFFQ_Q1 ETH_MACRXQCR_VFFQ_Q1_Msk /* Queue 1 */
#define ETH_MACRXQCR_VFFQE_Pos (16U)
#define ETH_MACRXQCR_VFFQE_Msk (0x1UL << ETH_MACRXQCR_VFFQE_Pos) /*!< 0x00010000 */
#define ETH_MACRXQCR_VFFQE ETH_MACRXQCR_VFFQE_Msk /* VLAN Tag Filter Fail Packets Queuing Enable */
#define ETH_MACRXQCR_MFFQ_Pos (9U)
#define ETH_MACRXQCR_MFFQ_Msk (0x1UL << ETH_MACRXQCR_MFFQ_Pos) /*!< 0x00000200 */
#define ETH_MACRXQCR_MFFQ ETH_MACRXQCR_MFFQ_Msk /* Multicast Address Filter Fail Packets Queue */
#define ETH_MACRXQCR_MFFQ_Q0 ((uint32_t)0x00000000) /* Queue 0 */
#define ETH_MACRXQCR_MFFQ_Q1_Pos (9U)
#define ETH_MACRXQCR_MFFQ_Q1_Msk (0x1UL << ETH_MACRXQCR_MFFQ_Q1_Pos) /*!< 0x00000200 */
#define ETH_MACRXQCR_MFFQ_Q1 ETH_MACRXQCR_MFFQ_Q1_Msk /* Queue 1 */
#define ETH_MACRXQCR_MFFQE_Pos (8U)
#define ETH_MACRXQCR_MFFQE_Msk (0x1UL << ETH_MACRXQCR_MFFQE_Pos) /*!< 0x00000100 */
#define ETH_MACRXQCR_MFFQE ETH_MACRXQCR_MFFQE_Msk /* Multicast Address Filter Fail Packets Queuing Enable */
#define ETH_MACRXQCR_UFFQ_Pos (1U)
#define ETH_MACRXQCR_UFFQ_Msk (0x1UL << ETH_MACRXQCR_UFFQ_Pos) /*!< 0x00000002 */
#define ETH_MACRXQCR_UFFQ ETH_MACRXQCR_UFFQ_Msk /* Unicast Address Filter Fail Packets Queue */
#define ETH_MACRXQCR_UFFQ_Q0 ((uint32_t)0x00000000) /* Queue 0 */
#define ETH_MACRXQCR_UFFQ_Q1_Pos (9U)
#define ETH_MACRXQCR_UFFQ_Q1_Msk (0x1UL << ETH_MACRXQCR_UFFQ_Q1_Pos) /*!< 0x00000002 */
#define ETH_MACRXQCR_UFFQ_Q1 ETH_MACRXQCR_UFFQ_Q1_Msk /* Queue 1 */
#define ETH_MACRXQCR_UFFQE_Pos (0U)
#define ETH_MACRXQCR_UFFQE_Msk (0x1UL << ETH_MACRXQCR_UFFQE_Pos) /*!< 0x00000001 */
#define ETH_MACRXQCR_UFFQE ETH_MACRXQCR_UFFQE_Msk /* Unicast Address Filter Fail Packets Queuing Enable */
/************ Bit definition for Ethernet MAC Rx queue control 0 Register ***************/
#define ETH_MACRXQC0R_RXQ1EN_Pos (2U)
#define ETH_MACRXQC0R_RXQ1EN_Msk (0x3UL << ETH_MACRXQC0R_RXQ1EN_Pos) /*!< 0x0000000C */
#define ETH_MACRXQC0R_RXQ1EN ETH_MACRXQC0R_RXQ1EN_Msk /* Receive Queue 1 Enable */
#define ETH_MACRXQC0R_RXQ1EN_NOT ((uint32_t)0x00000000) /* Queue 1 Not enabled */
#define ETH_MACRXQC0R_RXQ1EN_AV_Pos (2U)
#define ETH_MACRXQC0R_RXQ1EN_AV_Msk (0x1UL << ETH_MACRXQC0R_RXQ1EN_AV_Pos) /*!< 0x00000004 */
#define ETH_MACRXQC0R_RXQ1EN_AV ETH_MACRXQC0R_RXQ1EN_AV_Msk /* Queue 1 enabled for AV */
#define ETH_MACRXQC0R_RXQ1EN_GT_Pos (3U)
#define ETH_MACRXQC0R_RXQ1EN_GT_Msk (0x1UL << ETH_MACRXQC0R_RXQ1EN_GT_Pos) /*!< 0x00000008 */
#define ETH_MACRXQC0R_RXQ1EN_GT ETH_MACRXQC0R_RXQ1EN_GT_Msk /* Queue 1 enabled for Generic traffic */
#define ETH_MACRXQC0R_RXQ0EN_Pos (0U)
#define ETH_MACRXQC0R_RXQ0EN_Msk (0x3UL << ETH_MACRXQC0R_RXQ0EN_Pos) /*!< 0x00000003 */
#define ETH_MACRXQC0R_RXQ0EN ETH_MACRXQC0R_RXQ0EN_Msk /* Receive Queue 0 Enable */
#define ETH_MACRXQC0R_RXQ0EN_NOT ((uint32_t)0x00000000) /* Queue 0 Not enabled */
#define ETH_MACRXQC0R_RXQ0EN_AV_Pos (0U)
#define ETH_MACRXQC0R_RXQ0EN_AV_Msk (0x1UL << ETH_MACRXQC0R_RXQ0EN_AV_Pos) /*!< 0x00000001 */
#define ETH_MACRXQC0R_RXQ0EN_AV ETH_MACRXQC0R_RXQ0EN_AV_Msk /* Queue 0 enabled for AV */
#define ETH_MACRXQC0R_RXQ0EN_GT_Pos (1U)
#define ETH_MACRXQC0R_RXQ0EN_GT_Msk (0x1UL << ETH_MACRXQC0R_RXQ0EN_GT_Pos) /*!< 0x00000002 */
#define ETH_MACRXQC0R_RXQ0EN_GT ETH_MACRXQC0R_RXQ0EN_GT_Msk /* Queue 0 enabled for Generic traffic */
/************ Bit definition for Ethernet MAC Rx queue control 1 Register ***************/
#define ETH_MACRXQC1R_TBRQE_Pos (29U)
#define ETH_MACRXQC1R_TBRQE_Msk (0x1UL << ETH_MACRXQC1R_TBRQE_Pos) /*!< 0x20000000 */
#define ETH_MACRXQC1R_TBRQE ETH_MACRXQC1R_TBRQE_Msk /* Type Field Based Rx Queuing Enable */
#define ETH_MACRXQC1R_OMCBCQ_Pos (28U)
#define ETH_MACRXQC1R_OMCBCQ_Msk (0x1UL << ETH_MACRXQC1R_OMCBCQ_Pos) /*!< 0x10000000 */
#define ETH_MACRXQC1R_OMCBCQ ETH_MACRXQC1R_OMCBCQ_Msk /* Overriding MC-BC queue priority select */
#define ETH_MACRXQC1R_FPRQ_Pos (24U)
#define ETH_MACRXQC1R_FPRQ_Msk (0x7UL << ETH_MACRXQC1R_FPRQ_Pos) /*!< 0x07000000 */
#define ETH_MACRXQC1R_FPRQ ETH_MACRXQC1R_FPRQ_Msk /* Frame Preemption Residue Queue */
#define ETH_MACRXQC1R_FPRQ_RXQ1_Pos (24U)
#define ETH_MACRXQC1R_FPRQ_RXQ1_Msk (0x1UL << ETH_MACRXQC1R_FPRQ_RXQ1_Pos) /*!< 0x01000000 */
#define ETH_MACRXQC1R_FPRQ_RXQ1 ETH_MACRXQC1R_FPRQ_RXQ1_Msk /* Rx queue 1 */
#define ETH_MACRXQC1R_TPQC_Pos (22U)
#define ETH_MACRXQC1R_TPQC_Msk (0x3UL << ETH_MACRXQC1R_TPQC_Pos) /*!< 0x07000000 */
#define ETH_MACRXQC1R_TPQC ETH_MACRXQC1R_TPQC_Msk /* Tagged PTP over Ethernet Packets Queuing Control */
#define ETH_MACRXQC1R_TPQC_PTPGENVLANTAG ((uint32_t)0x00000000) /* VLAN tagged PTPoE packets are routed as generic VLAN tagged packet */
#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos (22U)
#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk (0x1UL << ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Pos) /*!< 0x000400000 */
#define ETH_MACRXQC1R_TPQC_PTPRXQPTPQ ETH_MACRXQC1R_TPQC_PTPRXQPTPQ_Msk /* VLAN tagged PTPoE packets are routed to Rx Queue specified by PTPQ field */
#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos (23U)
#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk (0x1UL << ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Pos) /*!< 0x00080000 */
#define ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ ETH_MACRXQC1R_TPQC_PTPAVRXQPSRQ_Msk /* VLAN tagged PTPoE packets are routed to only AV enabled Rx queues based on PSRQ */
#define ETH_MACRXQC1R_TACPQE_Pos (21U)
#define ETH_MACRXQC1R_TACPQE_Msk (0x1UL << ETH_MACRXQC1R_TACPQE_Pos) /*!< 0x00200000 */
#define ETH_MACRXQC1R_TACPQE ETH_MACRXQC1R_TACPQE_Msk /* Tagged AV Control Packets Queuing Enable */
#define ETH_MACRXQC1R_MCBCQEN_Pos (20U)
#define ETH_MACRXQC1R_MCBCQEN_Msk (0x1UL << ETH_MACRXQC1R_MCBCQEN_Pos) /*!< 0x00100000 */
#define ETH_MACRXQC1R_MCBCQEN ETH_MACRXQC1R_MCBCQEN_Msk /* Multicast and Broadcast Queue Enable */
#define ETH_MACRXQC1R_MCBCQ_Pos (16U)
#define ETH_MACRXQC1R_MCBCQ_Msk (0x7UL << ETH_MACRXQC1R_MCBCQ_Pos) /*!< 0x00070000 */
#define ETH_MACRXQC1R_MCBCQ ETH_MACRXQC1R_MCBCQ_Msk /* Multicast and Broadcast Queue */
#define ETH_MACRXQC1R_MCBCQ_RXQ0 ((uint32_t)0x00000000) /* Rx queue 0 */
#define ETH_MACRXQC1R_MCBCQ_RXQ1_Pos (16U)
#define ETH_MACRXQC1R_MCBCQ_RXQ1_Msk (0x1UL << ETH_MACRXQC1R_MCBCQ_RXQ1_Pos) /*!< 0x00010000 */
#define ETH_MACRXQC1R_MCBCQ_RXQ1 ETH_MACRXQC1R_MCBCQ_RXQ1_Msk /* Rx queue 1 */
#define ETH_MACRXQC1R_UPQ_Pos (12U)
#define ETH_MACRXQC1R_UPQ_Msk (0x7UL << ETH_MACRXQC1R_UPQ_Pos) /*!< 0x00007000 */
#define ETH_MACRXQC1R_UPQ ETH_MACRXQC1R_UPQ_Msk /* Untagged Packet Queue */
#define ETH_MACRXQC1R_UPQ_RXQ0 ((uint32_t)0x00000000) /* Rx queue 0 */
#define ETH_MACRXQC1R_UPQ_RXQ1_Pos (12U)
#define ETH_MACRXQC1R_UPQ_RXQ1_Msk (0x1UL << ETH_MACRXQC1R_UPQ_RXQ1_Pos) /*!< 0x00001000 */
#define ETH_MACRXQC1R_UPQ_RXQ1 ETH_MACRXQC1R_UPQ_RXQ1_Msk /* Rx queue 1 */
#define ETH_MACRXQC1R_PTPQ_Pos (4U)
#define ETH_MACRXQC1R_PTPQ_Msk (0x7UL << ETH_MACRXQC1R_PTPQ_Pos) /*!< 0x00000070 */
#define ETH_MACRXQC1R_PTPQ ETH_MACRXQC1R_PTPQ_Msk /* PTP Packets Queue */
#define ETH_MACRXQC1R_PTPQ_RXQ0 ((uint32_t)0x00000000) /* Rx queue 0 */
#define ETH_MACRXQC1R_PTPQ_RXQ1_Pos (4U)
#define ETH_MACRXQC1R_PTPQ_RXQ1_Msk (0x1UL << ETH_MACRXQC1R_PTPQ_RXQ1_Pos) /*!< 0x00000010 */
#define ETH_MACRXQC1R_PTPQ_RXQ1 ETH_MACRXQC1R_PTPQ_RXQ1_Msk /* Rx queue 1 */
#define ETH_MACRXQC1R_AVCPQ_Pos (0U)
#define ETH_MACRXQC1R_AVCPQ_Msk (0x7UL << ETH_MACRXQC1R_AVCPQ_Pos) /*!< 0x00000007 */
#define ETH_MACRXQC1R_AVCPQ ETH_MACRXQC1R_AVCPQ_Msk /* AV Untagged Control Packets Queue */
#define ETH_MACRXQC1R_AVCPQ_RXQ0 ((uint32_t)0x00000000) /* Rx queue 0 */
#define ETH_MACRXQC1R_AVCPQ_RXQ1_Pos (0U)
#define ETH_MACRXQC1R_AVCPQ_RXQ1_Msk (0x1UL << ETH_MACRXQC1R_AVCPQ_RXQ1_Pos) /*!< 0x00000001 */
#define ETH_MACRXQC1R_AVCPQ_RXQ1 ETH_MACRXQC1R_AVCPQ_RXQ1_Msk /* Rx queue 1 */
/************ Bit definition for Ethernet MAC Rx queue control 2 Register ***************/
#define ETH_MACRXQC2R_PSRQ1_Pos (8U)
#define ETH_MACRXQC2R_PSRQ1_Msk (0xFFUL << ETH_MACRXQC2R_PSRQ1_Pos) /*!< 0x0000FF00 */
#define ETH_MACRXQC2R_PSRQ1 ETH_MACRXQC2R_PSRQ1_Msk /* Priorities Selected in the Receive Queue 1 */
#define ETH_MACRXQC2R_PSRQ0_Pos (0U)
#define ETH_MACRXQC2R_PSRQ0_Msk (0xFFUL << ETH_MACRXQC2R_PSRQ0_Pos) /*!< 0x000000FF */
#define ETH_MACRXQC2R_PSRQ0 ETH_MACRXQC2R_PSRQ0_Msk /* Priorities Selected in the Receive Queue 0 */
/************ Bit definition for Ethernet MAC Interrupt Status Register ***************/
#define ETH_MACISR_MFRIS_Pos (20U)
#define ETH_MACISR_MFRIS_Msk (0x1UL << ETH_MACISR_MFRIS_Pos) /*!< 0x00100000 */
#define ETH_MACISR_MFRIS ETH_MACISR_MFRIS_Msk /* MMC FPE Receive Interrupt Status */
#define ETH_MACISR_MFTIS_Pos (19U)
#define ETH_MACISR_MFTIS_Msk (0x1UL << ETH_MACISR_MFTIS_Pos) /*!< 0x00080000 */
#define ETH_MACISR_MFTIS ETH_MACISR_MFTIS_Msk /* MMC FPE Transmit Interrupt Status */
#define ETH_MACISR_MDIOIS_Pos (18U)
#define ETH_MACISR_MDIOIS_Msk (0x1UL << ETH_MACISR_MDIOIS_Pos) /*!< 0x00040000 */
#define ETH_MACISR_MDIOIS ETH_MACISR_MDIOIS_Msk /* MDIO Interrupt Status*/
#define ETH_MACISR_FPEIS_Pos (17U)
#define ETH_MACISR_FPEIS_Msk (0x1UL << ETH_MACISR_FPEIS_Pos) /*!< 0x00020000 */
#define ETH_MACISR_FPEIS ETH_MACISR_FPEIS_Msk /* Frame Preemption Interrupt Status */
#define ETH_MACISR_RXSTSIS_Pos (14U)
#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
#define ETH_MACISR_TXSTSIS_Pos (13U)
#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
#define ETH_MACISR_TSIS_Pos (12U)
#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
#define ETH_MACISR_MMCTXIS_Pos (10U)
#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
#define ETH_MACISR_MMCRXIS_Pos (9U)
#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
#define ETH_MACISR_MMCIS_Pos (8U)
#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
#define ETH_MACISR_LPIIS_Pos (5U)
#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
#define ETH_MACISR_PMTIS_Pos (4U)
#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
#define ETH_MACISR_PHYIS_Pos (3U)
#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
#define ETH_MACISR_RGSMIIIS_Pos (0U)
#define ETH_MACISR_RGSMIIIS_Msk (0x1UL << ETH_MACISR_RGSMIIIS_Pos) /*!< 0x00000001 */
#define ETH_MACISR_RGSMIIIS ETH_MACISR_RGSMIIIS_Msk /* RGMII Interrupt Status */
/************ Bit definition for Ethernet MAC Interrupt Status Register ***************/
#define ETH_MACISR_MDIOIE_Pos (18U)
#define ETH_MACISR_MDIOIE_Msk (0x1UL << ETH_MACISR_MDIOIE_Pos) /*!< 0x00040000 */
#define ETH_MACISR_MDIOIE ETH_MACISR_MDIOIE_Msk /* Receive Interrupt Enable*/
#define ETH_MACISR_FPEIE_Pos (17U)
#define ETH_MACISR_FPEIE_Msk (0x1UL << ETH_MACISR_FPEIE_Pos) /*!< 0x00020000 */
#define ETH_MACISR_FPEIE ETH_MACISR_FPEIE_Msk /* Frame Preemption Interrupt Enable */
#define ETH_MACIER_RXSTSIE_Pos (14U)
#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
#define ETH_MACIER_TXSTSIE_Pos (13U)
#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
#define ETH_MACIER_TSIE_Pos (12U)
#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
#define ETH_MACIER_LPIIE_Pos (5U)
#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
#define ETH_MACIER_PMTIE_Pos (4U)
#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
#define ETH_MACIER_PHYIE_Pos (3U)
#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
#define ETH_MACISR_RGSMIIIE_Pos (0U)
#define ETH_MACISR_RGSMIIIE_Msk (0x1UL << ETH_MACISR_RGSMIIIE_Pos) /*!< 0x00000001 */
#define ETH_MACISR_RGSMIIIE ETH_MACISR_RGSMIIIE_Msk /* RGMII Interrupt Enable */
/************ Bit definition for Ethernet MAC Rx Tx Status Register ***************/
#define ETH_MACRXTXSR_RWT_Pos (8U)
#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
#define ETH_MACRXTXSR_EXCOL_Pos (5U)
#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
#define ETH_MACRXTXSR_LCOL_Pos (4U)
#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
#define ETH_MACRXTXSR_EXDEF_Pos (3U)
#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
#define ETH_MACRXTXSR_LCARR_Pos (2U)
#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
#define ETH_MACRXTXSR_NCARR_Pos (1U)
#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
#define ETH_MACRXTXSR_TJT_Pos (0U)
#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
/************ Bit definition for Ethernet MAC PMT Control Status Register ***************/
#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
#define ETH_MACPCSR_RWKPTR_Pos (24U)
#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
#define ETH_MACPCSR_RWKPFE_Pos (10U)
#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
#define ETH_MACPCSR_PWRDWN_Pos (0U)
#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
/************ Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register ***************/
#define ETH_MACRWKPFR_MACRWKPFR_Pos (0U)
#define ETH_MACRWKPFR_MACRWKPFR_Msk (0xFFFFFFFFUL << ETH_MACRWKPFR_MACRWKPFR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACRWKPFR_MACRWKPFR ETH_MACRWKPFR_MACRWKPFR_Msk /* Wake-up Packet filter register data */
/************ Bit definition for Ethernet MAC LPI Control Status Register ***************/
#define ETH_MACLCSR_LPITCSE_Pos (21U)
#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
#define ETH_MACLCSR_LPITE_Pos (20U)
#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
#define ETH_MACLCSR_LPITXA_Pos (19U)
#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
#define ETH_MACLCSR_PLSEN_Pos (18U)
#define ETH_MACLCSR_PLSEN_Msk (0x1UL << ETH_MACLCSR_PLSEN_Pos) /*!< 0x00040000 */
#define ETH_MACLCSR_PLSEN ETH_MACLCSR_PLSEN_Msk /* PHY Link Status Enable */
#define ETH_MACLCSR_PLS_Pos (17U)
#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
#define ETH_MACLCSR_LPIEN_Pos (16U)
#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
#define ETH_MACLCSR_RLPIST_Pos (9U)
#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
#define ETH_MACLCSR_TLPIST_Pos (8U)
#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
#define ETH_MACLCSR_RLPIEX_Pos (3U)
#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
#define ETH_MACLCSR_RLPIEN_Pos (2U)
#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
#define ETH_MACLCSR_TLPIEX_Pos (1U)
#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
#define ETH_MACLCSR_TLPIEN_Pos (0U)
#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
/************ Bit definition for Ethernet MAC LPI Timers Control Register ***************/
#define ETH_MACLTCR_LST_Pos (16U)
#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
#define ETH_MACLTCR_TWT_Pos (0U)
#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
/************ Bit definition for Ethernet MAC LPI Entry Timer Register ***************/
#define ETH_MACLETR_LPIET_Pos (0U)
#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
/************ Bit definition for Ethernet MAC 1US Tic Counter Register ***************/
#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
/************ Bit definition for Ethernet MAC PHYIF control status Register ***************/
#define ETH_MACPHYCSR_LNKSTS_Pos (19U)
#define ETH_MACPHYCSR_LNKSTS_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_Pos) /*!< 0x00080000 */
#define ETH_MACPHYCSR_LNKSTS ETH_MACPHYCSR_LNKSTS_Msk /* Link Status */
#define ETH_MACPHYCSR_LNKSTS_LD ((uint32_t)0x00000000) /* Link down */
#define ETH_MACPHYCSR_LNKSTS_LU_Pos (19U)
#define ETH_MACPHYCSR_LNKSTS_LU_Msk (0x1UL << ETH_MACPHYCSR_LNKSTS_LU_Pos) /*!< 0x00080000 */
#define ETH_MACPHYCSR_LNKSTS_LU ETH_MACPHYCSR_LNKSTS_LU_Msk /* Link up */
#define ETH_MACPHYCSR_LNKSPEED_Pos (17U)
#define ETH_MACPHYCSR_LNKSPEED_Msk (0x3UL << ETH_MACPHYCSR_LNKSPEED_Pos) /*!< 0x00060000 */
#define ETH_MACPHYCSR_LNKSPEED ETH_MACPHYCSR_LNKSPEED_Msk /* Link Speed */
#define ETH_MACPHYCSR_LNKSPEED_2_5MHZ ((uint32_t)0x00000000) /* 2.5 MHz */
#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos (17U)
#define ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk (0x1UL << ETH_MACPHYCSR_LNKSPEED_25MHZ_Pos) /*!< 0x00020000 */
#define ETH_MACPHYCSR_LNKSPEED_25MHZ ETH_MACPHYCSR_LNKSPEED_25MHZ_Msk /* 25 MHz */
#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos (18U)
#define ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk (0x1UL << ETH_MACPHYCSR_LNKSPEED_125MHZ_Pos) /*!< 0x00040000 */
#define ETH_MACPHYCSR_LNKSPEED_125MHZ ETH_MACPHYCSR_LNKSPEED_125MHZ_Msk /* 125 MHz */
#define ETH_MACPHYCSR_LNKMOD_Pos (16U)
#define ETH_MACPHYCSR_LNKMOD_Msk (0x1UL << ETH_MACPHYCSR_LNKMOD_Pos) /*!< 0x00080000 */
#define ETH_MACPHYCSR_LNKMOD ETH_MACPHYCSR_LNKMOD_Msk /* Link Mode */
#define ETH_MACPHYCSR_LNKMOD_HD ((uint32_t)0x00000000) /* Half-duplex mode */
#define ETH_MACPHYCSR_LNKMOD_FD_Pos (16U)
#define ETH_MACPHYCSR_LNKMOD_FD_Msk (0x1UL << ETH_MACPHYCSR_LNKMOD_FD_Pos) /*!< 0x00010000 */
#define ETH_MACPHYCSR_LNKMOD_FD ETH_MACPHYCSR_LNKMOD_FD_Msk /* Full-duplex mode */
#define ETH_MACPHYCSR_LUD_Pos (1U)
#define ETH_MACPHYCSR_LUD_Msk (0x1UL << ETH_MACPHYCSR_LUD_Pos) /*!< 0x00000002 */
#define ETH_MACPHYCSR_LUD ETH_MACPHYCSR_LUD_Msk /* Link Up or Down */
#define ETH_MACPHYCSR_LUD_LD ((uint32_t)0x00000000) /* Link down */
#define ETH_MACPHYCSR_LUD_LU_Pos (1U)
#define ETH_MACPHYCSR_LUD_LU_Msk (0x1UL << ETH_MACPHYCSR_LUD_LU_Pos) /*!< 0x00000002 */
#define ETH_MACPHYCSR_LUD_LU ETH_MACPHYCSR_LUD_LU_Msk /* Link up */
#define ETH_MACPHYCSR_TC_Pos (0U)
#define ETH_MACPHYCSR_TC_Msk (0x1UL << ETH_MACPHYCSR_TC_Pos) /*!< 0x00000001 */
#define ETH_MACPHYCSR_TC ETH_MACPHYCSR_TC_Msk /* Transmit Configuration in RGMII */
/************ Bit definition for Ethernet MAC Version Register ***************/
#define ETH_MACVR_USERVER_Pos (8U)
#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
#define ETH_MACVR_SNPSVER_Pos (0U)
#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
/************ Bit definition for Ethernet MAC Debug Register ***************/
#define ETH_MACDR_TFCSTS_Pos (17U)
#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
#define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
#define ETH_MACDR_TPESTS_Pos (16U)
#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
#define ETH_MACDR_RFCFCSTS_Pos (1U)
#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
#define ETH_MACDR_RPESTS_Pos (0U)
#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
/************ Bit definition for Ethernet MAC HW Feature 0 Register ***************/
#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
#define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos (28U)
#define ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RGMII_Pos) /*!< 0x10000000 */
#define ETH_MACHWF0R_ACTPHYSEL_RGMII ETH_MACHWF0R_ACTPHYSEL_RGMII_Msk /* RGMII */
#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos (29U)
#define ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_SGMII_Pos) /*!< 0x20000000 */
#define ETH_MACHWF0R_ACTPHYSEL_SGMII ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SGMII */
#define ETH_MACHWF0R_ACTPHYSEL_TBI_Pos (28U)
#define ETH_MACHWF0R_ACTPHYSEL_TBI_Msk (0x3UL << ETH_MACHWF0R_ACTPHYSEL_TBI_Pos) /*!< 0x30000000 */
#define ETH_MACHWF0R_ACTPHYSEL_TBI ETH_MACHWF0R_ACTPHYSEL_TBI_Msk /* TBI */
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos (28U)
#define ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk (0x5UL << ETH_MACHWF0R_ACTPHYSEL_RTBI_Pos) /*!< 0x50000000 */
#define ETH_MACHWF0R_ACTPHYSEL_RTBI ETH_MACHWF0R_ACTPHYSEL_RTBI_Msk /* RTBI */
#define ETH_MACHWF0R_ACTPHYSEL_SMII_Pos (29U)
#define ETH_MACHWF0R_ACTPHYSEL_SMII_Msk (0x3UL << ETH_MACHWF0R_ACTPHYSEL_SMII_Pos) /*!< 0x60000000 */
#define ETH_MACHWF0R_ACTPHYSEL_SMII ETH_MACHWF0R_ACTPHYSEL_SGMII_Msk /* SMII */
#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
#define ETH_MACHWF0R_EEESEL_Pos (13U)
#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
#define ETH_MACHWF0R_TSSEL_Pos (12U)
#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
#define ETH_MACHWF0R_MMCSEL_Pos (8U)
#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
#define ETH_MACHWF0R_MGKSEL_Pos (7U)
#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
#define ETH_MACHWF0R_RWKSEL_Pos (6U)
#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
#define ETH_MACHWF0R_SMASEL_Pos (5U)
#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
#define ETH_MACHWF0R_VLHASH_Pos (4U)
#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
#define ETH_MACHWF0R_PCSSEL_Pos (3U)
#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
#define ETH_MACHWF0R_HDSEL_Pos (2U)
#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
#define ETH_MACHWF0R_GMIISEL_Pos (1U)
#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
#define ETH_MACHWF0R_MIISEL_Pos (0U)
#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
/************ Bit definition for Ethernet MAC HW Feature 1 Register ***************/
#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
#define ETH_MACHWF1R_HASHTBLSZ_NOHASH ((uint32_t)0x00000000) /* No Hash table */
#define ETH_MACHWF1R_HASHTBLSZ_64_Pos (24U)
#define ETH_MACHWF1R_HASHTBLSZ_64_Msk (0x1UL << ETH_MACHWF1R_HASHTBLSZ_64_Pos) /*!< 0x03000000 */
#define ETH_MACHWF1R_HASHTBLSZ_64 ETH_MACHWF1R_HASHTBLSZ_64_Msk /* 64 */
#define ETH_MACHWF1R_HASHTBLSZ_128_Pos (25U)
#define ETH_MACHWF1R_HASHTBLSZ_128_Msk (0x1UL << ETH_MACHWF1R_HASHTBLSZ_128_Pos) /*!< 0x03000000 */
#define ETH_MACHWF1R_HASHTBLSZ_128 ETH_MACHWF1R_HASHTBLSZ_128_Msk /* 128 */
#define ETH_MACHWF1R_HASHTBLSZ_256_Pos (24U)
#define ETH_MACHWF1R_HASHTBLSZ_256_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_256_Pos) /*!< 0x03000000 */
#define ETH_MACHWF1R_HASHTBLSZ_256 ETH_MACHWF1R_HASHTBLSZ_256_Msk /* 256 */
#define ETH_MACHWF1R_POUOST_Pos (23U)
#define ETH_MACHWF1R_POUOST_Msk (0x1UL << ETH_MACHWF1R_POUOST_Pos) /*!< 0x00100000 */
#define ETH_MACHWF1R_POUOST ETH_MACHWF1R_POUOST_Msk /* One Step for PTP over UDP/IP Feature Enable */
#define ETH_MACHWF1R_RAVSEL_Pos (21U)
#define ETH_MACHWF1R_RAVSEL_Msk (0x1UL << ETH_MACHWF1R_RAVSEL_Pos) /*!< 0x00100000 */
#define ETH_MACHWF1R_RAVSEL ETH_MACHWF1R_RAVSEL_Msk /* Rx Side Only AV Feature Enable */
#define ETH_MACHWF1R_AVSEL_Pos (20U)
#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
#define ETH_MACHWF1R_TSOEN_Pos (18U)
#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
#define ETH_MACHWF1R_SPHEN_Pos (17U)
#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
#define ETH_MACHWF1R_DCBEN_Pos (16U)
#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
#define ETH_MACHWF1R_ADDR64_Pos (14U)
#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
#define ETH_MACHWF1R_PTOEN_Pos (12U)
#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
#define ETH_MACHWF1R_OSTEN_Pos (11U)
#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
#define ETH_MACHWF1R_SPRAM_Pos (5U)
#define ETH_MACHWF1R_SPRAM_Msk (0x1FUL << ETH_MACHWF1R_SPRAM_Pos) /*!< 0x00000020 */
#define ETH_MACHWF1R_SPRAM ETH_MACHWF1R_SPRAM_Msk /* MTL Receive FIFO Size */
#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
/************ Bit definition for Ethernet MAC HW Feature 2 Register ***************/
#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
#define ETH_MACHWF2R_TDCSZ_Pos (22U)
#define ETH_MACHWF2R_TDCSZ_Msk (0x3UL << ETH_MACHWF2R_TDCSZ_Pos) /*!< 0x00C00000 */
#define ETH_MACHWF2R_TDCSZ ETH_MACHWF2R_TDCSZ_Msk /* Tx DMA Descriptor Cache Size in terms of 16-byte descriptors */
#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
#define ETH_MACHWF2R_TXCHCNT_1DMATXCH ((uint32_t)0x00000000) /* 1 DMA Tx Channel */
#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos (18U)
#define ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk (0x1UL << ETH_MACHWF2R_TXCHCNT_2DMATXCH_Pos) /*!< 0x00040000 */
#define ETH_MACHWF2R_TXCHCNT_2DMATXCH ETH_MACHWF2R_TXCHCNT_2DMATXCH_Msk /* 2 DMA Tx Channels */
#define ETH_MACHWF2R_RDCSZ_Pos (16U)
#define ETH_MACHWF2R_RDCSZ_Msk (0x3UL << ETH_MACHWF2R_RDCSZ_Pos) /*!< 0x00C00000 */
#define ETH_MACHWF2R_RDCSZ ETH_MACHWF2R_RDCSZ_Msk /* Rx DMA Descriptor Cache Size in terms of 16-byte descriptors */
#define ETH_MACHWF2R_RXCHCNT_Pos (12U)
#define ETH_MACHWF2R_RXCHCNT_Msk (0xFUL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000F000 */
#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
#define ETH_MACHWF2R_RXCHCNT_1DMARXCH ((uint32_t)0x00000000) /* 1 DMA Rx Channel */
#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos (12U)
#define ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk (0x1UL << ETH_MACHWF2R_RXCHCNT_2DMARXCH_Pos) /*!< 0x00040000 */
#define ETH_MACHWF2R_RXCHCNT_2DMARXCH ETH_MACHWF2R_RXCHCNT_2DMARXCH_Msk /* 2 DMA Rx Channels */
#define ETH_MACHWF2R_TXQCNT_Pos (6U)
#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
#define ETH_MACHWF2R_TXQCNT_1MTLTXQ ((uint32_t)0x00000000) /* 1 MTL Tx queue */
#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos (6U)
#define ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk (0x1UL << ETH_MACHWF2R_TXQCNT_2MTLTXQ_Pos) /*!< 0x00000040 */
#define ETH_MACHWF2R_TXQCNT_2MTLTXQ ETH_MACHWF2R_TXQCNT_2MTLTXQ_Msk /* 2 MTL Tx queue */
#define ETH_MACHWF2R_RXQCNT_Pos (0U)
#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
#define ETH_MACHWF2R_RXQCNT_1MTLRXQ ((uint32_t)0x00000000) /* 1 MTL Rx queue */
#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos (0U)
#define ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk (0x1UL << ETH_MACHWF2R_RXQCNT_2MTLRXQ_Pos) /*!< 0x00000001 */
#define ETH_MACHWF2R_RXQCNT_2MTLRXQ ETH_MACHWF2R_RXQCNT_2MTLRXQ_Msk /* 2 MTL Rx queue */
/************ Bit definition for Ethernet MAC HW Feature 3 Register ***************/
#define ETH_MACHWF3R_ASP_Pos (28U)
#define ETH_MACHWF3R_ASP_Msk (0x3UL << ETH_MACHWF3R_ASP_Pos) /*!< 0x30000000 */
#define ETH_MACHWF3R_ASP ETH_MACHWF3R_ASP_Msk /* Automotive Safety Package */
#define ETH_MACHWF3R_ASP_NONE ((uint32_t)0x00000000) /* None */
#define ETH_MACHWF3R_ASP_ECC_Pos (28U)
#define ETH_MACHWF3R_ASP_ECC_Msk (0x1UL << ETH_MACHWF3R_ASP_ECC_Pos) /*!< 0x10000000 */
#define ETH_MACHWF3R_ASP_ECC ETH_MACHWF3R_ASP_ECC_Msk /* ECC only */
#define ETH_MACHWF3R_ASP_ASNPPE_Pos (29U)
#define ETH_MACHWF3R_ASP_ASNPPE_Msk (0x1UL << ETH_MACHWF3R_ASP_ASNPPE_Pos) /*!< 0x20000000 */
#define ETH_MACHWF3R_ASP_ASNPPE ETH_MACHWF3R_ASP_ASNPPE_Msk /* AS_NPPE */
#define ETH_MACHWF3R_ASP_ASPPE_Pos (28U)
#define ETH_MACHWF3R_ASP_ASPPE_Msk (0x3UL << ETH_MACHWF3R_ASP_ASPPE_Pos) /*!< 0x30000000 */
#define ETH_MACHWF3R_ASP_ASPPE ETH_MACHWF3R_ASP_ASPPE_Msk /* AS_PPE */
#define ETH_MACHWF3R_TBSSEL_Pos (27U)
#define ETH_MACHWF3R_TBSSEL_Msk (0x1UL << ETH_MACHWF3R_TBSSEL_Pos) /*!< 0x08000000 */
#define ETH_MACHWF3R_TBSSEL ETH_MACHWF3R_TBSSEL_Msk /* Time-based scheduling Enable */
#define ETH_MACHWF3R_FPESEL_Pos (26U)
#define ETH_MACHWF3R_FPESEL_Msk (0x1UL << ETH_MACHWF3R_FPESEL_Pos) /*!< 0x04000000 */
#define ETH_MACHWF3R_FPESEL ETH_MACHWF3R_FPESEL_Msk /* Frame Preemption Enable */
#define ETH_MACHWF3R_ESTWID_Pos (20U)
#define ETH_MACHWF3R_ESTWID_Msk (0x3UL << ETH_MACHWF3R_ESTWID_Pos) /*!< 0x00300000 */
#define ETH_MACHWF3R_ESTWID ETH_MACHWF3R_ESTWID_Msk /* Width of the Time Interval field in the Gate Control List */
#define ETH_MACHWF3R_ESTWID_NOWIDTH ((uint32_t)0x00000000) /* No Width */
#define ETH_MACHWF3R_ESTWID_16_Pos (20U)
#define ETH_MACHWF3R_ESTWID_16_Msk (0x1UL << ETH_MACHWF3R_ESTWID_16_Pos) /*!< 0x00100000 */
#define ETH_MACHWF3R_ESTWID_16 ETH_MACHWF3R_ESTWID_16_Msk /* 16 Width */
#define ETH_MACHWF3R_ESTWID_20_Pos (21U)
#define ETH_MACHWF3R_ESTWID_20_Msk (0x1UL << ETH_MACHWF3R_ESTWID_20_Pos) /*!< 0x00200000 */
#define ETH_MACHWF3R_ESTWID_20 ETH_MACHWF3R_ESTWID_20_Msk /* 20 Width */
#define ETH_MACHWF3R_ESTWID_24_Pos (20U)
#define ETH_MACHWF3R_ESTWID_24_Msk (0x3UL << ETH_MACHWF3R_ESTWID_24_Pos) /*!< 0x00300000 */
#define ETH_MACHWF3R_ESTWID_24 ETH_MACHWF3R_ESTWID_24_Msk /* 24 Width */
#define ETH_MACHWF3R_ESTDEP_Pos (17U)
#define ETH_MACHWF3R_ESTDEP_Msk (0x7UL << ETH_MACHWF3R_ESTDEP_Pos) /*!< 0x000E0000 */
#define ETH_MACHWF3R_ESTDEP ETH_MACHWF3R_ESTDEP_Msk /* Depth of the Gate Control List */
#define ETH_MACHWF3R_ESTDEP_NODEPTH ((uint32_t)0x00000000) /* No depth */
#define ETH_MACHWF3R_ESTDEP_64_Pos (17U)
#define ETH_MACHWF3R_ESTDEP_64_Msk (0x1UL << ETH_MACHWF3R_ESTDEP_64_Pos) /*!< 0x00020000 */
#define ETH_MACHWF3R_ESTDEP_64 ETH_MACHWF3R_ESTDEP_64_Msk /* 64 depth */
#define ETH_MACHWF3R_ESTDEP_128_Pos (18U)
#define ETH_MACHWF3R_ESTDEP_128_Msk (0x1UL << ETH_MACHWF3R_ESTDEP_128_Pos) /*!< 0x00040000 */
#define ETH_MACHWF3R_ESTDEP_128 ETH_MACHWF3R_ESTDEP_128_Msk /* 128 depth */
#define ETH_MACHWF3R_ESTDEP_256_Pos (17U)
#define ETH_MACHWF3R_ESTDEP_256_Msk (0x3UL << ETH_MACHWF3R_ESTDEP_256_Pos) /*!< 0x00060000 */
#define ETH_MACHWF3R_ESTDEP_256 ETH_MACHWF3R_ESTDEP_256_Msk /* 256 depth */
#define ETH_MACHWF3R_ESTDEP_512_Pos (19U)
#define ETH_MACHWF3R_ESTDEP_512_Msk (0x1UL << ETH_MACHWF3R_ESTDEP_512_Pos) /*!< 0x00080000 */
#define ETH_MACHWF3R_ESTDEP_512 ETH_MACHWF3R_ESTDEP_512_Msk /* 512 depth */
#define ETH_MACHWF3R_ESTDEP_1024_Pos (17U)
#define ETH_MACHWF3R_ESTDEP_1024_Msk (0x5UL << ETH_MACHWF3R_ESTDEP_1024_Pos) /*!< 0x000A0000 */
#define ETH_MACHWF3R_ESTDEP_1024 ETH_MACHWF3R_ESTDEP_1024_Msk /* 1024 depth */
#define ETH_MACHWF3R_ESTSEL_Pos (16U)
#define ETH_MACHWF3R_ESTSEL_Msk (0x1UL << ETH_MACHWF3R_ESTSEL_Pos) /*!< 0x00010000 */
#define ETH_MACHWF3R_ESTSEL ETH_MACHWF3R_ESTSEL_Msk /* Enhancements to Scheduled Traffic Enable */
#define ETH_MACHWF3R_FRPES_Pos (13U)
#define ETH_MACHWF3R_FRPES_Msk (0x3UL << ETH_MACHWF3R_FRPES_Pos) /*!< 0x00006000 */
#define ETH_MACHWF3R_FRPES ETH_MACHWF3R_FRPES_Msk /* Flexible Receive Parser Table Entries size */
#define ETH_MACHWF3R_FRPES_64 ((uint32_t)0x00000000) /* 64 entries */
#define ETH_MACHWF3R_FRPES_128_Pos (13U)
#define ETH_MACHWF3R_FRPES_128_Msk (0x1UL << ETH_MACHWF3R_FRPES_128_Pos) /*!< 0x00002000 */
#define ETH_MACHWF3R_FRPES_128 ETH_MACHWF3R_FRPES_128_Msk /* 128 entries */
#define ETH_MACHWF3R_FRPES_256_Pos (14U)
#define ETH_MACHWF3R_FRPES_256_Msk (0x1UL << ETH_MACHWF3R_FRPES_256_Pos) /*!< 0x00004000 */
#define ETH_MACHWF3R_FRPES_256 ETH_MACHWF3R_FRPES_256_Msk /* 256 entries */
#define ETH_MACHWF3R_FRPBS_Pos (11U)
#define ETH_MACHWF3R_FRPBS_Msk (0x3UL << ETH_MACHWF3R_FRPBS_Pos) /*!< 0x00001800 */
#define ETH_MACHWF3R_FRPBS ETH_MACHWF3R_FRPBS_Msk /* Flexible Receive Parser Buffer size */
#define ETH_MACHWF3R_FRPBS_64 ((uint32_t)0x00000000) /* 64 entries */
#define ETH_MACHWF3R_FRPBS_128_Pos (11U)
#define ETH_MACHWF3R_FRPBS_128_Msk (0x1UL << ETH_MACHWF3R_FRPBS_128_Pos) /*!< 0x00000100 */
#define ETH_MACHWF3R_FRPBS_128 ETH_MACHWF3R_FRPBS_128_Msk /* 128 entries */
#define ETH_MACHWF3R_FRPBS_256_Pos (12U)
#define ETH_MACHWF3R_FRPBS_256_Msk (0x1UL << ETH_MACHWF3R_FRPBS_256_Pos) /*!< 0x00001000 */
#define ETH_MACHWF3R_FRPBS_256 ETH_MACHWF3R_FRPBS_256_Msk /* 256 entries */
#define ETH_MACHWF3R_FRPSEL_Pos (10U)
#define ETH_MACHWF3R_FRPSEL_Msk (0x1UL << ETH_MACHWF3R_FRPSEL_Pos) /*!< 0x00000400 */
#define ETH_MACHWF3R_FRPSEL ETH_MACHWF3R_FRPSEL_Msk /* Flexible Receive Parser Selected */
#define ETH_MACHWF3R_PDUPSEL_Pos (9U)
#define ETH_MACHWF3R_PDUPSEL_Msk (0x1UL << ETH_MACHWF3R_PDUPSEL_Pos) /*!< 0x00000200 */
#define ETH_MACHWF3R_PDUPSEL ETH_MACHWF3R_PDUPSEL_Msk /* Broadcast/Multicast Packet Duplication */
#define ETH_MACHWF3R_DVLAN_Pos (5U)
#define ETH_MACHWF3R_DVLAN_Msk (0x1UL << ETH_MACHWF3R_DVLAN_Pos) /*!< 0x00000020 */
#define ETH_MACHWF3R_DVLAN ETH_MACHWF3R_DVLAN_Msk /* Double VLAN processing enable */
#define ETH_MACHWF3R_CBTISEL_Pos (4U)
#define ETH_MACHWF3R_CBTISEL_Msk (0x1UL << ETH_MACHWF3R_CBTISEL_Pos) /*!< 0x00000010 */
#define ETH_MACHWF3R_CBTISEL ETH_MACHWF3R_CBTISEL_Msk /* Queue/Channel based VLAN tag insertion on Tx enable */
#define ETH_MACHWF3R_NRVF_Pos (0U)
#define ETH_MACHWF3R_NRVF_Msk (0x7UL << ETH_MACHWF3R_NRVF_Pos) /*!< 0x00000007 */
#define ETH_MACHWF3R_NRVF ETH_MACHWF3R_NRVF_Msk /* Number of Extended VLAN Tag Filters Enabled */
#define ETH_MACHWF3R_NRVF_NOEXRXVLANFLTR ((uint32_t)0x00000000) /* No Extended Rx VLAN Filters */
#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos (0U)
#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk (0x1UL << ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Pos) /*!< 0x00000001 */
#define ETH_MACHWF3R_NRVF_4EXRXVLANFLTR ETH_MACHWF3R_NRVF_4EXRXVLANFLTR_Msk
#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos (1U)
#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk (0x1UL << ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Pos) /*!< 0x00000002 */
#define ETH_MACHWF3R_NRVF_8EXRXVLANFLTR ETH_MACHWF3R_NRVF_8EXRXVLANFLTR_Msk
#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos (0U)
#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk (0x3UL << ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Pos) /*!< 0x00000003 */
#define ETH_MACHWF3R_NRVF_16EXRXVLANFLTR ETH_MACHWF3R_NRVF_16EXRXVLANFLTR_Msk
#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos (2U)
#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk (0x1UL << ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Pos) /*!< 0x00000004 */
#define ETH_MACHWF3R_NRVF_24EXRXVLANFLTR ETH_MACHWF3R_NRVF_24EXRXVLANFLTR_Msk
#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos (0U)
#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk (0x5UL << ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Pos) /*!< 0x00000005 */
#define ETH_MACHWF3R_NRVF_32EXRXVLANFLTR ETH_MACHWF3R_NRVF_32EXRXVLANFLTR_Msk
/************ Bit definition for Ethernet MAC MDIO Address Register ***************/
#define ETH_MACMDIOAR_PSE_Pos (27U)
#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
#define ETH_MACMDIOAR_BTB_Pos (26U)
#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
#define ETH_MACMDIOAR_PA_Pos (21U)
#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
#define ETH_MACMDIOAR_RDA_Pos (16U)
#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
#define ETH_MACMDIOAR_NTC_Pos (12U)
#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
#define ETH_MACMDIOAR_CR_Pos (8U)
#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
#define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
#define ETH_MACMDIOAR_CR_DIV204_Pos (9U)
#define ETH_MACMDIOAR_CR_DIV204_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV204_Pos) /*!< 0x00000600 */
#define ETH_MACMDIOAR_CR_DIV204 ETH_MACMDIOAR_CR_DIV204_Msk /* CSR clock/204 */
#define ETH_MACMDIOAR_CR_DIV324_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV324_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV324_Pos) /*!< 0x00000700 */
#define ETH_MACMDIOAR_CR_DIV324 ETH_MACMDIOAR_CR_DIV324_Msk /* CSR clock/304 */
#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
#define ETH_MACMDIOAR_SKAP_Pos (4U)
#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
#define ETH_MACMDIOAR_GOC_Pos (2U)
#define ETH_MACMDIOAR_GOC_Msk (0x3UL << ETH_MACMDIOAR_GOC_Pos) /*!< 0x0000000C */
#define ETH_MACMDIOAR_GOC_0 (0x1U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x00000004 */
#define ETH_MACMDIOAR_GOC_1 (0x2U << ETH_MACMDIOAR_GOC_Pos) /*!< 0x00000008 */
#define ETH_MACMDIOAR_GOC ETH_MACMDIOAR_GOC_Msk /* GMII Operation Command */
#define ETH_MACMDIOAR_C45E_Pos (1U)
#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
#define ETH_MACMDIOAR_GB_Pos (0U)
#define ETH_MACMDIOAR_GB_Msk (0x1UL << ETH_MACMDIOAR_GB_Pos) /*!< 0x00000001 */
#define ETH_MACMDIOAR_GB ETH_MACMDIOAR_GB_Msk /* GMII Busy */
/************ Bit definition for Ethernet MAC MDIO Data Register ***************/
#define ETH_MACMDIODR_RA_Pos (16U)
#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
#define ETH_MACMDIODR_GD_Pos (0U)
#define ETH_MACMDIODR_GD_Msk (0xFFFFUL << ETH_MACMDIODR_GD_Pos) /*!< 0x0000FFFF */
#define ETH_MACMDIODR_GD ETH_MACMDIODR_GD_Msk /* GMII Data */
/************ Bit definition for Ethernet ARP Address Register ***************/
#define ETH_MACARPAR_ARPPA_Pos (0U)
#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
/************ Bit definition for Ethernet MAC CSR software control Register ***************/
#define ETH_MACCSRSWCR_SEEN_Pos (8U)
#define ETH_MACCSRSWCR_SEEN_Msk (0x1UL << ETH_MACCSRSWCR_SEEN_Pos) /*!< 0x00000100 */
#define ETH_MACCSRSWCR_SEEN ETH_MACCSRSWCR_SEEN_Msk /* Slave Error Response Enable */
#define ETH_MACCSRSWCR_RCWE_Pos (0U)
#define ETH_MACCSRSWCR_RCWE_Msk (0x1UL << ETH_MACCSRSWCR_RCWE_Pos) /*!< 0x00000001 */
#define ETH_MACCSRSWCR_RCWE ETH_MACCSRSWCR_RCWE_Msk /* Register Clear on Write 1 Enable */
/************ Bit definition for Ethernet MAC FPE control and status Register ***************/
#define ETH_MACFPECSR_TRSP_Pos (19U)
#define ETH_MACFPECSR_TRSP_Msk (0x1UL << ETH_MACFPECSR_TRSP_Pos) /*!< 0x00080000 */
#define ETH_MACFPECSR_TRSP ETH_MACFPECSR_TRSP_Msk /* Transmitted Respond Frame */
#define ETH_MACFPECSR_TVER_Pos (18U)
#define ETH_MACFPECSR_TVER_Msk (0x1UL << ETH_MACFPECSR_TVER_Pos) /*!< 0x00040000 */
#define ETH_MACFPECSR_TVER ETH_MACFPECSR_TVER_Msk /* Transmitted Verify Frame */
#define ETH_MACFPECSR_RRSP_Pos (17U)
#define ETH_MACFPECSR_RRSP_Msk (0x1UL << ETH_MACFPECSR_RRSP_Pos) /*!< 0x00020000 */
#define ETH_MACFPECSR_RRSP ETH_MACFPECSR_RRSP_Msk /* Received Respond Frame */
#define ETH_MACFPECSR_RVER_Pos (16U)
#define ETH_MACFPECSR_RVER_Msk (0x1UL << ETH_MACFPECSR_RVER_Pos) /*!< 0x00010000 */
#define ETH_MACFPECSR_RVER ETH_MACFPECSR_RVER_Msk /* Received Verify Frame */
#define ETH_MACFPECSR_SRSP_Pos (2U)
#define ETH_MACFPECSR_SRSP_Msk (0x1UL << ETH_MACFPECSR_SRSP_Pos) /*!< 0x00000004 */
#define ETH_MACFPECSR_SRSP ETH_MACFPECSR_SRSP_Msk /* Send Respond mPacket */
#define ETH_MACFPECSR_SVER_Pos (1U)
#define ETH_MACFPECSR_SVER_Msk (0x1UL << ETH_MACFPECSR_SVER_Pos) /*!< 0x00000002 */
#define ETH_MACFPECSR_SVER ETH_MACFPECSR_SVER_Msk /* Send Verify mPacket */
#define ETH_MACFPECSR_EFPE_Pos (0U)
#define ETH_MACFPECSR_EFPE_Msk (0x1UL << ETH_MACFPECSR_EFPE_Pos) /*!< 0x00000001 */
#define ETH_MACFPECSR_EFPE ETH_MACFPECSR_EFPE_Msk /* Enable Tx Frame Preemption */
/************ Bit definition for Ethernet MAC presentation time Register ***************/
#define ETH_MACPRSTIMR_MPTN_Pos (0U)
#define ETH_MACPRSTIMR_MPTN_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMR_MPTN_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPRSTIMR_MPTN ETH_MACPRSTIMR_MPTN_Msk /* MAC 1722 Presentation Time in ns */
/************ Bit definition for Ethernet MAC presentation time Register ***************/
#define ETH_MACPRSTIMUR_MPTU_Pos (0U)
#define ETH_MACPRSTIMUR_MPTU_Msk (0xFFFFFFFFUL << ETH_MACPRSTIMUR_MPTU_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPRSTIMUR_MPTU ETH_MACPRSTIMUR_MPTU_Msk /* MAC 1722 Presentation Time Update */
/************ Bit definition for Ethernet MAC Address 0 High Register ***************/
#define ETH_MACA0HR_AE_Pos (31U)
#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
#define ETH_MACA0HR_DCS_Pos (16U)
#define ETH_MACA0HR_DCS_Msk (0x1UL << ETH_MACA0HR_DCS_Pos) /*!< 0x80000000 */
#define ETH_MACA0HR_DCS ETH_MACA0HR_DCS_Msk /* DMA Channel Select */
#define ETH_MACA0HR_ADDRHI_Pos (0U)
#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
/************ Bit definition for Ethernet MAC Address x Low Register ***************/
#define ETH_MACAxLR_ADDRLO_Pos (0U)
#define ETH_MACAxLR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACAxLR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACAxLR_ADDRLO ETH_MACAxLR_ADDRLO_Msk /* MAC Address x*/
/************ Bit definition for Ethernet MAC Address x High Register ***************/
#define ETH_MACAxHR_AE_Pos (31U)
#define ETH_MACAxHR_AE_Msk (0x1UL << ETH_MACAxHR_AE_Pos) /*!< 0x80000000 */
#define ETH_MACAxHR_AE ETH_MACAxHR_AE_Msk /* Address Enable*/
#define ETH_MACAxHR_SA_Pos (30U)
#define ETH_MACAxHR_SA_Msk (0x1UL << ETH_MACAxHR_SA_Pos) /*!< 0x40000000 */
#define ETH_MACAxHR_SA ETH_MACAxHR_SA_Msk /* Source Address */
#define ETH_MACAxHR_MBC_Pos (24U)
#define ETH_MACAxHR_MBC_Msk (0x3FUL << ETH_MACAxHR_MBC_Pos) /*!< 0x3F000000 */
#define ETH_MACAxHR_MBC ETH_MACAxHR_MBC_Msk /* Mask Byte Control */
#define ETH_MACAxHR_DCS_Pos (16U)
#define ETH_MACAxHR_DCS_Msk (0x1UL << ETH_MACAxHR_DCS_Pos) /*!< 0x00010000 */
#define ETH_MACAxHR_DCS ETH_MACAxHR_DCS_Msk /* DMA Channel Select */
#define ETH_MACAxHR_ADDRHI_Pos (0U)
#define ETH_MACAxHR_ADDRHI_Msk (0xFFFFUL << ETH_MACAxHR_ADDRHI_Pos) /*!< 0x0000FFFF */
#define ETH_MACAxHR_ADDRHI ETH_MACAxHR_ADDRHI_Msk /* MAC Address 1*/
/************ Bit definition for Ethernet MMC Control Register ***************/
#define ETH_MMCCR_UCDBC_Pos (8U)
#define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
#define ETH_MMCCR_CNTPRST_Pos (4U)
#define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
#define ETH_MMCCR_CNTFREEZ_Pos (3U)
#define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
#define ETH_MMCCR_RSTONRD_Pos (2U)
#define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
#define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
#define ETH_MMCCR_CNTRST_Pos (0U)
#define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
/************ Bit definition for Ethernet MMC Rx Interrupt Register ***************/
#define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
#define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
#define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
#define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
#define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
#define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
#define ETH_MMCRIR_RXUCGPIS_Pos (17U)
#define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
#define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
#define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
#define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
#define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
#define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
#define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
#define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
/************ Bit definition for Ethernet MMC Tx Interrupt Register ***************/
#define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
#define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
#define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
#define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
#define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
#define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
#define ETH_MMCTIR_TXGPKTIS_Pos (21U)
#define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
#define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
#define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
#define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
#define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
#define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
#define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
#define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
/************ Bit definition for Ethernet MMC Rx interrupt Mask Register ***************/
#define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
#define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
#define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
#define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
#define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
#define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
#define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
#define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
#define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
#define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
#define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
#define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
#define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
#define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
#define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
/************ Bit definition for Ethernet MMC Tx Interrupt Mask Register ***************/
#define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
#define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
#define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
#define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
#define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
#define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
#define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
#define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
#define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
#define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
#define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
#define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
#define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
#define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
#define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
/************ Bit definition for Ethernet MMC Tx Single Collision Good Packets Register ***************/
#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
#define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
/************ Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register ***************/
#define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
#define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
/************ Bit definition for Ethernet MMC Tx Packet Count Good Register ***************/
#define ETH_MMCTPCGR_TXPKTG_Pos (0U)
#define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
/************ Bit definition for Ethernet MMC Rx CRC Error Packets Register ***************/
#define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
#define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
/************ Bit definition for Ethernet MMC Rx alignment error packets Register ***************/
#define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
#define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
/************ Bit definition for Ethernet MMC Rx Unicast Packets Good Register ***************/
#define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
#define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
/************ Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register ***************/
#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
#define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
/************ Bit definition for Ethernet MMC Tx LPI Transition Counter Register ***************/
#define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
#define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
/************ Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register ***************/
#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
#define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
/************ Bit definition for Ethernet MMC Rx LPI Transition Counter Register ***************/
#define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
#define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
/************ Bit definition for Ethernet MMC FPE Tx interrupt status Register ***************/
#define ETH_MMCFPETISR_HRCIS_Pos (1U)
#define ETH_MMCFPETISR_HRCIS_msk (0x1UL << ETH_MMCFPETISR_HRCIS_Pos) /*!< 0x00000002 */
#define ETH_MMCFPETISR_HRCIS ETH_MMCFPETISR_HRCIS_msk /* MMC Tx Hold Request Counter Interrupt Status */
#define ETH_MMCFPETISR_FCIS_Pos (0U)
#define ETH_MMCFPETISR_FCIS_msk (0x1UL << ETH_MMCFPETISR_FCIS_Pos) /*!< 0x00000001 */
#define ETH_MMCFPETISR_FCIS ETH_MMCFPETISR_FCIS_msk /* MMC Tx FPE Fragment Counter Interrupt status */
/************ Bit definition for Ethernet MMC FPE Tx interrupt mask Register ***************/
#define ETH_MMCFPETIMR_HRCIM_Pos (1U)
#define ETH_MMCFPETIMR_HRCIM_msk (0x1UL << ETH_MMCFPETIMR_HRCIM_Pos) /*!< 0x00000002 */
#define ETH_MMCFPETIMR_HRCIM ETH_MMCFPETIMR_HRCIM_msk /* MMC transmit Hold Request Counter Interrupt Mask */
#define ETH_MMCFPETIMR_FCIM_Pos (0U)
#define ETH_MMCFPETIMR_FCIM_msk (0x1UL << ETH_MMCFPETIMR_FCIM_Pos) /*!< 0x00000001 */
#define ETH_MMCFPETIMR_FCIM ETH_MMCFPETIMR_FCIM_msk /* MMC Transmit Fragment Counter Interrupt Mask */
/************ Bit definition for Ethernet MMC FPE Tx fragment counter Register ***************/
#define ETH_MMCFPETFCR_TXFFC_Pos (0U)
#define ETH_MMCFPETFCR_TXFFC_msk (0xFFFFFFFFUL << ETH_MMCFPETFCR_TXFFC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCFPETFCR_TXFFC ETH_MMCFPETFCR_TXFFC_msk /* MMC transmit Hold Request Counter Interrupt Mask */
/************ Bit definition for Ethernet MMC Tx hold request counter Register ***************/
#define ETH_MMCTHRCR_TXHRC_Pos (0U)
#define ETH_MMCTHRCR_TXHRC_msk (0xFFFFFFFFUL << ETH_MMCTHRCR_TXHRC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCTHRCR_TXHRC ETH_MMCTHRCR_TXHRC_msk /* Tx hold request counter */
/************ Bit definition for Ethernet MMC FPE Rx interrupt status Register ***************/
#define ETH_MMCFPERISR_FCIS_Pos (3U)
#define ETH_MMCFPERISR_FCIS_msk (0x1UL << ETH_MMCFPERISR_FCIS_Pos) /*!< 0x00000008 */
#define ETH_MMCFPERISR_FCIS ETH_MMCFPERISR_FCIS_msk /* MMC Rx FPE Fragment Counter Interrupt Status */
#define ETH_MMCFPERISR_PAOCIS_Pos (2U)
#define ETH_MMCFPERISR_PAOCIS_msk (0x1UL << ETH_MMCFPERISR_PAOCIS_Pos) /*!< 0x00000004 */
#define ETH_MMCFPERISR_PAOCIS ETH_MMCFPERISR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt status */
#define ETH_MMCFPERISR_PSECIS_Pos (1U)
#define ETH_MMCFPERISR_PSECIS_msk (0x1UL << ETH_MMCFPERISR_PSECIS_Pos) /*!< 0x00000002 */
#define ETH_MMCFPERISR_PSECIS ETH_MMCFPERISR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt status */
#define ETH_MMCFPERISR_PAECIS_Pos (0U)
#define ETH_MMCFPERISR_PAECIS_msk (0x1UL << ETH_MMCFPERISR_PAECIS_Pos) /*!< 0x00000001 */
#define ETH_MMCFPERISR_PAECIS ETH_MMCFPERISR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt status */
/************ Bit definition for Ethernet MMC FPE Rx interrupt mask Register ***************/
#define ETH_MMCFPERIMR_FCIM_Pos (3U)
#define ETH_MMCFPERIMR_FCIM_msk (0x1UL << ETH_MMCFPERIMR_FCIM_Pos) /*!< 0x00000008 */
#define ETH_MMCFPERIMR_FCIM ETH_MMCFPERIMR_FCIM_msk /* MMC Rx FPE Fragment Counter Interrupt Mask */
#define ETH_MMCFPERIMR_PAOCIS_Pos (2U)
#define ETH_MMCFPERIMR_PAOCIS_msk (0x1UL << ETH_MMCFPERIMR_PAOCIS_Pos) /*!< 0x00000004 */
#define ETH_MMCFPERIMR_PAOCIS ETH_MMCFPERIMR_PAOCIS_msk /* MMC Rx Packet Assembly OK counter interrupt Mask */
#define ETH_MMCFPERIMR_PSECIS_Pos (1U)
#define ETH_MMCFPERIMR_PSECIS_msk (0x1UL << ETH_MMCFPERIMR_PSECIS_Pos) /*!< 0x00000002 */
#define ETH_MMCFPERIMR_PSECIS ETH_MMCFPERIMR_PSECIS_msk /* MMC Rx Packet SMD Error counter interrupt Mask */
#define ETH_MMCFPERIMR_PAECIS_Pos (0U)
#define ETH_MMCFPERIMR_PAECIS_msk (0x1UL << ETH_MMCFPERIMR_PAECIS_Pos) /*!< 0x00000001 */
#define ETH_MMCFPERIMR_PAECIS ETH_MMCFPERIMR_PAECIS_msk /* MMC Rx Packet Assembly Error counter interrupt Mask */
/************ Bit definition for Ethernet MMC Rx packet assembly error Register ***************/
#define ETH_MMCRPAER_PAEC_Pos (0U)
#define ETH_MMCRPAER_PAEC_msk (0xFFFFFFFFUL << ETH_MMCRPAER_PAEC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRPAER_PAEC ETH_MMCRPAER_PAEC_msk /* Rx Packet Assembly Error Counter */
/************ Bit definition for Ethernet MMC Rx packet SMD error Register ***************/
#define ETH_MMCRPSMDER_PSEC_Pos (0U)
#define ETH_MMCRPSMDER_PSEC_msk (0xFFFFFFFFUL << ETH_MMCRPSMDER_PSEC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRPSMDER_PSEC ETH_MMCRPSMDER_PSEC_msk /* Rx Packet SMD Error Counter */
/************ Bit definition for Ethernet MMC Rx packet assembly OK Register ***************/
#define ETH_MMCRPAOKR_PAOC_Pos (0U)
#define ETH_MMCRPAOKR_PAOC_msk (0xFFFFFFFFUL << ETH_MMCRPAOKR_PAOC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCRPAOKR_PAOC ETH_MMCRPAOKR_PAOC_msk /* Rx Packet Assembly OK Counter */
/************ Bit definition for Ethernet MMC Rx FPE fragments counter Register ***************/
#define ETH_MMCFPERFCR_FFC_Pos (0U)
#define ETH_MMCFPERFCR_FFC_msk (0xFFFFFFFFUL << ETH_MMCFPERFCR_FFC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MMCFPERFCR_FFC ETH_MMCFPERFCR_FFC_msk /* Rx FPE Fragment Counter */
/************ Bit definition for Ethernet MAC L3 and L4 control 0 Register ***************/
#define ETH_MACL3L4C0R_DMCHEN0_Pos (28U)
#define ETH_MACL3L4C0R_DMCHEN0_Msk (0x1UL << ETH_MACL3L4C0R_DMCHEN0_Pos) /*!< 0x10000000 */
#define ETH_MACL3L4C0R_DMCHEN0 ETH_MACL3L4C0R_DMCHEN0_Msk /* DMA Channel Select Enable */
#define ETH_MACL3L4C0R_DMCHN0_Pos (24U)
#define ETH_MACL3L4C0R_DMCHN0_Msk (0x1UL << ETH_MACL3L4C0R_DMCHN0_Pos) /*!< 0x01000000 */
#define ETH_MACL3L4C0R_DMCHN0 ETH_MACL3L4C0R_DMCHN0_Msk /* DMA Channel Number */
#define ETH_MACL3L4C0R_L4DPIM0_Pos (21U)
#define ETH_MACL3L4C0R_L4DPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPIM0_Pos) /*!< 0x00200000 */
#define ETH_MACL3L4C0R_L4DPIM0 ETH_MACL3L4C0R_L4DPIM0_Msk /* Layer 4 Destination Port Inverse Match Enable */
#define ETH_MACL3L4C0R_L4DPM0_Pos (20U)
#define ETH_MACL3L4C0R_L4DPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4DPM0_Pos) /*!< 0x00100000 */
#define ETH_MACL3L4C0R_L4DPM0 ETH_MACL3L4C0R_L4DPM0_Msk /* Layer 4 Destination Port Match Enable */
#define ETH_MACL3L4C0R_L4SPIM0_Pos (19U)
#define ETH_MACL3L4C0R_L4SPIM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPIM0_Pos) /*!< 0x00080000 */
#define ETH_MACL3L4C0R_L4SPIM0 ETH_MACL3L4C0R_L4SPIM0_Msk /* Layer 4 Source Port Inverse Match Enable */
#define ETH_MACL3L4C0R_L4SPM0_Pos (18U)
#define ETH_MACL3L4C0R_L4SPM0_Msk (0x1UL << ETH_MACL3L4C0R_L4SPM0_Pos) /*!< 0x00040000 */
#define ETH_MACL3L4C0R_L4SPM0 ETH_MACL3L4C0R_L4SPM0_Msk /* Layer 4 Source Port Match Enable */
#define ETH_MACL3L4C0R_L4PEN0_Pos (16U)
#define ETH_MACL3L4C0R_L4PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L4PEN0_Pos) /*!< 0x00010000 */
#define ETH_MACL3L4C0R_L4PEN0 ETH_MACL3L4C0R_L4PEN0_Msk /* Layer 4 Protocol Enable */
#define ETH_MACL3L4C0R_L3HDBM0_Pos (11U)
#define ETH_MACL3L4C0R_L3HDBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HDBM0_Pos) /*!< 0x0000F800 */
#define ETH_MACL3L4C0R_L3HDBM0 ETH_MACL3L4C0R_L3HDBM0_Msk /* Layer 3 IP DA Higher Bits Match */
#define ETH_MACL3L4C0R_L3HSBM0_Pos (6U)
#define ETH_MACL3L4C0R_L3HSBM0_Msk (0x1FUL << ETH_MACL3L4C0R_L3HSBM0_Pos) /*!< 0x000007C0 */
#define ETH_MACL3L4C0R_L3HSBM0 ETH_MACL3L4C0R_L3HSBM0_Msk /* Layer 3 IP SA Higher Bits Match */
#define ETH_MACL3L4C0R_L3DAIM0_Pos (5U)
#define ETH_MACL3L4C0R_L3DAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAIM0_Pos) /*!< 0x00000020 */
#define ETH_MACL3L4C0R_L3DAIM0 ETH_MACL3L4C0R_L3DAIM0_Msk /* Layer 3 IP DA Inverse Match Enable */
#define ETH_MACL3L4C0R_L3DAM0_Pos (4U)
#define ETH_MACL3L4C0R_L3DAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3DAM0_Pos) /*!< 0x00000010 */
#define ETH_MACL3L4C0R_L3DAM0 ETH_MACL3L4C0R_L3DAM0_Msk /* Layer 3 IP DA Match Enable */
#define ETH_MACL3L4C0R_L3SAIM0_Pos (3U)
#define ETH_MACL3L4C0R_L3SAIM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAIM0_Pos) /*!< 0x00000008 */
#define ETH_MACL3L4C0R_L3SAIM0 ETH_MACL3L4C0R_L3SAIM0_Msk /* Layer 3 IP SA Inverse Match Enable */
#define ETH_MACL3L4C0R_L3SAM0_Pos (2U)
#define ETH_MACL3L4C0R_L3SAM0_Msk (0x1UL << ETH_MACL3L4C0R_L3SAM0_Pos) /*!< 0x00000004 */
#define ETH_MACL3L4C0R_L3SAM0 ETH_MACL3L4C0R_L3SAM0_Msk /* Layer 3 IP SA Match Enable*/
#define ETH_MACL3L4C0R_L3PEN0_Pos (0U)
#define ETH_MACL3L4C0R_L3PEN0_Msk (0x1UL << ETH_MACL3L4C0R_L3PEN0_Pos) /*!< 0x00000001 */
#define ETH_MACL3L4C0R_L3PEN0 ETH_MACL3L4C0R_L3PEN0_Msk /* Layer 3 Protocol Enable */
/************ Bit definition for Ethernet MAC Layer4 Address filter Register ***************/
#define ETH_MACL4A0R_L4DP0_Pos (16U)
#define ETH_MACL4A0R_L4DP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4DP0_Pos) /*!< 0xFFFF0000 */
#define ETH_MACL4A0R_L4DP0 ETH_MACL4A0R_L4DP0_Msk /* Layer 4 Destination Port Number Field */
#define ETH_MACL4A0R_L4SP0_Pos (0U)
#define ETH_MACL4A0R_L4SP0_Msk (0xFFFFUL << ETH_MACL4A0R_L4SP0_Pos) /*!< 0x0000FFFF */
#define ETH_MACL4A0R_L4SP0 ETH_MACL4A0R_L4SP0_Msk /* Layer 4 Source Port Number Field */
/************ Bit definition for Ethernet MAC Layer3 Address 0 Register ***************/
#define ETH_MACL3A0R_L3A0_Pos (0U)
#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
/************ Bit definition for Ethernet MAC Layer3 Address 1 Register ***************/
#define ETH_MACL3A1R_L3A1_Pos (0U)
#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
/************ Bit definition for Ethernet MAC Layer3 Address 2 Register ***************/
#define ETH_MACL3A2R_L3A2_Pos (0U)
#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
/************ Bit definition for Ethernet MAC Layer3 Address 3 Register ***************/
#define ETH_MACL3A3R_L3A3_Pos (0U)
#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
/************ Bit definition for Ethernet MAC Indirect Access Control Register ***************/
#define ETH_MACIACR_MSEL_Pos (16U)
#define ETH_MACIACR_MSEL_Msk (0xFUL << ETH_MACIACR_MSEL_Pos) /*!< 0x000F0000 */
#define ETH_MACIACR_MSEL ETH_MACIACR_MSEL_Msk /* Mode Select */
#define ETH_MACIACR_MSEL_RXQ ((uint32_t)0x00000000) /* Type-based RXQ mapping */
#define ETH_MACIACR_AOFF_Pos (8U)
#define ETH_MACIACR_AOFF_Msk (0xFFUL << ETH_MACIACR_AOFF_Pos) /*!< 0x0000FF00 */
#define ETH_MACIACR_AOFF ETH_MACIACR_AOFF_Msk /* Address Offset */
#define ETH_MACIACR_AOFF_IndReg0 ((uint32_t)0x00000000) /* Indirect register 0 */
#define ETH_MACIACR_AOFF_IndReg1_Pos (8U)
#define ETH_MACIACR_AOFF_IndReg1_Msk (0x1UL << ETH_MACIACR_AOFF_IndReg1_Pos) /*!< 0x00000100 */
#define ETH_MACIACR_AOFF_IndReg1 ETH_MACIACR_AOFF_IndReg1_Msk /* Indirect register 1 */
#define ETH_MACIACR_AOFF_IndReg2_Pos (9U)
#define ETH_MACIACR_AOFF_IndReg2_Msk (0x1UL << ETH_MACIACR_AOFF_IndReg2_Pos) /*!< 0x00000200 */
#define ETH_MACIACR_AOFF_IndReg2 ETH_MACIACR_AOFF_IndReg2_Msk /* Indirect register 2 */
#define ETH_MACIACR_AOFF_IndReg3_Pos (8U)
#define ETH_MACIACR_AOFF_IndReg3_Msk (0x3UL << ETH_MACIACR_AOFF_IndReg3_Pos) /*!< 0x00000300 */
#define ETH_MACIACR_AOFF_IndReg3 ETH_MACIACR_AOFF_IndReg3_Msk /* Indirect register 3 */
#define ETH_MACIACR_AOFF_IndReg4_Pos (10U)
#define ETH_MACIACR_AOFF_IndReg4_Msk (0x1UL << ETH_MACIACR_AOFF_IndReg4_Pos) /*!< 0x00000400 */
#define ETH_MACIACR_AOFF_IndReg4 ETH_MACIACR_AOFF_IndReg4_Msk /* Indirect register 4 */
#define ETH_MACIACR_AOFF_IndReg5_Pos (8U)
#define ETH_MACIACR_AOFF_IndReg5_Msk (0x5UL << ETH_MACIACR_AOFF_IndReg5_Pos) /*!< 0x00000500 */
#define ETH_MACIACR_AOFF_IndReg5 ETH_MACIACR_AOFF_IndReg5_Msk /* Indirect register 5 */
#define ETH_MACIACR_AOFF_IndReg6_Pos (9U)
#define ETH_MACIACR_AOFF_IndReg6_Msk (0x3UL << ETH_MACIACR_AOFF_IndReg6_Pos) /*!< 0x00000600 */
#define ETH_MACIACR_AOFF_IndReg6 ETH_MACIACR_AOFF_IndReg6_Msk /* Indirect register 6 */
#define ETH_MACIACR_AOFF_IndReg7_Pos (8U)
#define ETH_MACIACR_AOFF_IndReg7_Msk (0x7UL << ETH_MACIACR_AOFF_IndReg7_Pos) /*!< 0x00000700 */
#define ETH_MACIACR_AOFF_IndReg7 ETH_MACIACR_AOFF_IndReg7_Msk /* Indirect register 7 */
#define ETH_MACIACR_AUTO_Pos (5U)
#define ETH_MACIACR_AUTO_Msk (0x1UL << ETH_MACIACR_AUTO_Pos) /*!< 0x00000020 */
#define ETH_MACIACR_AUTO ETH_MACIACR_AUTO_Msk /* Auto-increment */
#define ETH_MACIACR_COM_Pos (1U)
#define ETH_MACIACR_COM_Msk (0x1UL << ETH_MACIACR_COM_Pos) /*!< 0x00000002 */
#define ETH_MACIACR_COM ETH_MACIACR_COM_Msk /* Command type: 1: read operation / 0: write operation */
#define ETH_MACIACR_OB_Pos (0U)
#define ETH_MACIACR_OB_Msk (0x1UL << ETH_MACIACR_OB_Pos) /*!< 0x00000001 */
#define ETH_MACIACR_OB ETH_MACIACR_OB_Msk /* Operation Busy */
/************ Bit definition for Ethernet MAC type-based Rx Queue mapping Register ***************/
#define ETH_MACTMRQR_PFEX_Pos (20U)
#define ETH_MACTMRQR_PFEX_Msk (0x1UL << ETH_MACTMRQR_PFEX_Pos) /*!< 0x00100000 */
#define ETH_MACTMRQR_PFEX ETH_MACTMRQR_PFEX_Msk /* Preemption or Express Packet */
#define ETH_MACTMRQR_TMRQ_Pos (16U)
#define ETH_MACTMRQR_TMRQ_Msk (0x7UL << ETH_MACTMRQR_TMRQ_Pos) /*!< 0x00070000 */
#define ETH_MACTMRQR_TMRQ ETH_MACTMRQR_TMRQ_Msk /* Type Match Rx Queue Number */
#define ETH_MACTMRQR_TYP_Pos (0U)
#define ETH_MACTMRQR_TYP_Msk (0xFFFFUL << ETH_MACTMRQR_TYP_Pos) /*!< 0x0000FFFF */
#define ETH_MACTMRQR_TYP ETH_MACTMRQR_TYP_Msk /* Type field Value */
/************ Bit definition for Ethernet MAC Timestamp Control Register ***************/
#define ETH_MACTSCR_AV8021ASMEN_Pos (28U)
#define ETH_MACTSCR_AV8021ASMEN_Msk (0x1UL << ETH_MACTSCR_AV8021ASMEN_Pos) /*!< 0x10000000 */
#define ETH_MACTSCR_AV8021ASMEN ETH_MACTSCR_AV8021ASMEN_Msk /* AV 802.1AS Mode Enable */
#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
#define ETH_MACTSCR_ESTI_Pos (20U)
#define ETH_MACTSCR_ESTI_Msk (0x1UL << ETH_MACTSCR_ESTI_Pos) /*!< 0x00100000 */
#define ETH_MACTSCR_ESTI ETH_MACTSCR_ESTI_Msk /* External System Time Input */
#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
#define ETH_MACTSCR_TSIPENA_Pos (11U)
#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
#define ETH_MACTSCR_TSENALL_Pos (8U)
#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
#define ETH_MACTSCR_PTGE_Pos (6U)
#define ETH_MACTSCR_PTGE_Msk (0x1UL << ETH_MACTSCR_PTGE_Pos) /*!< 0x00000040 */
#define ETH_MACTSCR_PTGE ETH_MACTSCR_PTGE_Msk /* Presentation Time Generation Enable */
#define ETH_MACTSCR_TSADDREG_Pos (5U)
#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
#define ETH_MACTSCR_TSUPDT_Pos (3U)
#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
#define ETH_MACTSCR_TSINIT_Pos (2U)
#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
#define ETH_MACTSCR_TSENA_Pos (0U)
#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
/************ Bit definition for Ethernet MAC Sub-second Increment Register ***************/
#define ETH_MACMACSSIR_SSINC_Pos (16U)
#define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
#define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
/************ Bit definition for Ethernet MAC System Time Seconds Register ***************/
#define ETH_MACSTSR_TSS_Pos (0U)
#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
/************ Bit definition for Ethernet MAC System Time Nanoseconds Register ***************/
#define ETH_MACSTNR_TSSS_Pos (0U)
#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
/************ Bit definition for Ethernet MAC System Time Seconds Update Register ***************/
#define ETH_MACSTSUR_TSS_Pos (0U)
#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
/************ Bit definition for Ethernet MAC System Time Nanoseconds Update Register ***************/
#define ETH_MACSTNUR_ADDSUB_Pos (31U)
#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
#define ETH_MACSTNUR_TSSS_Pos (0U)
#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
/************ Bit definition for Ethernet MAC Timestamp Addend Register ***************/
#define ETH_MACTSAR_TSAR_Pos (0U)
#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
/************ Bit definition for Ethernet MAC Timestamp Status Register ***************/
#define ETH_MACTSSR_ATSNS_Pos (25U)
#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
#define ETH_MACTSSR_ATSSTM_Pos (24U)
#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
#define ETH_MACTSSR_ATSSTN_Pos (16U)
#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
#define ETH_MACTSSR_TXTSSIS_Pos (15U)
#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
#define ETH_MACTSSR_TSTRGTERR1_Pos (5U)
#define ETH_MACTSSR_TSTRGTERR1_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR1_Pos) /*!< 0x00000020 */
#define ETH_MACTSSR_TSTRGTERR1 ETH_MACTSSR_TSTRGTERR1_Msk /* Timestamp Target Time Error */
#define ETH_MACTSSR_TSTARGT1_Pos (4U)
#define ETH_MACTSSR_TSTARGT1_Msk (0x1UL << ETH_MACTSSR_TSTARGT1_Pos) /*!< 0x00000010 */
#define ETH_MACTSSR_TSTARGT1 ETH_MACTSSR_TSTARGT1_Msk /* Timestamp Target Time Reached */
#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
#define ETH_MACTSSR_TSTARGT0_Pos (1U)
#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
#define ETH_MACTSSR_TSSOVF_Pos (0U)
#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
/************ Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register ***************/
#define ETH_MACTXTSSNR_TXTSSMIS_Pos (31U)
#define ETH_MACTXTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTXTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
#define ETH_MACTXTSSNR_TXTSSMIS ETH_MACTXTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
#define ETH_MACTXTSSNR_TXTSSLO_Pos (0U)
#define ETH_MACTXTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTXTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACTXTSSNR_TXTSSLO ETH_MACTXTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
/************ Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register ***************/
#define ETH_MACTXTSSSR_TXTSSHI_Pos (0U)
#define ETH_MACTXTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTXTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTXTSSSR_TXTSSHI ETH_MACTXTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
/************ Bit definition for Ethernet MAC Auxiliary Control Register ***************/
#define ETH_MACACR_ATSEN3_Pos (7U)
#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
#define ETH_MACACR_ATSEN2_Pos (6U)
#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
#define ETH_MACACR_ATSEN1_Pos (5U)
#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
#define ETH_MACACR_ATSEN0_Pos (4U)
#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
#define ETH_MACACR_ATSFC_Pos (0U)
#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
/************ Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register ***************/
#define ETH_MACATSNR_AUXTSLO_Pos (0U)
#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
/************ Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register ***************/
#define ETH_MACATSSR_AUXTSHI_Pos (0U)
#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
/************ Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register ***************/
#define ETH_MACTSIACR_OSTIAC_Pos (0U)
#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
/************ Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction ***************/
#define ETH_MACTSEACR_OSTEAC_Pos (0U)
#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
/************ Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond ***************/
#define ETH_MACTSICNR_TSIC_Pos (0U)
#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
/************ Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond ***************/
#define ETH_MACTSECNR_TSEC_Pos (0U)
#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
/************ Bit definition for Ethernet MAC Timestamp Ingress Latency ***************/
#define ETH_MACTSILR_ITLNS_Pos (16U)
#define ETH_MACTSILR_ITLNS_Msk (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
#define ETH_MACTSILR_ITLNS ETH_MACTSILR_ITLNS_Msk /* Ingress Timestamp Latency, in nanoseconds */
#define ETH_MACTSILR_ITLSNS_Pos (8U)
#define ETH_MACTSILR_ITLSNS_Msk (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
#define ETH_MACTSILR_ITLSNS ETH_MACTSILR_ITLSNS_Msk /* Ingress Timestamp Latency, in subnanoseconds */
/************ Bit definition for Ethernet MAC Timestamp Egress Latency Register ***************/
#define ETH_MACTSELR_ETLNS_Pos (16U)
#define ETH_MACTSELR_ETLNS_Msk (0xFFFUL << ETH_MACTSILR_ITLNS_Pos) /*!< 0x0FFF0000 */
#define ETH_MACTSELR_ETLNS ETH_MACTSILR_ITLNS_Msk /* Egress Timestamp Latency, in nanoseconds */
#define ETH_MACTSELR_ETLSNS_Pos (8U)
#define ETH_MACTSELR_ETLSNS_Msk (0xFFUL << ETH_MACTSILR_ITLSNS_Pos) /*!< 0x0000FF00 */
#define ETH_MACTSELR_ETLSNS ETH_MACTSILR_ITLSNS_Msk /* Egress Timestamp Latency, in subnanoseconds */
/************ Bit definition for Ethernet MAC PPS Control Register ***************/
#define ETH_MACPPSCR_TIMESEL_Pos (28U)
#define ETH_MACPPSCR_TIMESEL_Msk (0x1UL << ETH_MACPPSCR_TIMESEL_Pos) /*!< 0x10000000 */
#define ETH_MACPPSCR_TIMESEL ETH_MACPPSCR_TIMESEL_Msk /* Time Select */
#define ETH_MACPPSCR_MCGREN0_Pos (7U)
#define ETH_MACPPSCR_MCGREN0_Msk (0x1UL << ETH_MACPPSCR_MCGREN0_Pos) /*!< 0x00000080 */
#define ETH_MACPPSCR_MCGREN0 ETH_MACPPSCR_MCGREN0_Msk /* MCGR Mode Enable for PPS0 Output */
#define ETH_MACPPSCR_MCGREN0_PPS ((uint32_t)0x00000000) /* PPS mode */
#define ETH_MACPPSCR_MCGREN0_MCGR_Pos (7U)
#define ETH_MACPPSCR_MCGREN0_MCGR_Msk (0x1UL << ETH_MACPPSCR_MCGREN0_MCGR_Pos) /*!< 0x00000080 */
#define ETH_MACPPSCR_MCGREN0_MCGR ETH_MACPPSCR_MCGREN0_MCGR_Msk /* MCGR mode */
#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
#define ETH_MACPPSCR_PPSEN0_Pos (4U)
#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
/************ Bit definition for Ethernet MAC PPS x target time seconds Register ***************/
#define ETH_MACPPSTTSxR_TSTRH0_Pos (0U)
#define ETH_MACPPSTTSxR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSxR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSTTSxR_TSTRH0 ETH_MACPPSTTSxR_TSTRH0_Msk /* PPS Target Time Seconds Register */
/************ Bit definition for Ethernet MAC PPS x target time nanoseconds Register ***************/
#define ETH_MACPPSTTNxR_TRGTBUSY0_Pos (31U)
#define ETH_MACPPSTTNxR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNxR_TRGTBUSY0_Pos) /*!< 0x80000000 */
#define ETH_MACPPSTTNxR_TRGTBUSY0 ETH_MACPPSTTNxR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
#define ETH_MACPPSTTNxR_TTSL0_Pos (0U)
#define ETH_MACPPSTTNxR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNxR_TTSL0_Pos) /*!< 0x7FFFFFFF */
#define ETH_MACPPSTTNxR_TTSL0 ETH_MACPPSTTNxR_TTSL0_Msk /* Target Time Low for PPS Register */
/************ Bit definition for Ethernet MAC PPS x Interval Register ***************/
#define ETH_MACPPSIxR_PPSINT0_Pos (0U)
#define ETH_MACPPSIxR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIxR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSIxR_PPSINT0 ETH_MACPPSIxR_PPSINT0_Msk /* PPS Output Signal Interval */
/************ Bit definition for Ethernet MAC PPS x Width Register ***************/
#define ETH_MACPPSWxR_PPSWIDTH0_Pos (0U)
#define ETH_MACPPSWxR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWxR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACPPSWxR_PPSWIDTH0 ETH_MACPPSWxR_PPSWIDTH0_Msk /* PPS Output Signal Width */
/************ Bit definition for Ethernet MAC PTP Offload Control Register ***************/
#define ETH_MACPOCR_DN_Pos (8U)
#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
#define ETH_MACPOCR_PDRDIS_Pos (7U)
#define ETH_MACPOCR_PDRDIS_Msk (0x1UL << ETH_MACPOCR_PDRDIS_Pos) /*!< 0x00000080 */
#define ETH_MACPOCR_PDRDIS ETH_MACPOCR_PDRDIS_Msk /* Disable Peer Delay Response response generation */
#define ETH_MACPOCR_DRRDIS_Pos (6U)
#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
#define ETH_MACPOCR_APDREQEN_Pos (2U)
#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
#define ETH_MACPOCR_ASYNCEN_Pos (1U)
#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
#define ETH_MACPOCR_PTOEN_Pos (0U)
#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
/************ Bit definition for Ethernet MAC PTP Source Port Identity 0 Register ***************/
#define ETH_MACSPI0R_SPI0_Pos (0U)
#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
/************ Bit definition for Ethernet MAC PTP Source Port Identity 1 Register ***************/
#define ETH_MACSPI1R_SPI1_Pos (0U)
#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
/************ Bit definition for Ethernet MAC PTP Source Port Identity 2 Register ***************/
#define ETH_MACSPI2R_SPI2_Pos (0U)
#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
/************ Bit definition for Ethernet MAC Log Message Interval Register ***************/
#define ETH_MACLMIR_LMPDRI_Pos (24U)
#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
#define ETH_MACLMIR_DRSYNCR_Pos (8U)
#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
#define ETH_MACLMIR_LSI_Pos (0U)
#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
/************ Bit definition for Ethernet MTL Operation Mode Register ***************/
#define ETH_MTLOMR_CNTCLR_Pos (9U)
#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
#define ETH_MTLOMR_CNTPRST_Pos (8U)
#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
#define ETH_MTLOMR_SCHALG_Pos (5U)
#define ETH_MTLOMR_SCHALG_Msk (0x3UL << ETH_MTLOMR_SCHALG_Pos) /*!< 0x00000020 */
#define ETH_MTLOMR_SCHALG ETH_MTLOMR_SCHALG_Msk /* Tx Scheduling Algorithm */
#define ETH_MTLOMR_SCHALG_WRR ((uint32_t)0x00000000) /* Weighted round robin (WRR) algorithm */
#define ETH_MTLOMR_SCHALG_SP_Pos (5U)
#define ETH_MTLOMR_SCHALG_SP_Msk (0x3UL << ETH_MTLOMR_SCHALG_SP_Pos) /*!< 0x00000020 */
#define ETH_MTLOMR_SCHALG_SP ETH_MTLOMR_SCHALG_SP_Msk /* Strict priority (SP) algorithm */
#define ETH_MTLOMR_RAA_Pos (2U)
#define ETH_MTLOMR_RAA_Msk (0x1UL << ETH_MTLOMR_RAA_Pos) /*!< 0x00000004 */
#define ETH_MTLOMR_RAA ETH_MTLOMR_RAA_Msk /* Tx Scheduling Algorithm */
#define ETH_MTLOMR_RAA_SP ((uint32_t)0x00000000) /* Strict priority (SP). Queue 0 has the lowest priority and the last queue has the highest */
#define ETH_MTLOMR_RAA_WSP_Pos (2U)
#define ETH_MTLOMR_RAA_WSP_Msk (0x1UL << ETH_MTLOMR_RAA_WSP_Pos) /*!< 0x00000004 */
#define ETH_MTLOMR_RAA_WSP ETH_MTLOMR_RAA_WSP_Msk /* Weighted Strict priority (WSP) */
#define ETH_MTLOMR_DTXSTS_Pos (1U)
#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
/************ Bit definition for Ethernet MTL Interrupt Status Register ***************/
#define ETH_MTLISR_ESTIS_Pos (18U)
#define ETH_MTLISR_ESTIS_Msk (0x1UL << ETH_MTLISR_ESTIS_Pos) /*!< 0x00040000 */
#define ETH_MTLISR_ESTIS ETH_MTLISR_ESTIS_Msk /* EST (TAS- 802.1Qbv) Interrupt Status */
#define ETH_MTLISR_Q1IS_Pos (1U)
#define ETH_MTLISR_Q1IS_Msk (0x1UL << ETH_MTLISR_Q1IS_Pos) /*!< 0x00000002 */
#define ETH_MTLISR_Q1IS ETH_MTLISR_Q1IS_Msk /* Queue 1 Interrupt status */
#define ETH_MTLISR_Q0IS_Pos (0U)
#define ETH_MTLISR_Q0IS_Msk (0x1UL << ETH_MTLISR_Q0IS_Pos) /*!< 0x00000001 */
#define ETH_MTLISR_Q0IS ETH_MTLISR_Q0IS_Msk /* Queue 0 Interrupt status */
/************ Bit definition for Ethernet MTL Rx Queue and DMA Channel Mapping ***************/
#define ETH_MTLRXQDMAMR_Q1DDMACH_Pos (12U)
#define ETH_MTLRXQDMAMR_Q1DDMACH_Msk (0x1UL << ETH_MTLRXQDMAMR_Q1DDMACH_Pos) /*!< 0x00001000 */
#define ETH_MTLRXQDMAMR_Q1DDMACH ETH_MTLRXQDMAMR_Q1DDMACH_Msk /* Queue 1 Enabled for DA-based DMA Channel Selection */
#define ETH_MTLRXQDMAMR_Q1MDMACH_Pos (8U)
#define ETH_MTLRXQDMAMR_Q1MDMACH_Msk (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_Pos) /*!< 0x00000100 */
#define ETH_MTLRXQDMAMR_Q1MDMACH ETH_MTLRXQDMAMR_Q1MDMACH_Msk /* Queue 1 Mapped to DMA Channel */
#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH0 ((uint32_t)0x00000000) /* DMA Channel 0 */
#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos (8U)
#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk (0x1UL << ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Pos) /*!< 0x00000100 */
#define ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1 ETH_MTLRXQDMAMR_Q1MDMACH_DMACH1_Msk /* DMA Channel 1 */
#define ETH_MTLRXQDMAMR_Q0DDMACH_Pos (4U)
#define ETH_MTLRXQDMAMR_Q0DDMACH_Msk (0x1UL << ETH_MTLRXQDMAMR_Q0DDMACH_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQDMAMR_Q0DDMACH ETH_MTLRXQDMAMR_Q0DDMACH_Msk /* Queue 0 Enabled for DA-based DMA Channel Selection */
#define ETH_MTLRXQDMAMR_Q0MDMACH_Pos (0U)
#define ETH_MTLRXQDMAMR_Q0MDMACH_Msk (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQDMAMR_Q0MDMACH ETH_MTLRXQDMAMR_Q0MDMACH_Msk /* Queue 0 Mapped to DMA Channel */
#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH0 ((uint32_t)0x00000000) /* DMA Channel 0 */
#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos (0U)
#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk (0x1UL << ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1 ETH_MTLRXQDMAMR_Q0MDMACH_DMACH1_Msk /* DMA Channel 1 */
/************ Bit definition for Ethernet MTL TBS control Register ***************/
#define ETH_MTLTBSCR_LEOS_Pos (8U)
#define ETH_MTLTBSCR_LEOS_Msk (0xFFFFFFUL << ETH_MTLTBSCR_LEOS_Pos) /*!< 0xFFFFFF00 */
#define ETH_MTLTBSCR_LEOS ETH_MTLTBSCR_LEOS_Msk /* Launch Expiry Offset */
#define ETH_MTLTBSCR_LEGOS_Pos (4U)
#define ETH_MTLTBSCR_LEGOS_Msk (0x7UL << ETH_MTLTBSCR_LEGOS_Pos) /*!< 0xFFFFFF00 */
#define ETH_MTLTBSCR_LEGOS ETH_MTLTBSCR_LEGOS_Msk /* Launch Expiry GSN Offset */
#define ETH_MTLTBSCR_LEOV_Pos (1U)
#define ETH_MTLTBSCR_LEOV_Msk (0x1UL << ETH_MTLTBSCR_LEOV_Pos) /*!< 0x00000002 */
#define ETH_MTLTBSCR_LEOV ETH_MTLTBSCR_LEOV_Msk /* Launch expiry offset valid */
#define ETH_MTLTBSCR_ESTM_Pos (0U)
#define ETH_MTLTBSCR_ESTM_Msk (0x1UL << ETH_MTLTBSCR_ESTM_Pos) /*!< 0x00000001 */
#define ETH_MTLTBSCR_ESTM ETH_MTLTBSCR_ESTM_Msk /* EST offset mode */
#define ETH_MTLTBSCR_ESTM_ESTOFFDIS ((uint32_t)0x00000000) /* EST offset mode disabled */
#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos (0U)
#define ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk (0x1UL << ETH_MTLTBSCR_ESTM_ESTOFFEN_Pos) /*!< 0x00000001 */
#define ETH_MTLTBSCR_ESTM_ESTOFFEN ETH_MTLTBSCR_ESTM_ESTOFFEN_Msk /* EST offset mode enabled */
/************ Bit definition for Ethernet MTL EST Control Register ***************/
#define ETH_MTLESTCR_PTOV_Pos (24U)
#define ETH_MTLESTCR_PTOV_Msk (0xFFFFFFUL << ETH_MTLESTCR_PTOV_Pos) /*!< 0xFF000000 */
#define ETH_MTLESTCR_PTOV ETH_MTLESTCR_PTOV_Msk /* PTP Time Offset Value */
#define ETH_MTLESTCR_CTOV_Pos (12U)
#define ETH_MTLESTCR_CTOV_Msk (0xFFFUL << ETH_MTLESTCR_CTOV_Pos) /*!< 0x00FFF000 */
#define ETH_MTLESTCR_CTOV ETH_MTLESTCR_CTOV_Msk /* Current Time Offset Value */
#define ETH_MTLESTCR_TILS_Pos (8U)
#define ETH_MTLESTCR_TILS_Msk (0x7UL << ETH_MTLESTCR_TILS_Pos) /*!< 0x00000700 */
#define ETH_MTLESTCR_TILS ETH_MTLESTCR_TILS_Msk /* Time Interval Left Shift Amount */
#define ETH_MTLESTCR_LCSE_Pos (6U)
#define ETH_MTLESTCR_LCSE_Msk (0x3UL << ETH_MTLESTCR_LCSE_Pos) /*!< 0x000000C0 */
#define ETH_MTLESTCR_LCSE ETH_MTLESTCR_LCSE_Msk /* Loop Count to report Scheduling Error */
#define ETH_MTLESTCR_LCSE_4IT ((uint32_t)0x00000000) /* 4 iterations */
#define ETH_MTLESTCR_LCSE_8IT_Pos (6U)
#define ETH_MTLESTCR_LCSE_8IT_Msk (0x1UL << ETH_MTLESTCR_LCSE_8IT_Pos) /*!< 0x00000040 */
#define ETH_MTLESTCR_LCSE_8IT ETH_MTLESTCR_LCSE_8IT_Msk /* 8 iterations */
#define ETH_MTLESTCR_LCSE_16IT_Pos (7U)
#define ETH_MTLESTCR_LCSE_16IT_Msk (0x1UL << ETH_MTLESTCR_LCSE_16IT_Pos) /*!< 0x00000080 */
#define ETH_MTLESTCR_LCSE_16IT ETH_MTLESTCR_LCSE_16IT_Msk /* 16 iterations */
#define ETH_MTLESTCR_LCSE_32IT_Pos (6U)
#define ETH_MTLESTCR_LCSE_32IT_Msk (0x3UL << ETH_MTLESTCR_LCSE_32IT_Pos) /*!< 0x000000C0 */
#define ETH_MTLESTCR_LCSE_32IT ETH_MTLESTCR_LCSE_32IT_Msk /* 32 iterations */
#define ETH_MTLESTCR_DFBS_Pos (5U)
#define ETH_MTLESTCR_DFBS_Msk (0x1UL << ETH_MTLESTCR_DFBS_Pos) /*!< 0x00000020 */
#define ETH_MTLESTCR_DFBS ETH_MTLESTCR_DFBS_Msk /* Drop Frames causing Scheduling Error */
#define ETH_MTLESTCR_DDBF_Pos (4U)
#define ETH_MTLESTCR_DDBF_Msk (0x1UL << ETH_MTLESTCR_DDBF_Pos) /*!< 0x00000010 */
#define ETH_MTLESTCR_DDBF ETH_MTLESTCR_DDBF_Msk /* Do not Drop frames during Frame Size Error */
#define ETH_MTLESTCR_SSWL_Pos (1U)
#define ETH_MTLESTCR_SSWL_Msk (0x1UL << ETH_MTLESTCR_SSWL_Pos) /*!< 0x00000002 */
#define ETH_MTLESTCR_SSWL ETH_MTLESTCR_SSWL_Msk /* Switch to S/W owned list */
#define ETH_MTLESTCR_EEST_Pos (0U)
#define ETH_MTLESTCR_EEST_Msk (0x1UL << ETH_MTLESTCR_EEST_Pos) /*!< 0x00000001 */
#define ETH_MTLESTCR_EEST ETH_MTLESTCR_EEST_Msk /* Enable EST */
/************ Bit definition for Ethernet MTL EST Extended Control Register ***************/
/* Bit definition for Ethernet MTL EST Extended Control Register */
#define ETH_MTLESTECR_OVHD_Pos (0U)
#define ETH_MTLESTECR_OVHD_Msk (0x3FUL << ETH_MTLESTECR_OVHD_Pos) /*!< 0x0000003F */
#define ETH_MTLESTECR_OVHD ETH_MTLESTECR_OVHD_Msk /* Overhead Bytes Value */
/************ Bit definition for Ethernet MTL EST Status Register ***************/
#define ETH_MTLESTSR_CGSN_Pos (16U)
#define ETH_MTLESTSR_CGSN_Msk (0xFUL << ETH_MTLESTSR_CGSN_Pos) /*!< 0x000F0000 */
#define ETH_MTLESTSR_CGSN ETH_MTLESTSR_CGSN_Msk /* Current GCL slot number */
#define ETH_MTLESTSR_BTRL_Pos (8U)
#define ETH_MTLESTSR_BTRL_Msk (0xFFUL << ETH_MTLESTSR_BTRL_Pos) /*!< 0x00000F00 */
#define ETH_MTLESTSR_BTRL ETH_MTLESTSR_CGSN_Msk /* BTR Error Loop Count */
#define ETH_MTLESTSR_SWOL_Pos (7U)
#define ETH_MTLESTSR_SWOL_Msk (0x1UL << ETH_MTLESTSR_SWOL_Pos) /*!< 0x00000080 */
#define ETH_MTLESTSR_SWOL ETH_MTLESTSR_SWOL_Msk /* S/W owned list */
#define ETH_MTLESTSR_CGCE_Pos (4U)
#define ETH_MTLESTSR_CGCE_Msk (0x1UL << ETH_MTLESTSR_CGCE_Pos) /*!< 0x00000010 */
#define ETH_MTLESTSR_CGCE ETH_MTLESTSR_CGCE_Msk /* Constant Gate Control Error */
#define ETH_MTLESTSR_HLBS_Pos (3U)
#define ETH_MTLESTSR_HLBS_Msk (0x1UL << ETH_MTLESTSR_HLBS_Pos) /*!< 0x00000008 */
#define ETH_MTLESTSR_HLBS ETH_MTLESTSR_HLBS_Msk /* Head-Of-Line Blocking due to Scheduling */
#define ETH_MTLESTSR_HLBF_Pos (2U)
#define ETH_MTLESTSR_HLBF_Msk (0x1UL << ETH_MTLESTSR_HLBF_Pos) /*!< 0x00000004 */
#define ETH_MTLESTSR_HLBF ETH_MTLESTSR_HLBF_Msk /* Head-Of-Line Blocking due to Frame Size */
#define ETH_MTLESTSR_BTRE_Pos (1U)
#define ETH_MTLESTSR_BTRE_Msk (0x1UL << ETH_MTLESTSR_BTRE_Pos) /*!< 0x00000002 */
#define ETH_MTLESTSR_BTRE ETH_MTLESTSR_BTRE_Msk /* BTR Error */
#define ETH_MTLESTSR_SWLC_Pos (0U)
#define ETH_MTLESTSR_SWLC_Msk (0x1UL << ETH_MTLESTSR_SWLC_Pos) /*!< 0x00000001 */
#define ETH_MTLESTSR_SWLC ETH_MTLESTSR_SWLC_Msk /* Switch to S/W owned list Complete */
/************ Bit definition for Ethernet MTL EST Schedule Error Register ***************/
/* Bit definition for Ethernet MTL EST Schedule Error Register */
#define ETH_MTLESTSCHER_SEQN_Pos (0U)
#define ETH_MTLESTSCHER_SEQN_Msk (0x3UL << ETH_MTLESTSCHER_SEQN_Pos) /*!< 0x00000003 */
#define ETH_MTLESTSCHER_SEQN ETH_MTLESTSCHER_SEQN_Msk /* Schedule Error Queue Number */
/************ Bit definition for Ethernet MTL EST Frame size Error Register ***************/
#define ETH_MTLESTFSER_FEQN_Pos (0U)
#define ETH_MTLESTFSER_FEQN_Msk (0x3UL << ETH_MTLESTFSER_FEQN_Pos) /*!< 0x00000003 */
#define ETH_MTLESTFSER_FEQN ETH_MTLESTFSER_FEQN_Msk /* Frame Size Error Queue Number */
/************ Bit definition for Ethernet MTL EST Frame size Capture Register ***************/
#define ETH_MTLESTFSCR_HBFQ_Pos (16U)
#define ETH_MTLESTFSCR_HBFQ_Msk (0x1UL << ETH_MTLESTFSCR_HBFQ_Pos) /*!< 0x00010000 */
#define ETH_MTLESTFSCR_HBFQ ETH_MTLESTFSCR_HBFQ_Msk /* Queue Number of HLBF */
#define ETH_MTLESTFSCR_HBFS_Pos (0U)
#define ETH_MTLESTFSCR_HBFS_Msk (0x7FFFUL << ETH_MTLESTFSCR_HBFS_Pos) /*!< 0x00007FFF */
#define ETH_MTLESTFSCR_HBFS ETH_MTLESTFSCR_HBFS_Msk /* Frame Size of HLBF */
/************ Bit definition for Ethernet MTL EST Interrupt Enable Register ***************/
/* Bit definition for Ethernet MTL EST Interrupt Enable Register */
#define ETH_MTLESTIER_CGCE_Pos (4U)
#define ETH_MTLESTIER_CGCE_Msk (0x1UL << ETH_MTLESTIER_CGCE_Pos) /*!< 0x00000010 */
#define ETH_MTLESTIER_CGCE ETH_MTLESTIER_CGCE_Msk /* Interrupt Enable for CGCE */
#define ETH_MTLESTIER_IEHS_Pos (3U)
#define ETH_MTLESTIER_IEHS_Msk (0x1UL << ETH_MTLESTIER_IEHS_Pos) /*!< 0x00000008 */
#define ETH_MTLESTIER_IEHS ETH_MTLESTIER_IEHS_Msk /* Interrupt Enable for HLBS */
#define ETH_MTLESTIER_IEHF_Pos (2U)
#define ETH_MTLESTIER_IEHF_Msk (0x1UL << ETH_MTLESTIER_IEHF_Pos) /*!< 0x00000004 */
#define ETH_MTLESTIER_IEHF ETH_MTLESTIER_IEHF_Msk /* Interrupt Enable for HLBF */
#define ETH_MTLESTIER_IEBE_Pos (1U)
#define ETH_MTLESTIER_IEBE_Msk (0x1UL << ETH_MTLESTIER_IEBE_Pos) /*!< 0x00000002 */
#define ETH_MTLESTIER_IEBE ETH_MTLESTIER_IEBE_Msk /* Interrupt Enable for BTR Error */
#define ETH_MTLESTIER_IECC_Pos (0U)
#define ETH_MTLESTIER_IECC_Msk (0x1UL << ETH_MTLESTIER_IECC_Pos) /*!< 0x00000001 */
#define ETH_MTLESTIER_IECC ETH_MTLESTIER_IECC_Msk /* Interrupt Enable for Switch List */
/************ Bit definition for Ethernet MTL EST Gate Control List Register ***************/
#define ETH_MTLESTGCLCR_ADDR_Pos (8U)
#define ETH_MTLESTGCLCR_ADDR_Msk (0x3FUL << ETH_MTLESTGCLCR_ADDR_Pos) /*!< 0x00003F00 */
#define ETH_MTLESTGCLCR_ADDR ETH_MTLESTGCLCR_ADDR_Msk /* Gate Control List Address */
#define ETH_MTLESTGCLCR_ADDR_BTRLOW ((uint32_t)0x00000000) /* BTR Low (31:0) */
#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos (8U)
#define ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk (0x1UL << ETH_MTLESTGCLCR_ADDR_BTRHIGH_Pos) /*!< 0x00000100 */
#define ETH_MTLESTGCLCR_ADDR_BTRHIGH ETH_MTLESTGCLCR_ADDR_BTRHIGH_Msk /* BTR High (63:31) */
#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos (9U)
#define ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk (0x1UL << ETH_MTLESTGCLCR_ADDR_CTRLOW_Pos) /*!< 0x00000200 */
#define ETH_MTLESTGCLCR_ADDR_CTRLOW ETH_MTLESTGCLCR_ADDR_CTRLOW_Msk /* CTR Low (31:0) */
#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos (8U)
#define ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk (0x3UL << ETH_MTLESTGCLCR_ADDR_CTRHIGH_Pos) /*!< 0x00000300 */
#define ETH_MTLESTGCLCR_ADDR_CTRHIGH ETH_MTLESTGCLCR_ADDR_CTRHIGH_Msk /* CTR High (39:32) */
#define ETH_MTLESTGCLCR_ADDR_TER_Pos (10U)
#define ETH_MTLESTGCLCR_ADDR_TER_Msk (0x1UL << ETH_MTLESTGCLCR_ADDR_TER_Pos) /*!< 0x00000400 */
#define ETH_MTLESTGCLCR_ADDR_TER ETH_MTLESTGCLCR_ADDR_TER_Msk /* TER (30:0) */
#define ETH_MTLESTGCLCR_ADDR_LLR_Pos (8U)
#define ETH_MTLESTGCLCR_ADDR_LLR_Msk (0x5UL << ETH_MTLESTGCLCR_ADDR_LLR_Pos) /*!< 0x00000500 */
#define ETH_MTLESTGCLCR_ADDR_LLR ETH_MTLESTGCLCR_ADDR_LLR_Msk /* LLR (6:0) */
#define ETH_MTLESTGCLCR_DBGB_Pos (5U)
#define ETH_MTLESTGCLCR_DBGB_Msk (0x1UL << ETH_MTLESTGCLCR_DBGB_Pos) /*!< 0x00000020 */
#define ETH_MTLESTGCLCR_DBGB ETH_MTLESTGCLCR_DBGB_Msk /* Debug Mode Bank Select */
#define ETH_MTLESTGCLCR_DBGM_Pos (4U)
#define ETH_MTLESTGCLCR_DBGM_Msk (0x1UL << ETH_MTLESTGCLCR_DBGM_Pos) /*!< 0x00000010 */
#define ETH_MTLESTGCLCR_DBGM ETH_MTLESTGCLCR_DBGM_Msk /* Debug Mode */
#define ETH_MTLESTGCLCR_GCRR_Pos (2U)
#define ETH_MTLESTGCLCR_GCRR_Msk (0x1UL << ETH_MTLESTGCLCR_GCRR_Pos) /*!< 0x00000004 */
#define ETH_MTLESTGCLCR_GCRR ETH_MTLESTGCLCR_GCRR_Msk /* Gate Control Related Registers */
#define ETH_MTLESTGCLCR_R1W0_Pos (1U)
#define ETH_MTLESTGCLCR_R1W0_Msk (0x1UL << ETH_MTLESTGCLCR_R1W0_Pos) /*!< 0x00000002 */
#define ETH_MTLESTGCLCR_R1W0 ETH_MTLESTGCLCR_R1W0_Msk /* Read 1, Write 0 */
#define ETH_MTLESTGCLCR_SRWO_Pos (0U)
#define ETH_MTLESTGCLCR_SRWO_Msk (0x1UL << ETH_MTLESTGCLCR_SRWO_Pos) /*!< 0x00000001 */
#define ETH_MTLESTGCLCR_SRWO ETH_MTLESTGCLCR_SRWO_Msk /* Start Read/Write Operation */
/************ Bit definition for Ethernet MTL EST Gate Control List Data Register ***************/
#define ETH_MTLESTGCLDR_GCD_Pos (0U)
#define ETH_MTLESTGCLDR_GCD_Msk (0xFFFFFFFFUL << ETH_MTLESTGCLDR_GCD_Pos) /*!< 0xFFFFFFFF */
#define ETH_MTLESTGCLDR_GCD ETH_MTLESTGCLDR_GCD_Msk /* Gate Control Data */
/************ Bit definition for Ethernet MTL FPE Frame Preemption Control Status Register ***************/
#define ETH_MTLFPECSR_HRS_Pos (28U)
#define ETH_MTLFPECSR_HRS_Msk (0x1UL << ETH_MTLFPECSR_HRS_Pos) /*!< 0x10000000 */
#define ETH_MTLFPECSR_HRS ETH_MTLFPECSR_HRS_Msk /* Hold/Release Status */
#define ETH_MTLFPECSR_PEC_Pos (8U)
#define ETH_MTLFPECSR_PEC_Msk (0x3UL << ETH_MTLFPECSR_PEC_Pos) /*!< 0x00000300 */
#define ETH_MTLFPECSR_PEC ETH_MTLFPECSR_PEC_Msk /* Preemption Classification */
#define ETH_MTLFPECSR_AFSZ_Pos (0U)
#define ETH_MTLFPECSR_AFSZ_Msk (0x3UL << ETH_MTLFPECSR_AFSZ_Pos) /*!< 0x00000003 */
#define ETH_MTLFPECSR_AFSZ ETH_MTLFPECSR_AFSZ_Msk /* Additional Fragment Size */
/************ Bit definition for Ethernet MTL FPE Frame Preemption Advance Register ***************/
#define ETH_MTLFPEAR_RADV_Pos (16U)
#define ETH_MTLFPEAR_RADV_Msk (0xFFFFUL << ETH_MTLFPEAR_RADV_Pos) /*!< 0xFFFF0000 */
#define ETH_MTLFPEAR_RADV ETH_MTLFPEAR_RADV_Msk /* Release Advance */
#define ETH_MTLFPEAR_HADV_Pos (0U)
#define ETH_MTLFPEAR_HADV_Msk (0xFFFFUL << ETH_MTLFPEAR_HADV_Pos) /*!< 0x0000FFFF */
#define ETH_MTLFPEAR_HADV ETH_MTLFPEAR_HADV_Msk /* Hold Advance */
/************ Bit definition for Ethernet MTL Tx queue x operating mode Register ***************/
#define ETH_MTLTXQxOMR_TQS_Pos (16U)
#define ETH_MTLTXQxOMR_TQS_Msk (0xFUL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x000F0000 */
#define ETH_MTLTXQxOMR_TQS ETH_MTLTXQxOMR_TQS_Msk /* Transmit queue size */
#define ETH_MTLTXQxOMR_TQS_0 (0x1UL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x00010000 */
#define ETH_MTLTXQxOMR_TQS_1 (0x2UL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x00020000 */
#define ETH_MTLTXQxOMR_TQS_2 (0x4UL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x00040000 */
#define ETH_MTLTXQxOMR_TQS_3 (0x8UL << ETH_MTLTXQxOMR_TQS_Pos) /*!< 0x00080000 */
#define ETH_MTLTXQxOMR_TTC_Pos (4U)
#define ETH_MTLTXQxOMR_TTC_Msk (0x7UL << ETH_MTLTXQxOMR_TTC_Pos) /*!< 0x00000070 */
#define ETH_MTLTXQxOMR_TTC ETH_MTLTXQxOMR_TTC_Msk /* Transmit Threshold Control */
#define ETH_MTLTXQxOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
#define ETH_MTLTXQxOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
#define ETH_MTLTXQxOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
#define ETH_MTLTXQxOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
#define ETH_MTLTXQxOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
#define ETH_MTLTXQxOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
#define ETH_MTLTXQxOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
#define ETH_MTLTXQxOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
#define ETH_MTLTXQxOMR_TXQEN_Pos (2U)
#define ETH_MTLTXQxOMR_TXQEN_Msk (0x3UL << ETH_MTLTXQxOMR_TXQEN_Pos) /*!< 0x0000000C */
#define ETH_MTLTXQxOMR_TXQEN ETH_MTLTXQxOMR_TXQEN_Msk /* Transmit Queue Enable */
#define ETH_MTLTXQxOMR_TXQEN_NOT ((uint32_t)0x00000000) /* Not enabled */
#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos (2U)
#define ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk (0x1UL << ETH_MTLTXQxOMR_TXQEN_AVMODE_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQxOMR_TXQEN_AVMODE ETH_MTLTXQxOMR_TXQEN_AVMODE_Msk /* Enable in AV mode */
#define ETH_MTLTXQxOMR_TXQEN_EN_Pos (3U)
#define ETH_MTLTXQxOMR_TXQEN_EN_Msk (0x1UL << ETH_MTLTXQxOMR_TXQEN_EN_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQxOMR_TXQEN_EN ETH_MTLTXQxOMR_TXQEN_EN_Msk /* Enabled */
#define ETH_MTLTXQxOMR_TSF_Pos (1U)
#define ETH_MTLTXQxOMR_TSF_Msk (0x1UL << ETH_MTLTXQxOMR_TSF_Pos) /*!< 0x00000002 */
#define ETH_MTLTXQxOMR_TSF ETH_MTLTXQxOMR_TSF_Msk /* Transmit Store and Forward */
#define ETH_MTLTXQxOMR_FTQ_Pos (0U)
#define ETH_MTLTXQxOMR_FTQ_Msk (0x1UL << ETH_MTLTXQxOMR_FTQ_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQxOMR_FTQ ETH_MTLTXQxOMR_FTQ_Msk /* Flush Transmit Queue */
/************ Bit definition for Ethernet MTL Tx Queue x Underflow Register ***************/
#define ETH_MTLTXQxUR_UFCNTOVF_Pos (11U)
#define ETH_MTLTXQxUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTXQxUR_UFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLTXQxUR_UFCNTOVF ETH_MTLTXQxUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
#define ETH_MTLTXQxUR_UFPKTCNT_Pos (0U)
#define ETH_MTLTXQxUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTXQxUR_UFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLTXQxUR_UFPKTCNT ETH_MTLTXQxUR_UFPKTCNT_Msk /* Underflow Packet Counter */
/************ Bit definition for Ethernet MTL Tx Queue x Debug Register ***************/
#define ETH_MTLTXQxDR_STXSTSF_Pos (20U)
#define ETH_MTLTXQxDR_STXSTSF_Msk (0x7UL << ETH_MTLTXQxDR_STXSTSF_Pos) /*!< 0x00700000 */
#define ETH_MTLTXQxDR_STXSTSF ETH_MTLTXQxDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
#define ETH_MTLTXQxDR_PTXQ_Pos (16U)
#define ETH_MTLTXQxDR_PTXQ_Msk (0x7UL << ETH_MTLTXQxDR_PTXQ_Pos) /*!< 0x00070000 */
#define ETH_MTLTXQxDR_PTXQ ETH_MTLTXQxDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
#define ETH_MTLTXQxDR_TXSTSFSTS_Pos (5U)
#define ETH_MTLTXQxDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTXQxDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQxDR_TXSTSFSTS ETH_MTLTXQxDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
#define ETH_MTLTXQxDR_TXQSTS_Pos (4U)
#define ETH_MTLTXQxDR_TXQSTS_Msk (0x1UL << ETH_MTLTXQxDR_TXQSTS_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQxDR_TXQSTS ETH_MTLTXQxDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
#define ETH_MTLTXQxDR_TWCSTS_Pos (3U)
#define ETH_MTLTXQxDR_TWCSTS_Msk (0x1UL << ETH_MTLTXQxDR_TWCSTS_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQxDR_TWCSTS ETH_MTLTXQxDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
#define ETH_MTLTXQxDR_TRCSTS_Pos (1U)
#define ETH_MTLTXQxDR_TRCSTS_Msk (0x3UL << ETH_MTLTXQxDR_TRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLTXQxDR_TRCSTS ETH_MTLTXQ0DR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
#define ETH_MTLTXQxDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
#define ETH_MTLTXQxDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
#define ETH_MTLTXQxDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
#define ETH_MTLTXQxDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
#define ETH_MTLTXQxDR_TXQPAUSED_Pos (0U)
#define ETH_MTLTXQxDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTXQxDR_TXQPAUSED_Pos) /*!< 0x00000001 */
#define ETH_MTLTXQxDR_TXQPAUSED ETH_MTLTXQxDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
/************ Bit definition for Ethernet MTL Tx queue x ETS status Register ***************/
#define ETH_MTLTXQxESR_ABS_Pos (0U)
#define ETH_MTLTXQxESR_ABS_Msk (0xFFFFFFUL << ETH_MTLTXQxESR_ABS_Pos) /*!< 0x00FFFFFF */
#define ETH_MTLTXQxESR_ABS ETH_MTLTXQxESR_ABS_Msk /* Average Bits per Slot */
/************ Bit definition for Ethernet MTL Tx queue 0 quantum weight Register ***************/
#define ETH_MTLTXQ0QWR_ISCQW_Pos (0U)
#define ETH_MTLTXQ0QWR_ISCQW_Msk (0x7FUL << ETH_MTLTXQ0QWR_ISCQW_Pos) /*!< 0x0000007F */
#define ETH_MTLTXQ0QWR_ISCQW ETH_MTLTXQ0QWR_ISCQW_Msk /* Weights */
/************ Bit definition for Ethernet MTL Queue x Interrupt Control Status Register ***************/
#define ETH_MTLQxICSR_RXOIE_Pos (24U)
#define ETH_MTLQxICSR_RXOIE_Msk (0x1UL << ETH_MTLQxICSR_RXOIE_Pos) /*!< 0x01000000 */
#define ETH_MTLQxICSR_RXOIE ETH_MTLQxICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
#define ETH_MTLQxICSR_RXOVFIS_Pos (16U)
#define ETH_MTLQxICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQxICSR_RXOVFIS_Pos) /*!< 0x00010000 */
#define ETH_MTLQxICSR_RXOVFIS ETH_MTLQxICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
#define ETH_MTLQxICSR_ABPSIE_Pos (9U)
#define ETH_MTLQxICSR_ABPSIE_Msk (0x1UL << ETH_MTLQxICSR_ABPSIE_Pos) /*!< 0x00000200 */
#define ETH_MTLQxICSR_ABPSIE ETH_MTLQxICSR_ABPSIE_Msk /* Average Bits Per Slot Interrupt Enable */
#define ETH_MTLQxICSR_TXUIE_Pos (8U)
#define ETH_MTLQxICSR_TXUIE_Msk (0x1UL << ETH_MTLQxICSR_TXUIE_Pos) /*!< 0x00000100 */
#define ETH_MTLQxICSR_TXUIE ETH_MTLQxICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
#define ETH_MTLQxICSR_ABPSIS_Pos (1U)
#define ETH_MTLQxICSR_ABPSIS_Msk (0x1UL << ETH_MTLQxICSR_ABPSIS_Pos) /*!< 0x00000002 */
#define ETH_MTLQxICSR_ABPSIS ETH_MTLQxICSR_ABPSIS_Msk /* Average Bits Per Slot Interrupt Status */
#define ETH_MTLQxICSR_TXUNFIS_Pos (0U)
#define ETH_MTLQxICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQxICSR_TXUNFIS_Pos) /*!< 0x00000001 */
#define ETH_MTLQxICSR_TXUNFIS ETH_MTLQxICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
/************ Bit definition for Ethernet MTL Rx Queue x Operation Mode Register ***************/
#define ETH_MTLRXQxOMR_RQS_Pos (20U)
#define ETH_MTLRXQxOMR_RQS_Msk (0xFUL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00F00000 */
#define ETH_MTLRXQxOMR_RQS ETH_MTLRXQxOMR_RQS_Msk /* Receive Queue Size */
#define ETH_MTLRXQxOMR_RQS_0 (0x1UL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00100000 */
#define ETH_MTLRXQxOMR_RQS_1 (0x2UL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00200000 */
#define ETH_MTLRXQxOMR_RQS_2 (0x4UL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00400000 */
#define ETH_MTLRXQxOMR_RQS_3 (0x8UL << ETH_MTLRXQxOMR_RQS_Pos) /*!< 0x00800000 */
#define ETH_MTLRXQxOMR_RFD_Pos (14U)
#define ETH_MTLRXQxOMR_RFD_Msk (0x7UL << ETH_MTLRXQxOMR_RFD_Pos) /*!< 0x0001C000 */
#define ETH_MTLRXQxOMR_RFD ETH_MTLRXQxOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
#define ETH_MTLRXQxOMR_RFA_Pos (8U)
#define ETH_MTLRXQxOMR_RFA_Msk (0x7UL << ETH_MTLRXQ0OMR_RFA_Pos) /*!< 0x00000700 */
#define ETH_MTLRXQxOMR_RFA ETH_MTLRXQxOMR_RFA_Pos /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
#define ETH_MTLRXQxOMR_EHFC_Pos (7U)
#define ETH_MTLRXQxOMR_EHFC_Msk (0x1UL << ETH_MTLRXQxOMR_EHFC_Pos) /*!< 0x00000080 */
#define ETH_MTLRXQxOMR_EHFC ETH_MTLRXQxOMR_EHFC_Msk /* DEnable Hardware Flow Control */
#define ETH_MTLRXQxOMR_DISTCPEF_Pos (6U)
#define ETH_MTLRXQxOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRXQxOMR_DISTCPEF_Pos) /*!< 0x00000040 */
#define ETH_MTLRXQxOMR_DISTCPEF ETH_MTLRXQxOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
#define ETH_MTLRXQxOMR_RSF_Pos (5U)
#define ETH_MTLRXQxOMR_RSF_Msk (0x1UL << ETH_MTLRXQxOMR_RSF_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQxOMR_RSF ETH_MTLRXQxOMR_RSF_Msk /* Receive Queue Store and Forward */
#define ETH_MTLRXQxOMR_FEP_Pos (4U)
#define ETH_MTLRXQxOMR_FEP_Msk (0x1UL << ETH_MTLRXQxOMR_FEP_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQxOMR_FEP ETH_MTLRXQxOMR_FEP_Msk /* Forward Error Packets */
#define ETH_MTLRXQxOMR_FUP_Pos (3U)
#define ETH_MTLRXQxOMR_FUP_Msk (0x1UL << ETH_MTLRXQxOMR_FUP_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQxOMR_FUP ETH_MTLRXQxOMR_FUP_Msk /* Forward Undersized Good Packets */
#define ETH_MTLRXQxOMR_RTC_Pos (0U)
#define ETH_MTLRXQxOMR_RTC_Msk (0x3UL << ETH_MTLRXQxOMR_RTC_Pos) /*!< 0x00000003 */
#define ETH_MTLRXQxOMR_RTC ETH_MTLRXQxOMR_RTC_Msk /* Receive Queue Threshold Control */
#define ETH_MTLRXQxOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
#define ETH_MTLRXQxOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
#define ETH_MTLRXQxOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
#define ETH_MTLRXQxOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
/************ Bit definition for Ethernet MTL Rx Queue x Missed Packet Overflow Cnt Register ***************/
#define ETH_MTLRXQxMPOCR_MISCNTOVF_Pos (27U)
#define ETH_MTLRXQxMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRXQxMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
#define ETH_MTLRXQxMPOCR_MISCNTOVF ETH_MTLRXQxMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
#define ETH_MTLRXQxMPOCR_MISPKTCNT_Pos (16U)
#define ETH_MTLRXQxMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRXQxMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
#define ETH_MTLRXQxMPOCR_MISPKTCNT ETH_MTLRXQxMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos (11U)
#define ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRXQxMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
#define ETH_MTLRXQxMPOCR_OVFCNTOVF ETH_MTLRXQxMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos (0U)
#define ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRXQxMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
#define ETH_MTLRXQxMPOCR_OVFPKTCNT ETH_MTLRXQxMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
/************ Bit definition for Ethernet MTL Rx Queue x Debug Register ***************/
#define ETH_MTLRXQxDR_PRXQ_Pos (16U)
#define ETH_MTLRXQxDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRXQxDR_PRXQ_Pos) /*!< 0x3FFF0000 */
#define ETH_MTLRXQxDR_PRXQ ETH_MTLRXQxDR_PRXQ_Msk /* Number of Packets in Receive Queue */
#define ETH_MTLRXQxDR_RXQSTS_Pos (4U)
#define ETH_MTLRXQxDR_RXQSTS_Msk (0x3UL << ETH_MTLRXQxDR_RXQSTS_Pos) /*!< 0x00000030 */
#define ETH_MTLRXQxDR_RXQSTS ETH_MTLRXQxDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
#define ETH_MTLRXQxDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
#define ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRXQxDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
#define ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRXQxDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
#define ETH_MTLRXQxDR_RXQSTS_FULL_Pos (4U)
#define ETH_MTLRXQxDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRXQxDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
#define ETH_MTLRXQxDR_RXQSTS_FULL ETH_MTLRXQxDR_RXQSTS_FULL_Msk /* Rx Queue full */
#define ETH_MTLRXQxDR_RRCSTS_Pos (1U)
#define ETH_MTLRXQxDR_RRCSTS_Msk (0x3UL << ETH_MTLRXQxDR_RRCSTS_Pos) /*!< 0x00000006 */
#define ETH_MTLRXQxDR_RRCSTS ETH_MTLRXQxDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
#define ETH_MTLRXQxDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos (1U)
#define ETH_MTLRXQxDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
#define ETH_MTLRXQxDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos (2U)
#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
#define ETH_MTLRXQxDR_RRCSTS_READINGSTATUS ETH_MTLRXQxDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos (1U)
#define ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRXQxDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
#define ETH_MTLRXQxDR_RRCSTS_FLUSHING ETH_MTLRXQxDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
#define ETH_MTLRXQxDR_RWCSTS_Pos (0U)
#define ETH_MTLRXQxDR_RWCSTS_Msk (0x1UL << ETH_MTLRXQxDR_RWCSTS_Pos) /*!< 0x00000001 */
#define ETH_MTLRXQxDR_RWCSTS ETH_MTLRXQxDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
/************ Bit definition for Ethernet MTL Rx Queue x Control Register ***************/
#define ETH_MTLRXQxCR_RQPA_Pos (3U)
#define ETH_MTLRXQxCR_RQPA_Msk (0x1UL << ETH_MTLRXQxCR_RQPA_Pos) /*!< 0x00000008 */
#define ETH_MTLRXQxCR_RQPA ETH_MTLRXQxCR_RQPA_Msk /* Receive Queue Packet Arbitration */
#define ETH_MTLRXQxCR_RQW_Pos (0U)
#define ETH_MTLRXQxCR_RQW_Msk (0x7UL << ETH_MTLRXQxCR_RQW_Pos) /*!< 0x00000007 */
#define ETH_MTLRXQxCR_RQW ETH_MTLRXQxCR_RQW_Msk /* Receive Queue Weight */
/************ Bit definition for Ethernet MTL Tx queue 1 ETS control Register ***************/
#define ETH_MTLTXQ1ECR_SLC_Pos (4U)
#define ETH_MTLTXQ1ECR_SLC_Msk (0x7UL << ETH_MTLTXQ1ECR_SLC_Pos) /*!< 0x00000070 */
#define ETH_MTLTXQ1ECR_SLC ETH_MTLTXQ1ECR_SLC_Msk /* Slot Count */
#define ETH_MTLTXQ1ECR_SLC_1SLOT ((uint32_t)0x00000000) /* 1 Slot */
#define ETH_MTLTXQ1ECR_SLC_2SLOT_Pos (4U)
#define ETH_MTLTXQ1ECR_SLC_2SLOT_Msk (0x1UL << ETH_MTLTXQ1ECR_SLC_2SLOT_Pos) /*!< 0x00000010 */
#define ETH_MTLTXQ1ECR_SLC_2SLOT ETH_MTLTXQ1ECR_SLC_2SLOT_Msk /* 2 Slots */
#define ETH_MTLTXQ1ECR_SLC_4SLOT_Pos (5U)
#define ETH_MTLTXQ1ECR_SLC_4SLOT_Msk (0x1UL << ETH_MTLTXQ1ECR_SLC_4SLOT_Pos) /*!< 0x00000020 */
#define ETH_MTLTXQ1ECR_SLC_4SLOT ETH_MTLTXQ1ECR_SLC_4SLOT_Msk /* 4 Slots */
#define ETH_MTLTXQ1ECR_SLC_8SLOT_Pos (4U)
#define ETH_MTLTXQ1ECR_SLC_8SLOT_Msk (0x3UL << ETH_MTLTXQ1ECR_SLC_8SLOT_Pos) /*!< 0x00000030 */
#define ETH_MTLTXQ1ECR_SLC_8SLOT ETH_MTLTXQ1ECR_SLC_8SLOT_Msk /* 8 Slots */
#define ETH_MTLTXQ1ECR_SLC_16SLOT_Pos (6U)
#define ETH_MTLTXQ1ECR_SLC_16SLOT_Msk (0x1UL << ETH_MTLTXQ1ECR_SLC_16SLOT_Pos) /*!< 0x00000040 */
#define ETH_MTLTXQ1ECR_SLC_16SLOT ETH_MTLTXQ1ECR_SLC_16SLOT_Msk /* 16 Slots */
#define ETH_MTLTXQ1ECR_CC_Pos (3U)
#define ETH_MTLTXQ1ECR_CC_Msk (0x1UL << ETH_MTLTXQ1ECR_CC_Pos) /*!< 0x00000008 */
#define ETH_MTLTXQ1ECR_CC ETH_MTLTXQ1ECR_CC_Msk /* Credit Control */
#define ETH_MTLTXQ1ECR_AVALG_Pos (2U)
#define ETH_MTLTXQ1ECR_AVALG_Msk (0x1UL << ETH_MTLTXQ1ECR_AVALG_Pos) /*!< 0x00000004 */
#define ETH_MTLTXQ1ECR_AVALG ETH_MTLTXQ1ECR_AVALG_Msk /* Credit Control */
/************ Bit definition for Ethernet MTL Tx queue 1 quantum weight Register ***************/
#define ETH_MTLTXQ1QWR_ISCQW_Pos (0U)
#define ETH_MTLTXQ1QWR_ISCQW_Msk (0x3FFFUL << ETH_MTLTXQ1QWR_ISCQW_Pos) /*!< 0x00003FFF */
#define ETH_MTLTXQ1QWR_ISCQW ETH_MTLTXQ1QWR_ISCQW_Msk /* IdleSlopeCredit or Weights */
/************ Bit definition for Ethernet MTL Tx queue 1 send slope credit Register ***************/
#define ETH_MTLTXQ1SSCR_SSC_Pos (0U)
#define ETH_MTLTXQ1SSCR_SSC_Msk (0x3FFFUL << ETH_MTLTXQ1SSCR_SSC_Pos) /*!< 0x00003FFF */
#define ETH_MTLTXQ1SSCR_SSC ETH_MTLTXQ1SSCR_SSC_Msk /* sendSlopeCredit Value */
/************ Bit definition for Ethernet MTL Tx Queue 1 hiCredit Register ***************/
#define ETH_MTLTXQ1HCR_HC_Pos (0U)
#define ETH_MTLTXQ1HCR_HC_Msk (0x1FFFFFFFUL << ETH_MTLTXQ1HCR_HC_Pos) /*!< 0x1FFFFFFF */
#define ETH_MTLTXQ1HCR_HC ETH_MTLTXQ1HCR_HC_Msk /* hiCredit Value */
/************ Bit definition for Ethernet MTL Tx queue 1 loCredit Register ***************/
#define ETH_MTLTXQ1LCR_LC_Pos (0U)
#define ETH_MTLTXQ1LCR_LC_Msk (0x1FFFFFFFUL << ETH_MTLTXQ1LCR_LC_Pos) /*!< 0x1FFFFFFF */
#define ETH_MTLTXQ1LCR_LC ETH_MTLTXQ1LCR_LC_Msk /* loCredit Value */
/************ Bit definition for Ethernet DMA Mode Register ***************/
#define ETH_DMAMR_INTM_Pos (16U)
#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
#define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
#define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
#define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
#define ETH_DMAMR_TXPR_Pos (11U)
#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit priority */
#define ETH_DMAMR_DSPW_Pos (8U)
#define ETH_DMAMR_DSPW_Msk (0x1UL << ETH_DMAMR_DSPW_Pos) /*!< 0x00000100 */
#define ETH_DMAMR_DSPW ETH_DMAMR_DSPW_Msk /* Descriptor Posted Write */
#define ETH_DMAMR_TAA_Pos (2U)
#define ETH_DMAMR_TAA_Msk (0x7UL << ETH_DMAMR_TAA_Pos) /*!< 0x000001C0 */
#define ETH_DMAMR_TAA ETH_DMAMR_TAA_Msk /* Transmit Arbitration Algorithm */
#define ETH_DMAMR_TAA_FP ((uint32_t)0x00000000) /* Fixed priority */
#define ETH_DMAMR_TAA_WSP_Pos (2U)
#define ETH_DMAMR_TAA_WSP_Msk (0x1UL << ETH_DMAMR_TAA_WSP_Pos) /*!< 0x00000004 */
#define ETH_DMAMR_TAA_WSP ETH_DMAMR_TAA_WSP_Msk /* Weighted Strict priority (WSP) */
#define ETH_DMAMR_TAA_WRR_Pos (3U)
#define ETH_DMAMR_TAA_WRR_Msk (0x1UL << ETH_DMAMR_TAA_WRR_Pos) /*!< 0x00000008 */
#define ETH_DMAMR_TAA_WRR ETH_DMAMR_TAA_WRR_Msk /* Weighted Round-Robin (WRR) */
#define ETH_DMAMR_SWR_Pos (0U)
#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
/************ Bit definition for Ethernet DMA System bus mode Register ***************/
#define ETH_DMASBMR_ENLPI_Pos (31U)
#define ETH_DMASBMR_ENLPI_Msk (0x1UL << ETH_DMASBMR_ENLPI_Pos) /*!< 0x80000000 */
#define ETH_DMASBMR_ENLPI ETH_DMASBMR_ENLPI_Msk /* Enable Low Power Interface (LPI) */
#define ETH_DMASBMR_LPIXPKT_Pos (30U)
#define ETH_DMASBMR_LPIXPKT_Msk (0x1UL << ETH_DMASBMR_LPIXPKT_Pos) /*!< 0x40000000 */
#define ETH_DMASBMR_LPIXPKT ETH_DMASBMR_LPIXPKT_Msk /* Unlock on Magic Packet or Remote wakeup Packet */
#define ETH_DMASBMR_WR_OSR_LMT_Pos (24U)
#define ETH_DMASBMR_WR_OSR_LMT_Msk (0x3UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x03000000 */
#define ETH_DMASBMR_WR_OSR_LMT ETH_DMASBMR_WR_OSR_LMT_Msk /*!< AXI Maximum Write Outstanding Request Limit */
#define ETH_DMASBMR_WR_OSR_LMT_0 (0x1UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x01000000 */
#define ETH_DMASBMR_WR_OSR_LMT_1 (0x2UL << ETH_DMASBMR_WR_OSR_LMT_Pos) /*!< 0x02000000 */
#define ETH_DMASBMR_RD_OSR_LMT_Pos (16U)
#define ETH_DMASBMR_RD_OSR_LMT_Msk (0x3UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00030000 */
#define ETH_DMASBMR_RD_OSR_LMT ETH_DMASBMR_RD_OSR_LMT_Msk /*!< AXI Maximum Read Outstanding Request Limit */
#define ETH_DMASBMR_RD_OSR_LMT_0 (0x1UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00010000 */
#define ETH_DMASBMR_RD_OSR_LMT_1 (0x2UL << ETH_DMASBMR_RD_OSR_LMT_Pos) /*!< 0x00020000 */
#define ETH_DMASBMR_ONEKBBE_Pos (13U)
#define ETH_DMASBMR_ONEKBBE_Msk (0x1UL << ETH_DMASBMR_ONEKBBE_Pos) /*!< 0x00002000 */
#define ETH_DMASBMR_ONEKBBE ETH_DMASBMR_ONEKBBE_Msk /* 1 Kbyte Boundary Crossing Enable for the AXI Master */
#define ETH_DMASBMR_AAL_Pos (12U)
#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
#define ETH_DMASBMR_AALE_Pos (10U)
#define ETH_DMASBMR_AALE_Msk (0x1UL << ETH_DMASBMR_AALE_Pos) /*!< 0x00000400 */
#define ETH_DMASBMR_AALE ETH_DMASBMR_AALE_Msk /* Automatic AXI LPI enable */
#define ETH_DMASBMR_BLEN256_Pos (7U)
#define ETH_DMASBMR_BLEN256_Msk (0x1UL << ETH_DMASBMR_BLEN256_Pos) /*!< 0x00000080 */
#define ETH_DMASBMR_BLEN256 ETH_DMASBMR_BLEN256_Msk /* AXI Burst Length 256 */
#define ETH_DMASBMR_BLEN128_Pos (6U)
#define ETH_DMASBMR_BLEN128_Msk (0x1UL << ETH_DMASBMR_BLEN128_Pos) /*!< 0x00000040 */
#define ETH_DMASBMR_BLEN128 ETH_DMASBMR_BLEN128_Msk /* AXI Burst Length 128 */
#define ETH_DMASBMR_BLEN64_Pos (5U)
#define ETH_DMASBMR_BLEN64_Msk (0x1UL << ETH_DMASBMR_BLEN64_Pos) /*!< 0x00000020 */
#define ETH_DMASBMR_BLEN64 ETH_DMASBMR_BLEN64_Msk /* AXI Burst Length 64 */
#define ETH_DMASBMR_BLEN32_Pos (4U)
#define ETH_DMASBMR_BLEN32_Msk (0x1UL << ETH_DMASBMR_BLEN32_Pos) /*!< 0x00000010 */
#define ETH_DMASBMR_BLEN32 ETH_DMASBMR_BLEN32_Msk /* AXI Burst Length 32 */
#define ETH_DMASBMR_BLEN16_Pos (3U)
#define ETH_DMASBMR_BLEN16_Msk (0x1UL << ETH_DMASBMR_BLEN16_Pos) /*!< 0x00000008 */
#define ETH_DMASBMR_BLEN16 ETH_DMASBMR_BLEN16_Msk /* AXI Burst Length 16 */
#define ETH_DMASBMR_BLEN8_Pos (2U)
#define ETH_DMASBMR_BLEN8_Msk (0x1UL << ETH_DMASBMR_BLEN8_Pos) /*!< 0x00000004 */
#define ETH_DMASBMR_BLEN8 ETH_DMASBMR_BLEN8_Msk /* AXI Burst Length 8 */
#define ETH_DMASBMR_BLEN4_Pos (1U)
#define ETH_DMASBMR_BLEN4_Msk (0x1UL << ETH_DMASBMR_BLEN4_Pos) /*!< 0x00000002 */
#define ETH_DMASBMR_BLEN4 ETH_DMASBMR_BLEN4_Msk /* AXI Burst Length 4 */
#define ETH_DMASBMR_FB_Pos (0U)
#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
/************ Bit definition for Ethernet DMA Interrupt Status Register ***************/
#define ETH_DMAISR_MACIS_Pos (17U)
#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
#define ETH_DMAISR_MTLIS_Pos (16U)
#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
#define ETH_DMAISR_DMAC1IS_Pos (1U)
#define ETH_DMAISR_DMAC1IS_Msk (0x1UL << ETH_DMAISR_DMAC1IS_Pos) /*!< 0x00000001 */
#define ETH_DMAISR_DMAC1IS ETH_DMAISR_DMAC1IS_Msk /* DMA Channel 1 Interrupt Status */
#define ETH_DMAISR_DMAC0IS_Pos (0U)
#define ETH_DMAISR_DMAC0IS_Msk (0x1UL << ETH_DMAISR_DMAC0IS_Pos) /*!< 0x00000001 */
#define ETH_DMAISR_DMAC0IS ETH_DMAISR_DMAC0IS_Msk /* DMA Channel 0 Interrupt Status */
/************ Bit definition for Ethernet DMA Debug Status Register ***************/
#define ETH_DMADSR_TPS1_Pos (20U)
#define ETH_DMADSR_TPS1_Msk (0xFUL << ETH_DMADSR_TPS1_Pos) /*!< 0x00F00000 */
#define ETH_DMADSR_TPS1 ETH_DMADSR_TPS1_Msk /* DMA Channel 1 Transmit Process State */
#define ETH_DMADSR_TPS1_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
#define ETH_DMADSR_TPS1_FETCHING_Pos (20U)
#define ETH_DMADSR_TPS1_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS1_FETCHING_Pos) /*!< 0x00100000 */
#define ETH_DMADSR_TPS1_FETCHING ETH_DMADSR_TPS1_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
#define ETH_DMADSR_TPS1_WAITING_Pos (21U)
#define ETH_DMADSR_TPS1_WAITING_Msk (0x1UL << ETH_DMADSR_TPS1_WAITING_Pos) /*!< 0x00200000 */
#define ETH_DMADSR_TPS1_WAITING ETH_DMADSR_TPS1_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_TPS1_READING_Pos (20U)
#define ETH_DMADSR_TPS1_READING_Msk (0x3UL << ETH_DMADSR_TPS1_READING_Pos) /*!< 0x00300000 */
#define ETH_DMADSR_TPS1_READING ETH_DMADSR_TPS1_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos (22U)
#define ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS1_TIMESTAMP_WR_Pos) /*!< 0x00400000 */
#define ETH_DMADSR_TPS1_TIMESTAMP_WR ETH_DMADSR_TPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_TPS1_SUSPENDED_Pos (21U)
#define ETH_DMADSR_TPS1_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS1_SUSPENDED_Pos) /*!< 0x00600000 */
#define ETH_DMADSR_TPS1_SUSPENDED ETH_DMADSR_TPS1_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
#define ETH_DMADSR_TPS1_CLOSING_Pos (20U)
#define ETH_DMADSR_TPS1_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS1_CLOSING_Pos) /*!< 0x00700000 */
#define ETH_DMADSR_TPS1_CLOSING ETH_DMADSR_TPS1_CLOSING_Msk /* Running (Closing Tx Descriptor) */
#define ETH_DMADSR_RPS1_Pos (16U)
#define ETH_DMADSR_RPS1_Msk (0xFUL << ETH_DMADSR_RPS1_Pos) /*!< 0x000F0000 */
#define ETH_DMADSR_RPS1 ETH_DMADSR_RPS1_Msk /* DMA Channel 1 Receive Process State */
#define ETH_DMADSR_RPS1_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
#define ETH_DMADSR_RPS1_FETCHING_Pos (16U)
#define ETH_DMADSR_RPS1_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS1_FETCHING_Pos) /*!< 0x00010000 */
#define ETH_DMADSR_RPS1_FETCHING ETH_DMADSR_RPS1_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
#define ETH_DMADSR_RPS1_WAITING_Pos (16U)
#define ETH_DMADSR_RPS1_WAITING_Msk (0x3UL << ETH_DMADSR_RPS1_WAITING_Pos) /*!< 0x00030000 */
#define ETH_DMADSR_RPS1_WAITING ETH_DMADSR_RPS1_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_RPS1_SUSPENDED_Pos (18U)
#define ETH_DMADSR_RPS1_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS1_SUSPENDED_Pos) /*!< 0x00040000 */
#define ETH_DMADSR_RPS1_SUSPENDED ETH_DMADSR_RPS1_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
#define ETH_DMADSR_RPS1_CLOSING_Pos (16U)
#define ETH_DMADSR_RPS1_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS1_CLOSING_Pos) /*!< 0x00050000 */
#define ETH_DMADSR_RPS1_CLOSING ETH_DMADSR_RPS1_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos (17U)
#define ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS1_TIMESTAMP_WR_Pos) /*!< 0x00060000 */
#define ETH_DMADSR_RPS1_TIMESTAMP_WR ETH_DMADSR_RPS1_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_RPS1_TRANSFERRING_Pos (16U)
#define ETH_DMADSR_RPS1_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS1_TRANSFERRING_Pos) /*!< 0x00070000 */
#define ETH_DMADSR_RPS1_TRANSFERRING ETH_DMADSR_RPS1_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
#define ETH_DMADSR_TPS0_Pos (12U)
#define ETH_DMADSR_TPS0_Msk (0xFUL << ETH_DMADSR_TPS0_Pos) /*!< 0x0000F000 */
#define ETH_DMADSR_TPS0 ETH_DMADSR_TPS0_Msk /* DMA Channel 0 Transmit Process State */
#define ETH_DMADSR_TPS0_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
#define ETH_DMADSR_TPS0_FETCHING_Pos (12U)
#define ETH_DMADSR_TPS0_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS0_FETCHING_Pos) /*!< 0x00001000 */
#define ETH_DMADSR_TPS0_FETCHING ETH_DMADSR_TPS0_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
#define ETH_DMADSR_TPS0_WAITING_Pos (13U)
#define ETH_DMADSR_TPS0_WAITING_Msk (0x1UL << ETH_DMADSR_TPS0_WAITING_Pos) /*!< 0x00002000 */
#define ETH_DMADSR_TPS0_WAITING ETH_DMADSR_TPS0_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_TPS0_READING_Pos (12U)
#define ETH_DMADSR_TPS0_READING_Msk (0x3UL << ETH_DMADSR_TPS0_READING_Pos) /*!< 0x00003000 */
#define ETH_DMADSR_TPS0_READING ETH_DMADSR_TPS0_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos (14U)
#define ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS0_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
#define ETH_DMADSR_TPS0_TIMESTAMP_WR ETH_DMADSR_TPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_TPS0_SUSPENDED_Pos (13U)
#define ETH_DMADSR_TPS0_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS0_SUSPENDED_Pos) /*!< 0x00006000 */
#define ETH_DMADSR_TPS0_SUSPENDED ETH_DMADSR_TPS0_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
#define ETH_DMADSR_TPS0_CLOSING_Pos (12U)
#define ETH_DMADSR_TPS0_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS0_CLOSING_Pos) /*!< 0x00007000 */
#define ETH_DMADSR_TPS0_CLOSING ETH_DMADSR_TPS0_CLOSING_Msk /* Running (Closing Tx Descriptor) */
#define ETH_DMADSR_RPS0_Pos (8U)
#define ETH_DMADSR_RPS0_Msk (0xFUL << ETH_DMADSR_RPS0_Pos) /*!< 0x00000F00 */
#define ETH_DMADSR_RPS0 ETH_DMADSR_RPS0_Msk /* DMA Channel 0 Receive Process State */
#define ETH_DMADSR_RPS0_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
#define ETH_DMADSR_RPS0_FETCHING_Pos (8U)
#define ETH_DMADSR_RPS0_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS0_FETCHING_Pos) /*!< 0x00000100 */
#define ETH_DMADSR_RPS0_FETCHING ETH_DMADSR_RPS0_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
#define ETH_DMADSR_RPS0_WAITING_Pos (8U)
#define ETH_DMADSR_RPS0_WAITING_Msk (0x3UL << ETH_DMADSR_RPS0_WAITING_Pos) /*!< 0x00000300 */
#define ETH_DMADSR_RPS0_WAITING ETH_DMADSR_RPS0_WAITING_Msk /* Running (Waiting for status) */
#define ETH_DMADSR_RPS0_SUSPENDED_Pos (10U)
#define ETH_DMADSR_RPS0_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS0_SUSPENDED_Pos) /*!< 0x00000400 */
#define ETH_DMADSR_RPS0_SUSPENDED ETH_DMADSR_RPS0_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
#define ETH_DMADSR_RPS0_CLOSING_Pos (8U)
#define ETH_DMADSR_RPS0_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS0_CLOSING_Pos) /*!< 0x00000500 */
#define ETH_DMADSR_RPS0_CLOSING ETH_DMADSR_RPS0_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos (9U)
#define ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS0_TIMESTAMP_WR_Pos) /*!< 0x00000600 */
#define ETH_DMADSR_RPS0_TIMESTAMP_WR ETH_DMADSR_RPS0_TIMESTAMP_WR_Msk /* Timestamp write state */
#define ETH_DMADSR_RPS0_TRANSFERRING_Pos (8U)
#define ETH_DMADSR_RPS0_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS0_TRANSFERRING_Pos) /*!< 0x00000700 */
#define ETH_DMADSR_RPS0_TRANSFERRING ETH_DMADSR_RPS0_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
#define ETH_DMADSR_AXRHSTS_Pos (1U)
#define ETH_DMADSR_AXRHSTS_Msk (0x1UL << ETH_DMADSR_AXRHSTS_Pos) /*!< 0x00000002 */
#define ETH_DMADSR_AXRHSTS ETH_DMADSR_AXRHSTS_Msk /* AXI Master Read Channel Status */
#define ETH_DMADSR_AXWHSTS_Pos (1U)
#define ETH_DMADSR_AXWHSTS_Msk (0x1UL << ETH_DMADSR_AXWHSTS_Pos) /*!< 0x00000001 */
#define ETH_DMADSR_AXWHSTS ETH_DMADSR_AXWHSTS_Msk /* AXI Master Write Channel */
/************ Bit definition for Ethernet DMA AXI4 transmit channel ACE control Register ***************/
#define ETH_DMAA4TXACR_THC_Pos (16U)
#define ETH_DMAA4TXACR_THC_Msk (0xFUL << ETH_DMAA4TXACR_THC_Pos) /*!< 0x000F0000 */
#define ETH_DMAA4TXACR_THC ETH_DMAA4TXACR_THC_Msk /* Transmit DMA First Packet Buffer or TSO Header Cache Control */
#define ETH_DMAA4TXACR_TEC_Pos (8U)
#define ETH_DMAA4TXACR_TEC_Msk (0xFUL << ETH_DMAA4TXACR_TEC_Pos) /*!< 0x00000F00 */
#define ETH_DMAA4TXACR_TEC ETH_DMAA4TXACR_TEC_Msk /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
#define ETH_DMAA4TXACR_TDRC_Pos (0U)
#define ETH_DMAA4TXACR_TDRC_Msk (0xFUL << ETH_DMAA4TXACR_TDRC_Pos) /*!< 0x0000000F */
#define ETH_DMAA4TXACR_TDRC ETH_DMAA4TXACR_TDRC_Msk /* Transmit DMA Extended Packet Buffer or TSO Payload Cache Control */
/************ Bit definition for Ethernet DMA AXI4 receive channel ACE control Register ***************/
#define ETH_DMAA4RXACR_RDC_Pos (24U)
#define ETH_DMAA4RXACR_RDC_Msk (0xFUL << ETH_DMAA4RXACR_RDC_Pos) /*!< 0x0F000000 */
#define ETH_DMAA4RXACR_RDC ETH_DMAA4RXACR_RDC_Msk /* Receive DMA Buffer Cache Control */
#define ETH_DMAA4RXACR_RHC_Pos (16U)
#define ETH_DMAA4RXACR_RHC_Msk (0xFUL << ETH_DMAA4RXACR_RHC_Pos) /*!< 0x000F0000 */
#define ETH_DMAA4RXACR_RHC ETH_DMAA4RXACR_RHC_Msk /* Receive DMA Header Cache Control */
#define ETH_DMAA4RXACR_RPC_Pos (8U)
#define ETH_DMAA4RXACR_RPC_Msk (0xFUL << ETH_DMAA4RXACR_RPC_Pos) /*!< 0x00000F00 */
#define ETH_DMAA4RXACR_RPC ETH_DMAA4RXACR_RPC_Msk /* Receive DMA Payload Cache Control */
#define ETH_DMAA4RXACR_RDWC_Pos (0U)
#define ETH_DMAA4RXACR_RDWC_Msk (0xFUL << ETH_DMAA4RXACR_RDWC_Pos) /*!< 0x0000000F */
#define ETH_DMAA4RXACR_RDWC ETH_DMAA4RXACR_RDWC_Msk /* Receive DMA Write Descriptor Cache Control */
/************ Bit definition for Ethernet DMA AXI4 descriptor ACE control Register ***************/
#define ETH_DMAA4DACR_RDRC_Pos (8U)
#define ETH_DMAA4DACR_RDRC_Msk (0xFUL << ETH_DMAA4DACR_RDRC_Pos) /*!< 0x00000F00 */
#define ETH_DMAA4DACR_RDRC ETH_DMAA4DACR_RDRC_Msk /* Receive DMA Read Descriptor Cache control */
#define ETH_DMAA4DACR_TDWD_Pos (4U)
#define ETH_DMAA4DACR_TDWD_Msk (0xFUL << ETH_DMAA4DACR_TDWD_Pos) /*!< 0x00000030 */
#define ETH_DMAA4DACR_TDWD ETH_DMAA4DACR_TDWD_Msk /* Transmit DMA Write Descriptor Domain control */
#define ETH_DMAA4DACR_TDWC_Pos (0U)
#define ETH_DMAA4DACR_TDWC_Msk (0xFUL << ETH_DMAA4DACR_TDWC_Pos) /*!< 0x0000000F */
#define ETH_DMAA4DACR_TDWC ETH_DMAA4DACR_TDWC_Msk /* Transmit DMA Write Descriptor Cache control */
/************ Bit definition for Ethernet DMA AXI4 LPI Entry Interval Register ***************/
/* Bit definition for Ethernet DMA AXI4 LPI Entry Interval register */
#define ETH_DMALPIEI_LPIEI_Pos (0U)
#define ETH_DMALPIEI_LPIEI_Msk (0xFUL << ETH_DMALPIEI_LPIEI_Pos) /*!< 0x0000000F */
#define ETH_DMALPIEI_LPIEI ETH_DMALPIEI_LPIEI_Msk /* LPI Entry Interval */
/************ Bit definition for Ethernet DMA TBS control Register ***************/
#define ETH_DMATBSCTRL0R_FTOS_Pos (8U)
#define ETH_DMATBSCTRL0R_FTOS_Msk (0xFFFFFFUL << ETH_DMATBSCTRL0R_FTOS_Pos) /*!< 0xFFFFFF00 */
#define ETH_DMATBSCTRL0R_FTOS ETH_DMATBSCTRL0R_FTOS_Msk /* Fetch time offset */
#define ETH_DMATBSCTRL0R_FGOS_Pos (4U)
#define ETH_DMATBSCTRL0R_FGOS_Msk (0x7UL << ETH_DMATBSCTRL0R_FGOS_Pos) /*!< 0x00000070 */
#define ETH_DMATBSCTRL0R_FGOS ETH_DMATBSCTRL0R_FGOS_Msk /* Fetch GSN offset */
#define ETH_DMATBSCTRL0R_FTOV_Pos (0U)
#define ETH_DMATBSCTRL0R_FTOV_Msk (0x1UL << ETH_DMATBSCTRL0R_FTOV_Pos) /*!< 0x00000001 */
#define ETH_DMATBSCTRL0R_FTOV ETH_DMATBSCTRL0R_FTOV_Msk /* Fetch time offset valid */
/************ Bit definition for Ethernet DMA Channel x Control Register ***************/
#define ETH_DMACxCR_DSL_Pos (18U)
#define ETH_DMACxCR_DSL_Msk (0x7UL << ETH_DMACxCR_DSL_Pos) /*!< 0x001C0000 */
#define ETH_DMACxCR_DSL ETH_DMACxCR_DSL_Msk /* Descriptor Skip Length */
#define ETH_DMACxCR_DSL_0BIT ((uint32_t)0x00000000)
#define ETH_DMACxCR_DSL_32BIT ((uint32_t)0x00040000)
#define ETH_DMACxCR_DSL_64BIT ((uint32_t)0x00080000)
#define ETH_DMACxCR_DSL_128BIT ((uint32_t)0x00100000)
#define ETH_DMACxCR_PBLX8_Pos (16U)
#define ETH_DMACxCR_PBLX8_Msk (0x1UL << ETH_DMACxCR_PBLX8_Pos) /*!< 0x00010000 */
#define ETH_DMACxCR_PBLX8 ETH_DMACxCR_PBLX8_Msk /* 8xPBL mode */
#define ETH_DMACxCR_MSS_Pos (0U)
#define ETH_DMACxCR_MSS_Msk (0x3FFFUL << ETH_DMACxCR_MSS_Pos) /*!< 0x00003FFF */
#define ETH_DMACxCR_MSS ETH_DMACxCR_MSS_Msk /* Maximum Segment Size */
/************ Bit definition for Ethernet DMA Channel x transmit control Register ***************/
#define ETH_DMACxTXCR_EDSE_Pos (28U)
#define ETH_DMACxTXCR_EDSE_Msk (0x1UL << ETH_DMACxTXCR_EDSE_Pos) /*!< 0x10000000 */
#define ETH_DMACxTXCR_EDSE ETH_DMACxTXCR_EDSE_Msk /* Enhanced Descriptor Enable */
#define ETH_DMACxTXCR_TQOS_Pos (24U)
#define ETH_DMACxTXCR_TQOS_Msk (0xFUL << ETH_DMACxTXCR_TQOS_Pos) /*!< 0x0F000000 */
#define ETH_DMACxTXCR_TQOS ETH_DMACxTXCR_TQOS_Msk /* Transmit QOS */
#define ETH_DMACxTXCR_TXPBL_Pos (16U)
#define ETH_DMACxTXCR_TXPBL_Msk (0x3FUL << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMACxTXCR_TXPBL ETH_DMACxTXCR_TXPBL_Msk /* Transmit Programmable Burst Length */
#define ETH_DMACxTXCR_TXPBL_1PBL (0x1U << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x00010000 */
#define ETH_DMACxTXCR_TXPBL_2PBL (0x2U << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x00020000 */
#define ETH_DMACxTXCR_TXPBL_4PBL (0x4U << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x00040000 */
#define ETH_DMACxTXCR_TXPBL_8PBL (0x8U << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x00080000 */
#define ETH_DMACxTXCR_TXPBL_16PBL (0x10U << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x00100000 */
#define ETH_DMACxTXCR_TXPBL_32PBL (0x20U << ETH_DMACxTXCR_TXPBL_Pos) /*!< 0x00200000 */
#define ETH_DMACxTXCR_IPBL_Pos (15U)
#define ETH_DMACxTXCR_IPBL_Msk (0x1UL << ETH_DMACxTXCR_IPBL_Pos) /*!< 0x00008000 */
#define ETH_DMACxTXCR_IPBL ETH_DMACxTXCR_IPBL_Msk /* Ignore PBL Requirement */
#define ETH_DMACxTXCR_TSE_Pos (12U)
#define ETH_DMACxTXCR_TSE_Msk (0x1UL << ETH_DMACxTXCR_TSE_Pos) /*!< 0x00001000 */
#define ETH_DMACxTXCR_TSE ETH_DMACxTXCR_TSE_Msk /* TCP Segmentation Enabled */
#define ETH_DMACxTXCR_OSF_Pos (4U)
#define ETH_DMACxTXCR_OSF_Msk (0x1UL << ETH_DMACxTXCR_OSF_Pos) /*!< 0x00000010 */
#define ETH_DMACxTXCR_OSF ETH_DMACxTXCR_OSF_Msk /* Operate on Second Packet */
#define ETH_DMACxTXCR_TCW_Pos (1U)
#define ETH_DMACxTXCR_TCW_Msk (0x7UL << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000E */
#define ETH_DMACxTXCR_TCW ETH_DMACxTXCR_TCW_Msk /* Transmit Channel Weight */
#define ETH_DMACxTXCR_TCW_1 (0x1U << ETH_DMACxTXCR_TCW_Pos) /*!< 0x00000002 */
#define ETH_DMACxTXCR_TCW_2 (0x2U << ETH_DMACxTXCR_TCW_Pos) /*!< 0x00000004 */
#define ETH_DMACxTXCR_TCW_3 (0x3U << ETH_DMACxTXCR_TCW_Pos) /*!< 0x00000006 */
#define ETH_DMACxTXCR_TCW_4 (0x4U << ETH_DMACxTXCR_TCW_Pos) /*!< 0x00000008 */
#define ETH_DMACxTXCR_TCW_5 (0x5U << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000A */
#define ETH_DMACxTXCR_TCW_6 (0x6U << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000C */
#define ETH_DMACxTXCR_TCW_7 (0x7U << ETH_DMACxTXCR_TCW_Pos) /*!< 0x0000000E */
#define ETH_DMACxTXCR_ST_Pos (0U)
#define ETH_DMACxTXCR_ST_Msk (0x1UL << ETH_DMACxTXCR_ST_Pos) /*!< 0x00000001 */
#define ETH_DMACxTXCR_ST ETH_DMACxTXCR_ST_Msk /* Start or Stop Transmission Command */
/************ Bit definition for Ethernet DMA Channel x receive control Register ***************/
#define ETH_DMACxRXCR_RPF_Pos (31U)
#define ETH_DMACxRXCR_RPF_Msk (0x1UL << ETH_DMACxRXCR_RPF_Pos) /*!< 0x80000000 */
#define ETH_DMACxRXCR_RPF ETH_DMACxRXCR_RPF_Msk /* DMA Rx Channel Packet Flush */
#define ETH_DMACxRXCR_RQOS_Pos (24U)
#define ETH_DMACxRXCR_RQOS_Msk (0xFUL << ETH_DMACxRXCR_RQOS_Pos) /*!< 0x0F000000 */
#define ETH_DMACxRXCR_RQOS ETH_DMACxRXCR_RQOS_Msk /* Rx AXI4 QOS */
#define ETH_DMACxRXCR_RXPBL_Pos (16U)
#define ETH_DMACxRXCR_RXPBL_Msk (0x3FUL << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x003F0000 */
#define ETH_DMACxRXCR_RXPBL ETH_DMACxRXCR_RXPBL_Msk /* Rx AXI4 QOS */
#define ETH_DMACxRXCR_RXPBL_1PBL (0x1U << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x00010000 */
#define ETH_DMACxRXCR_RXPBL_2PBL (0x2U << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x00020000 */
#define ETH_DMACxRXCR_RXPBL_4PBL (0x4U << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x00040000 */
#define ETH_DMACxRXCR_RXPBL_8PBL (0x8U << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x00080000 */
#define ETH_DMACxRXCR_RXPBL_16PBL (0x10U << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x00100000 */
#define ETH_DMACxRXCR_RXPBL_32PBL (0x20U << ETH_DMACxRXCR_RXPBL_Pos) /*!< 0x00200000 */
#define ETH_DMACxRXCR_RBSZ_Pos (1U)
#define ETH_DMACxRXCR_RBSZ_Msk (0x1FFFUL << ETH_DMACxRXCR_RBSZ_Pos) /*!< 0x00003FFE */
#define ETH_DMACxRXCR_RBSZ ETH_DMACxRXCR_RBSZ_Msk /* Receive Buffer size */
#define ETH_DMACxRXCR_SR_Pos (0U)
#define ETH_DMACxRXCR_SR_Msk (0x1UL << ETH_DMACxRXCR_SR_Pos) /*!< 0x00000001 */
#define ETH_DMACxRXCR_SR ETH_DMACxRXCR_SR_Msk /* Start or Stop Receive */
/************ Bit definition for Ethernet DMA Channel x Tx descriptor list address Register ***************/
#define ETH_DMACxTXDLAR_TDESLA_Pos (0U)
#define ETH_DMACxTXDLAR_TDESLA_Msk (0xFFFFFFFFUL << ETH_DMACxTXDLAR_TDESLA_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxTXDLAR_TDESLA ETH_DMACxTXDLAR_TDESLA_Msk /* Start of Transmit List */
/************ Bit definition for Ethernet DMA Channel x Rx descriptor list address Register ***************/
#define ETH_DMACxRXDLAR_RDESLA_Pos (0U)
#define ETH_DMACxRXDLAR_RDESLA_Msk (0xFFFFFFFFUL << ETH_DMACxRXDLAR_RDESLA_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxRXDLAR_RDESLA ETH_DMACxRXDLAR_RDESLA_Msk /* Start of Receive List */
/************ Bit definition for Ethernet DMA Channel x Tx descriptor tail pointer Register ***************/
#define ETH_DMACxTXDTPR_TDT_Pos (0U)
#define ETH_DMACxTXDTPR_TDT_Msk (0xFFFFFFFFUL << ETH_DMACxTXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxTXDTPR_TDT ETH_DMACxTXDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
/************ Bit definition for Ethernet DMA Channel x Rx descriptor tail pointer Register ***************/
#define ETH_DMACxRXDTPR_TDT_Pos (0U)
#define ETH_DMACxRXDTPR_TDT_Msk (0xFFFFFFFFUL << ETH_DMACxRXDTPR_TDT_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxRXDTPR_TDT ETH_DMACxRXDTPR_TDT_Msk /* Receive Descriptor Tail Pointer */
/************ Bit definition for Ethernet DMA Channel x Tx descriptor ring length Register ***************/
#define ETH_DMACxTXRLR_TDRL_Pos (0U)
#define ETH_DMACxTXRLR_TDRL_Msk (0x3FFUL << ETH_DMACxTXRLR_TDRL_Pos) /*!< 0x0000003FF */
#define ETH_DMACxTXRLR_TDRL ETH_DMACxTXRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
/************ Bit definition for Ethernet DMA Channel x Rx descriptor ring length Register ***************/
#define ETH_DMACxRXRLR_ARBS_Pos (17U)
#define ETH_DMACxRXRLR_ARBS_Msk (0x7FUL << ETH_DMACxRXRLR_ARBS_Pos) /*!< 0x000FE0000 */
#define ETH_DMACxRXRLR_ARBS ETH_DMACxRXRLR_ARBS_Msk /* Alternate Receive Buffer Size */
#define ETH_DMACxRXRLR_RDRL_Pos (0U)
#define ETH_DMACxRXRLR_RDRL_Msk (0x3FFUL << ETH_DMACxRXRLR_RDRL_Pos) /*!< 0x0000003FF */
#define ETH_DMACxRXRLR_RDRL ETH_DMACxRXRLR_RDRL_Msk /* Receive Descriptor Ring Length */
/************ Bit definition for Ethernet DMA Channel x Interrupt Enable Register ***************/
#define ETH_DMACxIER_NIE_Pos (15U)
#define ETH_DMACxIER_NIE_Msk (0x1UL << ETH_DMACxIER_NIE_Pos) /*!< 0x00008000 */
#define ETH_DMACxIER_NIE ETH_DMACxIER_NIE_Msk /* Normal Interrupt Summary Enable */
#define ETH_DMACxIER_AIE_Pos (14U)
#define ETH_DMACxIER_AIE_Msk (0x1UL << ETH_DMACxIER_AIE_Pos) /*!< 0x00004000 */
#define ETH_DMACxIER_AIE ETH_DMACxIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
#define ETH_DMACxIER_CDEE_Pos (13U)
#define ETH_DMACxIER_CDEE_Msk (0x1UL << ETH_DMACxIER_CDEE_Pos) /*!< 0x00002000 */
#define ETH_DMACxIER_CDEE ETH_DMACxIER_CDEE_Msk /* Context Descriptor Error Enable */
#define ETH_DMACxIER_FBEE_Pos (12U)
#define ETH_DMACxIER_FBEE_Msk (0x1UL << ETH_DMACxIER_FBEE_Pos) /*!< 0x00001000 */
#define ETH_DMACxIER_FBEE ETH_DMACxIER_FBEE_Msk /* Fatal Bus Error Enable */
#define ETH_DMACxIER_ERIE_Pos (11U)
#define ETH_DMACxIER_ERIE_Msk (0x1UL << ETH_DMACxIER_ERIE_Pos) /*!< 0x00000800 */
#define ETH_DMACxIER_ERIE ETH_DMACxIER_ERIE_Msk /* Early Receive Interrupt Enable */
#define ETH_DMACxIER_ETIE_Pos (10U)
#define ETH_DMACxIER_ETIE_Msk (0x1UL << ETH_DMACxIER_ETIE_Pos) /*!< 0x00000400 */
#define ETH_DMACxIER_ETIE ETH_DMACxIER_ETIE_Msk /* Early Transmit Interrupt Enable */
#define ETH_DMACxIER_RWTE_Pos (9U)
#define ETH_DMACxIER_RWTE_Msk (0x1UL << ETH_DMACxIER_RWTE_Pos) /*!< 0x00000200 */
#define ETH_DMACxIER_RWTE ETH_DMACxIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
#define ETH_DMACxIER_RSE_Pos (8U)
#define ETH_DMACxIER_RSE_Msk (0x1UL << ETH_DMACxIER_RSE_Pos) /*!< 0x00000100 */
#define ETH_DMACxIER_RSE ETH_DMACxIER_RSE_Msk /* Receive Stopped Enable */
#define ETH_DMACxIER_RBUE_Pos (7U)
#define ETH_DMACxIER_RBUE_Msk (0x1UL << ETH_DMACxIER_RBUE_Pos) /*!< 0x00000080 */
#define ETH_DMACxIER_RBUE ETH_DMACxIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
#define ETH_DMACxIER_RIE_Pos (6U)
#define ETH_DMACxIER_RIE_Msk (0x1UL << ETH_DMACxIER_RIE_Pos) /*!< 0x00000040 */
#define ETH_DMACxIER_RIE ETH_DMACxIER_RIE_Msk /* Receive Interrupt Enable */
#define ETH_DMACxIER_TBUE_Pos (2U)
#define ETH_DMACxIER_TBUE_Msk (0x1UL << ETH_DMACxIER_TBUE_Pos) /*!< 0x00000004 */
#define ETH_DMACxIER_TBUE ETH_DMACxIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
#define ETH_DMACxIER_TXSE_Pos (1U)
#define ETH_DMACxIER_TXSE_Msk (0x1UL << ETH_DMACxIER_TXSE_Pos) /*!< 0x00000002 */
#define ETH_DMACxIER_TXSE ETH_DMACxIER_TXSE_Msk /* Transmit Stopped Enable */
#define ETH_DMACxIER_TIE_Pos (0U)
#define ETH_DMACxIER_TIE_Msk (0x1UL << ETH_DMACxIER_TIE_Pos) /*!< 0x00000001 */
#define ETH_DMACxIER_TIE ETH_DMACxIER_TIE_Msk /* Transmit Interrupt Enable */
/************ Bit definition for Ethernet DMA Channel x Rx Interrupt Watchdog Timer Register ***************/
#define ETH_DMACxRXIWTR_RWTU_Pos (16U)
#define ETH_DMACxRXIWTR_RWTU_Msk (0x3UL << ETH_DMACxRXIWTR_RWTU_Pos) /*!< 0x00030000 */
#define ETH_DMACxRXIWTR_RWTU ETH_DMACxRXIWTR_RWTU_Msk /* Receive Interrupt Watchdog Timer Count Units */
#define ETH_DMACxRXIWTR_RWTU_256 ((uint32_t)0x00000000) /* 256 */
#define ETH_DMACxRXIWTR_RWTU_512_Pos (16U)
#define ETH_DMACxRXIWTR_RWTU_512_Msk (0x1UL << ETH_DMACxRXIWTR_RWTU_512_Pos) /*!< 0x00010000 */
#define ETH_DMACxRXIWTR_RWTU_512 ETH_DMACxRXIWTR_RWTU_512_Msk /* 512 */
#define ETH_DMACxRXIWTR_RWTU_1024_Pos (17U)
#define ETH_DMACxRXIWTR_RWTU_1024_Msk (0x1UL << ETH_DMACxRXIWTR_RWTU_1024_Pos) /*!< 0x00020000 */
#define ETH_DMACxRXIWTR_RWTU_1024 ETH_DMACxRXIWTR_RWTU_1024_Msk /* 1024 */
#define ETH_DMACxRXIWTR_RWTU_2048_Pos (16U)
#define ETH_DMACxRXIWTR_RWTU_2048_Msk (0x3UL << ETH_DMACxRXIWTR_RWTU_2048_Pos) /*!< 0x00030000 */
#define ETH_DMACxRXIWTR_RWTU_2048 ETH_DMACxRXIWTR_RWTU_2048_Msk /* 2048 */
#define ETH_DMACxRXIWTR_RWT_Pos (0U)
#define ETH_DMACxRXIWTR_RWT_Msk (0xFFUL << ETH_DMACxRXIWTR_RWT_Pos) /*!< 0x000000FF */
#define ETH_DMACxRXIWTR_RWT ETH_DMACxRXIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
/************ Bit definition for Ethernet DMA Channel x slot function control status Register ***************/
#define ETH_DMACxSFCSR_RSN_Pos (16U)
#define ETH_DMACxSFCSR_RSN_Msk (0xFUL << ETH_DMACxSFCSR_RSN_Pos) /*!< 0x000F0000 */
#define ETH_DMACxSFCSR_RSN ETH_DMACxSFCSR_RSN_Msk /* Reference Slot Number */
#define ETH_DMACxSFCSR_SIV_Pos (4U)
#define ETH_DMACxSFCSR_SIV_Msk (0xFFFUL << ETH_DMACxSFCSR_SIV_Pos) /*!< 0x0000FFF0 */
#define ETH_DMACxSFCSR_SIV ETH_DMACxSFCSR_SIV_Msk /* Slot Interval Value */
#define ETH_DMACxSFCSR_ASC_Pos (1U)
#define ETH_DMACxSFCSR_ASC_Msk (0x1UL << ETH_DMACxSFCSR_ASC_Pos) /*!< 0x00000002 */
#define ETH_DMACxSFCSR_ASC ETH_DMACxSFCSR_ASC_Msk /* Advance Slot Check */
#define ETH_DMACxSFCSR_ESC_Pos (0U)
#define ETH_DMACxSFCSR_ESC_Msk (0x1UL << ETH_DMACxSFCSR_ESC_Pos) /*!< 0x00000001 */
#define ETH_DMACxSFCSR_ESC ETH_DMACxSFCSR_ESC_Msk /* Enable Slot Comparison */
/************ Bit definition for Ethernet DMA Channel x Current App Tx Desc Register ***************/
#define ETH_DMACxCATXDR_CURTDESAPTR_Pos (0U)
#define ETH_DMACxCATXDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACxCATXDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxCATXDR_CURTDESAPTR ETH_DMACxCATXDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
/************ Bit definition for Ethernet DMA Channel x Current App Rx Desc Register ***************/
#define ETH_DMACxCARXDR_CURRDESAPTR_Pos (0U)
#define ETH_DMACxCARXDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACxCARXDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxCARXDR_CURRDESAPTR ETH_DMACxCARXDR_CURRDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
/************ Bit definition for Ethernet DMA Channel x Current App Tx Buffer Register ***************/
#define ETH_DMACxCATXBR_CURTBUFAPTR_Pos (0U)
#define ETH_DMACxCATXBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACxCATXBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxCATXBR_CURTBUFAPTR ETH_DMACxCATXBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
/************ Bit definition for Ethernet DMA Channel x Current App Rx Buffer Register ***************/
#define ETH_DMACxCARXBR_CURRBUFAPTR_Pos (0U)
#define ETH_DMACxCARXBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACxCARXBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
#define ETH_DMACxCARXBR_CURRBUFAPTR ETH_DMACxCARXBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
/************ Bit definition for Ethernet DMA Channel x Status Register ***************/
#define ETH_DMACxSR_REB_Pos (19U)
#define ETH_DMACxSR_REB_Msk (0x7UL << ETH_DMACxSR_REB_Pos) /*!< 0x00380000 */
#define ETH_DMACxSR_REB ETH_DMACxSR_REB_Msk /* Rx DMA Error Bits */
#define ETH_DMACxSR_TEB_Pos (16U)
#define ETH_DMACxSR_TEB_Msk (0x7UL << ETH_DMACxSR_TEB_Pos) /*!< 0x00070000 */
#define ETH_DMACxSR_TEB ETH_DMACxSR_TEB_Msk /* Tx DMA Error Bits */
#define ETH_DMACxSR_NIS_Pos (15U)
#define ETH_DMACxSR_NIS_Msk (0x1UL << ETH_DMACxSR_NIS_Pos) /*!< 0x00008000 */
#define ETH_DMACxSR_NIS ETH_DMACxSR_NIS_Msk /* Normal Interrupt Summary */
#define ETH_DMACxSR_AIS_Pos (14U)
#define ETH_DMACxSR_AIS_Msk (0x1UL << ETH_DMACxSR_AIS_Pos) /*!< 0x00004000 */
#define ETH_DMACxSR_AIS ETH_DMACxSR_AIS_Msk /* Abnormal Interrupt Summary */
#define ETH_DMACxSR_CDE_Pos (13U)
#define ETH_DMACxSR_CDE_Msk (0x1UL << ETH_DMACxSR_CDE_Pos) /*!< 0x00002000 */
#define ETH_DMACxSR_CDE ETH_DMACxSR_CDE_Msk /* Context Descriptor Error */
#define ETH_DMACxSR_FBE_Pos (12U)
#define ETH_DMACxSR_FBE_Msk (0x1UL << ETH_DMACxSR_FBE_Pos) /*!< 0x00001000 */
#define ETH_DMACxSR_FBE ETH_DMACxSR_FBE_Msk /* Fatal Bus Error */
#define ETH_DMACxSR_ERI_Pos (11U)
#define ETH_DMACxSR_ERI_Msk (0x1UL << ETH_DMACxSR_ERI_Pos) /*!< 0x00000800 */
#define ETH_DMACxSR_ERI ETH_DMACxSR_ERI_Msk /* Early Receive Interrupt */
#define ETH_DMACxSR_ETI_Pos (10U)
#define ETH_DMACxSR_ETI_Msk (0x1UL << ETH_DMACxSR_ETI_Pos) /*!< 0x00000400 */
#define ETH_DMACxSR_ETI ETH_DMACxSR_ETI_Msk /* Early Transmit Interrupt */
#define ETH_DMACxSR_RWT_Pos (9U)
#define ETH_DMACxSR_RWT_Msk (0x1UL << ETH_DMACxSR_RWT_Pos) /*!< 0x00000200 */
#define ETH_DMACxSR_RWT ETH_DMACxSR_RWT_Msk /* Receive Watchdog Timeout */
#define ETH_DMACxSR_RPS_Pos (8U)
#define ETH_DMACxSR_RPS_Msk (0x1UL << ETH_DMACxSR_RPS_Pos) /*!< 0x00000100 */
#define ETH_DMACxSR_RPS ETH_DMACxSR_RPS_Msk /* Receive Process Stopped */
#define ETH_DMACxSR_RBU_Pos (7U)
#define ETH_DMACxSR_RBU_Msk (0x1UL << ETH_DMACxSR_RBU_Pos) /*!< 0x00000080 */
#define ETH_DMACxSR_RBU ETH_DMACxSR_RBU_Msk /* Receive Buffer Unavailable */
#define ETH_DMACxSR_RI_Pos (6U)
#define ETH_DMACxSR_RI_Msk (0x1UL << ETH_DMACxSR_RI_Pos) /*!< 0x00000040 */
#define ETH_DMACxSR_RI ETH_DMACxSR_RI_Msk /* Receive Interrupt */
#define ETH_DMACxSR_TBU_Pos (2U)
#define ETH_DMACxSR_TBU_Msk (0x1UL << ETH_DMACxSR_TBU_Pos) /*!< 0x00000004 */
#define ETH_DMACxSR_TBU ETH_DMACxSR_TBU_Msk /* Transmit Buffer Unavailable */
#define ETH_DMACxSR_TPS_Pos (1U)
#define ETH_DMACxSR_TPS_Msk (0x1UL << ETH_DMACxSR_TPS_Pos) /*!< 0x00000002 */
#define ETH_DMACxSR_TPS ETH_DMACxSR_TPS_Msk /* Transmit Process Stopped */
#define ETH_DMACxSR_TI_Pos (0U)
#define ETH_DMACxSR_TI_Msk (0x1UL << ETH_DMACxSR_TI_Pos) /*!< 0x00000001 */
#define ETH_DMACxSR_TI ETH_DMACxSR_TI_Msk /* Transmit Interrupt */
/************ Bit definition for Ethernet DMA Channel x missed frame count Register ***************/
#define ETH_DMACxMFCR_MFCO_Pos (15U)
#define ETH_DMACxMFCR_MFCO_Msk (0x1UL << ETH_DMACxMFCR_MFCO_Pos) /*!< 0x00008000 */
#define ETH_DMACxMFCR_MFCO ETH_DMACxMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
#define ETH_DMACxMFCR_MFC_Pos (0U)
#define ETH_DMACxMFCR_MFC_Msk (0x7FFUL << ETH_DMACxMFCR_MFC_Pos) /*!< 0x000007FF */
#define ETH_DMACxMFCR_MFC ETH_DMACxMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_RTSR1 register *****************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger configuration for input line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger configuration for input line 21 */
/******************* Bit definition for EXTI_FTSR1 register *****************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger configuration for input line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger configuration for input line 21 */
/******************* Bit definition for EXTI_SWIER1 register ****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
/******************* Bit definition for EXTI_RPR1 register ******************/
#define EXTI_RPR1_RPIF0_Pos (0U)
#define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
#define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
#define EXTI_RPR1_RPIF1_Pos (1U)
#define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
#define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
#define EXTI_RPR1_RPIF2_Pos (2U)
#define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
#define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
#define EXTI_RPR1_RPIF3_Pos (3U)
#define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
#define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
#define EXTI_RPR1_RPIF4_Pos (4U)
#define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
#define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
#define EXTI_RPR1_RPIF5_Pos (5U)
#define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
#define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
#define EXTI_RPR1_RPIF6_Pos (6U)
#define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
#define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
#define EXTI_RPR1_RPIF7_Pos (7U)
#define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
#define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
#define EXTI_RPR1_RPIF8_Pos (8U)
#define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
#define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
#define EXTI_RPR1_RPIF9_Pos (9U)
#define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
#define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
#define EXTI_RPR1_RPIF10_Pos (10U)
#define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
#define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
#define EXTI_RPR1_RPIF11_Pos (11U)
#define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
#define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
#define EXTI_RPR1_RPIF12_Pos (12U)
#define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
#define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
#define EXTI_RPR1_RPIF13_Pos (13U)
#define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
#define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
#define EXTI_RPR1_RPIF14_Pos (14U)
#define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
#define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
#define EXTI_RPR1_RPIF15_Pos (15U)
#define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
#define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
#define EXTI_RPR1_RPIF20_Pos (20U)
#define EXTI_RPR1_RPIF20_Msk (0x1UL << EXTI_RPR1_RPIF20_Pos) /*!< 0x00020000 */
#define EXTI_RPR1_RPIF20 EXTI_RPR1_RPIF20_Msk /*!< Rising Pending Interrupt Flag on line 20 */
#define EXTI_RPR1_RPIF21_Pos (21U)
#define EXTI_RPR1_RPIF21_Msk (0x1UL << EXTI_RPR1_RPIF21_Pos) /*!< 0x00040000 */
#define EXTI_RPR1_RPIF21 EXTI_RPR1_RPIF21_Msk /*!< Rising Pending Interrupt Flag on line 21 */
/******************* Bit definition for EXTI_FPR1 register ******************/
#define EXTI_FPR1_FPIF0_Pos (0U)
#define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
#define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
#define EXTI_FPR1_FPIF1_Pos (1U)
#define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
#define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
#define EXTI_FPR1_FPIF2_Pos (2U)
#define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
#define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
#define EXTI_FPR1_FPIF3_Pos (3U)
#define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
#define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
#define EXTI_FPR1_FPIF4_Pos (4U)
#define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
#define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
#define EXTI_FPR1_FPIF5_Pos (5U)
#define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
#define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
#define EXTI_FPR1_FPIF6_Pos (6U)
#define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
#define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
#define EXTI_FPR1_FPIF7_Pos (7U)
#define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
#define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
#define EXTI_FPR1_FPIF8_Pos (8U)
#define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
#define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
#define EXTI_FPR1_FPIF9_Pos (9U)
#define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
#define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
#define EXTI_FPR1_FPIF10_Pos (10U)
#define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
#define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
#define EXTI_FPR1_FPIF11_Pos (11U)
#define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
#define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
#define EXTI_FPR1_FPIF12_Pos (12U)
#define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
#define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
#define EXTI_FPR1_FPIF13_Pos (13U)
#define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
#define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
#define EXTI_FPR1_FPIF14_Pos (14U)
#define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
#define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
#define EXTI_FPR1_FPIF15_Pos (15U)
#define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
#define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
#define EXTI_FPR1_FPIF20_Pos (20U)
#define EXTI_FPR1_FPIF20_Msk (0x1UL << EXTI_FPR1_FPIF20_Pos) /*!< 0x00020000 */
#define EXTI_FPR1_FPIF20 EXTI_FPR1_FPIF20_Msk /*!< Falling Pending Interrupt Flag on line 20 */
#define EXTI_FPR1_FPIF21_Pos (21U)
#define EXTI_FPR1_FPIF21_Msk (0x1UL << EXTI_FPR1_FPIF21_Pos) /*!< 0x00040000 */
#define EXTI_FPR1_FPIF21 EXTI_FPR1_FPIF21_Msk /*!< Falling Pending Interrupt Flag on line 21 */
/******************* Bit definition for EXTI_SECCFGR1 register ******************/
#define EXTI_SECCFGR1_SEC0_Pos (0U)
#define EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) /*!< 0x00000001 */
#define EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk /*!< Security enable on line 0 */
#define EXTI_SECCFGR1_SEC1_Pos (1U)
#define EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) /*!< 0x00000002 */
#define EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk /*!< Security enable on line 1 */
#define EXTI_SECCFGR1_SEC2_Pos (2U)
#define EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) /*!< 0x00000004 */
#define EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk /*!< Security enable on line 2 */
#define EXTI_SECCFGR1_SEC3_Pos (3U)
#define EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) /*!< 0x00000008 */
#define EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk /*!< Security enable on line 3 */
#define EXTI_SECCFGR1_SEC4_Pos (4U)
#define EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) /*!< 0x00000010 */
#define EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk /*!< Security enable on line 4 */
#define EXTI_SECCFGR1_SEC5_Pos (5U)
#define EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) /*!< 0x00000020 */
#define EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk /*!< Security enable on line 5 */
#define EXTI_SECCFGR1_SEC6_Pos (6U)
#define EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) /*!< 0x00000040 */
#define EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk /*!< Security enable on line 6 */
#define EXTI_SECCFGR1_SEC7_Pos (7U)
#define EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) /*!< 0x00000080 */
#define EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk /*!< Security enable on line 7 */
#define EXTI_SECCFGR1_SEC8_Pos (8U)
#define EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) /*!< 0x00000100 */
#define EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk /*!< Security enable on line 8 */
#define EXTI_SECCFGR1_SEC9_Pos (9U)
#define EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) /*!< 0x00000200 */
#define EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk /*!< Security enable on line 9 */
#define EXTI_SECCFGR1_SEC10_Pos (10U)
#define EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) /*!< 0x00000400 */
#define EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk /*!< Security enable on line 10 */
#define EXTI_SECCFGR1_SEC11_Pos (11U)
#define EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) /*!< 0x00000800 */
#define EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk /*!< Security enable on line 11 */
#define EXTI_SECCFGR1_SEC12_Pos (12U)
#define EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) /*!< 0x00001000 */
#define EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk /*!< Security enable on line 12 */
#define EXTI_SECCFGR1_SEC13_Pos (13U)
#define EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) /*!< 0x00002000 */
#define EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk /*!< Security enable on line 13 */
#define EXTI_SECCFGR1_SEC14_Pos (14U)
#define EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) /*!< 0x00004000 */
#define EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk /*!< Security enable on line 14 */
#define EXTI_SECCFGR1_SEC15_Pos (15U)
#define EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) /*!< 0x00008000 */
#define EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk /*!< Security enable on line 15 */
#define EXTI_SECCFGR1_SEC17_Pos (17U)
#define EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) /*!< 0x00020000 */
#define EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk /*!< Security enable on line 17 */
#define EXTI_SECCFGR1_SEC18_Pos (18U)
#define EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) /*!< 0x00040000 */
#define EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk /*!< Security enable on line 18 */
#define EXTI_SECCFGR1_SEC19_Pos (19U)
#define EXTI_SECCFGR1_SEC19_Msk (0x1UL << EXTI_SECCFGR1_SEC19_Pos) /*!< 0x00080000 */
#define EXTI_SECCFGR1_SEC19 EXTI_SECCFGR1_SEC19_Msk /*!< Security enable on line 19 */
#define EXTI_SECCFGR1_SEC20_Pos (20U)
#define EXTI_SECCFGR1_SEC20_Msk (0x1UL << EXTI_SECCFGR1_SEC20_Pos) /*!< 0x00100000 */
#define EXTI_SECCFGR1_SEC20 EXTI_SECCFGR1_SEC20_Msk /*!< Security enable on line 20 */
#define EXTI_SECCFGR1_SEC21_Pos (21U)
#define EXTI_SECCFGR1_SEC21_Msk (0x1UL << EXTI_SECCFGR1_SEC21_Pos) /*!< 0x00200000 */
#define EXTI_SECCFGR1_SEC21 EXTI_SECCFGR1_SEC21_Msk /*!< Security enable on line 21 */
#define EXTI_SECCFGR1_SEC22_Pos (22U)
#define EXTI_SECCFGR1_SEC22_Msk (0x1UL << EXTI_SECCFGR1_SEC22_Pos) /*!< 0x00400000 */
#define EXTI_SECCFGR1_SEC22 EXTI_SECCFGR1_SEC22_Msk /*!< Security enable on line 22 */
#define EXTI_SECCFGR1_SEC23_Pos (23U)
#define EXTI_SECCFGR1_SEC23_Msk (0x1UL << EXTI_SECCFGR1_SEC23_Pos) /*!< 0x00800000 */
#define EXTI_SECCFGR1_SEC23 EXTI_SECCFGR1_SEC23_Msk /*!< Security enable on line 23 */
#define EXTI_SECCFGR1_SEC24_Pos (24U)
#define EXTI_SECCFGR1_SEC24_Msk (0x1UL << EXTI_SECCFGR1_SEC24_Pos) /*!< 0x01000000 */
#define EXTI_SECCFGR1_SEC24 EXTI_SECCFGR1_SEC24_Msk /*!< Security enable on line 24 */
#define EXTI_SECCFGR1_SEC25_Pos (25U)
#define EXTI_SECCFGR1_SEC25_Msk (0x1UL << EXTI_SECCFGR1_SEC25_Pos) /*!< 0x02000000 */
#define EXTI_SECCFGR1_SEC25 EXTI_SECCFGR1_SEC25_Msk /*!< Security enable on line 25 */
#define EXTI_SECCFGR1_SEC26_Pos (26U)
#define EXTI_SECCFGR1_SEC26_Msk (0x1UL << EXTI_SECCFGR1_SEC26_Pos) /*!< 0x04000000 */
#define EXTI_SECCFGR1_SEC26 EXTI_SECCFGR1_SEC26_Msk /*!< Security enable on line 26 */
#define EXTI_SECCFGR1_SEC27_Pos (27U)
#define EXTI_SECCFGR1_SEC27_Msk (0x1UL << EXTI_SECCFGR1_SEC27_Pos) /*!< 0x08000000 */
#define EXTI_SECCFGR1_SEC27 EXTI_SECCFGR1_SEC27_Msk /*!< Security enable on line 27 */
#define EXTI_SECCFGR1_SEC28_Pos (28U)
#define EXTI_SECCFGR1_SEC28_Msk (0x1UL << EXTI_SECCFGR1_SEC28_Pos) /*!< 0x10000000 */
#define EXTI_SECCFGR1_SEC28 EXTI_SECCFGR1_SEC28_Msk /*!< Security enable on line 28 */
#define EXTI_SECCFGR1_SEC29_Pos (29U)
#define EXTI_SECCFGR1_SEC29_Msk (0x1UL << EXTI_SECCFGR1_SEC29_Pos) /*!< 0x20000000 */
#define EXTI_SECCFGR1_SEC29 EXTI_SECCFGR1_SEC29_Msk /*!< Security enable on line 29 */
#define EXTI_SECCFGR1_SEC30_Pos (30U)
#define EXTI_SECCFGR1_SEC30_Msk (0x1UL << EXTI_SECCFGR1_SEC30_Pos) /*!< 0x40000000 */
#define EXTI_SECCFGR1_SEC30 EXTI_SECCFGR1_SEC30_Msk /*!< Security enable on line 30 */
#define EXTI_SECCFGR1_SEC31_Pos (31U)
#define EXTI_SECCFGR1_SEC31_Msk (0x1UL << EXTI_SECCFGR1_SEC31_Pos) /*!< 0x80000000 */
#define EXTI_SECCFGR1_SEC31 EXTI_SECCFGR1_SEC31_Msk /*!< Security enable on line 31 */
/******************* Bit definition for EXTI_PRIVCFGR1 register ******************/
#define EXTI_PRIVCFGR1_PRIV0_Pos (0U)
#define EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) /*!< 0x00000001 */
#define EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk /*!< Privilege enable on line 0 */
#define EXTI_PRIVCFGR1_PRIV1_Pos (1U)
#define EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) /*!< 0x00000002 */
#define EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk /*!< Privilege enable on line 1 */
#define EXTI_PRIVCFGR1_PRIV2_Pos (2U)
#define EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) /*!< 0x00000004 */
#define EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk /*!< Privilege enable on line 2 */
#define EXTI_PRIVCFGR1_PRIV3_Pos (3U)
#define EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) /*!< 0x00000008 */
#define EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk /*!< Privilege enable on line 3 */
#define EXTI_PRIVCFGR1_PRIV4_Pos (4U)
#define EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) /*!< 0x00000010 */
#define EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk /*!< Privilege enable on line 4 */
#define EXTI_PRIVCFGR1_PRIV5_Pos (5U)
#define EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) /*!< 0x00000020 */
#define EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk /*!< Privilege enable on line 5 */
#define EXTI_PRIVCFGR1_PRIV6_Pos (6U)
#define EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) /*!< 0x00000040 */
#define EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk /*!< Privilege enable on line 6 */
#define EXTI_PRIVCFGR1_PRIV7_Pos (7U)
#define EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) /*!< 0x00000080 */
#define EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk /*!< Privilege enable on line 7 */
#define EXTI_PRIVCFGR1_PRIV8_Pos (8U)
#define EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) /*!< 0x00000100 */
#define EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk /*!< Privilege enable on line 8 */
#define EXTI_PRIVCFGR1_PRIV9_Pos (9U)
#define EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) /*!< 0x00000200 */
#define EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk /*!< Privilege enable on line 9 */
#define EXTI_PRIVCFGR1_PRIV10_Pos (10U)
#define EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) /*!< 0x00000400 */
#define EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk /*!< Privilege enable on line 10 */
#define EXTI_PRIVCFGR1_PRIV11_Pos (11U)
#define EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) /*!< 0x00000800 */
#define EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk /*!< Privilege enable on line 11 */
#define EXTI_PRIVCFGR1_PRIV12_Pos (12U)
#define EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) /*!< 0x00001000 */
#define EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk /*!< Privilege enable on line 12 */
#define EXTI_PRIVCFGR1_PRIV13_Pos (13U)
#define EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) /*!< 0x00002000 */
#define EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk /*!< Privilege enable on line 13 */
#define EXTI_PRIVCFGR1_PRIV14_Pos (14U)
#define EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) /*!< 0x00004000 */
#define EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk /*!< Privilege enable on line 14 */
#define EXTI_PRIVCFGR1_PRIV15_Pos (15U)
#define EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) /*!< 0x00008000 */
#define EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk /*!< Privilege enable on line 15 */
#define EXTI_PRIVCFGR1_PRIV17_Pos (17U)
#define EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) /*!< 0x00020000 */
#define EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk /*!< Privilege enable on line 17 */
#define EXTI_PRIVCFGR1_PRIV18_Pos (18U)
#define EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) /*!< 0x00040000 */
#define EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk /*!< Privilege enable on line 18 */
#define EXTI_PRIVCFGR1_PRIV19_Pos (19U)
#define EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) /*!< 0x00080000 */
#define EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk /*!< Privilege enable on line 19 */
#define EXTI_PRIVCFGR1_PRIV20_Pos (20U)
#define EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) /*!< 0x00100000 */
#define EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk /*!< Privilege enable on line 20 */
#define EXTI_PRIVCFGR1_PRIV21_Pos (21U)
#define EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) /*!< 0x00200000 */
#define EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk /*!< Privilege enable on line 21 */
#define EXTI_PRIVCFGR1_PRIV22_Pos (22U)
#define EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) /*!< 0x00400000 */
#define EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk /*!< Privilege enable on line 22 */
#define EXTI_PRIVCFGR1_PRIV23_Pos (23U)
#define EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) /*!< 0x00800000 */
#define EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk /*!< Privilege enable on line 23 */
#define EXTI_PRIVCFGR1_PRIV24_Pos (24U)
#define EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) /*!< 0x01000000 */
#define EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk /*!< Privilege enable on line 24 */
#define EXTI_PRIVCFGR1_PRIV25_Pos (25U)
#define EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) /*!< 0x02000000 */
#define EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk /*!< Privilege enable on line 25 */
#define EXTI_PRIVCFGR1_PRIV26_Pos (26U)
#define EXTI_PRIVCFGR1_PRIV26_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV26_Pos) /*!< 0x04000000 */
#define EXTI_PRIVCFGR1_PRIV26 EXTI_PRIVCFGR1_PRIV26_Msk /*!< Privilege enable on line 26 */
#define EXTI_PRIVCFGR1_PRIV27_Pos (27U)
#define EXTI_PRIVCFGR1_PRIV27_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV27_Pos) /*!< 0x08000000 */
#define EXTI_PRIVCFGR1_PRIV27 EXTI_PRIVCFGR1_PRIV27_Msk /*!< Privilege enable on line 27 */
#define EXTI_PRIVCFGR1_PRIV28_Pos (28U)
#define EXTI_PRIVCFGR1_PRIV28_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV28_Pos) /*!< 0x10000000 */
#define EXTI_PRIVCFGR1_PRIV28 EXTI_PRIVCFGR1_PRIV28_Msk /*!< Privilege enable on line 28 */
#define EXTI_PRIVCFGR1_PRIV29_Pos (29U)
#define EXTI_PRIVCFGR1_PRIV29_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV29_Pos) /*!< 0x20000000 */
#define EXTI_PRIVCFGR1_PRIV29 EXTI_PRIVCFGR1_PRIV29_Msk /*!< Privilege enable on line 29 */
#define EXTI_PRIVCFGR1_PRIV30_Pos (30U)
#define EXTI_PRIVCFGR1_PRIV30_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV30_Pos) /*!< 0x40000000 */
#define EXTI_PRIVCFGR1_PRIV30 EXTI_PRIVCFGR1_PRIV30_Msk /*!< Privilege enable on line 30 */
#define EXTI_PRIVCFGR1_PRIV31_Pos (31U)
#define EXTI_PRIVCFGR1_PRIV31_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV31_Pos) /*!< 0x80000000 */
#define EXTI_PRIVCFGR1_PRIV31 EXTI_PRIVCFGR1_PRIV31_Msk /*!< Privilege enable on line 31 */
/******************* Bit definition for EXTI_RTSR2 register *****************/
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger configuration for input line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger configuration for input line 40 */
#define EXTI_RTSR2_RT51_Pos (19U)
#define EXTI_RTSR2_RT51_Msk (0x1UL << EXTI_RTSR2_RT51_Pos) /*!< 0x00080000 */
#define EXTI_RTSR2_RT51 EXTI_RTSR2_RT51_Msk /*!< Rising trigger configuration for input line 51 */
#define EXTI_RTSR2_RT54_Pos (22U)
#define EXTI_RTSR2_RT54_Msk (0x1UL << EXTI_RTSR2_RT54_Pos) /*!< 0x00400000 */
#define EXTI_RTSR2_RT54 EXTI_RTSR2_RT54_Msk /*!< Rising trigger configuration for input line 54 */
#define EXTI_RTSR2_RT56_Pos (24U)
#define EXTI_RTSR2_RT56_Msk (0x1UL << EXTI_RTSR2_RT56_Pos) /*!< 0x00100000 */
#define EXTI_RTSR2_RT56 EXTI_RTSR2_RT56_Msk /*!< Rising trigger configuration for input line 56 */
/******************* Bit definition for EXTI_FTSR2 register *****************/
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger configuration for input line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger configuration for input line 40 */
#define EXTI_FTSR2_FT51_Pos (19U)
#define EXTI_FTSR2_FT51_Msk (0x1UL << EXTI_FTSR2_FT51_Pos) /*!< 0x00080000 */
#define EXTI_FTSR2_FT51 EXTI_FTSR2_FT51_Msk /*!< Falling trigger configuration for input line 51 */
#define EXTI_FTSR2_FT54_Pos (22U)
#define EXTI_FTSR2_FT54_Msk (0x1UL << EXTI_FTSR2_FT54_Pos) /*!< 0x00400000 */
#define EXTI_FTSR2_FT54 EXTI_FTSR2_FT54_Msk /*!< Falling trigger configuration for input line 54 */
#define EXTI_FTSR2_FT56_Pos (24U)
#define EXTI_FTSR2_FT56_Msk (0x1UL << EXTI_FTSR2_FT56_Pos) /*!< 0x00100000 */
#define EXTI_FTSR2_FT56 EXTI_FTSR2_FT56_Msk /*!< Falling trigger configuration for input line 56 */
/******************* Bit definition for EXTI_SWIER2 register ****************/
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI51_Pos (19U)
#define EXTI_SWIER2_SWI51_Msk (0x1UL << EXTI_SWIER2_SWI51_Pos) /*!< 0x00080000 */
#define EXTI_SWIER2_SWI51 EXTI_SWIER2_SWI51_Msk /*!< Software Interrupt on line 51 */
#define EXTI_SWIER2_SWI54_Pos (22U)
#define EXTI_SWIER2_SWI54_Msk (0x1UL << EXTI_SWIER2_SWI54_Pos) /*!< 0x00400000 */
#define EXTI_SWIER2_SWI54 EXTI_SWIER2_SWI54_Msk /*!< Software Interrupt on line 54 */
#define EXTI_SWIER2_SWI56_Pos (24U)
#define EXTI_SWIER2_SWI56_Msk (0x1UL << EXTI_SWIER2_SWI56_Pos) /*!< 0x00100000 */
#define EXTI_SWIER2_SWI56 EXTI_SWIER2_SWI56_Msk /*!< Software Interrupt on line 56 */
/******************* Bit definition for EXTI_RPR2 register ******************/
#define EXTI_RPR2_RPIF39_Pos (7U)
#define EXTI_RPR2_RPIF39_Msk (0x1UL << EXTI_RPR2_RPIF39_Pos) /*!< 0x00000080 */
#define EXTI_RPR2_RPIF39 EXTI_RPR2_RPIF39_Msk /*!< Rising Pending Interrupt Flag on line 39 */
#define EXTI_RPR2_RPIF40_Pos (8U)
#define EXTI_RPR2_RPIF40_Msk (0x1UL << EXTI_RPR2_RPIF40_Pos) /*!< 0x00000100 */
#define EXTI_RPR2_RPIF40 EXTI_RPR2_RPIF40_Msk /*!< Rising Pending Interrupt Flag on line 40 */
#define EXTI_RPR2_RPIF51_Pos (19U)
#define EXTI_RPR2_RPIF51_Msk (0x1UL << EXTI_RPR2_RPIF51_Pos) /*!< 0x00080000 */
#define EXTI_RPR2_RPIF51 EXTI_RPR2_RPIF51_Msk /*!< Rising Pending Interrupt Flag on line 51 */
#define EXTI_RPR2_RPIF54_Pos (22U)
#define EXTI_RPR2_RPIF54_Msk (0x1UL << EXTI_RPR2_RPIF54_Pos) /*!< 0x00400000 */
#define EXTI_RPR2_RPIF54 EXTI_RPR2_RPIF54_Msk /*!< Rising Pending Interrupt Flag on line 54 */
#define EXTI_RPR2_RPIF56_Pos (24U)
#define EXTI_RPR2_RPIF56_Msk (0x1UL << EXTI_RPR2_RPIF56_Pos) /*!< 0x00100000 */
#define EXTI_RPR2_RPIF56 EXTI_RPR2_RPIF56_Msk /*!< Rising Pending Interrupt Flag on line 56 */
/******************* Bit definition for EXTI_FPR2 register ******************/
#define EXTI_FPR2_FPIF39_Pos (7U)
#define EXTI_FPR2_FPIF39_Msk (0x1UL << EXTI_FPR2_FPIF39_Pos) /*!< 0x00000080 */
#define EXTI_FPR2_FPIF39 EXTI_FPR2_FPIF39_Msk /*!< Falling Pending Interrupt Flag on line 39 */
#define EXTI_FPR2_FPIF40_Pos (8U)
#define EXTI_FPR2_FPIF40_Msk (0x1UL << EXTI_FPR2_FPIF40_Pos) /*!< 0x00000100 */
#define EXTI_FPR2_FPIF40 EXTI_FPR2_FPIF40_Msk /*!< Falling Pending Interrupt Flag on line 40 */
#define EXTI_FPR2_FPIF51_Pos (19U)
#define EXTI_FPR2_FPIF51_Msk (0x1UL << EXTI_FPR2_FPIF51_Pos) /*!< 0x00080000 */
#define EXTI_FPR2_FPIF51 EXTI_FPR2_FPIF51_Msk /*!< Falling Pending Interrupt Flag on line 51 */
#define EXTI_FPR2_FPIF54_Pos (22U)
#define EXTI_FPR2_FPIF54_Msk (0x1UL << EXTI_FPR2_FPIF54_Pos) /*!< 0x00400000 */
#define EXTI_FPR2_FPIF54 EXTI_FPR2_FPIF54_Msk /*!< Falling Pending Interrupt Flag on line 54 */
#define EXTI_FPR2_FPIF56_Pos (24U)
#define EXTI_FPR2_FPIF56_Msk (0x1UL << EXTI_FPR2_FPIF56_Pos) /*!< 0x00100000 */
#define EXTI_FPR2_FPIF56 EXTI_FPR2_FPIF56_Msk /*!< Falling Pending Interrupt Flag on line 56 */
/******************* Bit definition for EXTI_SECCFGR2 register ******************/
#define EXTI_SECCFGR2_SEC32_Pos (0U)
#define EXTI_SECCFGR2_SEC32_Msk (0x1UL << EXTI_SECCFGR2_SEC32_Pos) /*!< 0x00000001 */
#define EXTI_SECCFGR2_SEC32 EXTI_SECCFGR2_SEC32_Msk /*!< Security enable on line 32 */
#define EXTI_SECCFGR2_SEC33_Pos (1U)
#define EXTI_SECCFGR2_SEC33_Msk (0x1UL << EXTI_SECCFGR2_SEC33_Pos) /*!< 0x00000002 */
#define EXTI_SECCFGR2_SEC33 EXTI_SECCFGR2_SEC33_Msk /*!< Security enable on line 33 */
#define EXTI_SECCFGR2_SEC34_Pos (2U)
#define EXTI_SECCFGR2_SEC34_Msk (0x1UL << EXTI_SECCFGR2_SEC34_Pos) /*!< 0x00000004 */
#define EXTI_SECCFGR2_SEC34 EXTI_SECCFGR2_SEC34_Msk /*!< Security enable on line 34 */
#define EXTI_SECCFGR2_SEC35_Pos (3U)
#define EXTI_SECCFGR2_SEC35_Msk (0x1UL << EXTI_SECCFGR2_SEC35_Pos) /*!< 0x00000008 */
#define EXTI_SECCFGR2_SEC35 EXTI_SECCFGR2_SEC35_Msk /*!< Security enable on line 35 */
#define EXTI_SECCFGR2_SEC36_Pos (4U)
#define EXTI_SECCFGR2_SEC36_Msk (0x1UL << EXTI_SECCFGR2_SEC36_Pos) /*!< 0x00000010 */
#define EXTI_SECCFGR2_SEC36 EXTI_SECCFGR2_SEC36_Msk /*!< Security enable on line 36 */
#define EXTI_SECCFGR2_SEC37_Pos (5U)
#define EXTI_SECCFGR2_SEC37_Msk (0x1UL << EXTI_SECCFGR2_SEC37_Pos) /*!< 0x00000020 */
#define EXTI_SECCFGR2_SEC37 EXTI_SECCFGR2_SEC37_Msk /*!< Security enable on line 37 */
#define EXTI_SECCFGR2_SEC38_Pos (6U)
#define EXTI_SECCFGR2_SEC38_Msk (0x1UL << EXTI_SECCFGR2_SEC38_Pos) /*!< 0x00000040 */
#define EXTI_SECCFGR2_SEC38 EXTI_SECCFGR2_SEC38_Msk /*!< Security enable on line 38 */
#define EXTI_SECCFGR2_SEC39_Pos (7U)
#define EXTI_SECCFGR2_SEC39_Msk (0x1UL << EXTI_SECCFGR2_SEC39_Pos) /*!< 0x00000080 */
#define EXTI_SECCFGR2_SEC39 EXTI_SECCFGR2_SEC39_Msk /*!< Security enable on line 39 */
#define EXTI_SECCFGR2_SEC40_Pos (8U)
#define EXTI_SECCFGR2_SEC40_Msk (0x1UL << EXTI_SECCFGR2_SEC40_Pos) /*!< 0x00000100 */
#define EXTI_SECCFGR2_SEC40 EXTI_SECCFGR2_SEC40_Msk /*!< Security enable on line 40 */
#define EXTI_SECCFGR2_SEC41_Pos (9U)
#define EXTI_SECCFGR2_SEC41_Msk (0x1UL << EXTI_SECCFGR2_SEC41_Pos) /*!< 0x00000200 */
#define EXTI_SECCFGR2_SEC41 EXTI_SECCFGR2_SEC41_Msk /*!< Security enable on line 41 */
#define EXTI_SECCFGR2_SEC42_Pos (10U)
#define EXTI_SECCFGR2_SEC42_Msk (0x1UL << EXTI_SECCFGR2_SEC42_Pos) /*!< 0x00000400 */
#define EXTI_SECCFGR2_SEC42 EXTI_SECCFGR2_SEC42_Msk /*!< Security enable on line 42 */
#define EXTI_SECCFGR2_SEC43_Pos (11U)
#define EXTI_SECCFGR2_SEC43_Msk (0x1UL << EXTI_SECCFGR2_SEC43_Pos) /*!< 0x00000800 */
#define EXTI_SECCFGR2_SEC43 EXTI_SECCFGR2_SEC43_Msk /*!< Security enable on line 43 */
#define EXTI_SECCFGR2_SEC44_Pos (12U)
#define EXTI_SECCFGR2_SEC44_Msk (0x1UL << EXTI_SECCFGR2_SEC44_Pos) /*!< 0x00001000 */
#define EXTI_SECCFGR2_SEC44 EXTI_SECCFGR2_SEC44_Msk /*!< Security enable on line 44 */
#define EXTI_SECCFGR2_SEC45_Pos (13U)
#define EXTI_SECCFGR2_SEC45_Msk (0x1UL << EXTI_SECCFGR2_SEC45_Pos) /*!< 0x00002000 */
#define EXTI_SECCFGR2_SEC45 EXTI_SECCFGR2_SEC45 /*!< Security enable on line 45 */
#define EXTI_SECCFGR2_SEC46_Pos (14U)
#define EXTI_SECCFGR2_SEC46_Msk (0x1UL << EXTI_SECCFGR2_SEC46_Pos) /*!< 0x00004000 */
#define EXTI_SECCFGR2_SEC46 EXTI_SECCFGR2_SEC46_Msk /*!< Security enable on line 46 */
#define EXTI_SECCFGR2_SEC47_Pos (15U)
#define EXTI_SECCFGR2_SEC47_Msk (0x1UL << EXTI_SECCFGR2_SEC47_Pos) /*!< 0x00008000 */
#define EXTI_SECCFGR2_SEC47 EXTI_SECCFGR2_SEC47_Msk /*!< Security enable on line 47 */
#define EXTI_SECCFGR2_SEC48_Pos (16U)
#define EXTI_SECCFGR2_SEC48_Msk (0x1UL << EXTI_SECCFGR2_SEC48_Pos) /*!< 0x00010000 */
#define EXTI_SECCFGR2_SEC48 EXTI_SECCFGR2_SEC48_Msk /*!< Security enable on line 48 */
#define EXTI_SECCFGR2_SEC49_Pos (17U)
#define EXTI_SECCFGR2_SEC49_Msk (0x1UL << EXTI_SECCFGR2_SEC49_Pos) /*!< 0x00020000 */
#define EXTI_SECCFGR2_SEC49 EXTI_SECCFGR2_SEC49_Msk /*!< Security enable on line 49 */
#define EXTI_SECCFGR2_SEC50_Pos (18U)
#define EXTI_SECCFGR2_SEC50_Msk (0x1UL << EXTI_SECCFGR2_SEC50_Pos) /*!< 0x00040000 */
#define EXTI_SECCFGR2_SEC50 EXTI_SECCFGR2_SEC50_Msk /*!< Security enable on line 50 */
#define EXTI_SECCFGR2_SEC51_Pos (19U)
#define EXTI_SECCFGR2_SEC51_Msk (0x1UL << EXTI_SECCFGR2_SEC51_Pos) /*!< 0x00080000 */
#define EXTI_SECCFGR2_SEC51 EXTI_SECCFGR2_SEC51_Msk /*!< Security enable on line 51 */
#define EXTI_SECCFGR2_SEC52_Pos (20U)
#define EXTI_SECCFGR2_SEC52_Msk (0x1UL << EXTI_SECCFGR2_SEC52_Pos) /*!< 0x00100000 */
#define EXTI_SECCFGR2_SEC52 EXTI_SECCFGR2_SEC52_Msk /*!< Security enable on line 52 */
#define EXTI_SECCFGR2_SEC53_Pos (21U)
#define EXTI_SECCFGR2_SEC53_Msk (0x1UL << EXTI_SECCFGR2_SEC53_Pos) /*!< 0x00200000 */
#define EXTI_SECCFGR2_SEC53 EXTI_SECCFGR2_SEC53_Msk /*!< Security enable on line 53 */
#define EXTI_SECCFGR2_SEC54_Pos (22U)
#define EXTI_SECCFGR2_SEC54_Msk (0x1UL << EXTI_SECCFGR2_SEC54_Pos) /*!< 0x00400000 */
#define EXTI_SECCFGR2_SEC54 EXTI_SECCFGR2_SEC54_Msk /*!< Security enable on line 54 */
#define EXTI_SECCFGR2_SEC55_Pos (23U)
#define EXTI_SECCFGR2_SEC55_Msk (0x1UL << EXTI_SECCFGR2_SEC55_Pos) /*!< 0x00800000 */
#define EXTI_SECCFGR2_SEC55 EXTI_SECCFGR2_SEC55_Msk /*!< Security enable on line 55 */
#define EXTI_SECCFGR2_SEC56_Pos (24U)
#define EXTI_SECCFGR2_SEC56_Msk (0x1UL << EXTI_SECCFGR2_SEC56_Pos) /*!< 0x01000000 */
#define EXTI_SECCFGR2_SEC56 EXTI_SECCFGR2_SEC56_Msk /*!< Security enable on line 56 */
#define EXTI_SECCFGR2_SEC57_Pos (25U)
#define EXTI_SECCFGR2_SEC57_Msk (0x1UL << EXTI_SECCFGR2_SEC57_Pos) /*!< 0x02000000 */
#define EXTI_SECCFGR2_SEC57 EXTI_SECCFGR2_SEC57_Msk /*!< Security enable on line 57 */
#define EXTI_SECCFGR2_SEC58_Pos (26U)
#define EXTI_SECCFGR2_SEC58_Msk (0x1UL << EXTI_SECCFGR2_SEC58_Pos) /*!< 0x04000000 */
#define EXTI_SECCFGR2_SEC58 EXTI_SECCFGR2_SEC58_Msk /*!< Security enable on line 58 */
#define EXTI_SECCFGR2_SEC60_Pos (28U)
#define EXTI_SECCFGR2_SEC60_Msk (0x1UL << EXTI_SECCFGR2_SEC60_Pos) /*!< 0x10000000 */
#define EXTI_SECCFGR2_SEC60 EXTI_SECCFGR2_SEC60_Msk /*!< Security enable on line 60 */
#define EXTI_SECCFGR2_SEC61_Pos (29U)
#define EXTI_SECCFGR2_SEC61_Msk (0x1UL << EXTI_SECCFGR2_SEC61_Pos) /*!< 0x20000000 */
#define EXTI_SECCFGR2_SEC61 EXTI_SECCFGR2_SEC61_Msk /*!< Security enable on line 61 */
#define EXTI_SECCFGR2_SEC62_Pos (30U)
#define EXTI_SECCFGR2_SEC62_Msk (0x1UL << EXTI_SECCFGR2_SEC62_Pos) /*!< 0x40000000 */
#define EXTI_SECCFGR2_SEC62 EXTI_SECCFGR2_SEC62_Msk /*!< Security enable on line 62 */
#define EXTI_SECCFGR2_SEC63_Pos (31U)
#define EXTI_SECCFGR2_SEC63_Msk (0x1UL << EXTI_SECCFGR2_SEC63_Pos) /*!< 0x80000000 */
#define EXTI_SECCFGR2_SEC63 EXTI_SECCFGR2_SEC63_Msk /*!< Security enable on line 63 */
/******************* Bit definition for EXTI_PRIVCFGR2 register ******************/
#define EXTI_PRIVCFGR2_PRIV32_Pos (0U)
#define EXTI_PRIVCFGR2_PRIV32_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV32_Pos) /*!< 0x00000001 */
#define EXTI_PRIVCFGR2_PRIV32 EXTI_PRIVCFGR2_PRIV32_Msk /*!< Privilege enable on line 32 */
#define EXTI_PRIVCFGR2_PRIV33_Pos (1U)
#define EXTI_PRIVCFGR2_PRIV33_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV33_Pos) /*!< 0x00000002 */
#define EXTI_PRIVCFGR2_PRIV33 EXTI_PRIVCFGR2_PRIV33_Msk /*!< Privilege enable on line 33 */
#define EXTI_PRIVCFGR2_PRIV34_Pos (2U)
#define EXTI_PRIVCFGR2_PRIV34_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV34_Pos) /*!< 0x00000004 */
#define EXTI_PRIVCFGR2_PRIV34 EXTI_PRIVCFGR2_PRIV34_Msk /*!< Privilege enable on line 34 */
#define EXTI_PRIVCFGR2_PRIV35_Pos (3U)
#define EXTI_PRIVCFGR2_PRIV35_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV35_Pos) /*!< 0x00000008 */
#define EXTI_PRIVCFGR2_PRIV35 EXTI_PRIVCFGR2_PRIV35_Msk /*!< Privilege enable on line 35 */
#define EXTI_PRIVCFGR2_PRIV36_Pos (4U)
#define EXTI_PRIVCFGR2_PRIV36_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV36_Pos) /*!< 0x00000010 */
#define EXTI_PRIVCFGR2_PRIV36 EXTI_PRIVCFGR2_PRIV36_Msk /*!< Privilege enable on line 36 */
#define EXTI_PRIVCFGR2_PRIV37_Pos (5U)
#define EXTI_PRIVCFGR2_PRIV37_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV37_Pos) /*!< 0x00000020 */
#define EXTI_PRIVCFGR2_PRIV37 EXTI_PRIVCFGR2_PRIV37_Msk /*!< Privilege enable on line 37 */
#define EXTI_PRIVCFGR2_PRIV38_Pos (6U)
#define EXTI_PRIVCFGR2_PRIV38_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV38_Pos) /*!< 0x00000040 */
#define EXTI_PRIVCFGR2_PRIV38 EXTI_PRIVCFGR2_PRIV38_Msk /*!< Privilege enable on line 38 */
#define EXTI_PRIVCFGR2_PRIV39_Pos (7U)
#define EXTI_PRIVCFGR2_PRIV39_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV39_Pos) /*!< 0x00000080 */
#define EXTI_PRIVCFGR2_PRIV39 EXTI_PRIVCFGR2_PRIV39_Msk /*!< Privilege enable on line 39 */
#define EXTI_PRIVCFGR2_PRIV40_Pos (8U)
#define EXTI_PRIVCFGR2_PRIV40_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV40_Pos) /*!< 0x00000100 */
#define EXTI_PRIVCFGR2_PRIV40 EXTI_PRIVCFGR2_PRIV40_Msk /*!< Privilege enable on line 40 */
#define EXTI_PRIVCFGR2_PRIV41_Pos (9U)
#define EXTI_PRIVCFGR2_PRIV41_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV41_Pos) /*!< 0x00000200 */
#define EXTI_PRIVCFGR2_PRIV41 EXTI_PRIVCFGR2_PRIV41_Msk /*!< Privilege enable on line 41 */
#define EXTI_PRIVCFGR2_PRIV42_Pos (10U)
#define EXTI_PRIVCFGR2_PRIV42_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV42_Pos) /*!< 0x00000400 */
#define EXTI_PRIVCFGR2_PRIV42 EXTI_PRIVCFGR2_PRIV42_Msk /*!< Privilege enable on line 42 */
#define EXTI_PRIVCFGR2_PRIV43_Pos (11U)
#define EXTI_PRIVCFGR2_PRIV43_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV43_Pos) /*!< 0x00000800 */
#define EXTI_PRIVCFGR2_PRIV43 EXTI_PRIVCFGR2_PRIV43_Msk /*!< Privilege enable on line 43 */
#define EXTI_PRIVCFGR2_PRIV44_Pos (12U)
#define EXTI_PRIVCFGR2_PRIV44_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV44_Pos) /*!< 0x00001000 */
#define EXTI_PRIVCFGR2_PRIV44 EXTI_PRIVCFGR2_PRIV44_Msk /*!< Privilege enable on line 44 */
#define EXTI_PRIVCFGR2_PRIV45_Pos (13U)
#define EXTI_PRIVCFGR2_PRIV45_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV45_Pos) /*!< 0x00002000 */
#define EXTI_PRIVCFGR2_PRIV45 EXTI_PRIVCFGR2_PRIV45 /*!< Privilege enable on line 45 */
#define EXTI_PRIVCFGR2_PRIV46_Pos (14U)
#define EXTI_PRIVCFGR2_PRIV46_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV46_Pos) /*!< 0x00004000 */
#define EXTI_PRIVCFGR2_PRIV46 EXTI_PRIVCFGR2_PRIV46_Msk /*!< Privilege enable on line 46 */
#define EXTI_PRIVCFGR2_PRIV47_Pos (15U)
#define EXTI_PRIVCFGR2_PRIV47_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV47_Pos) /*!< 0x00008000 */
#define EXTI_PRIVCFGR2_PRIV47 EXTI_PRIVCFGR2_PRIV47_Msk /*!< Privilege enable on line 47 */
#define EXTI_PRIVCFGR2_PRIV48_Pos (16U)
#define EXTI_PRIVCFGR2_PRIV48_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV48_Pos) /*!< 0x00010000 */
#define EXTI_PRIVCFGR2_PRIV48 EXTI_PRIVCFGR2_PRIV48_Msk /*!< Privilege enable on line 48 */
#define EXTI_PRIVCFGR2_PRIV49_Pos (17U)
#define EXTI_PRIVCFGR2_PRIV49_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV49_Pos) /*!< 0x00020000 */
#define EXTI_PRIVCFGR2_PRIV49 EXTI_PRIVCFGR2_PRIV49_Msk /*!< Privilege enable on line 49 */
#define EXTI_PRIVCFGR2_PRIV50_Pos (18U)
#define EXTI_PRIVCFGR2_PRIV50_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV50_Pos) /*!< 0x00040000 */
#define EXTI_PRIVCFGR2_PRIV50 EXTI_PRIVCFGR2_PRIV50_Msk /*!< Privilege enable on line 50 */
#define EXTI_PRIVCFGR2_PRIV51_Pos (19U)
#define EXTI_PRIVCFGR2_PRIV51_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV51_Pos) /*!< 0x00080000 */
#define EXTI_PRIVCFGR2_PRIV51 EXTI_PRIVCFGR2_PRIV51_Msk /*!< Privilege enable on line 51 */
#define EXTI_PRIVCFGR2_PRIV52_Pos (20U)
#define EXTI_PRIVCFGR2_PRIV52_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV52_Pos) /*!< 0x00100000 */
#define EXTI_PRIVCFGR2_PRIV52 EXTI_PRIVCFGR2_PRIV52_Msk /*!< Privilege enable on line 52 */
#define EXTI_PRIVCFGR2_PRIV53_Pos (21U)
#define EXTI_PRIVCFGR2_PRIV53_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV53_Pos) /*!< 0x00200000 */
#define EXTI_PRIVCFGR2_PRIV53 EXTI_PRIVCFGR2_PRIV53_Msk /*!< Privilege enable on line 53 */
#define EXTI_PRIVCFGR2_PRIV54_Pos (22U)
#define EXTI_PRIVCFGR2_PRIV54_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV54_Pos) /*!< 0x00400000 */
#define EXTI_PRIVCFGR2_PRIV54 EXTI_PRIVCFGR2_PRIV54_Msk /*!< Privilege enable on line 54 */
#define EXTI_PRIVCFGR2_PRIV55_Pos (23U)
#define EXTI_PRIVCFGR2_PRIV55_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV55_Pos) /*!< 0x00800000 */
#define EXTI_PRIVCFGR2_PRIV55 EXTI_PRIVCFGR2_PRIV55_Msk /*!< Privilege enable on line 55 */
#define EXTI_PRIVCFGR2_PRIV56_Pos (24U)
#define EXTI_PRIVCFGR2_PRIV56_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV56_Pos) /*!< 0x01000000 */
#define EXTI_PRIVCFGR2_PRIV56 EXTI_PRIVCFGR2_PRIV56_Msk /*!< Privilege enable on line 56 */
#define EXTI_PRIVCFGR2_PRIV57_Pos (25U)
#define EXTI_PRIVCFGR2_PRIV57_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV57_Pos) /*!< 0x02000000 */
#define EXTI_PRIVCFGR2_PRIV57 EXTI_PRIVCFGR2_PRIV57_Msk /*!< Privilege enable on line 57 */
#define EXTI_PRIVCFGR2_PRIV58_Pos (26U)
#define EXTI_PRIVCFGR2_PRIV58_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV58_Pos) /*!< 0x04000000 */
#define EXTI_PRIVCFGR2_PRIV58 EXTI_PRIVCFGR2_PRIV58_Msk /*!< Privilege enable on line 58 */
#define EXTI_PRIVCFGR2_PRIV60_Pos (28U)
#define EXTI_PRIVCFGR2_PRIV60_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV60_Pos) /*!< 0x10000000 */
#define EXTI_PRIVCFGR2_PRIV60 EXTI_PRIVCFGR2_PRIV60_Msk /*!< Privilege enable on line 60 */
#define EXTI_PRIVCFGR2_PRIV61_Pos (29U)
#define EXTI_PRIVCFGR2_PRIV61_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV61_Pos) /*!< 0x20000000 */
#define EXTI_PRIVCFGR2_PRIV61 EXTI_PRIVCFGR2_PRIV61_Msk /*!< Privilege enable on line 61 */
#define EXTI_PRIVCFGR2_PRIV62_Pos (30U)
#define EXTI_PRIVCFGR2_PRIV62_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV62_Pos) /*!< 0x40000000 */
#define EXTI_PRIVCFGR2_PRIV62 EXTI_PRIVCFGR2_PRIV62_Msk /*!< Privilege enable on line 62 */
#define EXTI_PRIVCFGR2_PRIV63_Pos (31U)
#define EXTI_PRIVCFGR2_PRIV63_Msk (0x1UL << EXTI_PRIVCFGR2_PRIV63_Pos) /*!< 0x80000000 */
#define EXTI_PRIVCFGR2_PRIV63 EXTI_PRIVCFGR2_PRIV63_Msk /*!< Privilege enable on line 63 */
/******************* Bit definition for EXTI_RTSR3 register *****************/
#define EXTI_RTSR3_RT66_Pos (2U)
#define EXTI_RTSR3_RT66_Msk (0x1UL << EXTI_RTSR3_RT66_Pos) /*!< 0x00000004 */
#define EXTI_RTSR3_RT66 EXTI_RTSR3_RT66_Msk /*!< Rising trigger configuration for input line 66 */
#define EXTI_RTSR3_RT68_Pos (4U)
#define EXTI_RTSR3_RT68_Msk (0x1UL << EXTI_RTSR3_RT68_Pos) /*!< 0x00000010 */
#define EXTI_RTSR3_RT68 EXTI_RTSR3_RT68_Msk /*!< Rising trigger configuration for input line 68 */
#define EXTI_RTSR3_RT69_Pos (5U)
#define EXTI_RTSR3_RT69_Msk (0x1UL << EXTI_RTSR3_RT69_Pos) /*!< 0x00000020 */
#define EXTI_RTSR3_RT69 EXTI_RTSR3_RT69_Msk /*!< Rising trigger configuration for input line 69 */
#define EXTI_RTSR3_RT70_Pos (6U)
#define EXTI_RTSR3_RT70_Msk (0x1UL << EXTI_RTSR3_RT70_Pos) /*!< 0x00000040 */
#define EXTI_RTSR3_RT70 EXTI_RTSR3_RT70_Msk /*!< Rising trigger configuration for input line 70 */
#define EXTI_RTSR3_RT71_Pos (7U)
#define EXTI_RTSR3_RT71_Msk (0x1UL << EXTI_RTSR3_RT71_Pos) /*!< 0x00000080 */
#define EXTI_RTSR3_RT71 EXTI_RTSR3_RT71_Msk /*!< Rising trigger configuration for input line 71 */
#define EXTI_RTSR3_RT72_Pos (8U)
#define EXTI_RTSR3_RT72_Msk (0x1UL << EXTI_RTSR3_RT72_Pos) /*!< 0x00000100 */
#define EXTI_RTSR3_RT72 EXTI_RTSR3_RT72_Msk /*!< Rising trigger configuration for input line 72 */
#define EXTI_RTSR3_RT73_Pos (9U)
#define EXTI_RTSR3_RT73_Msk (0x1UL << EXTI_RTSR3_RT73_Pos) /*!< 0x00000200 */
#define EXTI_RTSR3_RT73 EXTI_RTSR3_RT73_Msk /*!< Rising trigger configuration for input line 73 */
#define EXTI_RTSR3_RT74_Pos (10U)
#define EXTI_RTSR3_RT74_Msk (0x1UL << EXTI_RTSR3_RT74_Pos) /*!< 0x00000400 */
#define EXTI_RTSR3_RT74 EXTI_RTSR3_RT74_Msk /*!< Rising trigger configuration for input line 74 */
/******************* Bit definition for EXTI_FTSR3 register *****************/
#define EXTI_FTSR3_FT66_Pos (2U)
#define EXTI_FTSR3_FT66_Msk (0x1UL << EXTI_FTSR3_FT66_Pos) /*!< 0x00000004 */
#define EXTI_FTSR3_FT66 EXTI_FTSR3_FT66_Msk /*!< Falling trigger configuration for input line 66 */
#define EXTI_FTSR3_FT68_Pos (4U)
#define EXTI_FTSR3_FT68_Msk (0x1UL << EXTI_FTSR3_FT68_Pos) /*!< 0x00000010 */
#define EXTI_FTSR3_FT68 EXTI_FTSR3_FT68_Msk /*!< Falling trigger configuration for input line 68 */
#define EXTI_FTSR3_FT69_Pos (5U)
#define EXTI_FTSR3_FT69_Msk (0x1UL << EXTI_FTSR3_FT69_Pos) /*!< 0x00000020 */
#define EXTI_FTSR3_FT69 EXTI_FTSR3_FT69_Msk /*!< Falling trigger configuration for input line 69 */
#define EXTI_FTSR3_FT70_Pos (6U)
#define EXTI_FTSR3_FT70_Msk (0x1UL << EXTI_FTSR3_FT70_Pos) /*!< 0x00000040 */
#define EXTI_FTSR3_FT70 EXTI_FTSR3_FT70_Msk /*!< Falling trigger configuration for input line 70 */
#define EXTI_FTSR3_FT71_Pos (7U)
#define EXTI_FTSR3_FT71_Msk (0x1UL << EXTI_FTSR3_FT71_Pos) /*!< 0x00000080 */
#define EXTI_FTSR3_FT71 EXTI_FTSR3_FT71_Msk /*!< Falling trigger configuration for input line 71 */
#define EXTI_FTSR3_FT72_Pos (8U)
#define EXTI_FTSR3_FT72_Msk (0x1UL << EXTI_FTSR3_FT72_Pos) /*!< 0x00000100 */
#define EXTI_FTSR3_FT72 EXTI_FTSR3_FT72_Msk /*!< Falling trigger configuration for input line 72 */
#define EXTI_FTSR3_FT73_Pos (9U)
#define EXTI_FTSR3_FT73_Msk (0x1UL << EXTI_FTSR3_FT73_Pos) /*!< 0x00000200 */
#define EXTI_FTSR3_FT73 EXTI_FTSR3_FT73_Msk /*!< Falling trigger configuration for input line 73 */
#define EXTI_FTSR3_FT74_Pos (10U)
#define EXTI_FTSR3_FT74_Msk (0x1UL << EXTI_FTSR3_FT74_Pos) /*!< 0x00000400 */
#define EXTI_FTSR3_FT74 EXTI_FTSR3_FT74_Msk /*!< Falling trigger configuration for input line 74 */
/******************* Bit definition for EXTI_SWIER3 register ****************/
#define EXTI_SWIER3_SWI66_Pos (2U)
#define EXTI_SWIER3_SWI66_Msk (0x1UL << EXTI_SWIER3_SWI66_Pos) /*!< 0x00000004 */
#define EXTI_SWIER3_SWI66 EXTI_SWIER3_SWI66_Msk /*!< Software Interrupt on line 66 */
#define EXTI_SWIER3_SWI68_Pos (4U)
#define EXTI_SWIER3_SWI68_Msk (0x1UL << EXTI_SWIER3_SWI68_Pos) /*!< 0x00000010 */
#define EXTI_SWIER3_SWI68 EXTI_SWIER3_SWI68_Msk /*!< Software Interrupt on line 68 */
#define EXTI_SWIER3_SWI69_Pos (5U)
#define EXTI_SWIER3_SWI69_Msk (0x1UL << EXTI_SWIER3_SWI69_Pos) /*!< 0x00000020 */
#define EXTI_SWIER3_SWI69 EXTI_SWIER3_SWI69_Msk /*!< Software Interrupt on line 69 */
#define EXTI_SWIER3_SWI70_Pos (6U)
#define EXTI_SWIER3_SWI70_Msk (0x1UL << EXTI_SWIER3_SWI70_Pos) /*!< 0x00000040 */
#define EXTI_SWIER3_SWI70 EXTI_SWIER3_SWI70_Msk /*!< Software Interrupt on line 70 */
#define EXTI_SWIER3_SWI71_Pos (7U)
#define EXTI_SWIER3_SWI71_Msk (0x1UL << EXTI_SWIER3_SWI71_Pos) /*!< 0x00000080 */
#define EXTI_SWIER3_SWI71 EXTI_SWIER3_SWI71_Msk /*!< Software Interrupt on line 71 */
#define EXTI_SWIER3_SWI72_Pos (8U)
#define EXTI_SWIER3_SWI72_Msk (0x1UL << EXTI_SWIER3_SWI72_Pos) /*!< 0x00000100 */
#define EXTI_SWIER3_SWI72 EXTI_SWIER3_SWI72_Msk /*!< Software Interrupt on line 72 */
#define EXTI_SWIER3_SWI73_Pos (9U)
#define EXTI_SWIER3_SWI73_Msk (0x1UL << EXTI_SWIER3_SWI73_Pos) /*!< 0x00000200 */
#define EXTI_SWIER3_SWI73 EXTI_SWIER3_SWI73_Msk /*!< Software Interrupt on line 73 */
#define EXTI_SWIER3_SWI74_Pos (10U)
#define EXTI_SWIER3_SWI74_Msk (0x1UL << EXTI_SWIER3_SWI74_Pos) /*!< 0x00000400 */
#define EXTI_SWIER3_SWI74 EXTI_SWIER3_SWI74_Msk /*!< Software Interrupt on line 74 */
/******************* Bit definition for EXTI_RPR3 register ******************/
#define EXTI_RPR3_RPIF66_Pos (2U)
#define EXTI_RPR3_RPIF66_Msk (0x1UL << EXTI_RPR3_RPIF66_Pos) /*!< 0x00000004 */
#define EXTI_RPR3_RPIF66 EXTI_RPR3_RPIF66_Msk /*!< Rising Pending Interrupt Flag on line 66 */
#define EXTI_RPR3_RPIF68_Pos (4U)
#define EXTI_RPR3_RPIF68_Msk (0x1UL << EXTI_RPR3_RPIF68_Pos) /*!< 0x00000010 */
#define EXTI_RPR3_RPIF68 EXTI_RPR3_RPIF68_Msk /*!< Rising Pending Interrupt Flag on line 68 */
#define EXTI_RPR3_RPIF69_Pos (5U)
#define EXTI_RPR3_RPIF69_Msk (0x1UL << EXTI_RPR3_RPIF69_Pos) /*!< 0x00000020 */
#define EXTI_RPR3_RPIF69 EXTI_RPR3_RPIF69_Msk /*!< Rising Pending Interrupt Flag on line 69 */
#define EXTI_RPR3_RPIF70_Pos (6U)
#define EXTI_RPR3_RPIF70_Msk (0x1UL << EXTI_RPR3_RPIF70_Pos) /*!< 0x00000040 */
#define EXTI_RPR3_RPIF70 EXTI_RPR3_RPIF70_Msk /*!< Rising Pending Interrupt Flag on line 70 */
#define EXTI_RPR3_RPIF71_Pos (7U)
#define EXTI_RPR3_RPIF71_Msk (0x1UL << EXTI_RPR3_RPIF71_Pos) /*!< 0x00000080 */
#define EXTI_RPR3_RPIF71 EXTI_RPR3_RPIF71_Msk /*!< Rising Pending Interrupt Flag on line 71 */
#define EXTI_RPR3_RPIF72_Pos (8U)
#define EXTI_RPR3_RPIF72_Msk (0x1UL << EXTI_RPR3_RPIF72_Pos) /*!< 0x00000100 */
#define EXTI_RPR3_RPIF72 EXTI_RPR3_RPIF72_Msk /*!< Rising Pending Interrupt Flag on line 72 */
#define EXTI_RPR3_RPIF73_Pos (9U)
#define EXTI_RPR3_RPIF73_Msk (0x1UL << EXTI_RPR3_RPIF73_Pos) /*!< 0x00000200 */
#define EXTI_RPR3_RPIF73 EXTI_RPR3_RPIF73_Msk /*!< Rising Pending Interrupt Flag on line 73 */
#define EXTI_RPR3_RPIF74_Pos (10U)
#define EXTI_RPR3_RPIF74_Msk (0x1UL << EXTI_RPR3_RPIF74_Pos) /*!< 0x00000400 */
#define EXTI_RPR3_RPIF74 EXTI_RPR3_RPIF74_Msk /*!< Rising Pending Interrupt Flag on line 74 */
/******************* Bit definition for EXTI_FPR3 register ******************/
#define EXTI_FPR3_FPIF66_Pos (2U)
#define EXTI_FPR3_FPIF66_Msk (0x1UL << EXTI_FPR3_FPIF66_Pos) /*!< 0x00000004 */
#define EXTI_FPR3_FPIF66 EXTI_FPR3_FPIF66_Msk /*!< Falling Pending Interrupt Flag on line 66 */
#define EXTI_FPR3_FPIF68_Pos (4U)
#define EXTI_FPR3_FPIF68_Msk (0x1UL << EXTI_FPR3_FPIF68_Pos) /*!< 0x00000010 */
#define EXTI_FPR3_FPIF68 EXTI_FPR3_FPIF68_Msk /*!< Falling Pending Interrupt Flag on line 68 */
#define EXTI_FPR3_FPIF69_Pos (5U)
#define EXTI_FPR3_FPIF69_Msk (0x1UL << EXTI_FPR3_FPIF69_Pos) /*!< 0x00000020 */
#define EXTI_FPR3_FPIF69 EXTI_FPR3_FPIF69_Msk /*!< Falling Pending Interrupt Flag online 69 */
#define EXTI_FPR3_FPIF70_Pos (6U)
#define EXTI_FPR3_FPIF70_Msk (0x1UL << EXTI_FPR3_FPIF70_Pos) /*!< 0x00000040 */
#define EXTI_FPR3_FPIF70 EXTI_FPR3_FPIF70_Msk /*!< Falling Pending Interrupt Flag on line 70 */
#define EXTI_FPR3_FPIF71_Pos (7U)
#define EXTI_FPR3_FPIF71_Msk (0x1UL << EXTI_FPR3_FPIF71_Pos) /*!< 0x00000080 */
#define EXTI_FPR3_FPIF71 EXTI_FPR3_FPIF71_Msk /*!< Falling Pending Interrupt Flag on line 71 */
#define EXTI_FPR3_FPIF72_Pos (8U)
#define EXTI_FPR3_FPIF72_Msk (0x1UL << EXTI_FPR3_FPIF72_Pos) /*!< 0x00000100 */
#define EXTI_FPR3_FPIF72 EXTI_FPR3_FPIF72_Msk /*!< Falling Pending Interrupt Flag on line 72 */
#define EXTI_FPR3_FPIF73_Pos (9U)
#define EXTI_FPR3_FPIF73_Msk (0x1UL << EXTI_FPR3_FPIF73_Pos) /*!< 0x00000200 */
#define EXTI_FPR3_FPIF73 EXTI_FPR3_FPIF73_Msk /*!< Falling Pending Interrupt Flag on line 73 */
#define EXTI_FPR3_FPIF74_Pos (10U)
#define EXTI_FPR3_FPIF74_Msk (0x1UL << EXTI_FPR3_FPIF74_Pos) /*!< 0x00000400 */
#define EXTI_FPR3_FPIF74 EXTI_FPR3_FPIF74_Msk /*!< Falling Pending Interrupt Flag on line 74 */
/******************* Bit definition for EXTI_SECCFGR3 register ******************/
#define EXTI_SECCFGR3_SEC64_Pos (0U)
#define EXTI_SECCFGR3_SEC64_Msk (0x1UL << EXTI_SECCFGR3_SEC64_Pos) /*!< 0x00000001 */
#define EXTI_SECCFGR3_SEC64 EXTI_SECCFGR3_SEC64_Msk /*!< Security enable on line 64 */
#define EXTI_SECCFGR3_SEC65_Pos (1U)
#define EXTI_SECCFGR3_SEC65_Msk (0x1UL << EXTI_SECCFGR3_SEC65_Pos) /*!< 0x00000002 */
#define EXTI_SECCFGR3_SEC65 EXTI_SECCFGR3_SEC65_Msk /*!< Security enable on line 65 */
#define EXTI_SECCFGR3_SEC66_Pos (2U)
#define EXTI_SECCFGR3_SEC66_Msk (0x1UL << EXTI_SECCFGR3_SEC66_Pos) /*!< 0x00000004 */
#define EXTI_SECCFGR3_SEC66 EXTI_SECCFGR3_SEC66_Msk /*!< Security enable on line 66 */
#define EXTI_SECCFGR3_SEC68_Pos (4U)
#define EXTI_SECCFGR3_SEC68_Msk (0x1UL << EXTI_SECCFGR3_SEC68_Pos) /*!< 0x00000010 */
#define EXTI_SECCFGR3_SEC68 EXTI_SECCFGR3_SEC68_Msk /*!< Security enable on line 68 */
#define EXTI_SECCFGR3_SEC69_Pos (5U)
#define EXTI_SECCFGR3_SEC69_Msk (0x1UL << EXTI_SECCFGR3_SEC69_Pos) /*!< 0x00000020 */
#define EXTI_SECCFGR3_SEC69 EXTI_SECCFGR3_SEC69_Msk /*!< Security enable on line 69 */
#define EXTI_SECCFGR3_SEC70_Pos (6U)
#define EXTI_SECCFGR3_SEC70_Msk (0x1UL << EXTI_SECCFGR3_SEC70_Pos) /*!< 0x00000040 */
#define EXTI_SECCFGR3_SEC70 EXTI_SECCFGR3_SEC70_Msk /*!< Security enable on line 70 */
#define EXTI_SECCFGR3_SEC71_Pos (7U)
#define EXTI_SECCFGR3_SEC71_Msk (0x1UL << EXTI_SECCFGR3_SEC71_Pos) /*!< 0x00000080 */
#define EXTI_SECCFGR3_SEC71 EXTI_SECCFGR3_SEC71_Msk /*!< Security enable on line 71 */
#define EXTI_SECCFGR3_SEC72_Pos (8U)
#define EXTI_SECCFGR3_SEC72_Msk (0x1UL << EXTI_SECCFGR3_SEC72_Pos) /*!< 0x00000100 */
#define EXTI_SECCFGR3_SEC72 EXTI_SECCFGR3_SEC72_Msk /*!< Security enable on line 72 */
#define EXTI_SECCFGR3_SEC73_Pos (9U)
#define EXTI_SECCFGR3_SEC73_Msk (0x1UL << EXTI_SECCFGR3_SEC73_Pos) /*!< 0x00000200 */
#define EXTI_SECCFGR3_SEC73 EXTI_SECCFGR3_SEC73_Msk /*!< Security enable on line 73 */
#define EXTI_SECCFGR3_SEC74_Pos (10U)
#define EXTI_SECCFGR3_SEC74_Msk (0x1UL << EXTI_SECCFGR3_SEC74_Pos) /*!< 0x00000400 */
#define EXTI_SECCFGR3_SEC74 EXTI_SECCFGR3_SEC74_Msk /*!< Security enable on line 74 */
#define EXTI_SECCFGR3_SEC77_Pos (13U)
#define EXTI_SECCFGR3_SEC77_Msk (0x1UL << EXTI_SECCFGR3_SEC77_Pos) /*!< 0x00002000 */
#define EXTI_SECCFGR3_SEC77 EXTI_SECCFGR3_SEC77_Msk /*!< Security enable on line 77 */
/******************* Bit definition for EXTI_PRIVCFGR3 register ******************/
#define EXTI_PRIVCFGR3_PRIV64_Pos (0U)
#define EXTI_PRIVCFGR3_PRIV64_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV64_Pos) /*!< 0x00000001 */
#define EXTI_PRIVCFGR3_PRIV64 EXTI_PRIVCFGR3_PRIV64_Msk /*!< Privilege enable on line 64 */
#define EXTI_PRIVCFGR3_PRIV65_Pos (1U)
#define EXTI_PRIVCFGR3_PRIV65_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV65_Pos) /*!< 0x00000002 */
#define EXTI_PRIVCFGR3_PRIV65 EXTI_PRIVCFGR3_PRIV65_Msk /*!< Privilege enable on line 65 */
#define EXTI_PRIVCFGR3_PRIV66_Pos (2U)
#define EXTI_PRIVCFGR3_PRIV66_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV66_Pos) /*!< 0x00000004 */
#define EXTI_PRIVCFGR3_PRIV66 EXTI_PRIVCFGR3_PRIV66_Msk /*!< Privilege enable on line 66 */
#define EXTI_PRIVCFGR3_PRIV68_Pos (4U)
#define EXTI_PRIVCFGR3_PRIV68_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV68_Pos) /*!< 0x00000010 */
#define EXTI_PRIVCFGR3_PRIV68 EXTI_PRIVCFGR3_PRIV68_Msk /*!< Privilege enable on line 68 */
#define EXTI_PRIVCFGR3_PRIV69_Pos (5U)
#define EXTI_PRIVCFGR3_PRIV69_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV69_Pos) /*!< 0x00000020 */
#define EXTI_PRIVCFGR3_PRIV69 EXTI_PRIVCFGR3_PRIV69_Msk /*!< Privilege enable on line 69 */
#define EXTI_PRIVCFGR3_PRIV70_Pos (6U)
#define EXTI_PRIVCFGR3_PRIV70_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV70_Pos) /*!< 0x00000040 */
#define EXTI_PRIVCFGR3_PRIV70 EXTI_PRIVCFGR3_PRIV70_Msk /*!< Privilege enable on line 70 */
#define EXTI_PRIVCFGR3_PRIV71_Pos (7U)
#define EXTI_PRIVCFGR3_PRIV71_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV71_Pos) /*!< 0x00000080 */
#define EXTI_PRIVCFGR3_PRIV71 EXTI_PRIVCFGR3_PRIV71_Msk /*!< Privilege enable on line 71 */
#define EXTI_PRIVCFGR3_PRIV72_Pos (8U)
#define EXTI_PRIVCFGR3_PRIV72_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV72_Pos) /*!< 0x00000100 */
#define EXTI_PRIVCFGR3_PRIV72 EXTI_PRIVCFGR3_PRIV72_Msk /*!< Privilege enable on line 72 */
#define EXTI_PRIVCFGR3_PRIV73_Pos (9U)
#define EXTI_PRIVCFGR3_PRIV73_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV73_Pos) /*!< 0x00000200 */
#define EXTI_PRIVCFGR3_PRIV73 EXTI_PRIVCFGR3_PRIV73_Msk /*!< Privilege enable on line 73 */
#define EXTI_PRIVCFGR3_PRIV74_Pos (10U)
#define EXTI_PRIVCFGR3_PRIV74_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV74_Pos) /*!< 0x00000400 */
#define EXTI_PRIVCFGR3_PRIV74 EXTI_PRIVCFGR3_PRIV74_Msk /*!< Privilege enable on line 74 */
#define EXTI_PRIVCFGR3_PRIV77_Pos (13U)
#define EXTI_PRIVCFGR3_PRIV77_Msk (0x1UL << EXTI_PRIVCFGR3_PRIV77_Pos) /*!< 0x00002000 */
#define EXTI_PRIVCFGR3_PRIV77 EXTI_PRIVCFGR3_PRIV77_Msk /*!< Privilege enable on line 77 */
/***************** Bit definition for EXTI_EXTICR1 register **************/
#define EXTI_EXTICR1_EXTI0_Pos (0U)
#define EXTI_EXTICR1_EXTI0_Msk (0xFFUL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x000000FF */
#define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
#define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR1_EXTI0_4 (0x10UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000010 */
#define EXTI_EXTICR1_EXTI0_5 (0x20UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000020 */
#define EXTI_EXTICR1_EXTI0_6 (0x40UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000040 */
#define EXTI_EXTICR1_EXTI0_7 (0x80UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000080 */
#define EXTI_EXTICR1_EXTI1_Pos (8U)
#define EXTI_EXTICR1_EXTI1_Msk (0xFFUL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x0000FF00 */
#define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
#define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR1_EXTI1_4 (0x10UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00001000 */
#define EXTI_EXTICR1_EXTI1_5 (0x20UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00002000 */
#define EXTI_EXTICR1_EXTI1_6 (0x40UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00004000 */
#define EXTI_EXTICR1_EXTI1_7 (0x80UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00008000 */
#define EXTI_EXTICR1_EXTI2_Pos (16U)
#define EXTI_EXTICR1_EXTI2_Msk (0xFFUL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00FF0000 */
#define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
#define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR1_EXTI2_4 (0x10UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00100000 */
#define EXTI_EXTICR1_EXTI2_5 (0x20UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00200000 */
#define EXTI_EXTICR1_EXTI2_6 (0x40UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00400000 */
#define EXTI_EXTICR1_EXTI2_7 (0x80UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00800000 */
#define EXTI_EXTICR1_EXTI3_Pos (24U)
#define EXTI_EXTICR1_EXTI3_Msk (0xFFUL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0xFF000000 */
#define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
#define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR1_EXTI3_4 (0x10UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x10000000 */
#define EXTI_EXTICR1_EXTI3_5 (0x20UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x20000000 */
#define EXTI_EXTICR1_EXTI3_6 (0x40UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x40000000 */
#define EXTI_EXTICR1_EXTI3_7 (0x80UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x80000000 */
/***************** Bit definition for EXTI_EXTICR2 register **************/
#define EXTI_EXTICR2_EXTI4_Pos (0U)
#define EXTI_EXTICR2_EXTI4_Msk (0xFFUL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x000000FF */
#define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
#define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR2_EXTI4_4 (0x10UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000010 */
#define EXTI_EXTICR2_EXTI4_5 (0x20UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000020 */
#define EXTI_EXTICR2_EXTI4_6 (0x40UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000040 */
#define EXTI_EXTICR2_EXTI4_7 (0x80UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000080 */
#define EXTI_EXTICR2_EXTI5_Pos (8U)
#define EXTI_EXTICR2_EXTI5_Msk (0xFFUL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x0000FF00 */
#define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
#define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR2_EXTI5_4 (0x10UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00001000 */
#define EXTI_EXTICR2_EXTI5_5 (0x20UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00002000 */
#define EXTI_EXTICR2_EXTI5_6 (0x40UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00004000 */
#define EXTI_EXTICR2_EXTI5_7 (0x80UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00008000 */
#define EXTI_EXTICR2_EXTI6_Pos (16U)
#define EXTI_EXTICR2_EXTI6_Msk (0xFFUL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00FF0000 */
#define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
#define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR2_EXTI6_4 (0x10UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00100000 */
#define EXTI_EXTICR2_EXTI6_5 (0x20UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00200000 */
#define EXTI_EXTICR2_EXTI6_6 (0x40UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00400000 */
#define EXTI_EXTICR2_EXTI6_7 (0x80UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00800000 */
#define EXTI_EXTICR2_EXTI7_Pos (24U)
#define EXTI_EXTICR2_EXTI7_Msk (0xFFUL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0xFF000000 */
#define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
#define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR2_EXTI7_4 (0x10UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x10000000 */
#define EXTI_EXTICR2_EXTI7_5 (0x20UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x20000000 */
#define EXTI_EXTICR2_EXTI7_6 (0x40UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x40000000 */
#define EXTI_EXTICR2_EXTI7_7 (0x80UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x80000000 */
/***************** Bit definition for EXTI_EXTICR3 register **************/
#define EXTI_EXTICR3_EXTI8_Pos (0U)
#define EXTI_EXTICR3_EXTI8_Msk (0xFFUL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x000000FF */
#define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
#define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR3_EXTI8_4 (0x10UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000010 */
#define EXTI_EXTICR3_EXTI8_5 (0x20UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000020 */
#define EXTI_EXTICR3_EXTI8_6 (0x40UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000040 */
#define EXTI_EXTICR3_EXTI8_7 (0x80UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000080 */
#define EXTI_EXTICR3_EXTI9_Pos (8U)
#define EXTI_EXTICR3_EXTI9_Msk (0xFFUL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x0000FF00 */
#define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
#define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR3_EXTI9_4 (0x10UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00001000 */
#define EXTI_EXTICR3_EXTI9_5 (0x20UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00002000 */
#define EXTI_EXTICR3_EXTI9_6 (0x40UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00004000 */
#define EXTI_EXTICR3_EXTI9_7 (0x80UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00008000 */
#define EXTI_EXTICR3_EXTI10_Pos (16U)
#define EXTI_EXTICR3_EXTI10_Msk (0xFFUL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00FF0000 */
#define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
#define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR3_EXTI10_4 (0x10UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00100000 */
#define EXTI_EXTICR3_EXTI10_5 (0x20UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00200000 */
#define EXTI_EXTICR3_EXTI10_6 (0x40UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00400000 */
#define EXTI_EXTICR3_EXTI10_7 (0x80UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00800000 */
#define EXTI_EXTICR3_EXTI11_Pos (24U)
#define EXTI_EXTICR3_EXTI11_Msk (0xFFUL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0xFF000000 */
#define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
#define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR3_EXTI11_4 (0x10UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x10000000 */
#define EXTI_EXTICR3_EXTI11_5 (0x20UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x20000000 */
#define EXTI_EXTICR3_EXTI11_6 (0x40UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x40000000 */
#define EXTI_EXTICR3_EXTI11_7 (0x80UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x80000000 */
/***************** Bit definition for EXTI_EXTICR4 register **************/
#define EXTI_EXTICR4_EXTI12_Pos (0U)
#define EXTI_EXTICR4_EXTI12_Msk (0xFFUL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x000000FF */
#define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
#define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
#define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
#define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
#define EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000008 */
#define EXTI_EXTICR4_EXTI12_4 (0x10UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000010 */
#define EXTI_EXTICR4_EXTI12_5 (0x20UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000020 */
#define EXTI_EXTICR4_EXTI12_6 (0x40UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000040 */
#define EXTI_EXTICR4_EXTI12_7 (0x80UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000080 */
#define EXTI_EXTICR4_EXTI13_Pos (8U)
#define EXTI_EXTICR4_EXTI13_Msk (0xFFUL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x0000FF00 */
#define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
#define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
#define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
#define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
#define EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000800 */
#define EXTI_EXTICR4_EXTI13_4 (0x10UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00001000 */
#define EXTI_EXTICR4_EXTI13_5 (0x20UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00002000 */
#define EXTI_EXTICR4_EXTI13_6 (0x40UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00004000 */
#define EXTI_EXTICR4_EXTI13_7 (0x80UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00008000 */
#define EXTI_EXTICR4_EXTI14_Pos (16U)
#define EXTI_EXTICR4_EXTI14_Msk (0xFFUL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00FF0000 */
#define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
#define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
#define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
#define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
#define EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00080000 */
#define EXTI_EXTICR4_EXTI14_4 (0x10UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00100000 */
#define EXTI_EXTICR4_EXTI14_5 (0x20UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00200000 */
#define EXTI_EXTICR4_EXTI14_6 (0x40UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00400000 */
#define EXTI_EXTICR4_EXTI14_7 (0x80UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00800000 */
#define EXTI_EXTICR4_EXTI15_Pos (24U)
#define EXTI_EXTICR4_EXTI15_Msk (0xFFUL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0xFF000000 */
#define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
#define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
#define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
#define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
#define EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x08000000 */
#define EXTI_EXTICR4_EXTI15_4 (0x10UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x10000000 */
#define EXTI_EXTICR4_EXTI15_5 (0x20UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x20000000 */
#define EXTI_EXTICR4_EXTI15_6 (0x40UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x40000000 */
#define EXTI_EXTICR4_EXTI15_7 (0x80UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x80000000 */
/******************* Bit definition I_LOCKR register ******************/
#define EXTI_LOCKR_LOCK_Pos (0U)
#define EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) /*!< 0x00000001 */
#define EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk /*!< Security and privilege configuration lock */
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0xFFFEFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFEFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
#define EXTI_EMR1_EM_Pos (0U)
#define EXTI_EMR1_EM_Msk (0xFFFEFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFEFFFF */
#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask All */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM32_Pos (0U)
#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM42_Pos (10U)
#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
#define EXTI_IMR2_IM43_Pos (11U)
#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
#define EXTI_IMR2_IM44_Pos (12U)
#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
#define EXTI_IMR2_IM45_Pos (13U)
#define EXTI_IMR2_IM45_Msk (0x1UL << EXTI_IMR2_IM45_Pos) /*!< 0x00002000 */
#define EXTI_IMR2_IM45 EXTI_IMR2_IM45_Msk /*!< Interrupt Mask on line 45 */
#define EXTI_IMR2_IM46_Pos (14U)
#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
#define EXTI_IMR2_IM47_Pos (15U)
#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
#define EXTI_IMR2_IM48_Pos (16U)
#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
#define EXTI_IMR2_IM49_Pos (17U)
#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
#define EXTI_IMR2_IM50_Pos (18U)
#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
#define EXTI_IMR2_IM51_Pos (19U)
#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
#define EXTI_IMR2_IM52_Pos (20U)
#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
#define EXTI_IMR2_IM53_Pos (21U)
#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
#define EXTI_IMR2_IM54_Pos (22U)
#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
#define EXTI_IMR2_IM55_Pos (23U)
#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
#define EXTI_IMR2_IM56_Pos (24U)
#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
#define EXTI_IMR2_IM57_Pos (25U)
#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
#define EXTI_IMR2_IM58_Pos (26U)
#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
#define EXTI_IMR2_IM60_Pos (28U)
#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
#define EXTI_IMR2_IM61_Pos (29U)
#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
#define EXTI_IMR2_IM62_Pos (30U)
#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
#define EXTI_IMR2_IM63_Pos (31U)
#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0xF7FFFFFFUL << EXTI_IMR2_IM_Pos) /*!< 0xF7FFFFFF */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM32_Pos (0U)
#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM42_Pos (10U)
#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
#define EXTI_EMR2_EM43_Pos (11U)
#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
#define EXTI_EMR2_EM44_Pos (12U)
#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
#define EXTI_EMR2_EM45_Pos (13U)
#define EXTI_EMR2_EM45_Msk (0x1UL << EXTI_EMR2_EM45_Pos) /*!< 0x00002000 */
#define EXTI_EMR2_EM45 EXTI_EMR2_EM45_Msk /*!< Event Mask on line 45 */
#define EXTI_EMR2_EM46_Pos (14U)
#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
#define EXTI_EMR2_EM47_Pos (15U)
#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
#define EXTI_EMR2_EM48_Pos (16U)
#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
#define EXTI_EMR2_EM49_Pos (17U)
#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
#define EXTI_EMR2_EM50_Pos (18U)
#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
#define EXTI_EMR2_EM51_Pos (19U)
#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
#define EXTI_EMR2_EM52_Pos (20U)
#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
#define EXTI_EMR2_EM53_Pos (21U)
#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
#define EXTI_EMR2_EM54_Pos (22U)
#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
#define EXTI_EMR2_EM55_Pos (23U)
#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
#define EXTI_EMR2_EM56_Pos (24U)
#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
#define EXTI_EMR2_EM57_Pos (25U)
#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
#define EXTI_EMR2_EM58_Pos (26U)
#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
#define EXTI_EMR2_EM60_Pos (28U)
#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
#define EXTI_EMR2_EM61_Pos (29U)
#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x20000000 */
#define EXTI_EMR2_EM61 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 61 */
#define EXTI_EMR2_EM62_Pos (30U)
#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x40000000 */
#define EXTI_EMR2_EM62 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 62 */
#define EXTI_EMR2_EM63_Pos (31U)
#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x80000000 */
#define EXTI_EMR2_EM63 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 63 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0xF7FFFFFFUL << EXTI_EMR2_EM_Pos) /*!< 0xF7FFFFFF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask All */
/******************* Bit definition for EXTI_IMR3 register ******************/
#define EXTI_IMR3_IM64_Pos (0U)
#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
#define EXTI_IMR3_IM65_Pos (1U)
#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
#define EXTI_IMR3_IM66_Pos (2U)
#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
#define EXTI_IMR3_IM68_Pos (4U)
#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
#define EXTI_IMR3_IM69_Pos (5U)
#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
#define EXTI_IMR3_IM70_Pos (6U)
#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
#define EXTI_IMR3_IM71_Pos (7U)
#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
#define EXTI_IMR3_IM72_Pos (8U)
#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
#define EXTI_IMR3_IM73_Pos (9U)
#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
#define EXTI_IMR3_IM74_Pos (10U)
#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
#define EXTI_IMR3_IM77_Pos (13U)
#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
#define EXTI_IMR3_IM_Pos (0U)
#define EXTI_IMR3_IM_Msk (0x27F7UL << EXTI_IMR3_IM_Pos) /*!< 0x000027F7 */
#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR3 register ******************/
#define EXTI_EMR3_EM64_Pos (0U)
#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64 */
#define EXTI_EMR3_EM65_Pos (1U)
#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65 */
#define EXTI_EMR3_EM66_Pos (2U)
#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66 */
#define EXTI_EMR3_EM68_Pos (4U)
#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68 */
#define EXTI_EMR3_EM69_Pos (5U)
#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69 */
#define EXTI_EMR3_EM70_Pos (6U)
#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70 */
#define EXTI_EMR3_EM71_Pos (7U)
#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71 */
#define EXTI_EMR3_EM72_Pos (8U)
#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72 */
#define EXTI_EMR3_EM73_Pos (9U)
#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73 */
#define EXTI_EMR3_EM74_Pos (10U)
#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
#define EXTI_EMR3_EM77_Pos (13U)
#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
#define EXTI_EMR3_EM_Pos (0U)
#define EXTI_EMR3_EM_Msk (0x27F7UL << EXTI_EMR3_EM_Pos) /*!< 0x000027F7 */
#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask All */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register *******************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register *******************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register *******************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register *******************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register *******************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register *******************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register ********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register ********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register *******************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register *********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0W_Pos (1U)
#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
#define FDCAN_IR_RF0F_Pos (2U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (3U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (4U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1W_Pos (5U)
#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
#define FDCAN_IR_RF1F_Pos (6U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (7U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (8U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (9U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (10U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (11U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (12U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFW_Pos (13U)
#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
#define FDCAN_IR_TEFF_Pos (14U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (15U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (16U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (17U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (18U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_DRX_Pos (19U)
#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
#define FDCAN_IR_ELO_Pos (22U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (23U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (24U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (25U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (26U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (27U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (28U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (29U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register *********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0WE_Pos (1U)
#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
#define FDCAN_IE_RF0FE_Pos (2U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (3U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (4U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1WE_Pos (5U)
#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
#define FDCAN_IE_RF1FE_Pos (6U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (7U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (8U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (9U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (10U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
#define FDCAN_IE_TFEE_Pos (11U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (12U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFWE_Pos (13U)
#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
#define FDCAN_IE_TEFFE_Pos (14U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (15U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (16U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (17U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (18U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_DRXE_Pos (19U)
#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
#define FDCAN_IE_BECE_Pos (20U)
#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
#define FDCAN_IE_BEUE_Pos (21U)
#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
#define FDCAN_IE_ELOE_Pos (22U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (23U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (24U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (25U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (26U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (27U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
#define FDCAN_IE_PEDE_Pos (28U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (29U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register ********************/
#define FDCAN_ILS_RF0NL_Pos (0U)
#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
#define FDCAN_ILS_RF0WL_Pos (1U)
#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
#define FDCAN_ILS_RF0FL_Pos (2U)
#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
#define FDCAN_ILS_RF0LL_Pos (3U)
#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
#define FDCAN_ILS_RF1NL_Pos (4U)
#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
#define FDCAN_ILS_RF1WL_Pos (5U)
#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
#define FDCAN_ILS_RF1FL_Pos (6U)
#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
#define FDCAN_ILS_RF1LL_Pos (7U)
#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
#define FDCAN_ILS_HPML_Pos (8U)
#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
#define FDCAN_ILS_TCL_Pos (9U)
#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
#define FDCAN_ILS_TCFL_Pos (10U)
#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
#define FDCAN_ILS_TFEL_Pos (11U)
#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
#define FDCAN_ILS_TEFNL_Pos (12U)
#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
#define FDCAN_ILS_TEFWL_Pos (13U)
#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
#define FDCAN_ILS_TEFFL_Pos (14U)
#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
#define FDCAN_ILS_TEFLL_Pos (15U)
#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
#define FDCAN_ILS_TSWL_Pos (16U)
#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
#define FDCAN_ILS_MRAFL_Pos (17U)
#define FDCAN_ILS_MRAFL_Msk (0x1UL << FDCAN_ILS_MRAFL_Pos) /*!< 0x00020000 */
#define FDCAN_ILS_MRAFL FDCAN_ILS_MRAFL_Msk /*!<Message RAM Access Failure Line */
#define FDCAN_ILS_TOOL_Pos (18U)
#define FDCAN_ILS_TOOL_Msk (0x1UL << FDCAN_ILS_TOOL_Pos) /*!< 0x00040000 */
#define FDCAN_ILS_TOOL FDCAN_ILS_TOOL_Msk /*!<Timeout Occurred Line */
#define FDCAN_ILS_DRXL_Pos (19U)
#define FDCAN_ILS_DRXL_Msk (0x1UL << FDCAN_ILS_DRXL_Pos) /*!< 0x00080000 */
#define FDCAN_ILS_DRXL FDCAN_ILS_DRXL_Msk /*!<Message stored to Dedicated Rx Buffer Line */
#define FDCAN_ILS_ELOL_Pos (22U)
#define FDCAN_ILS_ELOL_Msk (0x1UL << FDCAN_ILS_ELOL_Pos) /*!< 0x00400000 */
#define FDCAN_ILS_ELOL FDCAN_ILS_ELOL_Msk /*!<Error Logging Overflow Line */
#define FDCAN_ILS_EPL_Pos (23U)
#define FDCAN_ILS_EPL_Msk (0x1UL << FDCAN_ILS_EPL_Pos) /*!< 0x00800000 */
#define FDCAN_ILS_EPL FDCAN_ILS_EPL_Msk /*!<Error Passive Line */
#define FDCAN_ILS_EWL_Pos (24U)
#define FDCAN_ILS_EWL_Msk (0x1UL << FDCAN_ILS_EWL_Pos) /*!< 0x01000000 */
#define FDCAN_ILS_EWL FDCAN_ILS_EWL_Msk /*!<Warning Status Line */
#define FDCAN_ILS_BOL_Pos (25U)
#define FDCAN_ILS_BOL_Msk (0x1UL << FDCAN_ILS_BOL_Pos) /*!< 0x02000000 */
#define FDCAN_ILS_BOL FDCAN_ILS_BOL_Msk /*!<Bus_Off Status Line */
#define FDCAN_ILS_WDIL_Pos (26U)
#define FDCAN_ILS_WDIL_Msk (0x1UL << FDCAN_ILS_WDIL_Pos) /*!< 0x04000000 */
#define FDCAN_ILS_WDIL FDCAN_ILS_WDIL_Msk /*!<Watchdog Interrupt Line */
#define FDCAN_ILS_PEAL_Pos (27U)
#define FDCAN_ILS_PEAL_Msk (0x1UL << FDCAN_ILS_PEAL_Pos) /*!< 0x08000000 */
#define FDCAN_ILS_PEAL FDCAN_ILS_PEAL_Msk /*!<Protocol Error in Arbitration Phase Line */
#define FDCAN_ILS_PEDL_Pos (28U)
#define FDCAN_ILS_PEDL_Msk (0x1UL << FDCAN_ILS_PEDL_Pos) /*!< 0x10000000 */
#define FDCAN_ILS_PEDL FDCAN_ILS_PEDL_Msk /*!<Protocol Error in Data Phase Line */
#define FDCAN_ILS_ARAL_Pos (29U)
#define FDCAN_ILS_ARAL_Msk (0x1UL << FDCAN_ILS_ARAL_Pos) /*!< 0x20000000 */
#define FDCAN_ILS_ARAL FDCAN_ILS_ARAL_Msk /*!<Access to Reserved Address Line */
/***************** Bit definition for FDCAN_ILE register ********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_GFC register ******************/
#define FDCAN_GFC_RRFE_Pos (0U)
#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_GFC_RRFS_Pos (1U)
#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_GFC_ANFE_Pos (2U)
#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_GFC_ANFS_Pos (4U)
#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
/***************** Bit definition for FDCAN_SIDFC register ********************/
#define FDCAN_SIDFC_FLSSA_Pos (2U)
#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
#define FDCAN_SIDFC_LSS_Pos (16U)
#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
/***************** Bit definition for FDCAN_XIDFC register ********************/
#define FDCAN_XIDFC_FLESA_Pos (2U)
#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
#define FDCAN_XIDFC_LSE_Pos (16U)
#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ******************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *******************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_NDAT1 register ********************/
#define FDCAN_NDAT1_ND0_Pos (0U)
#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
#define FDCAN_NDAT1_ND1_Pos (1U)
#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
#define FDCAN_NDAT1_ND2_Pos (2U)
#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
#define FDCAN_NDAT1_ND3_Pos (3U)
#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
#define FDCAN_NDAT1_ND4_Pos (4U)
#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
#define FDCAN_NDAT1_ND5_Pos (5U)
#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
#define FDCAN_NDAT1_ND6_Pos (6U)
#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
#define FDCAN_NDAT1_ND7_Pos (7U)
#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
#define FDCAN_NDAT1_ND8_Pos (8U)
#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
#define FDCAN_NDAT1_ND9_Pos (9U)
#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
#define FDCAN_NDAT1_ND10_Pos (10U)
#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
#define FDCAN_NDAT1_ND11_Pos (11U)
#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
#define FDCAN_NDAT1_ND12_Pos (12U)
#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
#define FDCAN_NDAT1_ND13_Pos (13U)
#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
#define FDCAN_NDAT1_ND14_Pos (14U)
#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
#define FDCAN_NDAT1_ND15_Pos (15U)
#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
#define FDCAN_NDAT1_ND16_Pos (16U)
#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
#define FDCAN_NDAT1_ND17_Pos (17U)
#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
#define FDCAN_NDAT1_ND18_Pos (18U)
#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
#define FDCAN_NDAT1_ND19_Pos (19U)
#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
#define FDCAN_NDAT1_ND20_Pos (20U)
#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
#define FDCAN_NDAT1_ND21_Pos (21U)
#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
#define FDCAN_NDAT1_ND22_Pos (22U)
#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
#define FDCAN_NDAT1_ND23_Pos (23U)
#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
#define FDCAN_NDAT1_ND24_Pos (24U)
#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
#define FDCAN_NDAT1_ND25_Pos (25U)
#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
#define FDCAN_NDAT1_ND26_Pos (26U)
#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
#define FDCAN_NDAT1_ND27_Pos (27U)
#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
#define FDCAN_NDAT1_ND28_Pos (28U)
#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
#define FDCAN_NDAT1_ND29_Pos (29U)
#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
#define FDCAN_NDAT1_ND30_Pos (30U)
#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
#define FDCAN_NDAT1_ND31_Pos (31U)
#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
/***************** Bit definition for FDCAN_NDAT2 register ********************/
#define FDCAN_NDAT2_ND32_Pos (0U)
#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
#define FDCAN_NDAT2_ND33_Pos (1U)
#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
#define FDCAN_NDAT2_ND34_Pos (2U)
#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
#define FDCAN_NDAT2_ND35_Pos (3U)
#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
#define FDCAN_NDAT2_ND36_Pos (4U)
#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
#define FDCAN_NDAT2_ND37_Pos (5U)
#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
#define FDCAN_NDAT2_ND38_Pos (6U)
#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
#define FDCAN_NDAT2_ND39_Pos (7U)
#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
#define FDCAN_NDAT2_ND40_Pos (8U)
#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
#define FDCAN_NDAT2_ND41_Pos (9U)
#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
#define FDCAN_NDAT2_ND42_Pos (10U)
#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
#define FDCAN_NDAT2_ND43_Pos (11U)
#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
#define FDCAN_NDAT2_ND44_Pos (12U)
#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
#define FDCAN_NDAT2_ND45_Pos (13U)
#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
#define FDCAN_NDAT2_ND46_Pos (14U)
#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
#define FDCAN_NDAT2_ND47_Pos (15U)
#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
#define FDCAN_NDAT2_ND48_Pos (16U)
#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
#define FDCAN_NDAT2_ND49_Pos (17U)
#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
#define FDCAN_NDAT2_ND50_Pos (18U)
#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
#define FDCAN_NDAT2_ND51_Pos (19U)
#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
#define FDCAN_NDAT2_ND52_Pos (20U)
#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
#define FDCAN_NDAT2_ND53_Pos (21U)
#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
#define FDCAN_NDAT2_ND54_Pos (22U)
#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
#define FDCAN_NDAT2_ND55_Pos (23U)
#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
#define FDCAN_NDAT2_ND56_Pos (24U)
#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
#define FDCAN_NDAT2_ND57_Pos (25U)
#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
#define FDCAN_NDAT2_ND58_Pos (26U)
#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
#define FDCAN_NDAT2_ND59_Pos (27U)
#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
#define FDCAN_NDAT2_ND60_Pos (28U)
#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
#define FDCAN_NDAT2_ND61_Pos (29U)
#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
#define FDCAN_NDAT2_ND62_Pos (30U)
#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
#define FDCAN_NDAT2_ND63_Pos (31U)
#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
/***************** Bit definition for FDCAN_RXF0C register ********************/
#define FDCAN_RXF0C_F0SA_Pos (2U)
#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
#define FDCAN_RXF0C_F0S_Pos (16U)
#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
#define FDCAN_RXF0C_F0WM_Pos (24U)
#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
#define FDCAN_RXF0C_F0OM_Pos (31U)
#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
/***************** Bit definition for FDCAN_RXF0S register ******************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ******************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXBC register ********************/
#define FDCAN_RXBC_RBSA_Pos (2U)
#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
/***************** Bit definition for FDCAN_RXF1C register ******************/
#define FDCAN_RXF1C_F1SA_Pos (2U)
#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
#define FDCAN_RXF1C_F1S_Pos (16U)
#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
#define FDCAN_RXF1C_F1WM_Pos (24U)
#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
#define FDCAN_RXF1C_F1OM_Pos (31U)
#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
/***************** Bit definition for FDCAN_RXF1S register ******************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ******************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_RXESC register ******************/
#define FDCAN_RXESC_F0DS_Pos (0U)
#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
#define FDCAN_RXESC_F1DS_Pos (4U)
#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
#define FDCAN_RXESC_RBDS_Pos (8U)
#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
/***************** Bit definition for FDCAN_TXBC register *******************/
#define FDCAN_TXBC_TBSA_Pos (2U)
#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
#define FDCAN_TXBC_NDTB_Pos (16U)
#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
#define FDCAN_TXBC_TFQS_Pos (24U)
#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
#define FDCAN_TXBC_TFQM_Pos (30U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register ******************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXESC register ******************/
#define FDCAN_TXESC_TBDS_Pos (0U)
#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
/***************** Bit definition for FDCAN_TXBRP register ******************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register ******************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register ******************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register ******************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register ******************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register *****************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register ****************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFC register ******************/
#define FDCAN_TXEFC_EFSA_Pos (2U)
#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
#define FDCAN_TXEFC_EFS_Pos (16U)
#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
#define FDCAN_TXEFC_EFWM_Pos (24U)
#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
/***************** Bit definition for FDCAN_TXEFS register ******************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register ******************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/***************** Bit definition for FDCAN_TTTMC register ******************/
#define FDCAN_TTTMC_TMSA_Pos (2U)
#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
#define FDCAN_TTTMC_TME_Pos (16U)
#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
/***************** Bit definition for FDCAN_TTRMC register ******************/
#define FDCAN_TTRMC_RID_Pos (0U)
#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
#define FDCAN_TTRMC_XTD_Pos (30U)
#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
#define FDCAN_TTRMC_RMPS_Pos (31U)
#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
/***************** Bit definition for FDCAN_TTOCF register ******************/
#define FDCAN_TTOCF_OM_Pos (0U)
#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
#define FDCAN_TTOCF_GEN_Pos (3U)
#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
#define FDCAN_TTOCF_TM_Pos (4U)
#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
#define FDCAN_TTOCF_LDSDL_Pos (5U)
#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
#define FDCAN_TTOCF_IRTO_Pos (8U)
#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
#define FDCAN_TTOCF_EECS_Pos (15U)
#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
#define FDCAN_TTOCF_AWL_Pos (16U)
#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
#define FDCAN_TTOCF_EGTF_Pos (24U)
#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
#define FDCAN_TTOCF_ECC_Pos (25U)
#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
#define FDCAN_TTOCF_EVTP_Pos (26U)
#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
/***************** Bit definition for FDCAN_TTMLM register ******************/
#define FDCAN_TTMLM_CCM_Pos (0U)
#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
#define FDCAN_TTMLM_CSS_Pos (6U)
#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
#define FDCAN_TTMLM_TXEW_Pos (8U)
#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
#define FDCAN_TTMLM_ENTT_Pos (16U)
#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
/***************** Bit definition for FDCAN_TURCF register ******************/
#define FDCAN_TURCF_NCL_Pos (0U)
#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
#define FDCAN_TURCF_DC_Pos (16U)
#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
#define FDCAN_TURCF_ELT_Pos (31U)
#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
/***************** Bit definition for FDCAN_TTOCN register ******************/
#define FDCAN_TTOCN_SGT_Pos (0U)
#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
#define FDCAN_TTOCN_ECS_Pos (1U)
#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
#define FDCAN_TTOCN_SWP_Pos (2U)
#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
#define FDCAN_TTOCN_SWS_Pos (3U)
#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
#define FDCAN_TTOCN_RTIE_Pos (5U)
#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
#define FDCAN_TTOCN_TMC_Pos (6U)
#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
#define FDCAN_TTOCN_TTIE_Pos (8U)
#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
#define FDCAN_TTOCN_GCS_Pos (9U)
#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
#define FDCAN_TTOCN_FGP_Pos (10U)
#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
#define FDCAN_TTOCN_TMG_Pos (11U)
#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
#define FDCAN_TTOCN_NIG_Pos (12U)
#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
#define FDCAN_TTOCN_ESCN_Pos (13U)
#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
#define FDCAN_TTOCN_LCKC_Pos (15U)
#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
/***************** Bit definition for FDCAN_TTGTP register ******************/
#define FDCAN_TTGTP_TP_Pos (0U)
#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
#define FDCAN_TTGTP_CTP_Pos (16U)
#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
/***************** Bit definition for FDCAN_TTTMK register ******************/
#define FDCAN_TTTMK_TM_Pos (0U)
#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
#define FDCAN_TTTMK_TICC_Pos (16U)
#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
#define FDCAN_TTTMK_LCKM_Pos (31U)
#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
/***************** Bit definition for FDCAN_TTIR register *******************/
#define FDCAN_TTIR_SBC_Pos (0U)
#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
#define FDCAN_TTIR_SMC_Pos (1U)
#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
#define FDCAN_TTIR_CSM_Pos (2U)
#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
#define FDCAN_TTIR_SOG_Pos (3U)
#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
#define FDCAN_TTIR_RTMI_Pos (4U)
#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
#define FDCAN_TTIR_TTMI_Pos (5U)
#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
#define FDCAN_TTIR_SWE_Pos (6U)
#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
#define FDCAN_TTIR_GTW_Pos (7U)
#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
#define FDCAN_TTIR_GTD_Pos (8U)
#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
#define FDCAN_TTIR_GTE_Pos (9U)
#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
#define FDCAN_TTIR_TXU_Pos (10U)
#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
#define FDCAN_TTIR_TXO_Pos (11U)
#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
#define FDCAN_TTIR_SE1_Pos (12U)
#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
#define FDCAN_TTIR_SE2_Pos (13U)
#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
#define FDCAN_TTIR_ELC_Pos (14U)
#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
#define FDCAN_TTIR_IWT_Pos (15U)
#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
#define FDCAN_TTIR_WT_Pos (16U)
#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
#define FDCAN_TTIR_AW_Pos (17U)
#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
#define FDCAN_TTIR_CER_Pos (18U)
#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
/***************** Bit definition for FDCAN_TTIE register *******************/
#define FDCAN_TTIE_SBCE_Pos (0U)
#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
#define FDCAN_TTIE_SMCE_Pos (1U)
#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
#define FDCAN_TTIE_CSME_Pos (2U)
#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
#define FDCAN_TTIE_SOGE_Pos (3U)
#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
#define FDCAN_TTIE_RTMIE_Pos (4U)
#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
#define FDCAN_TTIE_TTMIE_Pos (5U)
#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
#define FDCAN_TTIE_SWEE_Pos (6U)
#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
#define FDCAN_TTIE_GTWE_Pos (7U)
#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
#define FDCAN_TTIE_GTDE_Pos (8U)
#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
#define FDCAN_TTIE_GTEE_Pos (9U)
#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
#define FDCAN_TTIE_TXUE_Pos (10U)
#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
#define FDCAN_TTIE_TXOE_Pos (11U)
#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
#define FDCAN_TTIE_SE1E_Pos (12U)
#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
#define FDCAN_TTIE_SE2E_Pos (13U)
#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
#define FDCAN_TTIE_ELCE_Pos (14U)
#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
#define FDCAN_TTIE_IWTE_Pos (15U)
#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
#define FDCAN_TTIE_WTE_Pos (16U)
#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
#define FDCAN_TTIE_AWE_Pos (17U)
#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
#define FDCAN_TTIE_CERE_Pos (18U)
#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
/***************** Bit definition for FDCAN_TTILS register ******************/
#define FDCAN_TTILS_SBCS_Pos (0U)
#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
#define FDCAN_TTILS_SMCS_Pos (1U)
#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
#define FDCAN_TTILS_CSMS_Pos (2U)
#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
#define FDCAN_TTILS_SOGS_Pos (3U)
#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
#define FDCAN_TTILS_RTMIS_Pos (4U)
#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
#define FDCAN_TTILS_TTMIS_Pos (5U)
#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
#define FDCAN_TTILS_SWES_Pos (6U)
#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
#define FDCAN_TTILS_GTWS_Pos (7U)
#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
#define FDCAN_TTILS_GTDS_Pos (8U)
#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
#define FDCAN_TTILS_GTES_Pos (9U)
#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
#define FDCAN_TTILS_TXUS_Pos (10U)
#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
#define FDCAN_TTILS_TXOS_Pos (11U)
#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
#define FDCAN_TTILS_SE1S_Pos (12U)
#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
#define FDCAN_TTILS_SE2S_Pos (13U)
#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
#define FDCAN_TTILS_ELCS_Pos (14U)
#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
#define FDCAN_TTILS_IWTS_Pos (15U)
#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
#define FDCAN_TTILS_WTS_Pos (16U)
#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
#define FDCAN_TTILS_AWS_Pos (17U)
#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
#define FDCAN_TTILS_CERS_Pos (18U)
#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
/***************** Bit definition for FDCAN_TTOST register ******************/
#define FDCAN_TTOST_EL_Pos (0U)
#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
#define FDCAN_TTOST_MS_Pos (2U)
#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
#define FDCAN_TTOST_SYS_Pos (4U)
#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
#define FDCAN_TTOST_QGTP_Pos (6U)
#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
#define FDCAN_TTOST_QCS_Pos (7U)
#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
#define FDCAN_TTOST_RTO_Pos (8U)
#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
#define FDCAN_TTOST_WGTD_Pos (22U)
#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
#define FDCAN_TTOST_GFI_Pos (23U)
#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
#define FDCAN_TTOST_TMP_Pos (24U)
#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
#define FDCAN_TTOST_GSI_Pos (27U)
#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
#define FDCAN_TTOST_WFE_Pos (28U)
#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
#define FDCAN_TTOST_AWE_Pos (29U)
#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
#define FDCAN_TTOST_WECS_Pos (30U)
#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
#define FDCAN_TTOST_SPL_Pos (31U)
#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
/***************** Bit definition for FDCAN_TURNA register ******************/
#define FDCAN_TURNA_NAV_Pos (0U)
#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
/***************** Bit definition for FDCAN_TTLGT register ******************/
#define FDCAN_TTLGT_LT_Pos (0U)
#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
#define FDCAN_TTLGT_GT_Pos (16U)
#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
/***************** Bit definition for FDCAN_TTCTC register ******************/
#define FDCAN_TTCTC_CT_Pos (0U)
#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
#define FDCAN_TTCTC_CC_Pos (16U)
#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
/***************** Bit definition for FDCAN_TTCPT register ******************/
#define FDCAN_TTCPT_CCV_Pos (0U)
#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
#define FDCAN_TTCPT_SWV_Pos (16U)
#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
/***************** Bit definition for FDCAN_TTCSM register ******************/
#define FDCAN_TTCSM_CSM_Pos (0U)
#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
/***************** Bit definition for FDCAN_TTTS register *******************/
#define FDCAN_TTTS_SWTSEL_Pos (0U)
#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
#define FDCAN_TTTS_EVTSEL_Pos (4U)
#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
/******************************************************************************/
/* */
/* FDCANCCU (Clock Calibration unit) */
/* */
/******************************************************************************/
/***************** Bit definition for FDCANCCU_CREL register ****************/
#define FDCANCCU_CREL_DAY_Pos (0U)
#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCANCCU_CREL_MON_Pos (8U)
#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
#define FDCANCCU_CREL_YEAR_Pos (16U)
#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCANCCU_CREL_STEP_Pos (24U)
#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
#define FDCANCCU_CREL_REL_Pos (28U)
#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCANCCU_CCFG register ****************/
#define FDCANCCU_CCFG_TQBT_Pos (0U)
#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
#define FDCANCCU_CCFG_BCC_Pos (6U)
#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
#define FDCANCCU_CCFG_CFL_Pos (7U)
#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
#define FDCANCCU_CCFG_OCPM_Pos (8U)
#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
#define FDCANCCU_CCFG_CDIV_Pos (16U)
#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
#define FDCANCCU_CCFG_SWR_Pos (31U)
#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
/***************** Bit definition for FDCANCCU_CSTAT register ***************/
#define FDCANCCU_CSTAT_OCPC_Pos (0U)
#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
#define FDCANCCU_CSTAT_TQC_Pos (18U)
#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
#define FDCANCCU_CSTAT_CALS_Pos (30U)
#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
/****************** Bit definition for FDCANCCU_CWD register ****************/
#define FDCANCCU_CWD_WDC_Pos (0U)
#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
#define FDCANCCU_CWD_WDV_Pos (16U)
#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
/****************** Bit definition for FDCANCCU_IR register *****************/
#define FDCANCCU_IR_CWE_Pos (0U)
#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
#define FDCANCCU_IR_CSC_Pos (1U)
#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
/****************** Bit definition for FDCANCCU_IE register *****************/
#define FDCANCCU_IE_CWEE_Pos (0U)
#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
#define FDCANCCU_IE_CSCE_Pos (1U)
#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCRx registers (x=1..4) **********/
#define FMC_BCRx_MBKEN_Pos (0U)
#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!< Memory bank enable bit */
#define FMC_BCRx_MUXEN_Pos (1U)
#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!< Address/data multiplexing enable bit */
#define FMC_BCRx_MTYP_Pos (2U)
#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!< Memory type */
#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCRx_MWID_Pos (4U)
#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!< Memory data bus width */
#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCRx_FACCEN_Pos (6U)
#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!< Flash access enable */
#define FMC_BCRx_BURSTEN_Pos (8U)
#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!< Burst enable bit */
#define FMC_BCRx_WAITPOL_Pos (9U)
#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!< Wait signal polarity bit */
#define FMC_BCRx_WAITCFG_Pos (11U)
#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!< Wait timing configuration */
#define FMC_BCRx_WREN_Pos (12U)
#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!< Write enable bit */
#define FMC_BCRx_WAITEN_Pos (13U)
#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!< Wait enable bit */
#define FMC_BCRx_EXTMOD_Pos (14U)
#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!< Extended mode enable */
#define FMC_BCRx_ASYNCWAIT_Pos (15U)
#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!< Wait signal during asynchronous transfers */
#define FMC_BCRx_CPSIZE_Pos (16U)
#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!< CRAM page size */
#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCRx_CBURSTRW_Pos (19U)
#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!< Write burst enable */
#define FMC_BCRx_CSCOUNT_Pos (20U)
#define FMC_BCRx_CSCOUNT_Msk (0x3UL << FMC_BCRx_CSCOUNT_Pos) /*!< 0x00300000 */
#define FMC_BCRx_CSCOUNT FMC_BCRx_CSCOUNT_Msk /*!< Chip Select (CS) counter */
#define FMC_BCRx_CSCOUNT_0 (0x1UL << FMC_BCRx_CSCOUNT_Pos) /*!< 0x00100000 */
#define FMC_BCRx_CSCOUNT_1 (0x2UL << FMC_BCRx_CSCOUNT_Pos) /*!< 0x00200000 */
#define FMC_BCRx_NBLSET_Pos (22U)
#define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!< Byte lane (NBL) setup */
#define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00400000 */
#define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BTRx registers (x=1..4) **********/
#define FMC_BTRx_ADDSET_Pos (0U)
#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!< Address setup phase duration */
#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTRx_ADDHLD_Pos (4U)
#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!< Address-hold phase duration */
#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTRx_DATAST_Pos (8U)
#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!< Data-phase duration */
#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTRx_BUSTURN_Pos (16U)
#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!< Bus turnaround phase duration */
#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTRx_CLKDIV_Pos (20U)
#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!< Clock divide ratio */
#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTRx_DATLAT_Pos (24U)
#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!< Data latency for synchronous memory */
#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTRx_ACCMOD_Pos (28U)
#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!< Access mode */
#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTRx_DATAHLD_Pos (30U)
#define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!< Data Hold phase duration */
#define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
/***************** Bit definition for FMC_CFGR register *****************/
#define FMC_CFGR_CLKDIV_Pos (16U)
#define FMC_CFGR_CLKDIV_Msk (0xFUL << FMC_CFGR_CLKDIV_Pos) /*!< 0x000F0000 */
#define FMC_CFGR_CLKDIV FMC_CFGR_CLKDIV_Msk /*!< Clock divide ratio (for FMC_CLK signal) */
#define FMC_CFGR_CLKDIV_0 (0x1UL << FMC_CFGR_CLKDIV_Pos) /*!< 0x00010000 */
#define FMC_CFGR_CLKDIV_1 (0x2UL << FMC_CFGR_CLKDIV_Pos) /*!< 0x00020000 */
#define FMC_CFGR_CLKDIV_2 (0x4UL << FMC_CFGR_CLKDIV_Pos) /*!< 0x00040000 */
#define FMC_CFGR_CLKDIV_3 (0x8UL << FMC_CFGR_CLKDIV_Pos) /*!< 0x00080000 */
#define FMC_CFGR_CCLKEN_Pos (20U)
#define FMC_CFGR_CCLKEN_Msk (0x1UL << FMC_CFGR_CCLKEN_Pos) /*!< 0x00100000 */
#define FMC_CFGR_CCLKEN FMC_CFGR_CCLKEN_Msk /*!< Continuous clock enable */
#define FMC_CFGR_BMAP_Pos (24U)
#define FMC_CFGR_BMAP_Msk (0x3UL << FMC_CFGR_BMAP_Pos) /*!< 0x03000000 */
#define FMC_CFGR_BMAP FMC_CFGR_BMAP_Msk /*!< FMC memory region mapping */
#define FMC_CFGR_BMAP_0 (0x1UL << FMC_CFGR_BMAP_Pos) /*!< 0x01000000 */
#define FMC_CFGR_BMAP_1 (0x2UL << FMC_CFGR_BMAP_Pos) /*!< 0x02000000 */
#define FMC_CFGR_FMCEN_Pos (31U)
#define FMC_CFGR_FMCEN_Msk (0x1UL << FMC_CFGR_FMCEN_Pos) /*!< 0x80000000 */
#define FMC_CFGR_FMCEN FMC_CFGR_FMCEN_Msk /*!< FMC controller enable */
/****************** Bit definition for FMC_PCR register *********************/
#define FMC_PCR_PWAITEN_Pos (1U)
#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!< Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos (2U)
#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!< NAND Flash memory bank enable bit */
#define FMC_PCR_PWID_Pos (4U)
#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!< Data bus width */
#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos (6U)
#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!< ECC computation logic enable bit */
#define FMC_PCR_ECCALG_Pos (8U)
#define FMC_PCR_ECCALG_Msk (0x1UL << FMC_PCR_ECCALG_Pos) /*!< 0x00000100 */
#define FMC_PCR_ECCALG FMC_PCR_ECCALG_Msk /*!< ECC algorithm */
#define FMC_PCR_TCLR_Pos (9U)
#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!< CLE to RE delay */
#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos (13U)
#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!< ALE to RE delay */
#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
#define FMC_PCR_ECCSS_Pos (17U)
#define FMC_PCR_ECCSS_Msk (0x7UL << FMC_PCR_ECCSS_Pos) /*!< 0x000E0000 */
#define FMC_PCR_ECCSS FMC_PCR_ECCSS_Msk /*!< ECC page size */
#define FMC_PCR_ECCSS_0 (0x1UL << FMC_PCR_ECCSS_Pos) /*!< 0x00020000 */
#define FMC_PCR_ECCSS_1 (0x2UL << FMC_PCR_ECCSS_Pos) /*!< 0x00040000 */
#define FMC_PCR_ECCSS_2 (0x4UL << FMC_PCR_ECCSS_Pos) /*!< 0x00080000 */
#define FMC_PCR_BCHECC_Pos (24U)
#define FMC_PCR_BCHECC_Msk (0x1UL << FMC_PCR_BCHECC_Pos) /*!< 0x01000000 */
#define FMC_PCR_BCHECC FMC_PCR_BCHECC_Msk /*!< BCH error correction capability */
#define FMC_PCR_WEN_Pos (25U)
#define FMC_PCR_WEN_Msk (0x1UL << FMC_PCR_WEN_Pos) /*!< 0x02000000 */
#define FMC_PCR_WEN FMC_PCR_WEN_Msk /*!< Write enable */
/****************** Bit definition for FMC_SR register ******************/
#define FMC_SR_ISOST_Pos (0U)
#define FMC_SR_ISOST_Msk (0x3UL << FMC_SR_ISOST_Pos) /*!< 0x00000003 */
#define FMC_SR_ISOST FMC_SR_ISOST_Msk /*!< FMC isolation state with respect to the AXI interface */
#define FMC_SR_PEF_Pos (4U)
#define FMC_SR_PEF_Msk (0x1UL << FMC_SR_PEF_Pos) /*!< 0x00000010 */
#define FMC_SR_PEF FMC_SR_PEF_Msk /*!< Pipe Empty Flag */
#define FMC_SR_NWRF_Pos (6U)
#define FMC_SR_NWRF_Msk (0x1UL << FMC_SR_NWRF_Pos) /*!< 0x00000040 */
#define FMC_SR_NWRF FMC_SR_NWRF_Msk /*!< NAND write request flag */
/****************** Bit definition for FMC_PMEM register ********************/
#define FMC_PMEM_MEMSET_Pos (0U)
#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!< Common memory setup time */
#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT_Pos (8U)
#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!< Common memory wait time */
#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD_Pos (16U)
#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!< Common memory hold time */
#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ_Pos (24U)
#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!< Common memory databus Hi-Z time */
#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PATT register ********************/
#define FMC_PATT_ATTSET_Pos (0U)
#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!< Attribute memory setup time */
#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT_Pos (8U)
#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!< Attribute memory wait time */
#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD_Pos (16U)
#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!< Attribute memory hold time */
#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ_Pos (24U)
#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!< Attribute memory data bus Hi-Z time */
#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
/***************** Bit definition for FMC_HPR register ******************/
#define FMC_HPR_HPR_Pos (0U)
#define FMC_HPR_HPR_Msk (0xFFFFFFFFUL << FMC_HPR_HPR_Pos) /*!< 0xFFFFFFFF */
#define FMC_HPR_HPR FMC_HPR_HPR_Msk /*!< Hamming parity result */
/**************** Bit definition for FMC_HECCR register *****************/
#define FMC_HECCR_HECC_Pos (0U)
#define FMC_HECCR_HECC_Msk (0xFFFFFFFFUL << FMC_HECCR_HECC_Pos) /*!< 0xFFFFFFFF */
#define FMC_HECCR_HECC FMC_HECCR_HECC_Msk /*!< ECC result */
/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
#define FMC_BWTRx_ADDSET_Pos (0U)
#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!< Address setup phase duration */
#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTRx_ADDHLD_Pos (4U)
#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!< Address-hold phase duration */
#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTRx_DATAST_Pos (8U)
#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!< Data-phase duration */
#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTRx_BUSTURN_Pos (16U)
#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!< Bus turnaround phase duration */
#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTRx_ACCMOD_Pos (28U)
#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!< Access mode */
#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTRx_DATAHLD_Pos (30U)
#define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!< Data Hold phase duration */
#define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
#define FMC_SDCRx_NC_Pos (0U)
#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!< Number of column address bits */
#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
#define FMC_SDCRx_NR_Pos (2U)
#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!< Number of row address bits */
#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
#define FMC_SDCRx_MWID_Pos (4U)
#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!< Memory data bus width */
#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
#define FMC_SDCRx_NB_Pos (6U)
#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!< Number of internal banks */
#define FMC_SDCRx_CAS_Pos (7U)
#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!< CAS latency */
#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
#define FMC_SDCRx_WP_Pos (9U)
#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!< Write protection */
#define FMC_SDCRx_SDCLK_Pos (10U)
#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!< SDRAM clock configuration */
#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
#define FMC_SDCRx_RPIPE_Pos (13U)
#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!< Read pipe */
#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
#define FMC_SDCRx_SDEN_Pos (16U)
#define FMC_SDCRx_SDEN_Msk (0x1UL << FMC_SDCRx_SDEN_Pos) /*!< 0x00010000 */
#define FMC_SDCRx_SDEN FMC_SDCRx_SDEN_Msk /*!< SDRAM device enable */
#define FMC_SDCRx_SDINIT_Pos (17U)
#define FMC_SDCRx_SDINIT_Msk (0x1UL << FMC_SDCRx_SDINIT_Pos) /*!< 0x00020000 */
#define FMC_SDCRx_SDINIT FMC_SDCRx_SDINIT_Msk /*!< SDRAM device initialization */
/****************** Bit definition for FMC_SDTRx(1,2) register **************/
#define FMC_SDTRx_TMRD_Pos (0U)
#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!< Load mode register to active */
#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
#define FMC_SDTRx_TXSR_Pos (4U)
#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<Exit self-refresh delay */
#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
#define FMC_SDTRx_TRAS_Pos (8U)
#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!< Self refresh time */
#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
#define FMC_SDTRx_TRC_Pos (12U)
#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!< Row cycle delay */
#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
#define FMC_SDTRx_TRC_3 (0x8UL << FMC_SDTRx_TRC_Pos) /*!< 0x00008000 */
#define FMC_SDTRx_TWR_Pos (16U)
#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!< Recovery delay */
#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
#define FMC_SDTRx_TWR_3 (0x8UL << FMC_SDTRx_TWR_Pos) /*!< 0x00080000 */
#define FMC_SDTRx_TRP_Pos (20U)
#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!< Row precharge delay */
#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
#define FMC_SDTRx_TRP_3 (0x8UL << FMC_SDTRx_TRP_Pos) /*!< 0x00800000 */
#define FMC_SDTRx_TRCD_Pos (24U)
#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!< Row to column delay */
#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
#define FMC_SDTRx_TRCD_3 (0x8UL << FMC_SDTRx_TRCD_Pos) /*!< 0x08000000 */
/****************** Bit definition for FMC_SDCMR register *******************/
#define FMC_SDCMR_MODE_Pos (0U)
#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!< Command mode */
#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
#define FMC_SDCMR_DS2_Pos (3U)
#define FMC_SDCMR_DS2_Msk (0x1UL << FMC_SDCMR_DS2_Pos) /*!< 0x00000008 */
#define FMC_SDCMR_DS2 FMC_SDCMR_DS2_Msk /*!< Command targeting SDRAM device 2 */
#define FMC_SDCMR_DS1_Pos (4U)
#define FMC_SDCMR_DS1_Msk (0x1UL << FMC_SDCMR_DS1_Pos) /*!< 0x00000010 */
#define FMC_SDCMR_DS1 FMC_SDCMR_DS1_Msk /*!< Command targeting SDRAM device 1 */
#define FMC_SDCMR_NRFS_Pos (5U)
#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!< Number of auto-refresh */
#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
#define FMC_SDCMR_MRD_Pos (9U)
#define FMC_SDCMR_MRD_Msk (0x3FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x007FFE00 */
#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!< Mode register definition */
/****************** Bit definition for FMC_SDRTR register *******************/
#define FMC_SDRTR_CRE_Pos (0U)
#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!< Clear refresh error flag */
#define FMC_SDRTR_RFSCNT_Pos (1U)
#define FMC_SDRTR_RFSCNT_Msk (0x1FFFUL << FMC_SDRTR_RFSCNT_Pos) /*!< 0x00003FFE */
#define FMC_SDRTR_RFSCNT FMC_SDRTR_RFSCNT_Msk /*!< Refresh timer count */
#define FMC_SDRTR_REIE_Pos (14U)
#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!< RES interrupt enable */
/****************** Bit definition for FMC_SDSR register ********************/
#define FMC_SDSR_RE_Pos (0U)
#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!< Refresh error flag */
#define FMC_SDSR_MODES1_Pos (1U)
#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!< Status mode for bank 1 */
#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
#define FMC_SDSR_MODES2_Pos (3U)
#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!< Status mode for bank 2 */
#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
#define FMC_SDSR_CMDOK_Pos (15U)
#define FMC_SDSR_CMDOK_Msk (0x1UL << FMC_SDSR_CMDOK_Pos) /*!< 0x00004000 */
#define FMC_SDSR_CMDOK FMC_SDSR_CMDOK_Msk /*!< Previous command status */
/******************* Bit definition for FMC_IER register ********************/
#define FMC_IER_IREE_Pos (0U)
#define FMC_IER_IREE_Msk (0x1UL << FMC_IER_IREE_Pos) /*!< 0x00000001 */
#define FMC_IER_IREE FMC_IER_IREE_Msk /*!< Interrupt rising edge detection enable bit */
#define FMC_IER_IHLE_Pos (1U)
#define FMC_IER_IHLE_Msk (0x1UL << FMC_IER_IHLE_Pos) /*!< 0x00000002 */
#define FMC_IER_IHLE FMC_IER_IHLE_Msk /*!< Interrupt high-level detection enable bit */
#define FMC_IER_IFEE_Pos (2U)
#define FMC_IER_IFEE_Msk (0x1UL << FMC_IER_IFEE_Pos) /*!< 0x00000004 */
#define FMC_IER_IFEE FMC_IER_IFEE_Msk /*!< Interrupt falling edge detection enable bit */
/******************* Bit definition for FMC_ISR register ********************/
#define FMC_ISR_IREF_Pos (0U)
#define FMC_ISR_IREF_Msk (0x1UL << FMC_ISR_IREF_Pos) /*!< 0x00000001 */
#define FMC_ISR_IREF FMC_ISR_IREF_Msk /*!< Interrupt rising edge flag */
#define FMC_ISR_IHLF_Pos (1U)
#define FMC_ISR_IHLF_Msk (0x1UL << FMC_ISR_IHLF_Pos) /*!< 0x00000002 */
#define FMC_ISR_IHLF FMC_ISR_IHLF_Msk /*!< Interrupt high-level flag */
#define FMC_ISR_IFEF_Pos (2U)
#define FMC_ISR_IFEF_Msk (0x1UL << FMC_ISR_IFEF_Pos) /*!< 0x00000004 */
#define FMC_ISR_IFEF FMC_ISR_IFEF_Msk /*!< Interrupt falling edge flag */
/******************* Bit definition for FMC_ICR register ********************/
#define FMC_ICR_CIREF_Pos (0U)
#define FMC_ICR_CIREF_Msk (0x1UL << FMC_ICR_CIREF_Pos) /*!< 0x00000001 */
#define FMC_ICR_CIREF FMC_ICR_CIREF_Msk /*!< Clear Interrupt rising edge flag */
#define FMC_ICR_CIHLF_Pos (1U)
#define FMC_ICR_CIHLF_Msk (0x1UL << FMC_ICR_CIHLF_Pos) /*!< 0x00000002 */
#define FMC_ICR_CIHLF FMC_ICR_CIHLF_Msk /*!< Clear Interrupt high-level flag */
#define FMC_ICR_CIFEF_Pos (2U)
#define FMC_ICR_CIFEF_Msk (0x1UL << FMC_ICR_CIFEF_Pos) /*!< 0x00000004 */
#define FMC_ICR_CIFEF FMC_ICR_CIFEF_Msk /*!< Clear Interrupt falling edge flag */
/**************** Bit definition for FMC_CSQCR register *****************/
#define FMC_CSQCR_CSQSTART_Pos (0U)
#define FMC_CSQCR_CSQSTART_Msk (0x1UL << FMC_CSQCR_CSQSTART_Pos) /*!< 0x00000001 */
#define FMC_CSQCR_CSQSTART FMC_CSQCR_CSQSTART_Msk /*!< Command Sequencer Enable */
/*************** Bit definition for FMC_CSQCFGR1 register ***************/
#define FMC_CSQCFGR1_CMD2EN_Pos (1U)
#define FMC_CSQCFGR1_CMD2EN_Msk (0x1UL << FMC_CSQCFGR1_CMD2EN_Pos) /*!< 0x00000002 */
#define FMC_CSQCFGR1_CMD2EN FMC_CSQCFGR1_CMD2EN_Msk /*!< Command cycle 2 Enable */
#define FMC_CSQCFGR1_DMADEN_Pos (2U)
#define FMC_CSQCFGR1_DMADEN_Msk (0x1UL << FMC_CSQCFGR1_DMADEN_Pos) /*!< 0x00000004 */
#define FMC_CSQCFGR1_DMADEN FMC_CSQCFGR1_DMADEN_Msk /*!< Command sequencer DMA request data enable */
#define FMC_CSQCFGR1_ACYNBR_Pos (4U)
#define FMC_CSQCFGR1_ACYNBR_Msk (0x7UL << FMC_CSQCFGR1_ACYNBR_Pos) /*!< 0x00000070 */
#define FMC_CSQCFGR1_ACYNBR FMC_CSQCFGR1_ACYNBR_Msk /*!< Address Cycle number */
#define FMC_CSQCFGR1_CMD1_Pos (8U)
#define FMC_CSQCFGR1_CMD1_Msk (0xFFUL << FMC_CSQCFGR1_CMD1_Pos) /*!< 0x0000FF00 */
#define FMC_CSQCFGR1_CMD1 FMC_CSQCFGR1_CMD1_Msk /*!< Command 1 sequencer */
#define FMC_CSQCFGR1_CMD2_Pos (16U)
#define FMC_CSQCFGR1_CMD2_Msk (0xFFUL << FMC_CSQCFGR1_CMD2_Pos) /*!< 0x00FF0000 */
#define FMC_CSQCFGR1_CMD2 FMC_CSQCFGR1_CMD2_Msk /*!< Command 2 sequencer */
#define FMC_CSQCFGR1_CMD1T_Pos (24U)
#define FMC_CSQCFGR1_CMD1T_Msk (0x1UL << FMC_CSQCFGR1_CMD1T_Pos) /*!< 0x01000000 */
#define FMC_CSQCFGR1_CMD1T FMC_CSQCFGR1_CMD1T_Msk /*!< Command 1 Sequencer timings */
#define FMC_CSQCFGR1_CMD2T_Pos (25U)
#define FMC_CSQCFGR1_CMD2T_Msk (0x1UL << FMC_CSQCFGR1_CMD2T_Pos) /*!< 0x02000000 */
#define FMC_CSQCFGR1_CMD2T FMC_CSQCFGR1_CMD2T_Msk /*!< Command 2 Sequencer timings */
/*************** Bit definition for FMC_CSQCFGR2 register ***************/
#define FMC_CSQCFGR2_SQSDTEN_Pos (0U)
#define FMC_CSQCFGR2_SQSDTEN_Msk (0x1UL << FMC_CSQCFGR2_SQSDTEN_Pos) /*!< 0x00000001 */
#define FMC_CSQCFGR2_SQSDTEN FMC_CSQCFGR2_SQSDTEN_Msk /*!< Sequencer spare data transfer enable */
#define FMC_CSQCFGR2_RCMD2EN_Pos (1U)
#define FMC_CSQCFGR2_RCMD2EN_Msk (0x1UL << FMC_CSQCFGR2_RCMD2EN_Pos) /*!< 0x00000002 */
#define FMC_CSQCFGR2_RCMD2EN FMC_CSQCFGR2_RCMD2EN_Msk /*!< Random Command 2 sequencer enable */
#define FMC_CSQCFGR2_DMASEN_Pos (2U)
#define FMC_CSQCFGR2_DMASEN_Msk (0x1UL << FMC_CSQCFGR2_DMASEN_Pos) /*!< 0x00000004 */
#define FMC_CSQCFGR2_DMASEN FMC_CSQCFGR2_DMASEN_Msk /*!< Command sequencer DMA request decoding status enable */
#define FMC_CSQCFGR2_RCMD1_Pos (8U)
#define FMC_CSQCFGR2_RCMD1_Msk (0xFFUL << FMC_CSQCFGR2_RCMD1_Pos) /*!< 0x0000FF00 */
#define FMC_CSQCFGR2_RCMD1 FMC_CSQCFGR2_RCMD1_Msk /*!< Random Command 1 sequencer */
#define FMC_CSQCFGR2_RCMD2_Pos (16U)
#define FMC_CSQCFGR2_RCMD2_Msk (0xFFUL << FMC_CSQCFGR2_RCMD2_Pos) /*!< 0x00FF0000 */
#define FMC_CSQCFGR2_RCMD2 FMC_CSQCFGR2_RCMD2_Msk /*!< Random Command 2 sequencer */
#define FMC_CSQCFGR2_RCMD1T_Pos (24U)
#define FMC_CSQCFGR2_RCMD1T_Msk (0x1UL << FMC_CSQCFGR2_RCMD1T_Pos) /*!< 0x01000000 */
#define FMC_CSQCFGR2_RCMD1T FMC_CSQCFGR2_RCMD1T_Msk /*!< Command 1 sequencer timings */
#define FMC_CSQCFGR2_RCMD2T_Pos (25U)
#define FMC_CSQCFGR2_RCMD2T_Msk (0x1UL << FMC_CSQCFGR2_RCMD2T_Pos) /*!< 0x02000000 */
#define FMC_CSQCFGR2_RCMD2T FMC_CSQCFGR2_RCMD2T_Msk /*!< Command 1 sequencer timings */
/*************** Bit definition for FMC_CSQCFGR3 register ***************/
#define FMC_CSQCFGR3_SNBR_Pos (8U)
#define FMC_CSQCFGR3_SNBR_Msk (0x3FUL << FMC_CSQCFGR3_SNBR_Pos) /*!< 0x00003F00 */
#define FMC_CSQCFGR3_SNBR FMC_CSQCFGR3_SNBR_Msk /*!< Number of sectors to be read/written */
#define FMC_CSQCFGR3_AC1T_Pos (16U)
#define FMC_CSQCFGR3_AC1T_Msk (0x1UL << FMC_CSQCFGR3_AC1T_Pos) /*!< 0x00010000 */
#define FMC_CSQCFGR3_AC1T FMC_CSQCFGR3_AC1T_Msk /*!< Address cycle 1 sequencer timings */
#define FMC_CSQCFGR3_AC2T_Pos (17U)
#define FMC_CSQCFGR3_AC2T_Msk (0x1UL << FMC_CSQCFGR3_AC2T_Pos) /*!< 0x00020000 */
#define FMC_CSQCFGR3_AC2T FMC_CSQCFGR3_AC2T_Msk /*!< Address cycle 2 sequencer timings */
#define FMC_CSQCFGR3_AC3T_Pos (18U)
#define FMC_CSQCFGR3_AC3T_Msk (0x1UL << FMC_CSQCFGR3_AC3T_Pos) /*!< 0x00040000 */
#define FMC_CSQCFGR3_AC3T FMC_CSQCFGR3_AC3T_Msk /*!< Address cycle 3 sequencer timings */
#define FMC_CSQCFGR3_AC4T_Pos (19U)
#define FMC_CSQCFGR3_AC4T_Msk (0x1UL << FMC_CSQCFGR3_AC4T_Pos) /*!< 0x00080000 */
#define FMC_CSQCFGR3_AC4T FMC_CSQCFGR3_AC4T_Msk /*!< Address cycle 4sequencer timings */
#define FMC_CSQCFGR3_AC5T_Pos (20U)
#define FMC_CSQCFGR3_AC5T_Msk (0x1UL << FMC_CSQCFGR3_AC5T_Pos) /*!< 0x00100000 */
#define FMC_CSQCFGR3_AC5T FMC_CSQCFGR3_AC5T_Msk /*!< Address cycle 5 sequencer timings */
#define FMC_CSQCFGR3_SDT_Pos (21U)
#define FMC_CSQCFGR3_SDT_Msk (0x1UL << FMC_CSQCFGR3_SDT_Pos) /*!< 0x00200000 */
#define FMC_CSQCFGR3_SDT FMC_CSQCFGR3_SDT_Msk /*!< Spare data transfer sequencer timings */
#define FMC_CSQCFGR3_RAC1T_Pos (22U)
#define FMC_CSQCFGR3_RAC1T_Msk (0x1UL << FMC_CSQCFGR3_RAC1T_Pos) /*!< 0x00400000 */
#define FMC_CSQCFGR3_RAC1T FMC_CSQCFGR3_RAC1T_Msk /*!< Random Address cycle 1 sequencer timings */
#define FMC_CSQCFGR3_RAC2T_Pos (23U)
#define FMC_CSQCFGR3_RAC2T_Msk (0x1UL << FMC_CSQCFGR3_RAC2T_Pos) /*!< 0x00800000 */
#define FMC_CSQCFGR3_RAC2T FMC_CSQCFGR3_RAC2T_Msk /*!< Random Address cycle 2 sequencer timings */
/**************** Bit definition for FMC_CSQAR1 register ****************/
#define FMC_CSQAR1_ADDC1_Pos (0U)
#define FMC_CSQAR1_ADDC1_Msk (0xFFUL << FMC_CSQAR1_ADDC1_Pos) /*!< 0x000000FF */
#define FMC_CSQAR1_ADDC1 FMC_CSQAR1_ADDC1_Msk /*!< Address Cycle 1 */
#define FMC_CSQAR1_ADDC2_Pos (8U)
#define FMC_CSQAR1_ADDC2_Msk (0xFFUL << FMC_CSQAR1_ADDC2_Pos) /*!< 0x0000FF00 */
#define FMC_CSQAR1_ADDC2 FMC_CSQAR1_ADDC2_Msk /*!< Address Cycle 2 */
#define FMC_CSQAR1_ADDC3_Pos (16U)
#define FMC_CSQAR1_ADDC3_Msk (0xFFUL << FMC_CSQAR1_ADDC3_Pos) /*!< 0x00FF0000 */
#define FMC_CSQAR1_ADDC3 FMC_CSQAR1_ADDC3_Msk /*!< Address Cycle 3 */
#define FMC_CSQAR1_ADDC4_Pos (24U)
#define FMC_CSQAR1_ADDC4_Msk (0xFFUL << FMC_CSQAR1_ADDC4_Pos) /*!< 0xFF000000 */
#define FMC_CSQAR1_ADDC4 FMC_CSQAR1_ADDC4_Msk /*!< Address Cycle 4 */
/**************** Bit definition for FMC_CSQAR2 register ****************/
#define FMC_CSQAR2_ADDC5_Pos (0U)
#define FMC_CSQAR2_ADDC5_Msk (0xFFUL << FMC_CSQAR2_ADDC5_Pos) /*!< 0x000000FF */
#define FMC_CSQAR2_ADDC5 FMC_CSQAR2_ADDC5_Msk /*!< Address Cycle 5 */
#define FMC_CSQAR2_SAO_Pos (16U)
#define FMC_CSQAR2_SAO_Msk (0xFFFFUL << FMC_CSQAR2_SAO_Pos) /*!< 0xFFFF0000 */
#define FMC_CSQAR2_SAO FMC_CSQAR2_SAO_Msk /*!< Spare Area Address Offset. */
/**************** Bit definition for FMC_CSQIER register ****************/
#define FMC_CSQIER_TCIE_Pos (0U)
#define FMC_CSQIER_TCIE_Msk (0x1UL << FMC_CSQIER_TCIE_Pos) /*!< 0x00000001 */
#define FMC_CSQIER_TCIE FMC_CSQIER_TCIE_Msk /*!< Transfer Complete Interrupt enable */
#define FMC_CSQIER_SCIE_Pos (1U)
#define FMC_CSQIER_SCIE_Msk (0x1UL << FMC_CSQIER_SCIE_Pos) /*!< 0x00000002 */
#define FMC_CSQIER_SCIE FMC_CSQIER_SCIE_Msk /*!< Sector Complete interrupt enable */
#define FMC_CSQIER_SEIE_Pos (2U)
#define FMC_CSQIER_SEIE_Msk (0x1UL << FMC_CSQIER_SEIE_Pos) /*!< 0x00000004 */
#define FMC_CSQIER_SEIE FMC_CSQIER_SEIE_Msk /*!< Sector Error interrupt enable */
#define FMC_CSQIER_SUEIE_Pos (3U)
#define FMC_CSQIER_SUEIE_Msk (0x1UL << FMC_CSQIER_SUEIE_Pos) /*!< 0x00000008 */
#define FMC_CSQIER_SUEIE FMC_CSQIER_SUEIE_Msk /*!< Sector Uncorrectable Error interrupt enable */
#define FMC_CSQIER_CMDTCIE_Pos (4U)
#define FMC_CSQIER_CMDTCIE_Msk (0x1UL << FMC_CSQIER_CMDTCIE_Pos) /*!< 0x00000010 */
#define FMC_CSQIER_CMDTCIE FMC_CSQIER_CMDTCIE_Msk /*!< Command Transfer Complete interrupt enable */
/**************** Bit definition for FMC_CSQISR register ****************/
#define FMC_CSQISR_TCF_Pos (0U)
#define FMC_CSQISR_TCF_Msk (0x1UL << FMC_CSQISR_TCF_Pos) /*!< 0x00000001 */
#define FMC_CSQISR_TCF FMC_CSQISR_TCF_Msk /*!< Transfer Complete flag */
#define FMC_CSQISR_SCF_Pos (1U)
#define FMC_CSQISR_SCF_Msk (0x1UL << FMC_CSQISR_SCF_Pos) /*!< 0x00000002 */
#define FMC_CSQISR_SCF FMC_CSQISR_SCF_Msk /*!< Sector Complete flag */
#define FMC_CSQISR_SEF_Pos (2U)
#define FMC_CSQISR_SEF_Msk (0x1UL << FMC_CSQISR_SEF_Pos) /*!< 0x00000004 */
#define FMC_CSQISR_SEF FMC_CSQISR_SEF_Msk /*!< Sector Error flag */
#define FMC_CSQISR_SUEF_Pos (3U)
#define FMC_CSQISR_SUEF_Msk (0x1UL << FMC_CSQISR_SUEF_Pos) /*!< 0x00000008 */
#define FMC_CSQISR_SUEF FMC_CSQISR_SUEF_Msk /*!< Sector Uncorrectable Error flag */
#define FMC_CSQISR_CMDTCF_Pos (4U)
#define FMC_CSQISR_CMDTCF_Msk (0x1UL << FMC_CSQISR_CMDTCF_Pos) /*!< 0x00000010 */
#define FMC_CSQISR_CMDTCF FMC_CSQISR_CMDTCF_Msk /*!< Command Transfer Complete flag */
/**************** Bit definition for FMC_CSQICR register ****************/
#define FMC_CSQICR_CTCF_Pos (0U)
#define FMC_CSQICR_CTCF_Msk (0x1UL << FMC_CSQICR_CTCF_Pos) /*!< 0x00000001 */
#define FMC_CSQICR_CTCF FMC_CSQICR_CTCF_Msk /*!< Clear Transfer Complete flag */
#define FMC_CSQICR_CSCF_Pos (1U)
#define FMC_CSQICR_CSCF_Msk (0x1UL << FMC_CSQICR_CSCF_Pos) /*!< 0x00000002 */
#define FMC_CSQICR_CSCF FMC_CSQICR_CSCF_Msk /*!< Clear Sector Complete flag */
#define FMC_CSQICR_CSEF_Pos (2U)
#define FMC_CSQICR_CSEF_Msk (0x1UL << FMC_CSQICR_CSEF_Pos) /*!< 0x00000004 */
#define FMC_CSQICR_CSEF FMC_CSQICR_CSEF_Msk /*!< Clear Sector Error flag */
#define FMC_CSQICR_CSUEF_Pos (3U)
#define FMC_CSQICR_CSUEF_Msk (0x1UL << FMC_CSQICR_CSUEF_Pos) /*!< 0x00000008 */
#define FMC_CSQICR_CSUEF FMC_CSQICR_CSUEF_Msk /*!< Clear Sector uncorrectable Error flag */
#define FMC_CSQICR_CCMDTCF_Pos (4U)
#define FMC_CSQICR_CCMDTCF_Msk (0x1UL << FMC_CSQICR_CCMDTCF_Pos) /*!< 0x00000010 */
#define FMC_CSQICR_CCMDTCF FMC_CSQICR_CCMDTCF_Msk /*!< Clear Command Transfer Complete flag */
/*************** Bit definition for FMC_CSQEMSR register ****************/
#define FMC_CSQEMSR_SEM_Pos (0U)
#define FMC_CSQEMSR_SEM_Msk (0xFFFFUL << FMC_CSQEMSR_SEM_Pos) /*!< 0x0000FFFF */
#define FMC_CSQEMSR_SEM FMC_CSQEMSR_SEM_Msk /*!< Sector Error mapping */
/**************** Bit definition for FMC_BCHIER register ****************/
#define FMC_BCHIER_DUEIE_Pos (0U)
#define FMC_BCHIER_DUEIE_Msk (0x1UL << FMC_BCHIER_DUEIE_Pos) /*!< 0x00000001 */
#define FMC_BCHIER_DUEIE FMC_BCHIER_DUEIE_Msk /*!< Decoder Uncorrectable Errors Interrupt enable */
#define FMC_BCHIER_DERIE_Pos (1U)
#define FMC_BCHIER_DERIE_Msk (0x1UL << FMC_BCHIER_DERIE_Pos) /*!< 0x00000002 */
#define FMC_BCHIER_DERIE FMC_BCHIER_DERIE_Msk /*!< Decoder Error Ready Interrupt enable */
#define FMC_BCHIER_DEFIE_Pos (2U)
#define FMC_BCHIER_DEFIE_Msk (0x1UL << FMC_BCHIER_DEFIE_Pos) /*!< 0x00000004 */
#define FMC_BCHIER_DEFIE FMC_BCHIER_DEFIE_Msk /*!< Decoder Error Found Interrupt enable */
#define FMC_BCHIER_DSRIE_Pos (3U)
#define FMC_BCHIER_DSRIE_Msk (0x1UL << FMC_BCHIER_DSRIE_Pos) /*!< 0x00000008 */
#define FMC_BCHIER_DSRIE FMC_BCHIER_DSRIE_Msk /*!< Decoder Syndrome Ready Interrupt enable */
#define FMC_BCHIER_EPBRIE_Pos (4U)
#define FMC_BCHIER_EPBRIE_Msk (0x1UL << FMC_BCHIER_EPBRIE_Pos) /*!< 0x00000010 */
#define FMC_BCHIER_EPBRIE FMC_BCHIER_EPBRIE_Msk /*!< Decoder Parity Bits Ready Interrupt enable */
/**************** Bit definition for FMC_BCHISR register ****************/
#define FMC_BCHISR_DUEF_Pos (0U)
#define FMC_BCHISR_DUEF_Msk (0x1UL << FMC_BCHISR_DUEF_Pos) /*!< 0x00000001 */
#define FMC_BCHISR_DUEF FMC_BCHISR_DUEF_Msk /*!< Decoder Uncorrectable Errors flag */
#define FMC_BCHISR_DERF_Pos (1U)
#define FMC_BCHISR_DERF_Msk (0x1UL << FMC_BCHISR_DERF_Pos) /*!< 0x00000002 */
#define FMC_BCHISR_DERF FMC_BCHISR_DERF_Msk /*!< Decoder Error Ready flag */
#define FMC_BCHISR_DEFF_Pos (2U)
#define FMC_BCHISR_DEFF_Msk (0x1UL << FMC_BCHISR_DEFF_Pos) /*!< 0x00000004 */
#define FMC_BCHISR_DEFF FMC_BCHISR_DEFF_Msk /*!< Decoder Error Found flag */
#define FMC_BCHISR_DSRF_Pos (3U)
#define FMC_BCHISR_DSRF_Msk (0x1UL << FMC_BCHISR_DSRF_Pos) /*!< 0x00000008 */
#define FMC_BCHISR_DSRF FMC_BCHISR_DSRF_Msk /*!< Decoder Syndrome Ready flag */
#define FMC_BCHISR_EPBRF_Pos (4U)
#define FMC_BCHISR_EPBRF_Msk (0x1UL << FMC_BCHISR_EPBRF_Pos) /*!< 0x00000010 */
#define FMC_BCHISR_EPBRF FMC_BCHISR_EPBRF_Msk /*!< Encoder Parity Bits Ready flag */
/**************** Bit definition for FMC_BCHICR register ****************/
#define FMC_BCHICR_CDUEF_Pos (0U)
#define FMC_BCHICR_CDUEF_Msk (0x1UL << FMC_BCHICR_CDUEF_Pos) /*!< 0x00000001 */
#define FMC_BCHICR_CDUEF FMC_BCHICR_CDUEF_Msk /*!< Clear Decoder Uncorrectable Error flag */
#define FMC_BCHICR_CDERF_Pos (1U)
#define FMC_BCHICR_CDERF_Msk (0x1UL << FMC_BCHICR_CDERF_Pos) /*!< 0x00000002 */
#define FMC_BCHICR_CDERF FMC_BCHICR_CDERF_Msk /*!< Clear Decoder Error ready flag */
#define FMC_BCHICR_CDEFF_Pos (2U)
#define FMC_BCHICR_CDEFF_Msk (0x1UL << FMC_BCHICR_CDEFF_Pos) /*!< 0x00000004 */
#define FMC_BCHICR_CDEFF FMC_BCHICR_CDEFF_Msk /*!< Clear Decoder Error Found flag */
#define FMC_BCHICR_CDSRF_Pos (3U)
#define FMC_BCHICR_CDSRF_Msk (0x1UL << FMC_BCHICR_CDSRF_Pos) /*!< 0x00000008 */
#define FMC_BCHICR_CDSRF FMC_BCHICR_CDSRF_Msk /*!< Clear Decoder Syndrome Ready flag */
#define FMC_BCHICR_CEPBRF_Pos (4U)
#define FMC_BCHICR_CEPBRF_Msk (0x1UL << FMC_BCHICR_CEPBRF_Pos) /*!< 0x00000010 */
#define FMC_BCHICR_CEPBRF FMC_BCHICR_CEPBRF_Msk /*!< Clear Encoder Parity Bits Ready flag */
/*************** Bit definition for FMC_BCHPBR1 register ****************/
#define FMC_BCHPBR1_BCHPB_Pos (0U)
#define FMC_BCHPBR1_BCHPB_Msk (0xFFFFFFFFUL << FMC_BCHPBR1_BCHPB_Pos) /*!< 0xFFFFFFFF */
#define FMC_BCHPBR1_BCHPB FMC_BCHPBR1_BCHPB_Msk /*!< BCH parity bits */
/*************** Bit definition for FMC_BCHPBR2 register ****************/
#define FMC_BCHPBR2_BCHPB_Pos (0U)
#define FMC_BCHPBR2_BCHPB_Msk (0xFFFFFFFFUL << FMC_BCHPBR2_BCHPB_Pos) /*!< 0xFFFFFFFF */
#define FMC_BCHPBR2_BCHPB FMC_BCHPBR2_BCHPB_Msk /*!< BCH parity bits */
/*************** Bit definition for FMC_BCHPBR3 register ****************/
#define FMC_BCHPBR3_BCHPB_Pos (0U)
#define FMC_BCHPBR3_BCHPB_Msk (0xFFFFFFFFUL << FMC_BCHPBR3_BCHPB_Pos) /*!< 0xFFFFFFFF */
#define FMC_BCHPBR3_BCHPB FMC_BCHPBR3_BCHPB_Msk /*!< BCH parity bits */
/*************** Bit definition for FMC_BCHPBR4 register ****************/
#define FMC_BCHPBR4_BCHPB_Pos (0U)
#define FMC_BCHPBR4_BCHPB_Msk (0xFFUL << FMC_BCHPBR4_BCHPB_Pos) /*!< 0x000000FF */
#define FMC_BCHPBR4_BCHPB FMC_BCHPBR4_BCHPB_Msk /*!< BCH parity bits */
/*************** Bit definition for FMC_BCHDSR0 register ****************/
#define FMC_BCHDSR0_DUE_Pos (0U)
#define FMC_BCHDSR0_DUE_Msk (0x1UL << FMC_BCHDSR0_DUE_Pos) /*!< 0x00000001 */
#define FMC_BCHDSR0_DUE FMC_BCHDSR0_DUE_Msk /*!< Decoder uncorrectable error */
#define FMC_BCHDSR0_DEF_Pos (1U)
#define FMC_BCHDSR0_DEF_Msk (0x1UL << FMC_BCHDSR0_DEF_Pos) /*!< 0x00000002 */
#define FMC_BCHDSR0_DEF FMC_BCHDSR0_DEF_Msk /*!< Decoder error found */
#define FMC_BCHDSR0_DEN_Pos (4U)
#define FMC_BCHDSR0_DEN_Msk (0xFUL << FMC_BCHDSR0_DEN_Pos) /*!< 0x000000F0 */
#define FMC_BCHDSR0_DEN FMC_BCHDSR0_DEN_Msk /*!< Decoder error number */
/*************** Bit definition for FMC_BCHDSR1 register ****************/
#define FMC_BCHDSR1_EBP1_Pos (0U)
#define FMC_BCHDSR1_EBP1_Msk (0x1FFFUL << FMC_BCHDSR1_EBP1_Pos) /*!< 0x00001FFF */
#define FMC_BCHDSR1_EBP1 FMC_BCHDSR1_EBP1_Msk /*!< Error bit position for error number 1 */
#define FMC_BCHDSR1_EBP2_Pos (16U)
#define FMC_BCHDSR1_EBP2_Msk (0x1FFFUL << FMC_BCHDSR1_EBP2_Pos) /*!< 0x1FFF0000 */
#define FMC_BCHDSR1_EBP2 FMC_BCHDSR1_EBP2_Msk /*!< Error bit position for error number 2 */
/*************** Bit definition for FMC_BCHDSR2 register ****************/
#define FMC_BCHDSR2_EBP3_Pos (0U)
#define FMC_BCHDSR2_EBP3_Msk (0x1FFFUL << FMC_BCHDSR2_EBP3_Pos) /*!< 0x00001FFF */
#define FMC_BCHDSR2_EBP3 FMC_BCHDSR2_EBP3_Msk /*!< Error bit position for error number 3 */
#define FMC_BCHDSR2_EBP4_Pos (16U)
#define FMC_BCHDSR2_EBP4_Msk (0x1FFFUL << FMC_BCHDSR2_EBP4_Pos) /*!< 0x1FFF0000 */
#define FMC_BCHDSR2_EBP4 FMC_BCHDSR2_EBP4_Msk /*!< Error bit position for error number 4 */
/*************** Bit definition for FMC_BCHDSR3 register ****************/
#define FMC_BCHDSR3_EBP5_Pos (0U)
#define FMC_BCHDSR3_EBP5_Msk (0x1FFFUL << FMC_BCHDSR3_EBP5_Pos) /*!< 0x00001FFF */
#define FMC_BCHDSR3_EBP5 FMC_BCHDSR3_EBP5_Msk /*!< Error bit position for error number 5 */
#define FMC_BCHDSR3_EBP6_Pos (16U)
#define FMC_BCHDSR3_EBP6_Msk (0x1FFFUL << FMC_BCHDSR3_EBP6_Pos) /*!< 0x1FFF0000 */
#define FMC_BCHDSR3_EBP6 FMC_BCHDSR3_EBP6_Msk /*!< Error bit position for error number 6 */
/*************** Bit definition for FMC_BCHDSR4 register ****************/
#define FMC_BCHDSR4_EBP7_Pos (0U)
#define FMC_BCHDSR4_EBP7_Msk (0x1FFFUL << FMC_BCHDSR4_EBP7_Pos) /*!< 0x00001FFF */
#define FMC_BCHDSR4_EBP7 FMC_BCHDSR4_EBP7_Msk /*!< Error bit position for error number 7 */
#define FMC_BCHDSR4_EBP8_Pos (16U)
#define FMC_BCHDSR4_EBP8_Msk (0x1FFFUL << FMC_BCHDSR4_EBP8_Pos) /*!< 0x1FFF0000 */
#define FMC_BCHDSR4_EBP8 FMC_BCHDSR4_EBP8_Msk /*!< Error bit position for error number 8 */
/******************************************************************************/
/* */
/* Graphic MMU (GFXMMU) */
/* */
/******************************************************************************/
/****************** Bits definition for GFXMMU_CR register ********************/
#define GFXMMU_CR_B0OIE_Pos (0U)
#define GFXMMU_CR_B0OIE_Msk (0x1UL << GFXMMU_CR_B0OIE_Pos) /*!< 0x00000001 */
#define GFXMMU_CR_B0OIE GFXMMU_CR_B0OIE_Msk /*!< Buffer 0 overflow interrupt enable */
#define GFXMMU_CR_B1OIE_Pos (1U)
#define GFXMMU_CR_B1OIE_Msk (0x1UL << GFXMMU_CR_B1OIE_Pos) /*!< 0x00000002 */
#define GFXMMU_CR_B1OIE GFXMMU_CR_B1OIE_Msk /*!< Buffer 1 overflow interrupt enable */
#define GFXMMU_CR_B2OIE_Pos (2U)
#define GFXMMU_CR_B2OIE_Msk (0x1UL << GFXMMU_CR_B2OIE_Pos) /*!< 0x00000004 */
#define GFXMMU_CR_B2OIE GFXMMU_CR_B2OIE_Msk /*!< Buffer 2 overflow interrupt enable */
#define GFXMMU_CR_B3OIE_Pos (3U)
#define GFXMMU_CR_B3OIE_Msk (0x1UL << GFXMMU_CR_B3OIE_Pos) /*!< 0x00000008 */
#define GFXMMU_CR_B3OIE GFXMMU_CR_B3OIE_Msk /*!< Buffer 3 overflow interrupt enable */
#define GFXMMU_CR_AMEIE_Pos (4U)
#define GFXMMU_CR_AMEIE_Msk (0x1UL << GFXMMU_CR_AMEIE_Pos) /*!< 0x00000010 */
#define GFXMMU_CR_AMEIE GFXMMU_CR_AMEIE_Msk /*!< AHB master error interrupt enable */
#define GFXMMU_CR_BS_Pos (6U)
#define GFXMMU_CR_BS_Msk (0x1UL << GFXMMU_CR_BS_Pos) /*!< 0x00000040 */
#define GFXMMU_CR_BS GFXMMU_CR_BS_Msk /*!< Block size */
#define GFXMMU_CR_ATE_Pos (15U)
#define GFXMMU_CR_ATE_Msk (0x1UL << GFXMMU_CR_ATE_Pos) /*!< 0x00008000 */
#define GFXMMU_CR_ATE GFXMMU_CR_ATE_Msk /*!< Address translation enable */
#define GFXMMU_CR_B0PE_Pos (24U)
#define GFXMMU_CR_B0PE_Msk (0x1UL << GFXMMU_CR_B0PE_Pos) /*!< 0x01000000 */
#define GFXMMU_CR_B0PE GFXMMU_CR_B0PE_Msk /*!< Buffer 0 packing enable */
#define GFXMMU_CR_B0PM_Pos (25U)
#define GFXMMU_CR_B0PM_Msk (0x1UL << GFXMMU_CR_B0PM_Pos) /*!< 0x02000000 */
#define GFXMMU_CR_B0PM GFXMMU_CR_B0PM_Msk /*!< Buffer 0 packing mode */
#define GFXMMU_CR_B1PE_Pos (26U)
#define GFXMMU_CR_B1PE_Msk (0x1UL << GFXMMU_CR_B1PE_Pos) /*!< 0x04000000 */
#define GFXMMU_CR_B1PE GFXMMU_CR_B1PE_Msk /*!< Buffer 1 packing enable */
#define GFXMMU_CR_B1PM_Pos (27U)
#define GFXMMU_CR_B1PM_Msk (0x1UL << GFXMMU_CR_B1PM_Pos) /*!< 0x08000000 */
#define GFXMMU_CR_B1PM GFXMMU_CR_B1PM_Msk /*!< Buffer 1 packing mode */
#define GFXMMU_CR_B2PE_Pos (28U)
#define GFXMMU_CR_B2PE_Msk (0x1UL << GFXMMU_CR_B2PE_Pos) /*!< 0x10000000 */
#define GFXMMU_CR_B2PE GFXMMU_CR_B2PE_Msk /*!< Buffer 0 packing enable */
#define GFXMMU_CR_B2PM_Pos (29U)
#define GFXMMU_CR_B2PM_Msk (0x1UL << GFXMMU_CR_B2PM_Pos) /*!< 0x20000000 */
#define GFXMMU_CR_B2PM GFXMMU_CR_B2PM_Msk /*!< Buffer 0 packing mode */
#define GFXMMU_CR_B3PE_Pos (30U)
#define GFXMMU_CR_B3PE_Msk (0x1UL << GFXMMU_CR_B3PE_Pos) /*!< 0x40000000 */
#define GFXMMU_CR_B3PE GFXMMU_CR_B3PE_Msk /*!< Buffer 0 packing enable */
#define GFXMMU_CR_B3PM_Pos (31U)
#define GFXMMU_CR_B3PM_Msk (0x1UL << GFXMMU_CR_B3PM_Pos) /*!< 0x80000000 */
#define GFXMMU_CR_B3PM GFXMMU_CR_B3PM_Msk /*!< Buffer 0 packing mode */
/****************** Bits definition for GFXMMU_SR register ********************/
#define GFXMMU_SR_B0OF_Pos (0U)
#define GFXMMU_SR_B0OF_Msk (0x1UL << GFXMMU_SR_B0OF_Pos) /*!< 0x00000001 */
#define GFXMMU_SR_B0OF GFXMMU_SR_B0OF_Msk /*!< Buffer 0 overflow flag */
#define GFXMMU_SR_B1OF_Pos (1U)
#define GFXMMU_SR_B1OF_Msk (0x1UL << GFXMMU_SR_B1OF_Pos) /*!< 0x00000002 */
#define GFXMMU_SR_B1OF GFXMMU_SR_B1OF_Msk /*!< Buffer 1 overflow flag */
#define GFXMMU_SR_B2OF_Pos (2U)
#define GFXMMU_SR_B2OF_Msk (0x1UL << GFXMMU_SR_B2OF_Pos) /*!< 0x00000004 */
#define GFXMMU_SR_B2OF GFXMMU_SR_B2OF_Msk /*!< Buffer 2 overflow flag */
#define GFXMMU_SR_B3OF_Pos (3U)
#define GFXMMU_SR_B3OF_Msk (0x1UL << GFXMMU_SR_B3OF_Pos) /*!< 0x00000008 */
#define GFXMMU_SR_B3OF GFXMMU_SR_B3OF_Msk /*!< Buffer 3 overflow flag */
#define GFXMMU_SR_AMEF_Pos (4U)
#define GFXMMU_SR_AMEF_Msk (0x1UL << GFXMMU_SR_AMEF_Pos) /*!< 0x00000010 */
#define GFXMMU_SR_AMEF GFXMMU_SR_AMEF_Msk /*!< AXI master error flag */
/****************** Bits definition for GFXMMU_FCR register *******************/
#define GFXMMU_FCR_CB0OF_Pos (0U)
#define GFXMMU_FCR_CB0OF_Msk (0x1UL << GFXMMU_FCR_CB0OF_Pos) /*!< 0x00000001 */
#define GFXMMU_FCR_CB0OF GFXMMU_FCR_CB0OF_Msk /*!< Clear buffer 0 overflow flag */
#define GFXMMU_FCR_CB1OF_Pos (1U)
#define GFXMMU_FCR_CB1OF_Msk (0x1UL << GFXMMU_FCR_CB1OF_Pos) /*!< 0x00000002 */
#define GFXMMU_FCR_CB1OF GFXMMU_FCR_CB1OF_Msk /*!< Clear buffer 1 overflow flag */
#define GFXMMU_FCR_CB2OF_Pos (2U)
#define GFXMMU_FCR_CB2OF_Msk (0x1UL << GFXMMU_FCR_CB2OF_Pos) /*!< 0x00000004 */
#define GFXMMU_FCR_CB2OF GFXMMU_FCR_CB2OF_Msk /*!< Clear buffer 2 overflow flag */
#define GFXMMU_FCR_CB3OF_Pos (3U)
#define GFXMMU_FCR_CB3OF_Msk (0x1UL << GFXMMU_FCR_CB3OF_Pos) /*!< 0x00000008 */
#define GFXMMU_FCR_CB3OF GFXMMU_FCR_CB3OF_Msk /*!< Clear buffer 3 overflow flag */
#define GFXMMU_FCR_CAMEF_Pos (4U)
#define GFXMMU_FCR_CAMEF_Msk (0x1UL << GFXMMU_FCR_CAMEF_Pos) /*!< 0x00000010 */
#define GFXMMU_FCR_CAMEF GFXMMU_FCR_CAMEF_Msk /*!< Clear AHB master error flag */
/****************** Bits definition for GFXMMU_DVR register *******************/
#define GFXMMU_DVR_DV_Pos (0U)
#define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
#define GFXMMU_DVR_DV GFXMMU_DVR_DV_Msk /*!< DV[31:0] bits (Default value) */
/****************** Bits definition for GFXMMU_DAR register *******************/
#define GFXMMU_DAR_DA_Pos (0U)
#define GFXMMU_DAR_DA_Msk (0xFFUL << GFXMMU_DVR_DA_Pos) /*!< 0x000000FF */
#define GFXMMU_DAR_DA GFXMMU_DVR_DA_Msk /*!< DA[7:0] bits (Default alpha) */
/****************** Bits definition for GFXMMU_B0CR register ******************/
#define GFXMMU_B0CR_PBO_Pos (4U)
#define GFXMMU_B0CR_PBO_Msk (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B0CR_PBO GFXMMU_B0CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B0CR_PBBA_Pos (23U)
#define GFXMMU_B0CR_PBBA_Msk (0x1FFUL << GFXMMU_B0CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B0CR_PBBA GFXMMU_B0CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_B1CR register ******************/
#define GFXMMU_B1CR_PBO_Pos (4U)
#define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B1CR_PBO GFXMMU_B1CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B1CR_PBBA_Pos (23U)
#define GFXMMU_B1CR_PBBA_Msk (0x1FFUL << GFXMMU_B1CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B1CR_PBBA GFXMMU_B1CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_B2CR register ******************/
#define GFXMMU_B2CR_PBO_Pos (4U)
#define GFXMMU_B2CR_PBO_Msk (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B2CR_PBO GFXMMU_B2CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B2CR_PBBA_Pos (23U)
#define GFXMMU_B2CR_PBBA_Msk (0x1FFUL << GFXMMU_B2CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B2CR_PBBA GFXMMU_B2CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_B3CR register ******************/
#define GFXMMU_B3CR_PBO_Pos (4U)
#define GFXMMU_B3CR_PBO_Msk (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos) /*!< 0x007FFFF0 */
#define GFXMMU_B3CR_PBO GFXMMU_B3CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
#define GFXMMU_B3CR_PBBA_Pos (23U)
#define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
#define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
/****************** Bits definition for GFXMMU_LUTxL register *****************/
#define GFXMMU_LUTxL_EN_Pos (0U)
#define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
#define GFXMMU_LUTxL_EN GFXMMU_LUTxL_EN_Msk /*!< Enable */
#define GFXMMU_LUTxL_FVB_Pos (8U)
#define GFXMMU_LUTxL_FVB_Msk (0xFFUL << GFXMMU_LUTxL_FVB_Pos) /*!< 0x0000FF00 */
#define GFXMMU_LUTxL_FVB GFXMMU_LUTxL_FVB_Msk /*!< FVB[7:0] bits (First visible block) */
#define GFXMMU_LUTxL_LVB_Pos (16U)
#define GFXMMU_LUTxL_LVB_Msk (0xFFUL << GFXMMU_LUTxL_LVB_Pos) /*!< 0x00FF0000 */
#define GFXMMU_LUTxL_LVB GFXMMU_LUTxL_LVB_Msk /*!< LVB[7:0] bits (Last visible block) */
/****************** Bits definition for GFXMMU_LUTxH register *****************/
#define GFXMMU_LUTxH_LO_Pos (0U)
#define GFXMMU_LUTxH_LO_Msk (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos) /*!< 0x0003FFFF */
#define GFXMMU_LUTxH_LO GFXMMU_LUTxH_LO_Msk /*!< LO[17:0] bits (Line offset) */
/******************************************************************************/
/* */
/* Graphic Timer (GFXTIM) */
/* */
/******************************************************************************/
/****************** Bits definition for GFXTIM_CR register ******************/
#define GFXTIM_CR_TES_Pos (0U)
#define GFXTIM_CR_TES_Msk (0x3UL << GFXTIM_CR_TES_Pos) /*!< 0x00000003 */
#define GFXTIM_CR_TES GFXTIM_CR_TES_Msk
#define GFXTIM_CR_TES_0 (0x1UL << GFXTIM_CR_TES_Pos) /*!< 0x00000001 */
#define GFXTIM_CR_TES_1 (0x2UL << GFXTIM_CR_TES_Pos) /*!< 0x00000002 */
#define GFXTIM_CR_TEPOL_Pos (4U)
#define GFXTIM_CR_TEPOL_Msk (0x1UL << GFXTIM_CR_TEPOL_Pos) /*!< 0x00000010 */
#define GFXTIM_CR_TEPOL GFXTIM_CR_TEPOL_Msk
#define GFXTIM_CR_SYNCS_Pos (8U)
#define GFXTIM_CR_SYNCS_Msk (0x3UL << GFXTIM_CR_SYNCS_Pos) /*!< 0x00000300 */
#define GFXTIM_CR_SYNCS GFXTIM_CR_SYNCS_Msk
#define GFXTIM_CR_SYNCS_0 (0x1UL << GFXTIM_CR_SYNCS_Pos) /*!< 0x00000100 */
#define GFXTIM_CR_SYNCS_1 (0x2UL << GFXTIM_CR_SYNCS_Pos) /*!< 0x00000200 */
#define GFXTIM_CR_FCCOE_Pos (16U)
#define GFXTIM_CR_FCCOE_Msk (0x1UL << GFXTIM_CR_FCCOE_Pos) /*!< 0x00010000 */
#define GFXTIM_CR_FCCOE GFXTIM_CR_FCCOE_Msk
#define GFXTIM_CR_LCCOE_Pos (17U)
#define GFXTIM_CR_LCCOE_Msk (0x1UL << GFXTIM_CR_LCCOE_Pos) /*!< 0x00020000 */
#define GFXTIM_CR_LCCOE GFXTIM_CR_LCCOE_Msk
/****************** Bits definition for GFXTIM_CR register ******************/
#define GFXTIM_CGCR_LCS_Pos (0U)
#define GFXTIM_CGCR_LCS_Msk (0x7UL << GFXTIM_CGCR_LCS_Pos) /*!< 0x00000007 */
#define GFXTIM_CGCR_LCS GFXTIM_CGCR_LCS_Msk
#define GFXTIM_CGCR_LCS_0 (0x1UL << GFXTIM_CGCR_LCS_Pos) /*!< 0x00000001 */
#define GFXTIM_CGCR_LCS_1 (0x2UL << GFXTIM_CGCR_LCS_Pos) /*!< 0x00000002 */
#define GFXTIM_CGCR_LCS_2 (0x4UL << GFXTIM_CGCR_LCS_Pos) /*!< 0x00000004 */
#define GFXTIM_CGCR_LCCCS_Pos (4U)
#define GFXTIM_CGCR_LCCCS_Msk (0x1UL << GFXTIM_CGCR_LCCCS_Pos) /*!< 0x00000010 */
#define GFXTIM_CGCR_LCCCS GFXTIM_CGCR_LCCCS_Msk
#define GFXTIM_CGCR_LCCFR_Pos (8U)
#define GFXTIM_CGCR_LCCFR_Msk (0x1UL << GFXTIM_CGCR_LCCFR_Pos) /*!< 0x00000100 */
#define GFXTIM_CGCR_LCCFR GFXTIM_CGCR_LCCFR_Msk
#define GFXTIM_CGCR_LCCHRS_Pos (12U)
#define GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00007000 */
#define GFXTIM_CGCR_LCCHRS GFXTIM_CGCR_LCCHRS_Msk
#define GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00001000 */
#define GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00002000 */
#define GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) /*!< 0x00004000 */
#define GFXTIM_CGCR_FCS_Pos (16U)
#define GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00000007 */
#define GFXTIM_CGCR_FCS GFXTIM_CGCR_FCS_Msk
#define GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00001000 */
#define GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00002000 */
#define GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) /*!< 0x00004000 */
#define GFXTIM_CGCR_FCCCS_Pos (20U)
#define GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00070000 */
#define GFXTIM_CGCR_FCCCS GFXTIM_CGCR_FCCCS_Msk
#define GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00010000 */
#define GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00020000 */
#define GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) /*!< 0x00040000 */
#define GFXTIM_CGCR_FCCFR_Pos (24U)
#define GFXTIM_CGCR_FCCFR_Msk (0x1UL << GFXTIM_CGCR_FCCFR_Pos) /*!< 0x00100000 */
#define GFXTIM_CGCR_FCCFR GFXTIM_CGCR_FCCFR_Msk
#define GFXTIM_CGCR_FCCHRS_Pos (28U)
#define GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x70000000 */
#define GFXTIM_CGCR_FCCHRS GFXTIM_CGCR_FCCHRS_Msk
#define GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x10000000 */
#define GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x20000000 */
#define GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) /*!< 0x40000000 */
/****************** Bits definition for GFXTIM_TCR register *****************/
#define GFXTIM_TCR_AFCEN_Pos (0U)
#define GFXTIM_TCR_AFCEN_Msk (0x1UL << GFXTIM_TCR_AFCEN_Pos) /*!< 0x00000001 */
#define GFXTIM_TCR_AFCEN GFXTIM_TCR_AFCEN_Msk
#define GFXTIM_TCR_FAFCR_Pos (1U)
#define GFXTIM_TCR_FAFCR_Msk (0x1UL << GFXTIM_TCR_FAFCR_Pos) /*!< 0x00000002 */
#define GFXTIM_TCR_FAFCR GFXTIM_TCR_FAFCR_Msk
#define GFXTIM_TCR_ALCEN_Pos (4U)
#define GFXTIM_TCR_ALCEN_Msk (0x1UL << GFXTIM_TCR_ALCEN_Pos) /*!< 0x00000010 */
#define GFXTIM_TCR_ALCEN GFXTIM_TCR_ALCEN_Msk
#define GFXTIM_TCR_FALCR_Pos (5U)
#define GFXTIM_TCR_FALCR_Msk (0x1UL << GFXTIM_TCR_FALCR_Pos) /*!< 0x00000020 */
#define GFXTIM_TCR_FALCR GFXTIM_TCR_FALCR_Msk
#define GFXTIM_TCR_RFC1EN_Pos (16U)
#define GFXTIM_TCR_RFC1EN_Msk (0x1UL << GFXTIM_TCR_RFC1EN_Pos) /*!< 0x00010000 */
#define GFXTIM_TCR_RFC1EN GFXTIM_TCR_RFC1EN_Msk
#define GFXTIM_TCR_RFC1CM_Pos (17U)
#define GFXTIM_TCR_RFC1CM_Msk (0x1UL << GFXTIM_TCR_RFC1CM_Pos) /*!< 0x00020000 */
#define GFXTIM_TCR_RFC1CM GFXTIM_TCR_RFC1CM_Msk
#define GFXTIM_TCR_FRFC1R_Pos (18U)
#define GFXTIM_TCR_FRFC1R_Msk (0x1UL << GFXTIM_TCR_FRFC1R_Pos) /*!< 0x00040000 */
#define GFXTIM_TCR_FRFC1R GFXTIM_TCR_FRFC1R_Msk
#define GFXTIM_TCR_RFC2EN_Pos (20U)
#define GFXTIM_TCR_RFC2EN_Msk (0x1UL << GFXTIM_TCR_RFC2EN_Pos) /*!< 0x00100000 */
#define GFXTIM_TCR_RFC2EN GFXTIM_TCR_RFC2EN_Msk
#define GFXTIM_TCR_RFC2CM_Pos (21U)
#define GFXTIM_TCR_RFC2CM_Msk (0x1UL << GFXTIM_TCR_RFC2CM_Pos) /*!< 0x00200000 */
#define GFXTIM_TCR_RFC2CM GFXTIM_TCR_RFC2CM_Msk
#define GFXTIM_TCR_FRFC2R_Pos (22U)
#define GFXTIM_TCR_FRFC2R_Msk (0x1UL << GFXTIM_TCR_FRFC2R_Pos) /*!< 0x00400000 */
#define GFXTIM_TCR_FRFC2R GFXTIM_TCR_FRFC2R_Msk
/****************** Bits definition for GFXTIM_TDR register *****************/
#define GFXTIM_TDR_AFCDIS_Pos (0U)
#define GFXTIM_TDR_AFCDIS_Msk (0x1UL << GFXTIM_TDR_AFCDIS_Pos) /*!< 0x00000001 */
#define GFXTIM_TDR_AFCDIS GFXTIM_TDR_AFCDIS_Msk
#define GFXTIM_TDR_ALCDIS_Pos (4U)
#define GFXTIM_TDR_ALCDIS_Msk (0x1UL << GFXTIM_TDR_ALCDIS_Pos) /*!< 0x00000010 */
#define GFXTIM_TDR_ALCDIS GFXTIM_TDR_ALCDIS_Msk
#define GFXTIM_TDR_RFC1DIS_Pos (16U)
#define GFXTIM_TDR_RFC1DIS_Msk (0x1UL << GFXTIM_TDR_RFC1DIS_Pos) /*!< 0x00010000 */
#define GFXTIM_TDR_RFC1DIS GFXTIM_TDR_RFC1DIS_Msk
#define GFXTIM_TDR_RFC2DIS_Pos (20U)
#define GFXTIM_TDR_RFC2DIS_Msk (0x1UL << GFXTIM_TDR_RFC2DIS_Pos) /*!< 0x00100000 */
#define GFXTIM_TDR_RFC2DIS GFXTIM_TDR_RFC2DIS_Msk
/****************** Bits definition for GFXTIM_EVCR register ****************/
#define GFXTIM_EVCR_EV1EN_Pos (0U)
#define GFXTIM_EVCR_EV1EN_Msk (0x1UL << GFXTIM_EVCR_EV1EN_Pos) /*!< 0x00000001 */
#define GFXTIM_EVCR_EV1EN GFXTIM_EVCR_EV1EN_Msk
#define GFXTIM_EVCR_EV2EN_Pos (1U)
#define GFXTIM_EVCR_EV2EN_Msk (0x1UL << GFXTIM_EVCR_EV2EN_Pos) /*!< 0x00000002 */
#define GFXTIM_EVCR_EV2EN GFXTIM_EVCR_EV2EN_Msk
#define GFXTIM_EVCR_EV3EN_Pos (2U)
#define GFXTIM_EVCR_EV3EN_Msk (0x1UL << GFXTIM_EVCR_EV3EN_Pos) /*!< 0x00000004 */
#define GFXTIM_EVCR_EV3EN GFXTIM_EVCR_EV3EN_Msk
#define GFXTIM_EVCR_EV4EN_Pos (3U)
#define GFXTIM_EVCR_EV4EN_Msk (0x1UL << GFXTIM_EVCR_EV4EN_Pos) /*!< 0x00000008 */
#define GFXTIM_EVCR_EV4EN GFXTIM_EVCR_EV4EN_Msk
/****************** Bits definition for GFXTIM_EVSR register ****************/
#define GFXTIM_EVSR_LES1_Pos (0U)
#define GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000007 */
#define GFXTIM_EVSR_LES1 GFXTIM_EVSR_LES1_Msk
#define GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000001 */
#define GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000002 */
#define GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) /*!< 0x00000004 */
#define GFXTIM_EVSR_FES1_Pos (4U)
#define GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000070 */
#define GFXTIM_EVSR_FES1 GFXTIM_EVSR_FES1_Msk
#define GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000010 */
#define GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000020 */
#define GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) /*!< 0x00000040 */
#define GFXTIM_EVSR_LES2_Pos (8U)
#define GFXTIM_EVSR_LES2_Msk (0x7UL << GFXTIM_EVSR_LES2_Pos) /*!< 0x00000700 */
#define GFXTIM_EVSR_LES2 GFXTIM_EVSR_LES2_Msk
#define GFXTIM_EVSR_LES2_0 (0x1UL << GFXTIM_EVSR_LES2_Pos) /*!< 0x00000100 */
#define GFXTIM_EVSR_LES2_1 (0x2UL << GFXTIM_EVSR_LES2_Pos) /*!< 0x00000200 */
#define GFXTIM_EVSR_LES2_2 (0x4UL << GFXTIM_EVSR_LES2_Pos) /*!< 0x00000400 */
#define GFXTIM_EVSR_FES2_Pos (12U)
#define GFXTIM_EVSR_FES2_Msk (0x7UL << GFXTIM_EVSR_FES2_Pos) /*!< 0x00007000 */
#define GFXTIM_EVSR_FES2 GFXTIM_EVSR_FES2_Msk
#define GFXTIM_EVSR_FES2_0 (0x1UL << GFXTIM_EVSR_FES2_Pos) /*!< 0x00001000 */
#define GFXTIM_EVSR_FES2_1 (0x2UL << GFXTIM_EVSR_FES2_Pos) /*!< 0x00002000 */
#define GFXTIM_EVSR_FES2_2 (0x4UL << GFXTIM_EVSR_FES2_Pos) /*!< 0x00004000 */
#define GFXTIM_EVSR_LES3_Pos (16U)
#define GFXTIM_EVSR_LES3_Msk (0x7UL << GFXTIM_EVSR_LES3_Pos) /*!< 0x00070000 */
#define GFXTIM_EVSR_LES3 GFXTIM_EVSR_LES3_Msk
#define GFXTIM_EVSR_LES3_0 (0x1UL << GFXTIM_EVSR_LES3_Pos) /*!< 0x00010000 */
#define GFXTIM_EVSR_LES3_1 (0x2UL << GFXTIM_EVSR_LES3_Pos) /*!< 0x00020000 */
#define GFXTIM_EVSR_LES3_2 (0x4UL << GFXTIM_EVSR_LES3_Pos) /*!< 0x00040000 */
#define GFXTIM_EVSR_FES3_Pos (20U)
#define GFXTIM_EVSR_FES3_Msk (0x7UL << GFXTIM_EVSR_FES3_Pos) /*!< 0x00700000 */
#define GFXTIM_EVSR_FES3 GFXTIM_EVSR_FES3_Msk
#define GFXTIM_EVSR_FES3_0 (0x1UL << GFXTIM_EVSR_FES3_Pos) /*!< 0x00100000 */
#define GFXTIM_EVSR_FES3_1 (0x2UL << GFXTIM_EVSR_FES3_Pos) /*!< 0x00200000 */
#define GFXTIM_EVSR_FES3_2 (0x4UL << GFXTIM_EVSR_FES3_Pos) /*!< 0x00400000 */
#define GFXTIM_EVSR_LES4_Pos (24U)
#define GFXTIM_EVSR_LES4_Msk (0x7UL << GFXTIM_EVSR_LES4_Pos) /*!< 0x07000000 */
#define GFXTIM_EVSR_LES4 GFXTIM_EVSR_LES4_Msk
#define GFXTIM_EVSR_LES4_0 (0x1UL << GFXTIM_EVSR_LES4_Pos) /*!< 0x01000000 */
#define GFXTIM_EVSR_LES4_1 (0x2UL << GFXTIM_EVSR_LES4_Pos) /*!< 0x02000000 */
#define GFXTIM_EVSR_LES4_2 (0x4UL << GFXTIM_EVSR_LES4_Pos) /*!< 0x04000000 */
#define GFXTIM_EVSR_FES4_Pos (28U)
#define GFXTIM_EVSR_FES4_Msk (0x7UL << GFXTIM_EVSR_FES4_Pos) /*!< 0x70000000 */
#define GFXTIM_EVSR_FES4 GFXTIM_EVSR_FES4_Msk
#define GFXTIM_EVSR_FES4_0 (0x1UL << GFXTIM_EVSR_FES4_Pos) /*!< 0x10000000 */
#define GFXTIM_EVSR_FES4_1 (0x2UL << GFXTIM_EVSR_FES4_Pos) /*!< 0x20000000 */
#define GFXTIM_EVSR_FES4_2 (0x4UL << GFXTIM_EVSR_FES4_Pos) /*!< 0x40000000 */
/****************** Bits definition for GFXTIM_WDGTCR register **************/
#define GFXTIM_WDGTCR_WDGEN_Pos (0U)
#define GFXTIM_WDGTCR_WDGEN_Msk (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos) /*!< 0x00000001 */
#define GFXTIM_WDGTCR_WDGEN GFXTIM_WDGTCR_WDGEN_Msk
#define GFXTIM_WDGTCR_WDGDIS_Pos (1U)
#define GFXTIM_WDGTCR_WDGDIS_Msk (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos) /*!< 0x00000002 */
#define GFXTIM_WDGTCR_WDGDIS GFXTIM_WDGTCR_WDGDIS_Msk
#define GFXTIM_WDGTCR_WDGS_Pos (2U)
#define GFXTIM_WDGTCR_WDGS_Msk (0x1UL << GFXTIM_WDGTCR_WDGS_Pos) /*!< 0x00000004 */
#define GFXTIM_WDGTCR_WDGS GFXTIM_WDGTCR_WDGS_Msk
#define GFXTIM_WDGTCR_WDGHRC_Pos (4U)
#define GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000030 */
#define GFXTIM_WDGTCR_WDGHRC GFXTIM_WDGTCR_WDGHRC_Msk
#define GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000010 */
#define GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) /*!< 0x00000020 */
#define GFXTIM_WDGTCR_WDGCS_Pos (8U)
#define GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000700 */
#define GFXTIM_WDGTCR_WDGCS GFXTIM_WDGTCR_WDGCS_Msk
#define GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000100 */
#define GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000200 */
#define GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000400 */
#define GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) /*!< 0x00000800 */
#define GFXTIM_WDGTCR_FWDGR_Pos (16U)
#define GFXTIM_WDGTCR_FWDGR_Msk (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos) /*!< 0x00010000 */
#define GFXTIM_WDGTCR_FWDGR GFXTIM_WDGTCR_FWDGR_Msk
/****************** Bits definition for GFXTIM_ISR register *****************/
#define GFXTIM_ISR_AFCOF_Pos (0U)
#define GFXTIM_ISR_AFCOF_Msk (0x1UL << GFXTIM_ISR_AFCOF_Pos) /*!< 0x00000001 */
#define GFXTIM_ISR_AFCOF GFXTIM_ISR_AFCOF_Msk
#define GFXTIM_ISR_ALCOF_Pos (1U)
#define GFXTIM_ISR_ALCOF_Msk (0x1UL << GFXTIM_ISR_ALCOF_Pos) /*!< 0x00000002 */
#define GFXTIM_ISR_ALCOF GFXTIM_ISR_ALCOF_Msk
#define GFXTIM_ISR_TEF_Pos (2U)
#define GFXTIM_ISR_TEF_Msk (0x1UL << GFXTIM_ISR_TEF_Pos) /*!< 0x00000004 */
#define GFXTIM_ISR_TEF GFXTIM_ISR_TEF_Msk
#define GFXTIM_ISR_AFCC1F_Pos (4U)
#define GFXTIM_ISR_AFCC1F_Msk (0x1UL << GFXTIM_ISR_AFCC1F_Pos) /*!< 0x00000010 */
#define GFXTIM_ISR_AFCC1F GFXTIM_ISR_AFCC1F_Msk
#define GFXTIM_ISR_ALCC1F_Pos (8U)
#define GFXTIM_ISR_ALCC1F_Msk (0x1UL << GFXTIM_ISR_ALCC1F_Pos) /*!< 0x00000100 */
#define GFXTIM_ISR_ALCC1F GFXTIM_ISR_ALCC1F_Msk
#define GFXTIM_ISR_ALCC2F_Pos (9U)
#define GFXTIM_ISR_ALCC2F_Msk (0x1UL << GFXTIM_ISR_ALCC2F_Pos) /*!< 0x00000200 */
#define GFXTIM_ISR_ALCC2F GFXTIM_ISR_ALCC2F_Msk
#define GFXTIM_ISR_RFC1RF_Pos (12U)
#define GFXTIM_ISR_RFC1RF_Msk (0x1UL << GFXTIM_ISR_RFC1RF_Pos) /*!< 0x00001000 */
#define GFXTIM_ISR_RFC1RF GFXTIM_ISR_RFC1RF_Msk
#define GFXTIM_ISR_RFC2RF_Pos (13U)
#define GFXTIM_ISR_RFC2RF_Msk (0x1UL << GFXTIM_ISR_RFC2RF_Pos) /*!< 0x00002000 */
#define GFXTIM_ISR_RFC2RF GFXTIM_ISR_RFC2RF_Msk
#define GFXTIM_ISR_EV1F_Pos (16U)
#define GFXTIM_ISR_EV1F_Msk (0x1UL << GFXTIM_ISR_EV1F_Pos) /*!< 0x00010000 */
#define GFXTIM_ISR_EV1F GFXTIM_ISR_EV1F_Msk
#define GFXTIM_ISR_EV2F_Pos (17U)
#define GFXTIM_ISR_EV2F_Msk (0x1UL << GFXTIM_ISR_EV2F_Pos) /*!< 0x00020000 */
#define GFXTIM_ISR_EV2F GFXTIM_ISR_EV2F_Msk
#define GFXTIM_ISR_EV3F_Pos (18U)
#define GFXTIM_ISR_EV3F_Msk (0x1UL << GFXTIM_ISR_EV3F_Pos) /*!< 0x00040000 */
#define GFXTIM_ISR_EV3F GFXTIM_ISR_EV3F_Msk
#define GFXTIM_ISR_EV4F_Pos (19U)
#define GFXTIM_ISR_EV4F_Msk (0x1UL << GFXTIM_ISR_EV4F_Pos) /*!< 0x00080000 */
#define GFXTIM_ISR_EV4F GFXTIM_ISR_EV4F_Msk
#define GFXTIM_ISR_WDGAF_Pos (24U)
#define GFXTIM_ISR_WDGAF_Msk (0x1UL << GFXTIM_ISR_WDGAF_Pos) /*!< 0x01000000 */
#define GFXTIM_ISR_WDGAF GFXTIM_ISR_WDGAF_Msk
#define GFXTIM_ISR_WDGPF_Pos (25U)
#define GFXTIM_ISR_WDGPF_Msk (0x1UL << GFXTIM_ISR_WDGPF_Pos) /*!< 0x02000000 */
#define GFXTIM_ISR_WDGPF GFXTIM_ISR_WDGPF_Msk
/****************** Bits definition for GFXTIM_ICR register *****************/
#define GFXTIM_ICR_CAFCOF_Pos (0U)
#define GFXTIM_ICR_CAFCOF_Msk (0x1UL << GFXTIM_ICR_CAFCOF_Pos) /*!< 0x00000001 */
#define GFXTIM_ICR_CAFCOF GFXTIM_ICR_CAFCOF_Msk
#define GFXTIM_ICR_CALCOF_Pos (1U)
#define GFXTIM_ICR_CALCOF_Msk (0x1UL << GFXTIM_ICR_CALCOF_Pos) /*!< 0x00000002 */
#define GFXTIM_ICR_CALCOF GFXTIM_ICR_CALCOF_Msk
#define GFXTIM_ICR_CTEF_Pos (2U)
#define GFXTIM_ICR_CTEF_Msk (0x1UL << GFXTIM_ICR_CTEF_Pos) /*!< 0x00000004 */
#define GFXTIM_ICR_CTEF GFXTIM_ICR_CTEF_Msk
#define GFXTIM_ICR_CAFCC1F_Pos (4U)
#define GFXTIM_ICR_CAFCC1F_Msk (0x1UL << GFXTIM_ICR_CAFCC1F_Pos) /*!< 0x00000010 */
#define GFXTIM_ICR_CAFCC1F GFXTIM_ICR_CAFCC1F_Msk
#define GFXTIM_ICR_CALCC1F_Pos (8U)
#define GFXTIM_ICR_CALCC1F_Msk (0x1UL << GFXTIM_ICR_CALCC1F_Pos) /*!< 0x00000100 */
#define GFXTIM_ICR_CALCC1F GFXTIM_ICR_CALCC1F_Msk
#define GFXTIM_ICR_CALCC2F_Pos (9U)
#define GFXTIM_ICR_CALCC2F_Msk (0x1UL << GFXTIM_ICR_CALCC2F_Pos) /*!< 0x00000200 */
#define GFXTIM_ICR_CALCC2F GFXTIM_ICR_CALCC2F_Msk
#define GFXTIM_ICR_CRFC1RF_Pos (12U)
#define GFXTIM_ICR_CRFC1RF_Msk (0x1UL << GFXTIM_ICR_CRFC1RF_Pos) /*!< 0x00001000 */
#define GFXTIM_ICR_CRFC1RF GFXTIM_ICR_CRFC1RF_Msk
#define GFXTIM_ICR_CRFC2RF_Pos (13U)
#define GFXTIM_ICR_CRFC2RF_Msk (0x1UL << GFXTIM_ICR_CRFC2RF_Pos) /*!< 0x00002000 */
#define GFXTIM_ICR_CRFC2RF GFXTIM_ICR_CRFC2RF_Msk
#define GFXTIM_ICR_CEV1F_Pos (16U)
#define GFXTIM_ICR_CEV1F_Msk (0x1UL << GFXTIM_ICR_CEV1F_Pos) /*!< 0x00010000 */
#define GFXTIM_ICR_CEV1F GFXTIM_ICR_CEV1F_Msk
#define GFXTIM_ICR_CEV2F_Pos (17U)
#define GFXTIM_ICR_CEV2F_Msk (0x1UL << GFXTIM_ICR_CEV2F_Pos) /*!< 0x00020000 */
#define GFXTIM_ICR_CEV2F GFXTIM_ICR_CEV2F_Msk
#define GFXTIM_ICR_CEV3F_Pos (18U)
#define GFXTIM_ICR_CEV3F_Msk (0x1UL << GFXTIM_ICR_CEV3F_Pos) /*!< 0x00040000 */
#define GFXTIM_ICR_CEV3F GFXTIM_ICR_CEV3F_Msk
#define GFXTIM_ICR_CEV4F_Pos (19U)
#define GFXTIM_ICR_CEV4F_Msk (0x1UL << GFXTIM_ICR_CEV4F_Pos) /*!< 0x00080000 */
#define GFXTIM_ICR_CEV4F GFXTIM_ICR_CEV4F_Msk
#define GFXTIM_ICR_CWDGAF_Pos (24U)
#define GFXTIM_ICR_CWDGAF_Msk (0x1UL << GFXTIM_ICR_CWDGAF_Pos) /*!< 0x01000000 */
#define GFXTIM_ICR_CWDGAF GFXTIM_ICR_CWDGAF_Msk
#define GFXTIM_ICR_CWDGPF_Pos (25U)
#define GFXTIM_ICR_CWDGPF_Msk (0x1UL << GFXTIM_ICR_CWDGPF_Pos) /*!< 0x02000000 */
#define GFXTIM_ICR_CWDGPF GFXTIM_ICR_CWDGPF_Msk
/****************** Bits definition for GFXTIM_IER register *****************/
#define GFXTIM_IER_AFCOIE_Pos (0U)
#define GFXTIM_IER_AFCOIE_Msk (0x1UL << GFXTIM_IER_AFCOIE_Pos) /*!< 0x00000001 */
#define GFXTIM_IER_AFCOIE GFXTIM_IER_AFCOIE_Msk
#define GFXTIM_IER_ALCOIE_Pos (1U)
#define GFXTIM_IER_ALCOIE_Msk (0x1UL << GFXTIM_IER_ALCOIE_Pos) /*!< 0x00000002 */
#define GFXTIM_IER_ALCOIE GFXTIM_IER_ALCOIE_Msk
#define GFXTIM_IER_TEIE_Pos (2U)
#define GFXTIM_IER_TEIE_Msk (0x1UL << GFXTIM_IER_TEIE_Pos) /*!< 0x00000004 */
#define GFXTIM_IER_TEIE GFXTIM_IER_TEIE_Msk
#define GFXTIM_IER_AFCC1IE_Pos (4U)
#define GFXTIM_IER_AFCC1IE_Msk (0x1UL << GFXTIM_IER_AFCC1IE_Pos) /*!< 0x00000010 */
#define GFXTIM_IER_AFCC1IE GFXTIM_IER_AFCC1IE_Msk
#define GFXTIM_IER_ALCC1IE_Pos (8U)
#define GFXTIM_IER_ALCC1IE_Msk (0x1UL << GFXTIM_IER_ALCC1IE_Pos) /*!< 0x00000100 */
#define GFXTIM_IER_ALCC1IE GFXTIM_IER_ALCC1IE_Msk
#define GFXTIM_IER_ALCC2IE_Pos (9U)
#define GFXTIM_IER_ALCC2IE_Msk (0x1UL << GFXTIM_IER_ALCC2IE_Pos) /*!< 0x00000200 */
#define GFXTIM_IER_ALCC2IE GFXTIM_IER_ALCC2IE_Msk
#define GFXTIM_IER_RFC1RIE_Pos (12U)
#define GFXTIM_IER_RFC1RIE_Msk (0x1UL << GFXTIM_IER_RFC1RIE_Pos) /*!< 0x00001000 */
#define GFXTIM_IER_RFC1RIE GFXTIM_IER_RFC1RIE_Msk
#define GFXTIM_IER_RFC2RIE_Pos (13U)
#define GFXTIM_IER_RFC2RIE_Msk (0x1UL << GFXTIM_IER_RFC2RIE_Pos) /*!< 0x00002000 */
#define GFXTIM_IER_RFC2RIE GFXTIM_IER_RFC2RIE_Msk
#define GFXTIM_IER_EV1IE_Pos (16U)
#define GFXTIM_IER_EV1IE_Msk (0x1UL << GFXTIM_IER_EV1IE_Pos) /*!< 0x00010000 */
#define GFXTIM_IER_EV1IE GFXTIM_IER_EV1IE_Msk
#define GFXTIM_IER_EV2IE_Pos (17U)
#define GFXTIM_IER_EV2IE_Msk (0x1UL << GFXTIM_IER_EV2IE_Pos) /*!< 0x00020000 */
#define GFXTIM_IER_EV2IE GFXTIM_IER_EV2IE_Msk
#define GFXTIM_IER_EV3IE_Pos (18U)
#define GFXTIM_IER_EV3IE_Msk (0x1UL << GFXTIM_IER_EV3IE_Pos) /*!< 0x00040000 */
#define GFXTIM_IER_EV3IE GFXTIM_IER_EV3IE_Msk
#define GFXTIM_IER_EV4IE_Pos (19U)
#define GFXTIM_IER_EV4IE_Msk (0x1UL << GFXTIM_IER_EV4IE_Pos) /*!< 0x00080000 */
#define GFXTIM_IER_EV4IE GFXTIM_IER_EV4IE_Msk
#define GFXTIM_IER_WDGAIE_Pos (24U)
#define GFXTIM_IER_WDGAIE_Msk (0x1UL << GFXTIM_IER_WDGAIE_Pos) /*!< 0x01000000 */
#define GFXTIM_IER_WDGAIE GFXTIM_IER_WDGAIE_Msk
#define GFXTIM_IER_WDGPIE_Pos (25U)
#define GFXTIM_IER_WDGPIE_Msk (0x1UL << GFXTIM_IER_WDGPIE_Pos) /*!< 0x02000000 */
#define GFXTIM_IER_WDGPIE GFXTIM_IER_WDGPIE_Msk
/****************** Bits definition for GFXTIM_TSR register *****************/
#define GFXTIM_TSR_AFCS_Pos (0U)
#define GFXTIM_TSR_AFCS_Msk (0x1UL << GFXTIM_TSR_AFCS_Pos) /*!< 0x00000001 */
#define GFXTIM_TSR_AFCS GFXTIM_TSR_AFCS_Msk
#define GFXTIM_TSR_ALCS_Pos (4U)
#define GFXTIM_TSR_ALCS_Msk (0x1UL << GFXTIM_TSR_ALCS_Pos) /*!< 0x00000010 */
#define GFXTIM_TSR_ALCS GFXTIM_TSR_ALCS_Msk
#define GFXTIM_TSR_RFC1S_Pos (16U)
#define GFXTIM_TSR_RFC1S_Msk (0x1UL << GFXTIM_TSR_RFC1S_Pos) /*!< 0x00010000 */
#define GFXTIM_TSR_RFC1S GFXTIM_TSR_RFC1S_Msk
#define GFXTIM_TSR_RFC2S_Pos (20U)
#define GFXTIM_TSR_RFC2S_Msk (0x1UL << GFXTIM_TSR_RFC2S_Pos) /*!< 0x00100000 */
#define GFXTIM_TSR_RFC2S GFXTIM_TSR_RFC2S_Msk
/****************** Bits definition for GFXTIM_LCCRR register ***************/
#define GFXTIM_LCCRR_RELOAD_Pos (0U)
#define GFXTIM_LCCRR_RELOAD_Msk (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) /*!< 0x003FFFFF */
#define GFXTIM_LCCRR_RELOAD GFXTIM_LCCRR_RELOAD_Msk
/****************** Bits definition for GFXTIM_FCCRR register ***************/
#define GFXTIM_FCCRR_RELOAD_Pos (0U)
#define GFXTIM_FCCRR_RELOAD_Msk (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos) /*!< 0x00000FFF */
#define GFXTIM_FCCRR_RELOAD GFXTIM_FCCRR_RELOAD_Msk
/****************** Bits definition for GFXTIM_ATR register *****************/
#define GFXTIM_ATR_LINE_Pos (0U)
#define GFXTIM_ATR_LINE_Msk (0xFFFUL << GFXTIM_ATR_LINE_Pos) /*!< 0x00000FFF */
#define GFXTIM_ATR_LINE GFXTIM_ATR_LINE_Msk
#define GFXTIM_ATR_FRAME_Pos (12U)
#define GFXTIM_ATR_FRAME_Msk (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos) /*!< 0xFFFFF000 */
#define GFXTIM_ATR_FRAME GFXTIM_ATR_FRAME_Msk
/****************** Bits definition for GFXTIM_AFCR register ****************/
#define GFXTIM_AFCR_FRAME_Pos (0U)
#define GFXTIM_AFCR_FRAME_Msk (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos) /*!< 0x000FFFFF */
#define GFXTIM_AFCR_FRAME GFXTIM_AFCR_FRAME_Msk
/****************** Bits definition for GFXTIM_ALCR register ****************/
#define GFXTIM_ALCR_LINE_Pos (0U)
#define GFXTIM_ALCR_LINE_Msk (0xFFFUL << GFXTIM_ALCR_LINE_Pos) /*!< 0x00000FFF */
#define GFXTIM_ALCR_LINE GFXTIM_ALCR_LINE_Msk
/****************** Bits definition for GFXTIM_AFCC1R register **************/
#define GFXTIM_AFCC1R_FRAME_Pos (0U)
#define GFXTIM_AFCC1R_FRAME_Msk (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos) /*!< 0x000FFFFF */
#define GFXTIM_AFCC1R_FRAME GFXTIM_AFCC1R_FRAME_Msk
/****************** Bits definition for GFXTIM_ALCC1R register **************/
#define GFXTIM_ALCC1R_LINE_Pos (0U)
#define GFXTIM_ALCC1R_LINE_Msk (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos) /*!< 0x00000FFF */
#define GFXTIM_ALCC1R_LINE GFXTIM_ALCC1R_LINE_Msk
/****************** Bits definition for GFXTIM_ALCC2R register **************/
#define GFXTIM_ALCC2R_LINE_Pos (0U)
#define GFXTIM_ALCC2R_LINE_Msk (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos) /*!< 0x00000FFF */
#define GFXTIM_ALCC2R_LINE GFXTIM_ALCC2R_LINE_Msk
/****************** Bits definition for GFXTIM_RFC1R register ***************/
#define GFXTIM_RFC1R_FRAME_Pos (0U)
#define GFXTIM_RFC1R_FRAME_Msk (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos) /*!< 0x00000FFF */
#define GFXTIM_RFC1R_FRAME GFXTIM_RFC1R_FRAME_Msk
/****************** Bits definition for GFXTIM_RFC1RR register **************/
#define GFXTIM_RFC1RR_FRAME_Pos (0U)
#define GFXTIM_RFC1RR_FRAME_Msk (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos) /*!< 0x00000FFF */
#define GFXTIM_RFC1RR_FRAME GFXTIM_RFC1RR_FRAME_Msk
/****************** Bits definition for GFXTIM_RFC2R register ***************/
#define GFXTIM_RFC2R_FRAME_Pos (0U)
#define GFXTIM_RFC2R_FRAME_Msk (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos) /*!< 0x00000FFF */
#define GFXTIM_RFC2R_FRAME GFXTIM_RFC2R_FRAME_Msk
/****************** Bits definition for GFXTIM_RFC2RR register **************/
#define GFXTIM_RFC2RR_FRAME_Pos (0U)
#define GFXTIM_RFC2RR_FRAME_Msk (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos) /*!< 0x00000FFF */
#define GFXTIM_RFC2RR_FRAME GFXTIM_RFC2RR_FRAME_Msk
/****************** Bits definition for GFXTIM_WDGCR register ***************/
#define GFXTIM_WDGCR_VALUE_Pos (0U)
#define GFXTIM_WDGCR_VALUE_Msk (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos) /*!< 0x0000FFFF */
#define GFXTIM_WDGCR_VALUE GFXTIM_WDGCR_VALUE_Msk
/****************** Bits definition for GFXTIM_WDGRR register ***************/
#define GFXTIM_WDGRR_RELOAD_Pos (0U)
#define GFXTIM_WDGRR_RELOAD_Msk (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos) /*!< 0x0000FFFF */
#define GFXTIM_WDGRR_RELOAD GFXTIM_WDGRR_RELOAD_Msk
/****************** Bits definition for GFXTIM_WDGPAR register **************/
#define GFXTIM_WDGPAR_PREALARM_Pos (0U)
#define GFXTIM_WDGPAR_PREALARM_Msk (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos)/*!< 0x0000FFFF */
#define GFXTIM_WDGPAR_PREALARM GFXTIM_WDGPAR_PREALARM_Msk
/****************** Bits definition for GFXTIM_HWCFGR register **************/
/****************** Bits definition for GFXTIM_VERR register ****************/
#define GFXTIM_VERR_MINREV_Pos (0U)
#define GFXTIM_VERR_MINREV_Msk (0xFUL << GFXTIM_VERR_MINREV_Pos) /*!< 0x0000000F */
#define GFXTIM_VERR_MINREV GFXTIM_VERR_MINREV_Msk
#define GFXTIM_VERR_MAJREV_Pos (4U)
#define GFXTIM_VERR_MAJREV_Msk (0xFUL << GFXTIM_VERR_MAJREV_Pos) /*!< 0x000000F0 */
#define GFXTIM_VERR_MAJREV GFXTIM_VERR_MAJREV_Msk
/****************** Bits definition for GFXTIM_IPIDR register ***************/
#define GFXTIM_IPIDR_ID_Pos (0U)
#define GFXTIM_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
#define GFXTIM_IPIDR_ID GFXTIM_IPIDR_ID_Msk
/****************** Bits definition for GFXTIM_SIDR register ****************/
#define GFXTIM_SIDR_SID_Pos (0U)
#define GFXTIM_SIDR_SID_Msk (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
#define GFXTIM_SIDR_SID GFXTIM_SIDR_SID_Msk
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/****************** Bits definition for GPIO_SECCFGR register ******************/
#define GPIO_SECCFGR_SEC0_Pos (0U)
#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */
#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk
#define GPIO_SECCFGR_SEC1_Pos (1U)
#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */
#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk
#define GPIO_SECCFGR_SEC2_Pos (2U)
#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */
#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk
#define GPIO_SECCFGR_SEC3_Pos (3U)
#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */
#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk
#define GPIO_SECCFGR_SEC4_Pos (4U)
#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */
#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk
#define GPIO_SECCFGR_SEC5_Pos (5U)
#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */
#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk
#define GPIO_SECCFGR_SEC6_Pos (6U)
#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */
#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk
#define GPIO_SECCFGR_SEC7_Pos (7U)
#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */
#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk
#define GPIO_SECCFGR_SEC8_Pos (8U)
#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */
#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk
#define GPIO_SECCFGR_SEC9_Pos (9U)
#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */
#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk
#define GPIO_SECCFGR_SEC10_Pos (10U)
#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */
#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk
#define GPIO_SECCFGR_SEC11_Pos (11U)
#define GPIO_SECCFGR_SEC11_Msk (0x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */
#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk
#define GPIO_SECCFGR_SEC12_Pos (12U)
#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */
#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk
#define GPIO_SECCFGR_SEC13_Pos (13U)
#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */
#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk
#define GPIO_SECCFGR_SEC14_Pos (14U)
#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */
#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk
#define GPIO_SECCFGR_SEC15_Pos (15U)
#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */
#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk
/****************** Bits definition for GPIO_PRIVCFGR register ******************/
#define GPIO_PRIVCFGR_PRIV0_Pos (0U)
#define GPIO_PRIVCFGR_PRIV0_Msk (0x1UL << GPIO_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */
#define GPIO_PRIVCFGR_PRIV0 GPIO_PRIVCFGR_PRIV0_Msk
#define GPIO_PRIVCFGR_PRIV1_Pos (1U)
#define GPIO_PRIVCFGR_PRIV1_Msk (0x1UL << GPIO_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */
#define GPIO_PRIVCFGR_PRIV1 GPIO_PRIVCFGR_PRIV1_Msk
#define GPIO_PRIVCFGR_PRIV2_Pos (2U)
#define GPIO_PRIVCFGR_PRIV2_Msk (0x1UL << GPIO_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */
#define GPIO_PRIVCFGR_PRIV2 GPIO_PRIVCFGR_PRIV2_Msk
#define GPIO_PRIVCFGR_PRIV3_Pos (3U)
#define GPIO_PRIVCFGR_PRIV3_Msk (0x1UL << GPIO_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */
#define GPIO_PRIVCFGR_PRIV3 GPIO_PRIVCFGR_PRIV3_Msk
#define GPIO_PRIVCFGR_PRIV4_Pos (4U)
#define GPIO_PRIVCFGR_PRIV4_Msk (0x1UL << GPIO_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */
#define GPIO_PRIVCFGR_PRIV4 GPIO_PRIVCFGR_PRIV4_Msk
#define GPIO_PRIVCFGR_PRIV5_Pos (5U)
#define GPIO_PRIVCFGR_PRIV5_Msk (0x1UL << GPIO_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */
#define GPIO_PRIVCFGR_PRIV5 GPIO_PRIVCFGR_PRIV5_Msk
#define GPIO_PRIVCFGR_PRIV6_Pos (6U)
#define GPIO_PRIVCFGR_PRIV6_Msk (0x1UL << GPIO_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */
#define GPIO_PRIVCFGR_PRIV6 GPIO_PRIVCFGR_PRIV6_Msk
#define GPIO_PRIVCFGR_PRIV7_Pos (7U)
#define GPIO_PRIVCFGR_PRIV7_Msk (0x1UL << GPIO_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */
#define GPIO_PRIVCFGR_PRIV7 GPIO_PRIVCFGR_PRIV7_Msk
#define GPIO_PRIVCFGR_PRIV8_Pos (8U)
#define GPIO_PRIVCFGR_PRIV8_Msk (0x1UL << GPIO_PRIVCFGR_PRIV8_Pos) /*!< 0x00000100 */
#define GPIO_PRIVCFGR_PRIV8 GPIO_PRIVCFGR_PRIV8_Msk
#define GPIO_PRIVCFGR_PRIV9_Pos (9U)
#define GPIO_PRIVCFGR_PRIV9_Msk (0x1UL << GPIO_PRIVCFGR_PRIV9_Pos) /*!< 0x00000200 */
#define GPIO_PRIVCFGR_PRIV9 GPIO_PRIVCFGR_PRIV9_Msk
#define GPIO_PRIVCFGR_PRIV10_Pos (10U)
#define GPIO_PRIVCFGR_PRIV10_Msk (0x1UL << GPIO_PRIVCFGR_PRIV10_Pos) /*!< 0x00000400 */
#define GPIO_PRIVCFGR_PRIV10 GPIO_PRIVCFGR_PRIV10_Msk
#define GPIO_PRIVCFGR_PRIV11_Pos (11U)
#define GPIO_PRIVCFGR_PRIV11_Msk (0x1UL << GPIO_PRIVCFGR_PRIV11_Pos) /*!< 0x00000800 */
#define GPIO_PRIVCFGR_PRIV11 GPIO_PRIVCFGR_PRIV11_Msk
#define GPIO_PRIVCFGR_PRIV12_Pos (12U)
#define GPIO_PRIVCFGR_PRIV12_Msk (0x1UL << GPIO_PRIVCFGR_PRIV12_Pos) /*!< 0x00001000 */
#define GPIO_PRIVCFGR_PRIV12 GPIO_PRIVCFGR_PRIV12_Msk
#define GPIO_PRIVCFGR_PRIV13_Pos (13U)
#define GPIO_PRIVCFGR_PRIV13_Msk (0x1UL << GPIO_PRIVCFGR_PRIV13_Pos) /*!< 0x00002000 */
#define GPIO_PRIVCFGR_PRIV13 GPIO_PRIVCFGR_PRIV13_Msk
#define GPIO_PRIVCFGR_PRIV14_Pos (14U)
#define GPIO_PRIVCFGR_PRIV14_Msk (0x1UL << GPIO_PRIVCFGR_PRIV14_Pos) /*!< 0x00004000 */
#define GPIO_PRIVCFGR_PRIV14 GPIO_PRIVCFGR_PRIV14_Msk
#define GPIO_PRIVCFGR_PRIV15_Pos (15U)
#define GPIO_PRIVCFGR_PRIV15_Msk (0x1UL << GPIO_PRIVCFGR_PRIV15_Pos) /*!< 0x00008000 */
#define GPIO_PRIVCFGR_PRIV15 GPIO_PRIVCFGR_PRIV15_Msk
/****************** Bits definition for GPIO_RCFGLOCKR register ******************/
#define GPIO_RCFGLOCKR_RLOCK0_Pos (0U)
#define GPIO_RCFGLOCKR_RLOCK0_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK0_Pos) /*!< 0x00000001 */
#define GPIO_RCFGLOCKR_RLOCK0 GPIO_RCFGLOCKR_RLOCK0_Msk
#define GPIO_RCFGLOCKR_RLOCK1_Pos (1U)
#define GPIO_RCFGLOCKR_RLOCK1_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK1_Pos) /*!< 0x00000002 */
#define GPIO_RCFGLOCKR_RLOCK1 GPIO_RCFGLOCKR_RLOCK1_Msk
#define GPIO_RCFGLOCKR_RLOCK2_Pos (2U)
#define GPIO_RCFGLOCKR_RLOCK2_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK2_Pos) /*!< 0x00000004 */
#define GPIO_RCFGLOCKR_RLOCK2 GPIO_RCFGLOCKR_RLOCK2_Msk
#define GPIO_RCFGLOCKR_RLOCK3_Pos (3U)
#define GPIO_RCFGLOCKR_RLOCK3_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK3_Pos) /*!< 0x00000008 */
#define GPIO_RCFGLOCKR_RLOCK3 GPIO_RCFGLOCKR_RLOCK3_Msk
#define GPIO_RCFGLOCKR_RLOCK4_Pos (4U)
#define GPIO_RCFGLOCKR_RLOCK4_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK4_Pos) /*!< 0x00000010 */
#define GPIO_RCFGLOCKR_RLOCK4 GPIO_RCFGLOCKR_RLOCK4_Msk
#define GPIO_RCFGLOCKR_RLOCK5_Pos (5U)
#define GPIO_RCFGLOCKR_RLOCK5_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK5_Pos) /*!< 0x00000020 */
#define GPIO_RCFGLOCKR_RLOCK5 GPIO_RCFGLOCKR_RLOCK5_Msk
#define GPIO_RCFGLOCKR_RLOCK6_Pos (6U)
#define GPIO_RCFGLOCKR_RLOCK6_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK6_Pos) /*!< 0x00000040 */
#define GPIO_RCFGLOCKR_RLOCK6 GPIO_RCFGLOCKR_RLOCK6_Msk
#define GPIO_RCFGLOCKR_RLOCK7_Pos (7U)
#define GPIO_RCFGLOCKR_RLOCK7_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK7_Pos) /*!< 0x00000080 */
#define GPIO_RCFGLOCKR_RLOCK7 GPIO_RCFGLOCKR_RLOCK7_Msk
#define GPIO_RCFGLOCKR_RLOCK8_Pos (8U)
#define GPIO_RCFGLOCKR_RLOCK8_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK8_Pos) /*!< 0x00000100 */
#define GPIO_RCFGLOCKR_RLOCK8 GPIO_RCFGLOCKR_RLOCK8_Msk
#define GPIO_RCFGLOCKR_RLOCK9_Pos (9U)
#define GPIO_RCFGLOCKR_RLOCK9_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK9_Pos) /*!< 0x00000200 */
#define GPIO_RCFGLOCKR_RLOCK9 GPIO_RCFGLOCKR_RLOCK9_Msk
#define GPIO_RCFGLOCKR_RLOCK10_Pos (10U)
#define GPIO_RCFGLOCKR_RLOCK10_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK10_Pos) /*!< 0x00000400 */
#define GPIO_RCFGLOCKR_RLOCK10 GPIO_RCFGLOCKR_RLOCK10_Msk
#define GPIO_RCFGLOCKR_RLOCK11_Pos (11U)
#define GPIO_RCFGLOCKR_RLOCK11_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK11_Pos) /*!< 0x00000800 */
#define GPIO_RCFGLOCKR_RLOCK11 GPIO_RCFGLOCKR_RLOCK11_Msk
#define GPIO_RCFGLOCKR_RLOCK12_Pos (12U)
#define GPIO_RCFGLOCKR_RLOCK12_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK12_Pos) /*!< 0x00001000 */
#define GPIO_RCFGLOCKR_RLOCK12 GPIO_RCFGLOCKR_RLOCK12_Msk
#define GPIO_RCFGLOCKR_RLOCK13_Pos (13U)
#define GPIO_RCFGLOCKR_RLOCK13_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK13_Pos) /*!< 0x00002000 */
#define GPIO_RCFGLOCKR_RLOCK13 GPIO_RCFGLOCKR_RLOCK13_Msk
#define GPIO_RCFGLOCKR_RLOCK14_Pos (14U)
#define GPIO_RCFGLOCKR_RLOCK14_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK14_Pos) /*!< 0x00004000 */
#define GPIO_RCFGLOCKR_RLOCK14 GPIO_RCFGLOCKR_RLOCK14_Msk
#define GPIO_RCFGLOCKR_RLOCK15_Pos (15U)
#define GPIO_RCFGLOCKR_RLOCK15_Msk (0x1UL << GPIO_RCFGLOCKR_RLOCK15_Pos) /*!< 0x00008000 */
#define GPIO_RCFGLOCKR_RLOCK15 GPIO_RCFGLOCKR_RLOCK15_Msk
/****************** Bit definition for GPIO_DELAYRL register *********************/
#define GPIO_DELAYRL_DLY0_Pos (0U)
#define GPIO_DELAYRL_DLY0_Msk (0xFUL << GPIO_DELAYRL_DLY0_Pos) /*!< 0x0000000F */
#define GPIO_DELAYRL_DLY0 GPIO_DELAYRL_DLY0_Msk
#define GPIO_DELAYRL_DLY0_0 (0x1UL << GPIO_DELAYRL_DLY0_Pos) /*!< 0x00000001 */
#define GPIO_DELAYRL_DLY0_1 (0x2UL << GPIO_DELAYRL_DLY0_Pos) /*!< 0x00000002 */
#define GPIO_DELAYRL_DLY0_2 (0x4UL << GPIO_DELAYRL_DLY0_Pos) /*!< 0x00000004 */
#define GPIO_DELAYRL_DLY0_3 (0x8UL << GPIO_DELAYRL_DLY0_Pos) /*!< 0x00000008 */
#define GPIO_DELAYRL_DLY1_Pos (4U)
#define GPIO_DELAYRL_DLY1_Msk (0xFUL << GPIO_DELAYRL_DLY1_Pos) /*!< 0x000000F0 */
#define GPIO_DELAYRL_DLY1 GPIO_DELAYRL_DLY1_Msk
#define GPIO_DELAYRL_DLY1_0 (0x1UL << GPIO_DELAYRL_DLY1_Pos) /*!< 0x00000010 */
#define GPIO_DELAYRL_DLY1_1 (0x2UL << GPIO_DELAYRL_DLY1_Pos) /*!< 0x00000020 */
#define GPIO_DELAYRL_DLY1_2 (0x4UL << GPIO_DELAYRL_DLY1_Pos) /*!< 0x00000040 */
#define GPIO_DELAYRL_DLY1_3 (0x8UL << GPIO_DELAYRL_DLY1_Pos) /*!< 0x00000080 */
#define GPIO_DELAYRL_DLY2_Pos (8U)
#define GPIO_DELAYRL_DLY2_Msk (0xFUL << GPIO_DELAYRL_DLY2_Pos) /*!< 0x00000F00 */
#define GPIO_DELAYRL_DLY2 GPIO_DELAYRL_DLY2_Msk
#define GPIO_DELAYRL_DLY2_0 (0x1UL << GPIO_DELAYRL_DLY2_Pos) /*!< 0x00000100 */
#define GPIO_DELAYRL_DLY2_1 (0x2UL << GPIO_DELAYRL_DLY2_Pos) /*!< 0x00000200 */
#define GPIO_DELAYRL_DLY2_2 (0x4UL << GPIO_DELAYRL_DLY2_Pos) /*!< 0x00000400 */
#define GPIO_DELAYRL_DLY2_3 (0x8UL << GPIO_DELAYRL_DLY2_Pos) /*!< 0x00000800 */
#define GPIO_DELAYRL_DLY3_Pos (12U)
#define GPIO_DELAYRL_DLY3_Msk (0xFUL << GPIO_DELAYRL_DLY3_Pos) /*!< 0x0000F000 */
#define GPIO_DELAYRL_DLY3 GPIO_DELAYRL_DLY3_Msk
#define GPIO_DELAYRL_DLY3_0 (0x1UL << GPIO_DELAYRL_DLY3_Pos) /*!< 0x00001000 */
#define GPIO_DELAYRL_DLY3_1 (0x2UL << GPIO_DELAYRL_DLY3_Pos) /*!< 0x00002000 */
#define GPIO_DELAYRL_DLY3_2 (0x4UL << GPIO_DELAYRL_DLY3_Pos) /*!< 0x00004000 */
#define GPIO_DELAYRL_DLY3_3 (0x8UL << GPIO_DELAYRL_DLY3_Pos) /*!< 0x00008000 */
#define GPIO_DELAYRL_DLY4_Pos (16U)
#define GPIO_DELAYRL_DLY4_Msk (0xFUL << GPIO_DELAYRL_DLY4_Pos) /*!< 0x000F0000 */
#define GPIO_DELAYRL_DLY4 GPIO_DELAYRL_DLY4_Msk
#define GPIO_DELAYRL_DLY4_0 (0x1UL << GPIO_DELAYRL_DLY4_Pos) /*!< 0x00010000 */
#define GPIO_DELAYRL_DLY4_1 (0x2UL << GPIO_DELAYRL_DLY4_Pos) /*!< 0x00020000 */
#define GPIO_DELAYRL_DLY4_2 (0x4UL << GPIO_DELAYRL_DLY4_Pos) /*!< 0x00040000 */
#define GPIO_DELAYRL_DLY4_3 (0x8UL << GPIO_DELAYRL_DLY4_Pos) /*!< 0x00080000 */
#define GPIO_DELAYRL_DLY5_Pos (20U)
#define GPIO_DELAYRL_DLY5_Msk (0xFUL << GPIO_DELAYRL_DLY5_Pos) /*!< 0x00F00000 */
#define GPIO_DELAYRL_DLY5 GPIO_DELAYRL_DLY5_Msk
#define GPIO_DELAYRL_DLY5_0 (0x1UL << GPIO_DELAYRL_DLY5_Pos) /*!< 0x00100000 */
#define GPIO_DELAYRL_DLY5_1 (0x2UL << GPIO_DELAYRL_DLY5_Pos) /*!< 0x00200000 */
#define GPIO_DELAYRL_DLY5_2 (0x4UL << GPIO_DELAYRL_DLY5_Pos) /*!< 0x00400000 */
#define GPIO_DELAYRL_DLY5_3 (0x8UL << GPIO_DELAYRL_DLY5_Pos) /*!< 0x00800000 */
#define GPIO_DELAYRL_DLY6_Pos (24U)
#define GPIO_DELAYRL_DLY6_Msk (0xFUL << GPIO_DELAYRL_DLY6_Pos) /*!< 0x0F000000 */
#define GPIO_DELAYRL_DLY6 GPIO_DELAYRL_DLY6_Msk
#define GPIO_DELAYRL_DLY6_0 (0x1UL << GPIO_DELAYRL_DLY6_Pos) /*!< 0x01000000 */
#define GPIO_DELAYRL_DLY6_1 (0x2UL << GPIO_DELAYRL_DLY6_Pos) /*!< 0x02000000 */
#define GPIO_DELAYRL_DLY6_2 (0x4UL << GPIO_DELAYRL_DLY6_Pos) /*!< 0x04000000 */
#define GPIO_DELAYRL_DLY6_3 (0x8UL << GPIO_DELAYRL_DLY6_Pos) /*!< 0x08000000 */
#define GPIO_DELAYRL_DLY7_Pos (28U)
#define GPIO_DELAYRL_DLY7_Msk (0xFUL << GPIO_DELAYRL_DLY7_Pos) /*!< 0xF0000000 */
#define GPIO_DELAYRL_DLY7 GPIO_DELAYRL_DLY7_Msk
#define GPIO_DELAYRL_DLY7_0 (0x1UL << GPIO_DELAYRL_DLY7_Pos) /*!< 0x10000000 */
#define GPIO_DELAYRL_DLY7_1 (0x2UL << GPIO_DELAYRL_DLY7_Pos) /*!< 0x20000000 */
#define GPIO_DELAYRL_DLY7_2 (0x4UL << GPIO_DELAYRL_DLY7_Pos) /*!< 0x40000000 */
#define GPIO_DELAYRL_DLY7_3 (0x8UL << GPIO_DELAYRL_DLY7_Pos) /*!< 0x80000000 */
/****************** Bit definition for GPIO_DELAYRH register *********************/
#define GPIO_DELAYRH_DLY8_Pos (0U)
#define GPIO_DELAYRH_DLY8_Msk (0xFUL << GPIO_DELAYRH_DLY8_Pos) /*!< 0x0000000F */
#define GPIO_DELAYRH_DLY8 GPIO_DELAYRH_DLY8_Msk
#define GPIO_DELAYRH_DLY8_0 (0x1UL << GPIO_DELAYRH_DLY8_Pos) /*!< 0x00000001 */
#define GPIO_DELAYRH_DLY8_1 (0x2UL << GPIO_DELAYRH_DLY8_Pos) /*!< 0x00000002 */
#define GPIO_DELAYRH_DLY8_2 (0x4UL << GPIO_DELAYRH_DLY8_Pos) /*!< 0x00000004 */
#define GPIO_DELAYRH_DLY8_3 (0x8UL << GPIO_DELAYRH_DLY8_Pos) /*!< 0x00000008 */
#define GPIO_DELAYRH_DLY9_Pos (4U)
#define GPIO_DELAYRH_DLY9_Msk (0xFUL << GPIO_DELAYRH_DLY9_Pos) /*!< 0x000000F0 */
#define GPIO_DELAYRH_DLY9 GPIO_DELAYRH_DLY9_Msk
#define GPIO_DELAYRH_DLY9_0 (0x1UL << GPIO_DELAYRH_DLY9_Pos) /*!< 0x00000010 */
#define GPIO_DELAYRH_DLY9_1 (0x2UL << GPIO_DELAYRH_DLY9_Pos) /*!< 0x00000020 */
#define GPIO_DELAYRH_DLY9_2 (0x4UL << GPIO_DELAYRH_DLY9_Pos) /*!< 0x00000040 */
#define GPIO_DELAYRH_DLY9_3 (0x8UL << GPIO_DELAYRH_DLY9_Pos) /*!< 0x00000080 */
#define GPIO_DELAYRH_DLY10_Pos (8U)
#define GPIO_DELAYRH_DLY10_Msk (0xFUL << GPIO_DELAYRH_DLY10_Pos) /*!< 0x00000F00 */
#define GPIO_DELAYRH_DLY10 GPIO_DELAYRH_DLY10_Msk
#define GPIO_DELAYRH_DLY10_0 (0x1UL << GPIO_DELAYRH_DLY10_Pos) /*!< 0x00000100 */
#define GPIO_DELAYRH_DLY10_1 (0x2UL << GPIO_DELAYRH_DLY10_Pos) /*!< 0x00000200 */
#define GPIO_DELAYRH_DLY10_2 (0x4UL << GPIO_DELAYRH_DLY10_Pos) /*!< 0x00000400 */
#define GPIO_DELAYRH_DLY10_3 (0x8UL << GPIO_DELAYRH_DLY10_Pos) /*!< 0x00000800 */
#define GPIO_DELAYRH_DLY11_Pos (12U)
#define GPIO_DELAYRH_DLY11_Msk (0xFUL << GPIO_DELAYRH_DLY11_Pos) /*!< 0x0000F000 */
#define GPIO_DELAYRH_DLY11 GPIO_DELAYRH_DLY11_Msk
#define GPIO_DELAYRH_DLY11_0 (0x1UL << GPIO_DELAYRH_DLY11_Pos) /*!< 0x00001000 */
#define GPIO_DELAYRH_DLY11_1 (0x2UL << GPIO_DELAYRH_DLY11_Pos) /*!< 0x00002000 */
#define GPIO_DELAYRH_DLY11_2 (0x4UL << GPIO_DELAYRH_DLY11_Pos) /*!< 0x00004000 */
#define GPIO_DELAYRH_DLY11_3 (0x8UL << GPIO_DELAYRH_DLY11_Pos) /*!< 0x00008000 */
#define GPIO_DELAYRH_DLY12_Pos (16U)
#define GPIO_DELAYRH_DLY12_Msk (0xFUL << GPIO_DELAYRH_DLY12_Pos) /*!< 0x000F0000 */
#define GPIO_DELAYRH_DLY12 GPIO_DELAYRH_DLY12_Msk
#define GPIO_DELAYRH_DLY12_0 (0x1UL << GPIO_DELAYRH_DLY12_Pos) /*!< 0x00010000 */
#define GPIO_DELAYRH_DLY12_1 (0x2UL << GPIO_DELAYRH_DLY12_Pos) /*!< 0x00020000 */
#define GPIO_DELAYRH_DLY12_2 (0x4UL << GPIO_DELAYRH_DLY12_Pos) /*!< 0x00040000 */
#define GPIO_DELAYRH_DLY12_3 (0x8UL << GPIO_DELAYRH_DLY12_Pos) /*!< 0x00080000 */
#define GPIO_DELAYRH_DLY13_Pos (20U)
#define GPIO_DELAYRH_DLY13_Msk (0xFUL << GPIO_DELAYRH_DLY13_Pos) /*!< 0x00F00000 */
#define GPIO_DELAYRH_DLY13 GPIO_DELAYRH_DLY13_Msk
#define GPIO_DELAYRH_DLY13_0 (0x1UL << GPIO_DELAYRH_DLY13_Pos) /*!< 0x00100000 */
#define GPIO_DELAYRH_DLY13_1 (0x2UL << GPIO_DELAYRH_DLY13_Pos) /*!< 0x00200000 */
#define GPIO_DELAYRH_DLY13_2 (0x4UL << GPIO_DELAYRH_DLY13_Pos) /*!< 0x00400000 */
#define GPIO_DELAYRH_DLY13_3 (0x8UL << GPIO_DELAYRH_DLY13_Pos) /*!< 0x00800000 */
#define GPIO_DELAYRH_DLY14_Pos (24U)
#define GPIO_DELAYRH_DLY14_Msk (0xFUL << GPIO_DELAYRH_DLY14_Pos) /*!< 0x0F000000 */
#define GPIO_DELAYRH_DLY14 GPIO_DELAYRH_DLY14_Msk
#define GPIO_DELAYRH_DLY14_0 (0x1UL << GPIO_DELAYRH_DLY14_Pos) /*!< 0x01000000 */
#define GPIO_DELAYRH_DLY14_1 (0x2UL << GPIO_DELAYRH_DLY14_Pos) /*!< 0x02000000 */
#define GPIO_DELAYRH_DLY14_2 (0x4UL << GPIO_DELAYRH_DLY14_Pos) /*!< 0x04000000 */
#define GPIO_DELAYRH_DLY14_3 (0x8UL << GPIO_DELAYRH_DLY14_Pos) /*!< 0x08000000 */
#define GPIO_DELAYRH_DLY15_Pos (28U)
#define GPIO_DELAYRH_DLY15_Msk (0xFUL << GPIO_DELAYRH_DLY15_Pos) /*!< 0xF0000000 */
#define GPIO_DELAYRH_DLY15 GPIO_DELAYRH_DLY15_Msk
#define GPIO_DELAYRH_DLY15_0 (0x1UL << GPIO_DELAYRH_DLY15_Pos) /*!< 0x10000000 */
#define GPIO_DELAYRH_DLY15_1 (0x2UL << GPIO_DELAYRH_DLY15_Pos) /*!< 0x20000000 */
#define GPIO_DELAYRH_DLY15_2 (0x4UL << GPIO_DELAYRH_DLY15_Pos) /*!< 0x40000000 */
#define GPIO_DELAYRH_DLY15_3 (0x8UL << GPIO_DELAYRH_DLY15_Pos) /*!< 0x80000000 */
/****************** Bit definition for GPIO_ADVCFGRL register *********************/
#define GPIO_ADVCFGRL_0_Pos (0U)
#define GPIO_ADVCFGRL_0_Msk (0xFUL << GPIO_ADVCFGRL_0_Pos) /*!< 0x0000000F */
#define GPIO_ADVCFGRL_0 GPIO_ADVCFGRL_0_Msk
#define GPIO_ADVCFGRL_DLYPATH0 (0x1UL << GPIO_ADVCFGRL_0_Pos) /*!< 0x00000001 */
#define GPIO_ADVCFGRL_DE0 (0x2UL << GPIO_ADVCFGRL_0_Pos) /*!< 0x00000002 */
#define GPIO_ADVCFGRL_INVCLK0 (0x4UL << GPIO_ADVCFGRL_0_Pos) /*!< 0x00000004 */
#define GPIO_ADVCFGRL_RET0 (0x8UL << GPIO_ADVCFGRL_0_Pos) /*!< 0x00000008 */
#define GPIO_ADVCFGRL_1_Pos (4U)
#define GPIO_ADVCFGRL_1_Msk (0xFUL << GPIO_ADVCFGRL_1_Pos) /*!< 0x000000F0 */
#define GPIO_ADVCFGRL_1 GPIO_ADVCFGRL_1_Msk
#define GPIO_ADVCFGRL_DLYPATH1 (0x1UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000010 */
#define GPIO_ADVCFGRL_DE1 (0x2UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000020 */
#define GPIO_ADVCFGRL_INVCLK1 (0x4UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000040 */
#define GPIO_ADVCFGRL_RET1 (0x8UL << GPIO_ADVCFGRL_1_Pos) /*!< 0x00000080 */
#define GPIO_ADVCFGRL_2_Pos (8U)
#define GPIO_ADVCFGRL_2_Msk (0xFUL << GPIO_ADVCFGRL_2_Pos) /*!< 0x00000F00 */
#define GPIO_ADVCFGRL_2 GPIO_ADVCFGRL_2_Msk
#define GPIO_ADVCFGRL_DLYPATH2 (0x1UL << GPIO_ADVCFGRL_2_Pos) /*!< 0x00000100 */
#define GPIO_ADVCFGRL_DE2 (0x2UL << GPIO_ADVCFGRL_2_Pos) /*!< 0x00000200 */
#define GPIO_ADVCFGRL_INVCLK2 (0x4UL << GPIO_ADVCFGRL_2_Pos) /*!< 0x00000400 */
#define GPIO_ADVCFGRL_RET2 (0x8UL << GPIO_ADVCFGRL_2_Pos) /*!< 0x00000800 */
#define GPIO_ADVCFGRL_3_Pos (12U)
#define GPIO_ADVCFGRL_3_Msk (0xFUL << GPIO_ADVCFGRL_3_Pos) /*!< 0x0000F000 */
#define GPIO_ADVCFGRL_3 GPIO_ADVCFGRL_3_Msk
#define GPIO_ADVCFGRL_DLYPATH3 (0x1UL << GPIO_ADVCFGRL_3_Pos) /*!< 0x00001000 */
#define GPIO_ADVCFGRL_DE3 (0x2UL << GPIO_ADVCFGRL_3_Pos) /*!< 0x00002000 */
#define GPIO_ADVCFGRL_INVCLK3 (0x4UL << GPIO_ADVCFGRL_3_Pos) /*!< 0x00004000 */
#define GPIO_ADVCFGRL_RET3 (0x8UL << GPIO_ADVCFGRL_3_Pos) /*!< 0x00008000 */
#define GPIO_ADVCFGRL_4_Pos (16U)
#define GPIO_ADVCFGRL_4_Msk (0xFUL << GPIO_ADVCFGRL_4_Pos) /*!< 0x000F0000 */
#define GPIO_ADVCFGRL_4 GPIO_ADVCFGRL_4_Msk
#define GPIO_ADVCFGRL_DLYPATH4 (0x1UL << GPIO_ADVCFGRL_4_Pos) /*!< 0x00010000 */
#define GPIO_ADVCFGRL_DE4 (0x2UL << GPIO_ADVCFGRL_4_Pos) /*!< 0x00020000 */
#define GPIO_ADVCFGRL_INVCLK4 (0x4UL << GPIO_ADVCFGRL_4_Pos) /*!< 0x00040000 */
#define GPIO_ADVCFGRL_RET4 (0x8UL << GPIO_ADVCFGRL_4_Pos) /*!< 0x00080000 */
#define GPIO_ADVCFGRL_5_Pos (20U)
#define GPIO_ADVCFGRL_5_Msk (0xFUL << GPIO_ADVCFGRL_5_Pos) /*!< 0x00F00000 */
#define GPIO_ADVCFGRL_5 GPIO_ADVCFGRL_5_Msk
#define GPIO_ADVCFGRL_DLYPATH5 (0x1UL << GPIO_ADVCFGRL_5_Pos) /*!< 0x00100000 */
#define GPIO_ADVCFGRL_DE5 (0x2UL << GPIO_ADVCFGRL_5_Pos) /*!< 0x00200000 */
#define GPIO_ADVCFGRL_INVCLK5 (0x4UL << GPIO_ADVCFGRL_5_Pos) /*!< 0x00400000 */
#define GPIO_ADVCFGRL_RET5 (0x8UL << GPIO_ADVCFGRL_5_Pos) /*!< 0x00800000 */
#define GPIO_ADVCFGRL_6_Pos (24U)
#define GPIO_ADVCFGRL_6_Msk (0xFUL << GPIO_ADVCFGRL_6_Pos) /*!< 0x0F000000 */
#define GPIO_ADVCFGRL_6 GPIO_ADVCFGRL_6_Msk
#define GPIO_ADVCFGRL_DLYPATH6 (0x1UL << GPIO_ADVCFGRL_6_Pos) /*!< 0x01000000 */
#define GPIO_ADVCFGRL_DE6 (0x2UL << GPIO_ADVCFGRL_6_Pos) /*!< 0x02000000 */
#define GPIO_ADVCFGRL_INVCLK6 (0x4UL << GPIO_ADVCFGRL_6_Pos) /*!< 0x04000000 */
#define GPIO_ADVCFGRL_RET6 (0x8UL << GPIO_ADVCFGRL_6_Pos) /*!< 0x08000000 */
#define GPIO_ADVCFGRL_7_Pos (28U)
#define GPIO_ADVCFGRL_7_Msk (0xFUL << GPIO_ADVCFGRL_7_Pos) /*!< 0xF0000000 */
#define GPIO_ADVCFGRL_7 GPIO_ADVCFGRL_7_Msk
#define GPIO_ADVCFGRL_DLYPATH7 (0x1UL << GPIO_ADVCFGRL_7_Pos) /*!< 0x10000000 */
#define GPIO_ADVCFGRL_DE7 (0x2UL << GPIO_ADVCFGRL_7_Pos) /*!< 0x20000000 */
#define GPIO_ADVCFGRL_INVCLK7 (0x4UL << GPIO_ADVCFGRL_7_Pos) /*!< 0x40000000 */
#define GPIO_ADVCFGRL_RET7 (0x8UL << GPIO_ADVCFGRL_7_Pos) /*!< 0x80000000 */
/****************** Bit definition for GPIO_ADVCFGRH register *********************/
#define GPIO_ADVCFGRH_8_Pos (0U)
#define GPIO_ADVCFGRH_8_Msk (0xFUL << GPIO_ADVCFGRH_8_Pos) /*!< 0x0000000F */
#define GPIO_ADVCFGRH_8 GPIO_ADVCFGRH_8_Msk
#define GPIO_ADVCFGRH_DLYPATH8 (0x1UL << GPIO_ADVCFGRH_8_Pos) /*!< 0x00000001 */
#define GPIO_ADVCFGRH_DE8 (0x2UL << GPIO_ADVCFGRH_8_Pos) /*!< 0x00000002 */
#define GPIO_ADVCFGRH_INVCLK8 (0x4UL << GPIO_ADVCFGRH_8_Pos) /*!< 0x00000004 */
#define GPIO_ADVCFGRH_RET8 (0x8UL << GPIO_ADVCFGRH_8_Pos) /*!< 0x00000008 */
#define GPIO_ADVCFGRH_9_Pos (4U)
#define GPIO_ADVCFGRH_9_Msk (0xFUL << GPIO_ADVCFGRH_9_Pos) /*!< 0x000000F0 */
#define GPIO_ADVCFGRH_9 GPIO_ADVCFGRH_9_Msk
#define GPIO_ADVCFGRH_DLYPATH9 (0x1UL << GPIO_ADVCFGRH_9_Pos) /*!< 0x00000010 */
#define GPIO_ADVCFGRH_DE9 (0x2UL << GPIO_ADVCFGRH_9_Pos) /*!< 0x00000020 */
#define GPIO_ADVCFGRH_INVCLK9 (0x4UL << GPIO_ADVCFGRH_9_Pos) /*!< 0x00000040 */
#define GPIO_ADVCFGRH_RET9 (0x8UL << GPIO_ADVCFGRH_9_Pos) /*!< 0x00000080 */
#define GPIO_ADVCFGRH_10_Pos (8U)
#define GPIO_ADVCFGRH_10_Msk (0xFUL << GPIO_ADVCFGRH_10_Pos) /*!< 0x00000F00 */
#define GPIO_ADVCFGRH_10 GPIO_ADVCFGRH_10_Msk
#define GPIO_ADVCFGRH_DLYPATH10 (0x1UL << GPIO_ADVCFGRH_10_Pos) /*!< 0x00000100 */
#define GPIO_ADVCFGRH_DE10 (0x2UL << GPIO_ADVCFGRH_10_Pos) /*!< 0x00000200 */
#define GPIO_ADVCFGRH_INVCLK10 (0x4UL << GPIO_ADVCFGRH_10_Pos) /*!< 0x00000400 */
#define GPIO_ADVCFGRH_RET10 (0x8UL << GPIO_ADVCFGRH_10_Pos) /*!< 0x00000800 */
#define GPIO_ADVCFGRH_11_Pos (12U)
#define GPIO_ADVCFGRH_11_Msk (0xFUL << GPIO_ADVCFGRH_11_Pos) /*!< 0x0000F000 */
#define GPIO_ADVCFGRH_11 GPIO_ADVCFGRH_11_Msk
#define GPIO_ADVCFGRH_DLYPATH11 (0x1UL << GPIO_ADVCFGRH_11_Pos) /*!< 0x00001000 */
#define GPIO_ADVCFGRH_DE11 (0x2UL << GPIO_ADVCFGRH_11_Pos) /*!< 0x00002000 */
#define GPIO_ADVCFGRH_INVCLK11 (0x4UL << GPIO_ADVCFGRH_11_Pos) /*!< 0x00004000 */
#define GPIO_ADVCFGRH_RET11 (0x8UL << GPIO_ADVCFGRH_11_Pos) /*!< 0x00008000 */
#define GPIO_ADVCFGRH_12_Pos (16U)
#define GPIO_ADVCFGRH_12_Msk (0xFUL << GPIO_ADVCFGRH_12_Pos) /*!< 0x000F0000 */
#define GPIO_ADVCFGRH_12 GPIO_ADVCFGRH_12_Msk
#define GPIO_ADVCFGRH_DLYPATH12 (0x1UL << GPIO_ADVCFGRH_12_Pos) /*!< 0x00010000 */
#define GPIO_ADVCFGRH_DE12 (0x2UL << GPIO_ADVCFGRH_12_Pos) /*!< 0x00020000 */
#define GPIO_ADVCFGRH_INVCLK12 (0x4UL << GPIO_ADVCFGRH_12_Pos) /*!< 0x00040000 */
#define GPIO_ADVCFGRH_RET12 (0x8UL << GPIO_ADVCFGRH_12_Pos) /*!< 0x00080000 */
#define GPIO_ADVCFGRH_13_Pos (20U)
#define GPIO_ADVCFGRH_13_Msk (0xFUL << GPIO_ADVCFGRH_13_Pos) /*!< 0x00F00000 */
#define GPIO_ADVCFGRH_13 GPIO_ADVCFGRH_13_Msk
#define GPIO_ADVCFGRH_DLYPATH13 (0x1UL << GPIO_ADVCFGRH_13_Pos) /*!< 0x00100000 */
#define GPIO_ADVCFGRH_DE13 (0x2UL << GPIO_ADVCFGRH_13_Pos) /*!< 0x00200000 */
#define GPIO_ADVCFGRH_INVCLK13 (0x4UL << GPIO_ADVCFGRH_13_Pos) /*!< 0x00400000 */
#define GPIO_ADVCFGRH_RET13 (0x8UL << GPIO_ADVCFGRH_13_Pos) /*!< 0x00800000 */
#define GPIO_ADVCFGRH_14_Pos (24U)
#define GPIO_ADVCFGRH_14_Msk (0xFUL << GPIO_ADVCFGRH_14_Pos) /*!< 0x0F000000 */
#define GPIO_ADVCFGRH_14 GPIO_ADVCFGRH_14_Msk
#define GPIO_ADVCFGRH_DLYPATH14 (0x1UL << GPIO_ADVCFGRH_14_Pos) /*!< 0x01000000 */
#define GPIO_ADVCFGRH_DE14 (0x2UL << GPIO_ADVCFGRH_14_Pos) /*!< 0x02000000 */
#define GPIO_ADVCFGRH_INVCLK14 (0x4UL << GPIO_ADVCFGRH_14_Pos) /*!< 0x04000000 */
#define GPIO_ADVCFGRH_RET14 (0x8UL << GPIO_ADVCFGRH_14_Pos) /*!< 0x08000000 */
#define GPIO_ADVCFGRH_15_Pos (28U)
#define GPIO_ADVCFGRH_15_Msk (0xFUL << GPIO_ADVCFGRH_15_Pos) /*!< 0xF0000000 */
#define GPIO_ADVCFGRH_15 GPIO_ADVCFGRH_15_Msk
#define GPIO_ADVCFGRH_DLYPATH15 (0x1UL << GPIO_ADVCFGRH_15_Pos) /*!< 0x10000000 */
#define GPIO_ADVCFGRH_DE15 (0x2UL << GPIO_ADVCFGRH_15_Pos) /*!< 0x20000000 */
#define GPIO_ADVCFGRH_INVCLK15 (0x4UL << GPIO_ADVCFGRH_15_Pos) /*!< 0x40000000 */
#define GPIO_ADVCFGRH_RET15 (0x8UL << GPIO_ADVCFGRH_15_Pos) /*!< 0x80000000 */
/******************************************************************************/
/* */
/* HASH */
/* */
/******************************************************************************/
/****************** Bits definition for HASH_CR register ********************/
#define HASH_CR_INIT_Pos (2U)
#define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */
#define HASH_CR_INIT HASH_CR_INIT_Msk
#define HASH_CR_DMAE_Pos (3U)
#define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
#define HASH_CR_DMAE HASH_CR_DMAE_Msk
#define HASH_CR_DATATYPE_Pos (4U)
#define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
#define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
#define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
#define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
#define HASH_CR_MODE_Pos (6U)
#define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */
#define HASH_CR_MODE HASH_CR_MODE_Msk
#define HASH_CR_NBW_Pos (8U)
#define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
#define HASH_CR_NBW HASH_CR_NBW_Msk
#define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */
#define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */
#define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */
#define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */
#define HASH_CR_DINNE_Pos (12U)
#define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
#define HASH_CR_DINNE HASH_CR_DINNE_Msk
#define HASH_CR_MDMAT_Pos (13U)
#define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
#define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
#define HASH_CR_LKEY_Pos (16U)
#define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
#define HASH_CR_LKEY HASH_CR_LKEY_Msk
#define HASH_CR_ALGO_Pos (17U)
#define HASH_CR_ALGO_Msk (0xFUL << HASH_CR_ALGO_Pos) /*!< 0x001E0000 */
#define HASH_CR_ALGO HASH_CR_ALGO_Msk
#define HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) /*!< 0x00020000 */
#define HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
#define HASH_CR_ALGO_2 (0x4UL << HASH_CR_ALGO_Pos) /*!< 0x00080000 */
#define HASH_CR_ALGO_3 (0x8UL << HASH_CR_ALGO_Pos) /*!< 0x00100000 */
/****************** Bits definition for HASH_STR register *******************/
#define HASH_STR_NBLW_Pos (0U)
#define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
#define HASH_STR_NBLW HASH_STR_NBLW_Msk
#define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
#define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
#define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
#define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
#define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
#define HASH_STR_DCAL_Pos (8U)
#define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
#define HASH_STR_DCAL HASH_STR_DCAL_Msk
/****************** Bits definition for HASH_IMR register *******************/
#define HASH_IMR_DINIE_Pos (0U)
#define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
#define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
#define HASH_IMR_DCIE_Pos (1U)
#define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
#define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
/****************** Bits definition for HASH_SR register ********************/
#define HASH_SR_DINIS_Pos (0U)
#define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
#define HASH_SR_DINIS HASH_SR_DINIS_Msk
#define HASH_SR_DCIS_Pos (1U)
#define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
#define HASH_SR_DCIS HASH_SR_DCIS_Msk
#define HASH_SR_DMAS_Pos (2U)
#define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
#define HASH_SR_DMAS HASH_SR_DMAS_Msk
#define HASH_SR_BUSY_Pos (3U)
#define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
#define HASH_SR_BUSY HASH_SR_BUSY_Msk
#define HASH_SR_NBWE_Pos (16U)
#define HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) /*!< 0x000F0000 */
#define HASH_SR_NBWE HASH_SR_NBWE_Msk
#define HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) /*!< 0x00010000 */
#define HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) /*!< 0x00020000 */
#define HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) /*!< 0x00040000 */
#define HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) /*!< 0x00080000 */
#define HASH_SR_DINNE_Pos (15U)
#define HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) /*!< 0x00008000 */
#define HASH_SR_DINNE HASH_SR_DINNE_Msk
#define HASH_SR_NBWP_Pos (9U)
#define HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) /*!< 0x000F0000 */
#define HASH_SR_NBWP HASH_SR_NBWP_Msk
#define HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) /*!< 0x000O0200 */
#define HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) /*!< 0x00000400 */
#define HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) /*!< 0x00000800 */
#define HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) /*!< 0x00001000 */
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
#define I2C_CR1_FMP_Pos (24U)
#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */
#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */
#define I2C_CR1_ADDRACLR_Pos (30U)
#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */
#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */
#define I2C_CR1_STOPFACLR_Pos (31U)
#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */
#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Improved Inter-integrated Circuit Interface (I3C) */
/* */
/******************************************************************************/
/******************* Bit definition for I3C_CR register *********************/
#define I3C_CR_DCNT_Pos (0U)
#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */
#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */
#define I3C_CR_RNW_Pos (16U)
#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */
#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */
#define I3C_CR_CCC_Pos (16U)
#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */
#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */
#define I3C_CR_ADD_Pos (17U)
#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */
#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */
#define I3C_CR_MTYPE_Pos (27U)
#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */
#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */
#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */
#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */
#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */
#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */
#define I3C_CR_MEND_Pos (31U)
#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */
#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */
/******************* Bit definition for I3C_CFGR register *******************/
#define I3C_CFGR_EN_Pos (0U)
#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */
#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */
#define I3C_CFGR_CRINIT_Pos (1U)
#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */
#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */
#define I3C_CFGR_NOARBH_Pos (2U)
#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */
#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/
#define I3C_CFGR_RSTPTRN_Pos (3U)
#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */
#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */
#define I3C_CFGR_EXITPTRN_Pos (4U)
#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */
#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */
#define I3C_CFGR_HKSDAEN_Pos (5U)
#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */
#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */
#define I3C_CFGR_HJACK_Pos (7U)
#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */
#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */
#define I3C_CFGR_RXDMAEN_Pos (8U)
#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */
#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */
#define I3C_CFGR_RXFLUSH_Pos (9U)
#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */
#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */
#define I3C_CFGR_RXTHRES_Pos (10U)
#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */
#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */
#define I3C_CFGR_TXDMAEN_Pos (12U)
#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */
#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */
#define I3C_CFGR_TXFLUSH_Pos (13U)
#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */
#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */
#define I3C_CFGR_TXTHRES_Pos (14U)
#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */
#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */
#define I3C_CFGR_SDMAEN_Pos (16U)
#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */
#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */
#define I3C_CFGR_SFLUSH_Pos (17U)
#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */
#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */
#define I3C_CFGR_SMODE_Pos (18U)
#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */
#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */
#define I3C_CFGR_TMODE_Pos (19U)
#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */
#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */
#define I3C_CFGR_CDMAEN_Pos (20U)
#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */
#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */
#define I3C_CFGR_CFLUSH_Pos (21U)
#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */
#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */
#define I3C_CFGR_TSFSET_Pos (30U)
#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */
#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */
/******************* Bit definition for I3C_RDR register ********************/
#define I3C_RDR_RDB0_Pos (0U)
#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */
#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */
/****************** Bit definition for I3C_RDWR register ********************/
#define I3C_RDWR_RDBx_Pos (0U)
#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */
#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */
#define I3C_RDWR_RDB0_Pos (0U)
#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */
#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */
#define I3C_RDWR_RDB1_Pos (8U)
#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */
#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */
#define I3C_RDWR_RDB2_Pos (16U)
#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */
#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */
#define I3C_RDWR_RDB3_Pos (24U)
#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */
#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */
/******************* Bit definition for I3C_TDR register ********************/
#define I3C_TDR_TDB0_Pos (0U)
#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */
#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */
/****************** Bit definition for I3C_TDWR register ********************/
#define I3C_TDWR_TDBx_Pos (0U)
#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */
#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */
#define I3C_TDWR_TDB0_Pos (0U)
#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */
#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */
#define I3C_TDWR_TDB1_Pos (8U)
#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */
#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */
#define I3C_TDWR_TDB2_Pos (16U)
#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */
#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */
#define I3C_TDWR_TDB3_Pos (24U)
#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */
#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */
/******************* Bit definition for I3C_IBIDR register ******************/
#define I3C_IBIDR_IBIDBx_Pos (0U)
#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */
#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */
#define I3C_IBIDR_IBIDB0_Pos (0U)
#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */
#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */
#define I3C_IBIDR_IBIDB1_Pos (8U)
#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */
#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */
#define I3C_IBIDR_IBIDB2_Pos (16U)
#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */
#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */
#define I3C_IBIDR_IBIDB3_Pos (24U)
#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */
#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */
/****************** Bit definition for I3C_TGTTDR register ******************/
#define I3C_TGTTDR_TGTTDCNT_Pos (0U)
#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */
#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */
#define I3C_TGTTDR_PRELOAD_Pos (16U)
#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */
#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */
/******************* Bit definition for I3C_SR register *********************/
#define I3C_SR_XDCNT_Pos (0U)
#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */
#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */
#define I3C_SR_ABT_Pos (17U)
#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */
#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */
#define I3C_SR_DIR_Pos (18U)
#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */
#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */
#define I3C_SR_MID_Pos (24U)
#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */
#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */
/******************* Bit definition for I3C_SER register ********************/
#define I3C_SER_CODERR_Pos (0U)
#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */
#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */
#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */
#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */
#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */
#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */
#define I3C_SER_PERR_Pos (4U)
#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */
#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */
#define I3C_SER_STALL_Pos (5U)
#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */
#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */
#define I3C_SER_DOVR_Pos (6U)
#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */
#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */
#define I3C_SER_COVR_Pos (7U)
#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */
#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */
#define I3C_SER_ANACK_Pos (8U)
#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */
#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */
#define I3C_SER_DNACK_Pos (9U)
#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */
#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */
#define I3C_SER_DERR_Pos (10U)
#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */
#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */
/******************* Bit definition for I3C_RMR register ********************/
#define I3C_RMR_IBIRDCNT_Pos (0U)
#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */
#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */
#define I3C_RMR_RCODE_Pos (8U)
#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */
#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */
#define I3C_RMR_RADD_Pos (17U)
#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */
#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */
/******************* Bit definition for I3C_EVR register ********************/
#define I3C_EVR_CFEF_Pos (0U)
#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */
#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */
#define I3C_EVR_TXFEF_Pos (1U)
#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */
#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */
#define I3C_EVR_CFNFF_Pos (2U)
#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */
#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */
#define I3C_EVR_SFNEF_Pos (3U)
#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */
#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */
#define I3C_EVR_TXFNFF_Pos (4U)
#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */
#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */
#define I3C_EVR_RXFNEF_Pos (5U)
#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */
#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */
#define I3C_EVR_TXLASTF_Pos (6U)
#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */
#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */
#define I3C_EVR_RXLASTF_Pos (7U)
#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */
#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */
#define I3C_EVR_FCF_Pos (9U)
#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */
#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */
#define I3C_EVR_RXTGTENDF_Pos (10U)
#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */
#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */
#define I3C_EVR_ERRF_Pos (11U)
#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */
#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */
#define I3C_EVR_IBIF_Pos (15U)
#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */
#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */
#define I3C_EVR_IBIENDF_Pos (16U)
#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */
#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */
#define I3C_EVR_CRF_Pos (17U)
#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */
#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */
#define I3C_EVR_CRUPDF_Pos (18U)
#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */
#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */
#define I3C_EVR_HJF_Pos (19U)
#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */
#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */
#define I3C_EVR_WKPF_Pos (21U)
#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */
#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */
#define I3C_EVR_GETF_Pos (22U)
#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */
#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */
#define I3C_EVR_STAF_Pos (23U)
#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */
#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */
#define I3C_EVR_DAUPDF_Pos (24U)
#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */
#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */
#define I3C_EVR_MWLUPDF_Pos (25U)
#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */
#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */
#define I3C_EVR_MRLUPDF_Pos (26U)
#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */
#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */
#define I3C_EVR_RSTF_Pos (27U)
#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */
#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */
#define I3C_EVR_ASUPDF_Pos (28U)
#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */
#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */
#define I3C_EVR_INTUPDF_Pos (29U)
#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */
#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */
#define I3C_EVR_DEFF_Pos (30U)
#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */
#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */
#define I3C_EVR_GRPF_Pos (31U)
#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */
#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */
/******************* Bit definition for I3C_IER register ********************/
#define I3C_IER_CFNFIE_Pos (2U)
#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */
#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */
#define I3C_IER_SFNEIE_Pos (3U)
#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */
#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */
#define I3C_IER_TXFNFIE_Pos (4U)
#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */
#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */
#define I3C_IER_RXFNEIE_Pos (5U)
#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */
#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */
#define I3C_IER_FCIE_Pos (9U)
#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */
#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */
#define I3C_IER_RXTGTENDIE_Pos (10U)
#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */
#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */
#define I3C_IER_ERRIE_Pos (11U)
#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */
#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */
#define I3C_IER_IBIIE_Pos (15U)
#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */
#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */
#define I3C_IER_IBIENDIE_Pos (16U)
#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */
#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */
#define I3C_IER_CRIE_Pos (17U)
#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */
#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */
#define I3C_IER_CRUPDIE_Pos (18U)
#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */
#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */
#define I3C_IER_HJIE_Pos (19U)
#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */
#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */
#define I3C_IER_WKPIE_Pos (21U)
#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */
#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */
#define I3C_IER_GETIE_Pos (22U)
#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */
#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */
#define I3C_IER_STAIE_Pos (23U)
#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */
#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */
#define I3C_IER_DAUPDIE_Pos (24U)
#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */
#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */
#define I3C_IER_MWLUPDIE_Pos (25U)
#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */
#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */
#define I3C_IER_MRLUPDIE_Pos (26U)
#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */
#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */
#define I3C_IER_RSTIE_Pos (27U)
#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */
#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */
#define I3C_IER_ASUPDIE_Pos (28U)
#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */
#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */
#define I3C_IER_INTUPDIE_Pos (29U)
#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */
#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */
#define I3C_IER_DEFIE_Pos (30U)
#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */
#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */
#define I3C_IER_GRPIE_Pos (31U)
#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */
#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */
/******************* Bit definition for I3C_CEVR register *******************/
#define I3C_CEVR_CFCF_Pos (9U)
#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */
#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */
#define I3C_CEVR_CRXTGTENDF_Pos (10U)
#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */
#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */
#define I3C_CEVR_CERRF_Pos (11U)
#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */
#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */
#define I3C_CEVR_CIBIF_Pos (15U)
#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */
#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */
#define I3C_CEVR_CIBIENDF_Pos (16U)
#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */
#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */
#define I3C_CEVR_CCRF_Pos (17U)
#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */
#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */
#define I3C_CEVR_CCRUPDF_Pos (18U)
#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */
#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */
#define I3C_CEVR_CHJF_Pos (19U)
#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */
#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */
#define I3C_CEVR_CWKPF_Pos (21U)
#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */
#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */
#define I3C_CEVR_CGETF_Pos (22U)
#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */
#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */
#define I3C_CEVR_CSTAF_Pos (23U)
#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */
#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */
#define I3C_CEVR_CDAUPDF_Pos (24U)
#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */
#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */
#define I3C_CEVR_CMWLUPDF_Pos (25U)
#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */
#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */
#define I3C_CEVR_CMRLUPDF_Pos (26U)
#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */
#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */
#define I3C_CEVR_CRSTF_Pos (27U)
#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */
#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */
#define I3C_CEVR_CASUPDF_Pos (28U)
#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */
#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */
#define I3C_CEVR_CINTUPDF_Pos (29U)
#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */
#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */
#define I3C_CEVR_CDEFF_Pos (30U)
#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */
#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */
#define I3C_CEVR_CGRPF_Pos (31U)
#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */
#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */
/****************** Bit definition for I3C_DEVR0 register *******************/
#define I3C_DEVR0_DAVAL_Pos (0U)
#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */
#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */
#define I3C_DEVR0_DA_Pos (1U)
#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */
#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */
#define I3C_DEVR0_IBIEN_Pos (16U)
#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */
#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */
#define I3C_DEVR0_CREN_Pos (17U)
#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */
#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */
#define I3C_DEVR0_HJEN_Pos (19U)
#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */
#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */
#define I3C_DEVR0_AS_Pos (20U)
#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */
#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */
#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */
#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */
#define I3C_DEVR0_RSTACT_Pos (22U)
#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */
#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */
#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */
#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */
#define I3C_DEVR0_RSTVAL_Pos (24U)
#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */
#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */
/****************** Bit definition for I3C_DEVRX register *******************/
#define I3C_DEVRX_DA_Pos (1U)
#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */
#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */
#define I3C_DEVRX_IBIACK_Pos (16U)
#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */
#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */
#define I3C_DEVRX_CRACK_Pos (17U)
#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */
#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */
#define I3C_DEVRX_IBIDEN_Pos (18U)
#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */
#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */
#define I3C_DEVRX_SUSP_Pos (19U)
#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */
#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */
#define I3C_DEVRX_DIS_Pos (31U)
#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */
#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */
/****************** Bit definition for I3C_MAXRLR register ******************/
#define I3C_MAXRLR_MRL_Pos (0U)
#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */
#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */
#define I3C_MAXRLR_IBIP_Pos (16U)
#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */
#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */
#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */
#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */
#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */
/****************** Bit definition for I3C_MAXWLR register ******************/
#define I3C_MAXWLR_MWL_Pos (0U)
#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */
#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */
/**************** Bit definition for I3C_TIMINGR0 register ******************/
#define I3C_TIMINGR0_SCLL_PP_Pos (0U)
#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */
#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */
#define I3C_TIMINGR0_SCLH_I3C_Pos (8U)
#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */
#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
#define I3C_TIMINGR0_SCLL_OD_Pos (16U)
#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */
#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */
#define I3C_TIMINGR0_SCLH_I2C_Pos (24U)
#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */
#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */
/**************** Bit definition for I3C_TIMINGR1 register ******************/
#define I3C_TIMINGR1_AVAL_Pos (0U)
#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */
#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */
#define I3C_TIMINGR1_ASNCR_Pos (8U)
#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */
#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */
#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */
#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */
#define I3C_TIMINGR1_FREE_Pos (16U)
#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */
#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */
#define I3C_TIMINGR1_SDA_HD_Pos (28U)
#define I3C_TIMINGR1_SDA_HD_Msk (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x00010000 */
#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */
/**************** Bit definition for I3C_TIMINGR2 register ******************/
#define I3C_TIMINGR2_STALLT_Pos (0U)
#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x0000001 */
#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */
#define I3C_TIMINGR2_STALLD_Pos (1U)
#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x0000002 */
#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */
#define I3C_TIMINGR2_STALLC_Pos (2U)
#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x0000004 */
#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */
#define I3C_TIMINGR2_STALLA_Pos (3U)
#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x0000008 */
#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */
#define I3C_TIMINGR2_STALL_Pos (8U)
#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x000FF00 */
#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */
/******************* Bit definition for I3C_BCR register ********************/
#define I3C_BCR_BCR_Pos (0U)
#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */
#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */
#define I3C_BCR_BCR0_Pos (0U)
#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */
#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */
#define I3C_BCR_BCR1_Pos (1U)
#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */
#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */
#define I3C_BCR_BCR2_Pos (2U)
#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */
#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */
#define I3C_BCR_BCR3_Pos (3U)
#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */
#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */
#define I3C_BCR_BCR4_Pos (4U)
#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */
#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */
#define I3C_BCR_BCR5_Pos (5U)
#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */
#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */
#define I3C_BCR_BCR6_Pos (6U)
#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */
#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */
/******************* Bit definition for I3C_DCR register ********************/
#define I3C_DCR_DCR_Pos (0U)
#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x00000FF */
#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */
/***************** Bit definition for I3C_GETCAPR register ******************/
#define I3C_GETCAPR_CAPPEND_Pos (14U)
#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */
#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */
/***************** Bit definition for I3C_CRCAPR register *******************/
#define I3C_CRCAPR_CAPDHOFF_Pos (3U)
#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */
#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */
#define I3C_CRCAPR_CAPGRP_Pos (9U)
#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */
#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */
/**************** Bit definition for I3C_GETMXDSR register ******************/
#define I3C_GETMXDSR_HOFFAS_Pos (0U)
#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */
#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */
#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */
#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */
#define I3C_GETMXDSR_FMT_Pos (8U)
#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */
#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */
#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */
#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */
#define I3C_GETMXDSR_RDTURN_Pos (16U)
#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */
#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */
#define I3C_GETMXDSR_TSCO_Pos (24U)
#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */
#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */
/****************** Bit definition for I3C_EPIDR register *******************/
#define I3C_EPIDR_MIPIID_Pos (12U)
#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */
#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */
#define I3C_EPIDR_IDTSEL_Pos (16U)
#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */
#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */
#define I3C_EPIDR_MIPIMID_Pos (17U)
#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */
#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */
/******************************************************************************/
/* */
/* Illegal Access Controller (IAC) */
/* */
/******************************************************************************/
/******************* Bits definition for IAC_IER0 register *******************/
#define IAC_IER0_IAIE0_Pos (0U)
#define IAC_IER0_IAIE0_Msk (0x1UL << IAC_IER0_IAIE0_Pos) /*!< 0x00000001 */
#define IAC_IER0_IAIE0 IAC_IER0_IAIE0_Msk
#define IAC_IER0_IAIE1_Pos (1U)
#define IAC_IER0_IAIE1_Msk (0x1UL << IAC_IER0_IAIE1_Pos) /*!< 0x00000002 */
#define IAC_IER0_IAIE1 IAC_IER0_IAIE1_Msk
#define IAC_IER0_IAIE2_Pos (2U)
#define IAC_IER0_IAIE2_Msk (0x1UL << IAC_IER0_IAIE2_Pos) /*!< 0x00000004 */
#define IAC_IER0_IAIE2 IAC_IER0_IAIE2_Msk
#define IAC_IER0_IAIE3_Pos (3U)
#define IAC_IER0_IAIE3_Msk (0x1UL << IAC_IER0_IAIE3_Pos) /*!< 0x00000008 */
#define IAC_IER0_IAIE3 IAC_IER0_IAIE3_Msk
#define IAC_IER0_IAIE4_Pos (4U)
#define IAC_IER0_IAIE4_Msk (0x1UL << IAC_IER0_IAIE4_Pos) /*!< 0x00000010 */
#define IAC_IER0_IAIE4 IAC_IER0_IAIE4_Msk
#define IAC_IER0_IAIE5_Pos (5U)
#define IAC_IER0_IAIE5_Msk (0x1UL << IAC_IER0_IAIE5_Pos) /*!< 0x00000020 */
#define IAC_IER0_IAIE5 IAC_IER0_IAIE5_Msk
#define IAC_IER0_IAIE6_Pos (6U)
#define IAC_IER0_IAIE6_Msk (0x1UL << IAC_IER0_IAIE6_Pos) /*!< 0x00000040 */
#define IAC_IER0_IAIE6 IAC_IER0_IAIE6_Msk
#define IAC_IER0_IAIE8_Pos (8U)
#define IAC_IER0_IAIE8_Msk (0x1UL << IAC_IER0_IAIE8_Pos) /*!< 0x00000100 */
#define IAC_IER0_IAIE8 IAC_IER0_IAIE8_Msk
#define IAC_IER0_IAIE9_Pos (9U)
#define IAC_IER0_IAIE9_Msk (0x1UL << IAC_IER0_IAIE9_Pos) /*!< 0x00000200 */
#define IAC_IER0_IAIE9 IAC_IER0_IAIE9_Msk
#define IAC_IER0_IAIE10_Pos (10U)
#define IAC_IER0_IAIE10_Msk (0x1UL << IAC_IER0_IAIE10_Pos) /*!< 0x00000400 */
#define IAC_IER0_IAIE10 IAC_IER0_IAIE10_Msk
#define IAC_IER0_IAIE11_Pos (11U)
#define IAC_IER0_IAIE11_Msk (0x1UL << IAC_IER0_IAIE11_Pos) /*!< 0x00000800 */
#define IAC_IER0_IAIE11 IAC_IER0_IAIE11_Msk
#define IAC_IER0_IAIE12_Pos (12U)
#define IAC_IER0_IAIE12_Msk (0x1UL << IAC_IER0_IAIE12_Pos) /*!< 0x00001000 */
#define IAC_IER0_IAIE12 IAC_IER0_IAIE12_Msk
#define IAC_IER0_IAIE13_Pos (13U)
#define IAC_IER0_IAIE13_Msk (0x1UL << IAC_IER0_IAIE13_Pos) /*!< 0x00002000 */
#define IAC_IER0_IAIE13 IAC_IER0_IAIE13_Msk
#define IAC_IER0_IAIE14_Pos (14U)
#define IAC_IER0_IAIE14_Msk (0x1UL << IAC_IER0_IAIE14_Pos) /*!< 0x00004000 */
#define IAC_IER0_IAIE14 IAC_IER0_IAIE14_Msk
#define IAC_IER0_IAIE15_Pos (15U)
#define IAC_IER0_IAIE15_Msk (0x1UL << IAC_IER0_IAIE15_Pos) /*!< 0x00008000 */
#define IAC_IER0_IAIE15 IAC_IER0_IAIE15_Msk
#define IAC_IER0_IAIE16_Pos (16U)
#define IAC_IER0_IAIE16_Msk (0x1UL << IAC_IER0_IAIE16_Pos) /*!< 0x00010000 */
#define IAC_IER0_IAIE16 IAC_IER0_IAIE16_Msk
#define IAC_IER0_IAIE17_Pos (17U)
#define IAC_IER0_IAIE17_Msk (0x1UL << IAC_IER0_IAIE17_Pos) /*!< 0x00020000 */
#define IAC_IER0_IAIE17 IAC_IER0_IAIE17_Msk
#define IAC_IER0_IAIE18_Pos (18U)
#define IAC_IER0_IAIE18_Msk (0x1UL << IAC_IER0_IAIE18_Pos) /*!< 0x00040000 */
#define IAC_IER0_IAIE18 IAC_IER0_IAIE18_Msk
#define IAC_IER0_IAIE19_Pos (19U)
#define IAC_IER0_IAIE19_Msk (0x1UL << IAC_IER0_IAIE19_Pos) /*!< 0x00080000 */
#define IAC_IER0_IAIE19 IAC_IER0_IAIE19_Msk
#define IAC_IER0_IAIE20_Pos (20U)
#define IAC_IER0_IAIE20_Msk (0x1UL << IAC_IER0_IAIE20_Pos) /*!< 0x00100000 */
#define IAC_IER0_IAIE20 IAC_IER0_IAIE20_Msk
#define IAC_IER0_IAIE21_Pos (21U)
#define IAC_IER0_IAIE21_Msk (0x1UL << IAC_IER0_IAIE21_Pos) /*!< 0x00200000 */
#define IAC_IER0_IAIE21 IAC_IER0_IAIE21_Msk
#define IAC_IER0_IAIE22_Pos (22U)
#define IAC_IER0_IAIE22_Msk (0x1UL << IAC_IER0_IAIE22_Pos) /*!< 0x00400000 */
#define IAC_IER0_IAIE22 IAC_IER0_IAIE22_Msk
#define IAC_IER0_IAIE23_Pos (23U)
#define IAC_IER0_IAIE23_Msk (0x1UL << IAC_IER0_IAIE23_Pos) /*!< 0x00800000 */
#define IAC_IER0_IAIE23 IAC_IER0_IAIE23_Msk
#define IAC_IER0_IAIE24_Pos (24U)
#define IAC_IER0_IAIE24_Msk (0x1UL << IAC_IER0_IAIE24_Pos) /*!< 0x01000000 */
#define IAC_IER0_IAIE24 IAC_IER0_IAIE24_Msk
#define IAC_IER0_IAIE25_Pos (25U)
#define IAC_IER0_IAIE25_Msk (0x1UL << IAC_IER0_IAIE25_Pos) /*!< 0x02000000 */
#define IAC_IER0_IAIE25 IAC_IER0_IAIE25_Msk
#define IAC_IER0_IAIE26_Pos (26U)
#define IAC_IER0_IAIE26_Msk (0x1UL << IAC_IER0_IAIE26_Pos) /*!< 0x04000000 */
#define IAC_IER0_IAIE26 IAC_IER0_IAIE26_Msk
#define IAC_IER0_IAIE27_Pos (27U)
#define IAC_IER0_IAIE27_Msk (0x1UL << IAC_IER0_IAIE27_Pos) /*!< 0x08000000 */
#define IAC_IER0_IAIE27 IAC_IER0_IAIE27_Msk
#define IAC_IER0_IAIE28_Pos (28U)
#define IAC_IER0_IAIE28_Msk (0x1UL << IAC_IER0_IAIE28_Pos) /*!< 0x10000000 */
#define IAC_IER0_IAIE28 IAC_IER0_IAIE28_Msk
#define IAC_IER0_IAIE29_Pos (29U)
#define IAC_IER0_IAIE29_Msk (0x1UL << IAC_IER0_IAIE29_Pos) /*!< 0x20000000 */
#define IAC_IER0_IAIE29 IAC_IER0_IAIE29_Msk
#define IAC_IER0_IAIE30_Pos (30U)
#define IAC_IER0_IAIE30_Msk (0x1UL << IAC_IER0_IAIE30_Pos) /*!< 0x40000000 */
#define IAC_IER0_IAIE30 IAC_IER0_IAIE30_Msk
#define IAC_IER0_IAIE31_Pos (31U)
#define IAC_IER0_IAIE31_Msk (0x1UL << IAC_IER0_IAIE31_Pos) /*!< 0x80000000 */
#define IAC_IER0_IAIE31 IAC_IER0_IAIE31_Msk
/******************* Bits definition for IAC_IER1 register *******************/
#define IAC_IER1_IAIE32_Pos (0U)
#define IAC_IER1_IAIE32_Msk (0x1UL << IAC_IER1_IAIE32_Pos) /*!< 0x00000001 */
#define IAC_IER1_IAIE32 IAC_IER1_IAIE32_Msk
#define IAC_IER1_IAIE33_Pos (1U)
#define IAC_IER1_IAIE33_Msk (0x1UL << IAC_IER1_IAIE33_Pos) /*!< 0x00000002 */
#define IAC_IER1_IAIE33 IAC_IER1_IAIE33_Msk
#define IAC_IER1_IAIE34_Pos (2U)
#define IAC_IER1_IAIE34_Msk (0x1UL << IAC_IER1_IAIE34_Pos) /*!< 0x00000004 */
#define IAC_IER1_IAIE34 IAC_IER1_IAIE34_Msk
#define IAC_IER1_IAIE35_Pos (3U)
#define IAC_IER1_IAIE35_Msk (0x1UL << IAC_IER1_IAIE35_Pos) /*!< 0x00000008 */
#define IAC_IER1_IAIE35 IAC_IER1_IAIE35_Msk
#define IAC_IER1_IAIE36_Pos (4U)
#define IAC_IER1_IAIE36_Msk (0x1UL << IAC_IER1_IAIE36_Pos) /*!< 0x00000010 */
#define IAC_IER1_IAIE36 IAC_IER1_IAIE36_Msk
#define IAC_IER1_IAIE37_Pos (5U)
#define IAC_IER1_IAIE37_Msk (0x1UL << IAC_IER1_IAIE37_Pos) /*!< 0x00000020 */
#define IAC_IER1_IAIE37 IAC_IER1_IAIE37_Msk
#define IAC_IER1_IAIE38_Pos (6U)
#define IAC_IER1_IAIE38_Msk (0x1UL << IAC_IER1_IAIE38_Pos) /*!< 0x00000040 */
#define IAC_IER1_IAIE38 IAC_IER1_IAIE38_Msk
#define IAC_IER1_IAIE39_Pos (7U)
#define IAC_IER1_IAIE39_Msk (0x1UL << IAC_IER1_IAIE39_Pos) /*!< 0x00000080 */
#define IAC_IER1_IAIE39 IAC_IER1_IAIE39_Msk
#define IAC_IER1_IAIE40_Pos (8U)
#define IAC_IER1_IAIE40_Msk (0x1UL << IAC_IER1_IAIE40_Pos) /*!< 0x00000100 */
#define IAC_IER1_IAIE40 IAC_IER1_IAIE40_Msk
#define IAC_IER1_IAIE41_Pos (9U)
#define IAC_IER1_IAIE41_Msk (0x1UL << IAC_IER1_IAIE41_Pos) /*!< 0x00000200 */
#define IAC_IER1_IAIE41 IAC_IER1_IAIE41_Msk
#define IAC_IER1_IAIE42_Pos (10U)
#define IAC_IER1_IAIE42_Msk (0x1UL << IAC_IER1_IAIE42_Pos) /*!< 0x00000400 */
#define IAC_IER1_IAIE42 IAC_IER1_IAIE42_Msk
#define IAC_IER1_IAIE43_Pos (11U)
#define IAC_IER1_IAIE43_Msk (0x1UL << IAC_IER1_IAIE43_Pos) /*!< 0x00000800 */
#define IAC_IER1_IAIE43 IAC_IER1_IAIE43_Msk
#define IAC_IER1_IAIE44_Pos (12U)
#define IAC_IER1_IAIE44_Msk (0x1UL << IAC_IER1_IAIE44_Pos) /*!< 0x00001000 */
#define IAC_IER1_IAIE44 IAC_IER1_IAIE44_Msk
#define IAC_IER1_IAIE45_Pos (13U)
#define IAC_IER1_IAIE45_Msk (0x1UL << IAC_IER1_IAIE45_Pos) /*!< 0x00002000 */
#define IAC_IER1_IAIE45 IAC_IER1_IAIE45_Msk
#define IAC_IER1_IAIE46_Pos (14U)
#define IAC_IER1_IAIE46_Msk (0x1UL << IAC_IER1_IAIE46_Pos) /*!< 0x00004000 */
#define IAC_IER1_IAIE46 IAC_IER1_IAIE46_Msk
#define IAC_IER1_IAIE47_Pos (15U)
#define IAC_IER1_IAIE47_Msk (0x1UL << IAC_IER1_IAIE47_Pos) /*!< 0x00008000 */
#define IAC_IER1_IAIE47 IAC_IER1_IAIE47_Msk
#define IAC_IER1_IAIE48_Pos (16U)
#define IAC_IER1_IAIE48_Msk (0x1UL << IAC_IER1_IAIE48_Pos) /*!< 0x00010000 */
#define IAC_IER1_IAIE48 IAC_IER1_IAIE48_Msk
#define IAC_IER1_IAIE49_Pos (17U)
#define IAC_IER1_IAIE49_Msk (0x1UL << IAC_IER1_IAIE49_Pos) /*!< 0x00020000 */
#define IAC_IER1_IAIE49 IAC_IER1_IAIE49_Msk
#define IAC_IER1_IAIE50_Pos (18U)
#define IAC_IER1_IAIE50_Msk (0x1UL << IAC_IER1_IAIE50_Pos) /*!< 0x00040000 */
#define IAC_IER1_IAIE50 IAC_IER1_IAIE50_Msk
#define IAC_IER1_IAIE51_Pos (19U)
#define IAC_IER1_IAIE51_Msk (0x1UL << IAC_IER1_IAIE51_Pos) /*!< 0x00080000 */
#define IAC_IER1_IAIE51 IAC_IER1_IAIE51_Msk
#define IAC_IER1_IAIE52_Pos (20U)
#define IAC_IER1_IAIE52_Msk (0x1UL << IAC_IER1_IAIE52_Pos) /*!< 0x00100000 */
#define IAC_IER1_IAIE52 IAC_IER1_IAIE52_Msk
#define IAC_IER1_IAIE53_Pos (21U)
#define IAC_IER1_IAIE53_Msk (0x1UL << IAC_IER1_IAIE53_Pos) /*!< 0x00200000 */
#define IAC_IER1_IAIE53 IAC_IER1_IAIE53_Msk
#define IAC_IER1_IAIE54_Pos (22U)
#define IAC_IER1_IAIE54_Msk (0x1UL << IAC_IER1_IAIE54_Pos) /*!< 0x00400000 */
#define IAC_IER1_IAIE54 IAC_IER1_IAIE54_Msk
#define IAC_IER1_IAIE55_Pos (23U)
#define IAC_IER1_IAIE55_Msk (0x1UL << IAC_IER1_IAIE55_Pos) /*!< 0x00800000 */
#define IAC_IER1_IAIE55 IAC_IER1_IAIE55_Msk
#define IAC_IER1_IAIE56_Pos (24U)
#define IAC_IER1_IAIE56_Msk (0x1UL << IAC_IER1_IAIE56_Pos) /*!< 0x01000000 */
#define IAC_IER1_IAIE56 IAC_IER1_IAIE56_Msk
#define IAC_IER1_IAIE57_Pos (25U)
#define IAC_IER1_IAIE57_Msk (0x1UL << IAC_IER1_IAIE57_Pos) /*!< 0x02000000 */
#define IAC_IER1_IAIE57 IAC_IER1_IAIE57_Msk
#define IAC_IER1_IAIE58_Pos (26U)
#define IAC_IER1_IAIE58_Msk (0x1UL << IAC_IER1_IAIE58_Pos) /*!< 0x04000000 */
#define IAC_IER1_IAIE58 IAC_IER1_IAIE58_Msk
#define IAC_IER1_IAIE60_Pos (28U)
#define IAC_IER1_IAIE60_Msk (0x1UL << IAC_IER1_IAIE60_Pos) /*!< 0x10000000 */
#define IAC_IER1_IAIE60 IAC_IER1_IAIE60_Msk
#define IAC_IER1_IAIE61_Pos (29U)
#define IAC_IER1_IAIE61_Msk (0x1UL << IAC_IER1_IAIE61_Pos) /*!< 0x20000000 */
#define IAC_IER1_IAIE61 IAC_IER1_IAIE61_Msk
#define IAC_IER1_IAIE62_Pos (30U)
#define IAC_IER1_IAIE62_Msk (0x1UL << IAC_IER1_IAIE62_Pos) /*!< 0x40000000 */
#define IAC_IER1_IAIE62 IAC_IER1_IAIE62_Msk
/******************* Bits definition for IAC_IER2 register *******************/
#define IAC_IER2_IAIE64_Pos (0U)
#define IAC_IER2_IAIE64_Msk (0x1UL << IAC_IER2_IAIE64_Pos) /*!< 0x00000001 */
#define IAC_IER2_IAIE64 IAC_IER2_IAIE64_Msk
#define IAC_IER2_IAIE65_Pos (1U)
#define IAC_IER2_IAIE65_Msk (0x1UL << IAC_IER2_IAIE65_Pos) /*!< 0x00000002 */
#define IAC_IER2_IAIE65 IAC_IER2_IAIE65_Msk
#define IAC_IER2_IAIE67_Pos (3U)
#define IAC_IER2_IAIE67_Msk (0x1UL << IAC_IER2_IAIE67_Pos) /*!< 0x00000008 */
#define IAC_IER2_IAIE67 IAC_IER2_IAIE67_Msk
#define IAC_IER2_IAIE68_Pos (4U)
#define IAC_IER2_IAIE68_Msk (0x1UL << IAC_IER2_IAIE68_Pos) /*!< 0x00000010 */
#define IAC_IER2_IAIE68 IAC_IER2_IAIE68_Msk
#define IAC_IER2_IAIE69_Pos (5U)
#define IAC_IER2_IAIE69_Msk (0x1UL << IAC_IER2_IAIE69_Pos) /*!< 0x00000020 */
#define IAC_IER2_IAIE69 IAC_IER2_IAIE69_Msk
#define IAC_IER2_IAIE76_Pos (12U)
#define IAC_IER2_IAIE76_Msk (0x1UL << IAC_IER2_IAIE76_Pos) /*!< 0x00001000 */
#define IAC_IER2_IAIE76 IAC_IER2_IAIE76_Msk
#define IAC_IER2_IAIE77_Pos (13U)
#define IAC_IER2_IAIE77_Msk (0x1UL << IAC_IER2_IAIE77_Pos) /*!< 0x00002000 */
#define IAC_IER2_IAIE77 IAC_IER2_IAIE77_Msk
#define IAC_IER2_IAIE78_Pos (14U)
#define IAC_IER2_IAIE78_Msk (0x1UL << IAC_IER2_IAIE78_Pos) /*!< 0x00004000 */
#define IAC_IER2_IAIE78 IAC_IER2_IAIE78_Msk
#define IAC_IER2_IAIE79_Pos (15U)
#define IAC_IER2_IAIE79_Msk (0x1UL << IAC_IER2_IAIE79_Pos) /*!< 0x00008000 */
#define IAC_IER2_IAIE79 IAC_IER2_IAIE79_Msk
#define IAC_IER2_IAIE80_Pos (16U)
#define IAC_IER2_IAIE80_Msk (0x1UL << IAC_IER2_IAIE80_Pos) /*!< 0x00010000 */
#define IAC_IER2_IAIE80 IAC_IER2_IAIE80_Msk
#define IAC_IER2_IAIE81_Pos (17U)
#define IAC_IER2_IAIE81_Msk (0x1UL << IAC_IER2_IAIE81_Pos) /*!< 0x00020000 */
#define IAC_IER2_IAIE81 IAC_IER2_IAIE81_Msk
#define IAC_IER2_IAIE82_Pos (18U)
#define IAC_IER2_IAIE82_Msk (0x1UL << IAC_IER2_IAIE82_Pos) /*!< 0x00040000 */
#define IAC_IER2_IAIE82 IAC_IER2_IAIE82_Msk
#define IAC_IER2_IAIE83_Pos (19U)
#define IAC_IER2_IAIE83_Msk (0x1UL << IAC_IER2_IAIE83_Pos) /*!< 0x00080000 */
#define IAC_IER2_IAIE83 IAC_IER2_IAIE83_Msk
#define IAC_IER2_IAIE84_Pos (20U)
#define IAC_IER2_IAIE84_Msk (0x1UL << IAC_IER2_IAIE84_Pos) /*!< 0x00100000 */
#define IAC_IER2_IAIE84 IAC_IER2_IAIE84_Msk
#define IAC_IER2_IAIE86_Pos (22U)
#define IAC_IER2_IAIE86_Msk (0x1UL << IAC_IER2_IAIE86_Pos) /*!< 0x00400000 */
#define IAC_IER2_IAIE86 IAC_IER2_IAIE86_Msk
#define IAC_IER2_IAIE87_Pos (23U)
#define IAC_IER2_IAIE87_Msk (0x1UL << IAC_IER2_IAIE87_Pos) /*!< 0x00800000 */
#define IAC_IER2_IAIE87 IAC_IER2_IAIE87_Msk
#define IAC_IER2_IAIE88_Pos (24U)
#define IAC_IER2_IAIE88_Msk (0x1UL << IAC_IER2_IAIE88_Pos) /*!< 0x01000000 */
#define IAC_IER2_IAIE88 IAC_IER2_IAIE88_Msk
#define IAC_IER2_IAIE89_Pos (25U)
#define IAC_IER2_IAIE89_Msk (0x1UL << IAC_IER2_IAIE89_Pos) /*!< 0x02000000 */
#define IAC_IER2_IAIE89 IAC_IER2_IAIE89_Msk
#define IAC_IER2_IAIE90_Pos (26U)
#define IAC_IER2_IAIE90_Msk (0x1UL << IAC_IER2_IAIE90_Pos) /*!< 0x04000000 */
#define IAC_IER2_IAIE90 IAC_IER2_IAIE90_Msk
#define IAC_IER2_IAIE92_Pos (28U)
#define IAC_IER2_IAIE92_Msk (0x1UL << IAC_IER2_IAIE92_Pos) /*!< 0x10000000 */
#define IAC_IER2_IAIE92 IAC_IER2_IAIE92_Msk
#define IAC_IER2_IAIE93_Pos (29U)
#define IAC_IER2_IAIE93_Msk (0x1UL << IAC_IER2_IAIE93_Pos) /*!< 0x20000000 */
#define IAC_IER2_IAIE93 IAC_IER2_IAIE93_Msk
#define IAC_IER2_IAIE94_Pos (30U)
#define IAC_IER2_IAIE94_Msk (0x1UL << IAC_IER2_IAIE94_Pos) /*!< 0x40000000 */
#define IAC_IER2_IAIE94 IAC_IER2_IAIE94_Msk
#define IAC_IER2_IAIE95_Pos (31U)
#define IAC_IER2_IAIE95_Msk (0x1UL << IAC_IER2_IAIE95_Pos) /*!< 0x80000000 */
#define IAC_IER2_IAIE95 IAC_IER2_IAIE95_Msk
/******************* Bits definition for IAC_IER3 register *******************/
#define IAC_IER3_IAIE96_Pos (0U)
#define IAC_IER3_IAIE96_Msk (0x1UL << IAC_IER3_IAIE96_Pos) /*!< 0x00000001 */
#define IAC_IER3_IAIE96 IAC_IER3_IAIE96_Msk
#define IAC_IER3_IAIE97_Pos (1U)
#define IAC_IER3_IAIE97_Msk (0x1UL << IAC_IER3_IAIE97_Pos) /*!< 0x00000002 */
#define IAC_IER3_IAIE97 IAC_IER3_IAIE97_Msk
#define IAC_IER3_IAIE98_Pos (2U)
#define IAC_IER3_IAIE98_Msk (0x1UL << IAC_IER3_IAIE98_Pos) /*!< 0x00000004 */
#define IAC_IER3_IAIE98 IAC_IER3_IAIE98_Msk
#define IAC_IER3_IAIE99_Pos (3U)
#define IAC_IER3_IAIE99_Msk (0x1UL << IAC_IER3_IAIE99_Pos) /*!< 0x00000008 */
#define IAC_IER3_IAIE99 IAC_IER3_IAIE99_Msk
#define IAC_IER3_IAIE100_Pos (4U)
#define IAC_IER3_IAIE100_Msk (0x1UL << IAC_IER3_IAIE100_Pos) /*!< 0x00000010 */
#define IAC_IER3_IAIE100 IAC_IER3_IAIE100_Msk
#define IAC_IER3_IAIE101_Pos (5U)
#define IAC_IER3_IAIE101_Msk (0x1UL << IAC_IER3_IAIE101_Pos) /*!< 0x00000020 */
#define IAC_IER3_IAIE101 IAC_IER3_IAIE101_Msk
#define IAC_IER3_IAIE102_Pos (6U)
#define IAC_IER3_IAIE102_Msk (0x1UL << IAC_IER3_IAIE102_Pos) /*!< 0x00000040 */
#define IAC_IER3_IAIE102 IAC_IER3_IAIE102_Msk
#define IAC_IER3_IAIE103_Pos (7U)
#define IAC_IER3_IAIE103_Msk (0x1UL << IAC_IER3_IAIE103_Pos) /*!< 0x00000080 */
#define IAC_IER3_IAIE103 IAC_IER3_IAIE103_Msk
#define IAC_IER3_IAIE104_Pos (8U)
#define IAC_IER3_IAIE104_Msk (0x1UL << IAC_IER3_IAIE104_Pos) /*!< 0x00000100 */
#define IAC_IER3_IAIE104 IAC_IER3_IAIE104_Msk
#define IAC_IER3_IAIE106_Pos (10U)
#define IAC_IER3_IAIE106_Msk (0x1UL << IAC_IER3_IAIE106_Pos) /*!< 0x00000400 */
#define IAC_IER3_IAIE106 IAC_IER3_IAIE106_Msk
/******************* Bits definition for IAC_IER4 register *******************/
#define IAC_IER4_IAIE128_Pos (0U)
#define IAC_IER4_IAIE128_Msk (0x1UL << IAC_IER4_IAIE128_Pos) /*!< 0x00000001 */
#define IAC_IER4_IAIE128 IAC_IER4_IAIE128_Msk
#define IAC_IER4_IAIE129_Pos (1U)
#define IAC_IER4_IAIE129_Msk (0x1UL << IAC_IER4_IAIE129_Pos) /*!< 0x00000002 */
#define IAC_IER4_IAIE129 IAC_IER4_IAIE129_Msk
#define IAC_IER4_IAIE130_Pos (2U)
#define IAC_IER4_IAIE130_Msk (0x1UL << IAC_IER4_IAIE130_Pos) /*!< 0x00000004 */
#define IAC_IER4_IAIE130 IAC_IER4_IAIE130_Msk
#define IAC_IER4_IAIE131_Pos (3U)
#define IAC_IER4_IAIE131_Msk (0x1UL << IAC_IER4_IAIE131_Pos) /*!< 0x00000008 */
#define IAC_IER4_IAIE131 IAC_IER4_IAIE131_Msk
#define IAC_IER4_IAIE133_Pos (5U)
#define IAC_IER4_IAIE133_Msk (0x1UL << IAC_IER4_IAIE133_Pos) /*!< 0x00000020 */
#define IAC_IER4_IAIE133 IAC_IER4_IAIE133_Msk
#define IAC_IER4_IAIE134_Pos (6U)
#define IAC_IER4_IAIE134_Msk (0x1UL << IAC_IER4_IAIE134_Pos) /*!< 0x00000040 */
#define IAC_IER4_IAIE134 IAC_IER4_IAIE134_Msk
#define IAC_IER4_IAIE135_Pos (7U)
#define IAC_IER4_IAIE135_Msk (0x1UL << IAC_IER4_IAIE135_Pos) /*!< 0x00000080 */
#define IAC_IER4_IAIE135 IAC_IER4_IAIE135_Msk
#define IAC_IER4_IAIE136_Pos (8U)
#define IAC_IER4_IAIE136_Msk (0x1UL << IAC_IER4_IAIE136_Pos) /*!< 0x00000100 */
#define IAC_IER4_IAIE136 IAC_IER4_IAIE136_Msk
#define IAC_IER4_IAIE137_Pos (9U)
#define IAC_IER4_IAIE137_Msk (0x1UL << IAC_IER4_IAIE137_Pos) /*!< 0x00000200 */
#define IAC_IER4_IAIE137 IAC_IER4_IAIE137_Msk
#define IAC_IER4_IAIE138_Pos (10U)
#define IAC_IER4_IAIE138_Msk (0x1UL << IAC_IER4_IAIE138_Pos) /*!< 0x00000400 */
#define IAC_IER4_IAIE138 IAC_IER4_IAIE138_Msk
#define IAC_IER4_IAIE139_Pos (11U)
#define IAC_IER4_IAIE139_Msk (0x1UL << IAC_IER4_IAIE139_Pos) /*!< 0x00000800 */
#define IAC_IER4_IAIE139 IAC_IER4_IAIE139_Msk
#define IAC_IER4_IAIE140_Pos (12U)
#define IAC_IER4_IAIE140_Msk (0x1UL << IAC_IER4_IAIE140_Pos) /*!< 0x00001000 */
#define IAC_IER4_IAIE140 IAC_IER4_IAIE140_Msk
#define IAC_IER4_IAIE141_Pos (13U)
#define IAC_IER4_IAIE141_Msk (0x1UL << IAC_IER4_IAIE141_Pos) /*!< 0x00002000 */
#define IAC_IER4_IAIE141 IAC_IER4_IAIE141_Msk
#define IAC_IER4_IAIE142_Pos (14U)
#define IAC_IER4_IAIE142_Msk (0x1UL << IAC_IER4_IAIE142_Pos) /*!< 0x00004000 */
#define IAC_IER4_IAIE142 IAC_IER4_IAIE142_Msk
#define IAC_IER4_IAIE143_Pos (15U)
#define IAC_IER4_IAIE143_Msk (0x1UL << IAC_IER4_IAIE143_Pos) /*!< 0x00008000 */
#define IAC_IER4_IAIE143 IAC_IER4_IAIE143_Msk
#define IAC_IER4_IAIE144_Pos (16U)
#define IAC_IER4_IAIE144_Msk (0x1UL << IAC_IER4_IAIE144_Pos) /*!< 0x00010000 */
#define IAC_IER4_IAIE144 IAC_IER4_IAIE144_Msk
#define IAC_IER4_IAIE145_Pos (17U)
#define IAC_IER4_IAIE145_Msk (0x1UL << IAC_IER4_IAIE145_Pos) /*!< 0x00020000 */
#define IAC_IER4_IAIE145 IAC_IER4_IAIE145_Msk
#define IAC_IER4_IAIE146_Pos (18U)
#define IAC_IER4_IAIE146_Msk (0x1UL << IAC_IER4_IAIE146_Pos) /*!< 0x00040000 */
#define IAC_IER4_IAIE146 IAC_IER4_IAIE146_Msk
#define IAC_IER4_IAIE147_Pos (19U)
#define IAC_IER4_IAIE147_Msk (0x1UL << IAC_IER4_IAIE147_Pos) /*!< 0x00080000 */
#define IAC_IER4_IAIE147 IAC_IER4_IAIE147_Msk
#define IAC_IER4_IAIE149_Pos (21U)
#define IAC_IER4_IAIE149_Msk (0x1UL << IAC_IER4_IAIE149_Pos) /*!< 0x00200000 */
#define IAC_IER4_IAIE149 IAC_IER4_IAIE149_Msk
#define IAC_IER4_IAIE150_Pos (22U)
#define IAC_IER4_IAIE150_Msk (0x1UL << IAC_IER4_IAIE150_Pos) /*!< 0x00400000 */
#define IAC_IER4_IAIE150 IAC_IER4_IAIE150_Msk
#define IAC_IER4_IAIE151_Pos (23U)
#define IAC_IER4_IAIE151_Msk (0x1UL << IAC_IER4_IAIE151_Pos) /*!< 0x00800000 */
#define IAC_IER4_IAIE151 IAC_IER4_IAIE151_Msk
#define IAC_IER4_IAIE152_Pos (24U)
#define IAC_IER4_IAIE152_Msk (0x1UL << IAC_IER4_IAIE152_Pos) /*!< 0x01000000 */
#define IAC_IER4_IAIE152 IAC_IER4_IAIE152_Msk
#define IAC_IER4_IAIE153_Pos (25U)
#define IAC_IER4_IAIE153_Msk (0x1UL << IAC_IER4_IAIE153_Pos) /*!< 0x02000000 */
#define IAC_IER4_IAIE153 IAC_IER4_IAIE153_Msk
#define IAC_IER4_IAIE155_Pos (27U)
#define IAC_IER4_IAIE155_Msk (0x1UL << IAC_IER4_IAIE155_Pos) /*!< 0x08000000 */
#define IAC_IER4_IAIE155 IAC_IER4_IAIE155_Msk
#define IAC_IER4_IAIE156_Pos (28U)
#define IAC_IER4_IAIE156_Msk (0x1UL << IAC_IER4_IAIE156_Pos) /*!< 0x10000000 */
#define IAC_IER4_IAIE156 IAC_IER4_IAIE156_Msk
#define IAC_IER4_IAIE157_Pos (29U)
#define IAC_IER4_IAIE157_Msk (0x1UL << IAC_IER4_IAIE157_Pos) /*!< 0x20000000 */
#define IAC_IER4_IAIE157 IAC_IER4_IAIE157_Msk
/******************* Bits definition for IAC_ISR0 register *******************/
#define IAC_ISR0_IAF0_Pos (0U)
#define IAC_ISR0_IAF0_Msk (0x1UL << IAC_ISR0_IAF0_Pos) /*!< 0x00000001 */
#define IAC_ISR0_IAF0 IAC_ISR0_IAF0_Msk
#define IAC_ISR0_IAF1_Pos (1U)
#define IAC_ISR0_IAF1_Msk (0x1UL << IAC_ISR0_IAF1_Pos) /*!< 0x00000002 */
#define IAC_ISR0_IAF1 IAC_ISR0_IAF1_Msk
#define IAC_ISR0_IAF2_Pos (2U)
#define IAC_ISR0_IAF2_Msk (0x1UL << IAC_ISR0_IAF2_Pos) /*!< 0x00000004 */
#define IAC_ISR0_IAF2 IAC_ISR0_IAF2_Msk
#define IAC_ISR0_IAF3_Pos (3U)
#define IAC_ISR0_IAF3_Msk (0x1UL << IAC_ISR0_IAF3_Pos) /*!< 0x00000008 */
#define IAC_ISR0_IAF3 IAC_ISR0_IAF3_Msk
#define IAC_ISR0_IAF4_Pos (4U)
#define IAC_ISR0_IAF4_Msk (0x1UL << IAC_ISR0_IAF4_Pos) /*!< 0x00000010 */
#define IAC_ISR0_IAF4 IAC_ISR0_IAF4_Msk
#define IAC_ISR0_IAF5_Pos (5U)
#define IAC_ISR0_IAF5_Msk (0x1UL << IAC_ISR0_IAF5_Pos) /*!< 0x00000020 */
#define IAC_ISR0_IAF5 IAC_ISR0_IAF5_Msk
#define IAC_ISR0_IAF6_Pos (6U)
#define IAC_ISR0_IAF6_Msk (0x1UL << IAC_ISR0_IAF6_Pos) /*!< 0x00000040 */
#define IAC_ISR0_IAF6 IAC_ISR0_IAF6_Msk
#define IAC_ISR0_IAF8_Pos (8U)
#define IAC_ISR0_IAF8_Msk (0x1UL << IAC_ISR0_IAF8_Pos) /*!< 0x00000100 */
#define IAC_ISR0_IAF8 IAC_ISR0_IAF8_Msk
#define IAC_ISR0_IAF9_Pos (9U)
#define IAC_ISR0_IAF9_Msk (0x1UL << IAC_ISR0_IAF9_Pos) /*!< 0x00000200 */
#define IAC_ISR0_IAF9 IAC_ISR0_IAF9_Msk
#define IAC_ISR0_IAF10_Pos (10U)
#define IAC_ISR0_IAF10_Msk (0x1UL << IAC_ISR0_IAF10_Pos) /*!< 0x00000400 */
#define IAC_ISR0_IAF10 IAC_ISR0_IAF10_Msk
#define IAC_ISR0_IAF11_Pos (11U)
#define IAC_ISR0_IAF11_Msk (0x1UL << IAC_ISR0_IAF11_Pos) /*!< 0x00000800 */
#define IAC_ISR0_IAF11 IAC_ISR0_IAF11_Msk
#define IAC_ISR0_IAF12_Pos (12U)
#define IAC_ISR0_IAF12_Msk (0x1UL << IAC_ISR0_IAF12_Pos) /*!< 0x00001000 */
#define IAC_ISR0_IAF12 IAC_ISR0_IAF12_Msk
#define IAC_ISR0_IAF13_Pos (13U)
#define IAC_ISR0_IAF13_Msk (0x1UL << IAC_ISR0_IAF13_Pos) /*!< 0x00002000 */
#define IAC_ISR0_IAF13 IAC_ISR0_IAF13_Msk
#define IAC_ISR0_IAF14_Pos (14U)
#define IAC_ISR0_IAF14_Msk (0x1UL << IAC_ISR0_IAF14_Pos) /*!< 0x00004000 */
#define IAC_ISR0_IAF14 IAC_ISR0_IAF14_Msk
#define IAC_ISR0_IAF15_Pos (15U)
#define IAC_ISR0_IAF15_Msk (0x1UL << IAC_ISR0_IAF15_Pos) /*!< 0x00008000 */
#define IAC_ISR0_IAF15 IAC_ISR0_IAF15_Msk
#define IAC_ISR0_IAF16_Pos (16U)
#define IAC_ISR0_IAF16_Msk (0x1UL << IAC_ISR0_IAF16_Pos) /*!< 0x00010000 */
#define IAC_ISR0_IAF16 IAC_ISR0_IAF16_Msk
#define IAC_ISR0_IAF17_Pos (17U)
#define IAC_ISR0_IAF17_Msk (0x1UL << IAC_ISR0_IAF17_Pos) /*!< 0x00020000 */
#define IAC_ISR0_IAF17 IAC_ISR0_IAF17_Msk
#define IAC_ISR0_IAF18_Pos (18U)
#define IAC_ISR0_IAF18_Msk (0x1UL << IAC_ISR0_IAF18_Pos) /*!< 0x00040000 */
#define IAC_ISR0_IAF18 IAC_ISR0_IAF18_Msk
#define IAC_ISR0_IAF19_Pos (19U)
#define IAC_ISR0_IAF19_Msk (0x1UL << IAC_ISR0_IAF19_Pos) /*!< 0x00080000 */
#define IAC_ISR0_IAF19 IAC_ISR0_IAF19_Msk
#define IAC_ISR0_IAF20_Pos (20U)
#define IAC_ISR0_IAF20_Msk (0x1UL << IAC_ISR0_IAF20_Pos) /*!< 0x00100000 */
#define IAC_ISR0_IAF20 IAC_ISR0_IAF20_Msk
#define IAC_ISR0_IAF21_Pos (21U)
#define IAC_ISR0_IAF21_Msk (0x1UL << IAC_ISR0_IAF21_Pos) /*!< 0x00200000 */
#define IAC_ISR0_IAF21 IAC_ISR0_IAF21_Msk
#define IAC_ISR0_IAF22_Pos (22U)
#define IAC_ISR0_IAF22_Msk (0x1UL << IAC_ISR0_IAF22_Pos) /*!< 0x00400000 */
#define IAC_ISR0_IAF22 IAC_ISR0_IAF22_Msk
#define IAC_ISR0_IAF23_Pos (23U)
#define IAC_ISR0_IAF23_Msk (0x1UL << IAC_ISR0_IAF23_Pos) /*!< 0x00800000 */
#define IAC_ISR0_IAF23 IAC_ISR0_IAF23_Msk
#define IAC_ISR0_IAF24_Pos (24U)
#define IAC_ISR0_IAF24_Msk (0x1UL << IAC_ISR0_IAF24_Pos) /*!< 0x01000000 */
#define IAC_ISR0_IAF24 IAC_ISR0_IAF24_Msk
#define IAC_ISR0_IAF25_Pos (25U)
#define IAC_ISR0_IAF25_Msk (0x1UL << IAC_ISR0_IAF25_Pos) /*!< 0x02000000 */
#define IAC_ISR0_IAF25 IAC_ISR0_IAF25_Msk
#define IAC_ISR0_IAF26_Pos (26U)
#define IAC_ISR0_IAF26_Msk (0x1UL << IAC_ISR0_IAF26_Pos) /*!< 0x04000000 */
#define IAC_ISR0_IAF26 IAC_ISR0_IAF26_Msk
#define IAC_ISR0_IAF27_Pos (27U)
#define IAC_ISR0_IAF27_Msk (0x1UL << IAC_ISR0_IAF27_Pos) /*!< 0x08000000 */
#define IAC_ISR0_IAF27 IAC_ISR0_IAF27_Msk
#define IAC_ISR0_IAF28_Pos (28U)
#define IAC_ISR0_IAF28_Msk (0x1UL << IAC_ISR0_IAF28_Pos) /*!< 0x10000000 */
#define IAC_ISR0_IAF28 IAC_ISR0_IAF28_Msk
#define IAC_ISR0_IAF29_Pos (29U)
#define IAC_ISR0_IAF29_Msk (0x1UL << IAC_ISR0_IAF29_Pos) /*!< 0x20000000 */
#define IAC_ISR0_IAF29 IAC_ISR0_IAF29_Msk
#define IAC_ISR0_IAF30_Pos (30U)
#define IAC_ISR0_IAF30_Msk (0x1UL << IAC_ISR0_IAF30_Pos) /*!< 0x40000000 */
#define IAC_ISR0_IAF30 IAC_ISR0_IAF30_Msk
#define IAC_ISR0_IAF31_Pos (31U)
#define IAC_ISR0_IAF31_Msk (0x1UL << IAC_ISR0_IAF31_Pos) /*!< 0x80000000 */
#define IAC_ISR0_IAF31 IAC_ISR0_IAF31_Msk
/******************* Bits definition for IAC_ISR1 register *******************/
#define IAC_ISR1_IAF32_Pos (0U)
#define IAC_ISR1_IAF32_Msk (0x1UL << IAC_ISR1_IAF32_Pos) /*!< 0x00000001 */
#define IAC_ISR1_IAF32 IAC_ISR1_IAF32_Msk
#define IAC_ISR1_IAF33_Pos (1U)
#define IAC_ISR1_IAF33_Msk (0x1UL << IAC_ISR1_IAF33_Pos) /*!< 0x00000002 */
#define IAC_ISR1_IAF33 IAC_ISR1_IAF33_Msk
#define IAC_ISR1_IAF34_Pos (2U)
#define IAC_ISR1_IAF34_Msk (0x1UL << IAC_ISR1_IAF34_Pos) /*!< 0x00000004 */
#define IAC_ISR1_IAF34 IAC_ISR1_IAF34_Msk
#define IAC_ISR1_IAF35_Pos (3U)
#define IAC_ISR1_IAF35_Msk (0x1UL << IAC_ISR1_IAF35_Pos) /*!< 0x00000008 */
#define IAC_ISR1_IAF35 IAC_ISR1_IAF35_Msk
#define IAC_ISR1_IAF36_Pos (4U)
#define IAC_ISR1_IAF36_Msk (0x1UL << IAC_ISR1_IAF36_Pos) /*!< 0x00000010 */
#define IAC_ISR1_IAF36 IAC_ISR1_IAF36_Msk
#define IAC_ISR1_IAF37_Pos (5U)
#define IAC_ISR1_IAF37_Msk (0x1UL << IAC_ISR1_IAF37_Pos) /*!< 0x00000020 */
#define IAC_ISR1_IAF37 IAC_ISR1_IAF37_Msk
#define IAC_ISR1_IAF38_Pos (6U)
#define IAC_ISR1_IAF38_Msk (0x1UL << IAC_ISR1_IAF38_Pos) /*!< 0x00000040 */
#define IAC_ISR1_IAF38 IAC_ISR1_IAF38_Msk
#define IAC_ISR1_IAF39_Pos (7U)
#define IAC_ISR1_IAF39_Msk (0x1UL << IAC_ISR1_IAF39_Pos) /*!< 0x00000080 */
#define IAC_ISR1_IAF39 IAC_ISR1_IAF39_Msk
#define IAC_ISR1_IAF40_Pos (8U)
#define IAC_ISR1_IAF40_Msk (0x1UL << IAC_ISR1_IAF40_Pos) /*!< 0x00000100 */
#define IAC_ISR1_IAF40 IAC_ISR1_IAF40_Msk
#define IAC_ISR1_IAF41_Pos (9U)
#define IAC_ISR1_IAF41_Msk (0x1UL << IAC_ISR1_IAF41_Pos) /*!< 0x00000200 */
#define IAC_ISR1_IAF41 IAC_ISR1_IAF41_Msk
#define IAC_ISR1_IAF42_Pos (10U)
#define IAC_ISR1_IAF42_Msk (0x1UL << IAC_ISR1_IAF42_Pos) /*!< 0x00000400 */
#define IAC_ISR1_IAF42 IAC_ISR1_IAF42_Msk
#define IAC_ISR1_IAF43_Pos (11U)
#define IAC_ISR1_IAF43_Msk (0x1UL << IAC_ISR1_IAF43_Pos) /*!< 0x00000800 */
#define IAC_ISR1_IAF43 IAC_ISR1_IAF43_Msk
#define IAC_ISR1_IAF44_Pos (12U)
#define IAC_ISR1_IAF44_Msk (0x1UL << IAC_ISR1_IAF44_Pos) /*!< 0x00001000 */
#define IAC_ISR1_IAF44 IAC_ISR1_IAF44_Msk
#define IAC_ISR1_IAF45_Pos (13U)
#define IAC_ISR1_IAF45_Msk (0x1UL << IAC_ISR1_IAF45_Pos) /*!< 0x00002000 */
#define IAC_ISR1_IAF45 IAC_ISR1_IAF45_Msk
#define IAC_ISR1_IAF46_Pos (14U)
#define IAC_ISR1_IAF46_Msk (0x1UL << IAC_ISR1_IAF46_Pos) /*!< 0x00004000 */
#define IAC_ISR1_IAF46 IAC_ISR1_IAF46_Msk
#define IAC_ISR1_IAF47_Pos (15U)
#define IAC_ISR1_IAF47_Msk (0x1UL << IAC_ISR1_IAF47_Pos) /*!< 0x00008000 */
#define IAC_ISR1_IAF47 IAC_ISR1_IAF47_Msk
#define IAC_ISR1_IAF48_Pos (16U)
#define IAC_ISR1_IAF48_Msk (0x1UL << IAC_ISR1_IAF48_Pos) /*!< 0x00010000 */
#define IAC_ISR1_IAF48 IAC_ISR1_IAF48_Msk
#define IAC_ISR1_IAF49_Pos (17U)
#define IAC_ISR1_IAF49_Msk (0x1UL << IAC_ISR1_IAF49_Pos) /*!< 0x00020000 */
#define IAC_ISR1_IAF49 IAC_ISR1_IAF49_Msk
#define IAC_ISR1_IAF50_Pos (18U)
#define IAC_ISR1_IAF50_Msk (0x1UL << IAC_ISR1_IAF50_Pos) /*!< 0x00040000 */
#define IAC_ISR1_IAF50 IAC_ISR1_IAF50_Msk
#define IAC_ISR1_IAF51_Pos (19U)
#define IAC_ISR1_IAF51_Msk (0x1UL << IAC_ISR1_IAF51_Pos) /*!< 0x00080000 */
#define IAC_ISR1_IAF51 IAC_ISR1_IAF51_Msk
#define IAC_ISR1_IAF52_Pos (20U)
#define IAC_ISR1_IAF52_Msk (0x1UL << IAC_ISR1_IAF52_Pos) /*!< 0x00100000 */
#define IAC_ISR1_IAF52 IAC_ISR1_IAF52_Msk
#define IAC_ISR1_IAF53_Pos (21U)
#define IAC_ISR1_IAF53_Msk (0x1UL << IAC_ISR1_IAF53_Pos) /*!< 0x00200000 */
#define IAC_ISR1_IAF53 IAC_ISR1_IAF53_Msk
#define IAC_ISR1_IAF54_Pos (22U)
#define IAC_ISR1_IAF54_Msk (0x1UL << IAC_ISR1_IAF54_Pos) /*!< 0x00400000 */
#define IAC_ISR1_IAF54 IAC_ISR1_IAF54_Msk
#define IAC_ISR1_IAF55_Pos (23U)
#define IAC_ISR1_IAF55_Msk (0x1UL << IAC_ISR1_IAF55_Pos) /*!< 0x00800000 */
#define IAC_ISR1_IAF55 IAC_ISR1_IAF55_Msk
#define IAC_ISR1_IAF56_Pos (24U)
#define IAC_ISR1_IAF56_Msk (0x1UL << IAC_ISR1_IAF56_Pos) /*!< 0x01000000 */
#define IAC_ISR1_IAF56 IAC_ISR1_IAF56_Msk
#define IAC_ISR1_IAF57_Pos (25U)
#define IAC_ISR1_IAF57_Msk (0x1UL << IAC_ISR1_IAF57_Pos) /*!< 0x02000000 */
#define IAC_ISR1_IAF57 IAC_ISR1_IAF57_Msk
#define IAC_ISR1_IAF58_Pos (26U)
#define IAC_ISR1_IAF58_Msk (0x1UL << IAC_ISR1_IAF58_Pos) /*!< 0x04000000 */
#define IAC_ISR1_IAF58 IAC_ISR1_IAF58_Msk
#define IAC_ISR1_IAF60_Pos (28U)
#define IAC_ISR1_IAF60_Msk (0x1UL << IAC_ISR1_IAF60_Pos) /*!< 0x10000000 */
#define IAC_ISR1_IAF60 IAC_ISR1_IAF60_Msk
#define IAC_ISR1_IAF61_Pos (29U)
#define IAC_ISR1_IAF61_Msk (0x1UL << IAC_ISR1_IAF61_Pos) /*!< 0x20000000 */
#define IAC_ISR1_IAF61 IAC_ISR1_IAF61_Msk
#define IAC_ISR1_IAF62_Pos (30U)
#define IAC_ISR1_IAF62_Msk (0x1UL << IAC_ISR1_IAF62_Pos) /*!< 0x40000000 */
#define IAC_ISR1_IAF62 IAC_ISR1_IAF62_Msk
/******************* Bits definition for IAC_ISR2 register *******************/
#define IAC_ISR2_IAF64_Pos (0U)
#define IAC_ISR2_IAF64_Msk (0x1UL << IAC_ISR2_IAF64_Pos) /*!< 0x00000001 */
#define IAC_ISR2_IAF64 IAC_ISR2_IAF64_Msk
#define IAC_ISR2_IAF65_Pos (1U)
#define IAC_ISR2_IAF65_Msk (0x1UL << IAC_ISR2_IAF65_Pos) /*!< 0x00000002 */
#define IAC_ISR2_IAF65 IAC_ISR2_IAF65_Msk
#define IAC_ISR2_IAF67_Pos (3U)
#define IAC_ISR2_IAF67_Msk (0x1UL << IAC_ISR2_IAF67_Pos) /*!< 0x00000008 */
#define IAC_ISR2_IAF67 IAC_ISR2_IAF67_Msk
#define IAC_ISR2_IAF68_Pos (4U)
#define IAC_ISR2_IAF68_Msk (0x1UL << IAC_ISR2_IAF68_Pos) /*!< 0x00000010 */
#define IAC_ISR2_IAF68 IAC_ISR2_IAF68_Msk
#define IAC_ISR2_IAF69_Pos (5U)
#define IAC_ISR2_IAF69_Msk (0x1UL << IAC_ISR2_IAF69_Pos) /*!< 0x00000020 */
#define IAC_ISR2_IAF69 IAC_ISR2_IAF69_Msk
#define IAC_ISR2_IAF76_Pos (12U)
#define IAC_ISR2_IAF76_Msk (0x1UL << IAC_ISR2_IAF76_Pos) /*!< 0x00001000 */
#define IAC_ISR2_IAF76 IAC_ISR2_IAF76_Msk
#define IAC_ISR2_IAF77_Pos (13U)
#define IAC_ISR2_IAF77_Msk (0x1UL << IAC_ISR2_IAF77_Pos) /*!< 0x00002000 */
#define IAC_ISR2_IAF77 IAC_ISR2_IAF77_Msk
#define IAC_ISR2_IAF78_Pos (14U)
#define IAC_ISR2_IAF78_Msk (0x1UL << IAC_ISR2_IAF78_Pos) /*!< 0x00004000 */
#define IAC_ISR2_IAF78 IAC_ISR2_IAF78_Msk
#define IAC_ISR2_IAF79_Pos (15U)
#define IAC_ISR2_IAF79_Msk (0x1UL << IAC_ISR2_IAF79_Pos) /*!< 0x00008000 */
#define IAC_ISR2_IAF79 IAC_ISR2_IAF79_Msk
#define IAC_ISR2_IAF80_Pos (16U)
#define IAC_ISR2_IAF80_Msk (0x1UL << IAC_ISR2_IAF80_Pos) /*!< 0x00010000 */
#define IAC_ISR2_IAF80 IAC_ISR2_IAF80_Msk
#define IAC_ISR2_IAF81_Pos (17U)
#define IAC_ISR2_IAF81_Msk (0x1UL << IAC_ISR2_IAF81_Pos) /*!< 0x00020000 */
#define IAC_ISR2_IAF81 IAC_ISR2_IAF81_Msk
#define IAC_ISR2_IAF82_Pos (18U)
#define IAC_ISR2_IAF82_Msk (0x1UL << IAC_ISR2_IAF82_Pos) /*!< 0x00040000 */
#define IAC_ISR2_IAF82 IAC_ISR2_IAF82_Msk
#define IAC_ISR2_IAF83_Pos (19U)
#define IAC_ISR2_IAF83_Msk (0x1UL << IAC_ISR2_IAF83_Pos) /*!< 0x00080000 */
#define IAC_ISR2_IAF83 IAC_ISR2_IAF83_Msk
#define IAC_ISR2_IAF84_Pos (20U)
#define IAC_ISR2_IAF84_Msk (0x1UL << IAC_ISR2_IAF84_Pos) /*!< 0x00100000 */
#define IAC_ISR2_IAF84 IAC_ISR2_IAF84_Msk
#define IAC_ISR2_IAF86_Pos (22U)
#define IAC_ISR2_IAF86_Msk (0x1UL << IAC_ISR2_IAF86_Pos) /*!< 0x00400000 */
#define IAC_ISR2_IAF86 IAC_ISR2_IAF86_Msk
#define IAC_ISR2_IAF87_Pos (23U)
#define IAC_ISR2_IAF87_Msk (0x1UL << IAC_ISR2_IAF87_Pos) /*!< 0x00800000 */
#define IAC_ISR2_IAF87 IAC_ISR2_IAF87_Msk
#define IAC_ISR2_IAF88_Pos (24U)
#define IAC_ISR2_IAF88_Msk (0x1UL << IAC_ISR2_IAF88_Pos) /*!< 0x01000000 */
#define IAC_ISR2_IAF88 IAC_ISR2_IAF88_Msk
#define IAC_ISR2_IAF89_Pos (25U)
#define IAC_ISR2_IAF89_Msk (0x1UL << IAC_ISR2_IAF89_Pos) /*!< 0x02000000 */
#define IAC_ISR2_IAF89 IAC_ISR2_IAF89_Msk
#define IAC_ISR2_IAF90_Pos (26U)
#define IAC_ISR2_IAF90_Msk (0x1UL << IAC_ISR2_IAF90_Pos) /*!< 0x04000000 */
#define IAC_ISR2_IAF90 IAC_ISR2_IAF90_Msk
#define IAC_ISR2_IAF92_Pos (28U)
#define IAC_ISR2_IAF92_Msk (0x1UL << IAC_ISR2_IAF92_Pos) /*!< 0x10000000 */
#define IAC_ISR2_IAF92 IAC_ISR2_IAF92_Msk
#define IAC_ISR2_IAF93_Pos (29U)
#define IAC_ISR2_IAF93_Msk (0x1UL << IAC_ISR2_IAF93_Pos) /*!< 0x20000000 */
#define IAC_ISR2_IAF93 IAC_ISR2_IAF93_Msk
#define IAC_ISR2_IAF94_Pos (30U)
#define IAC_ISR2_IAF94_Msk (0x1UL << IAC_ISR2_IAF94_Pos) /*!< 0x40000000 */
#define IAC_ISR2_IAF94 IAC_ISR2_IAF94_Msk
#define IAC_ISR2_IAF95_Pos (31U)
#define IAC_ISR2_IAF95_Msk (0x1UL << IAC_ISR2_IAF95_Pos) /*!< 0x80000000 */
#define IAC_ISR2_IAF95 IAC_ISR2_IAF95_Msk
/******************* Bits definition for IAC_ISR3 register *******************/
#define IAC_ISR3_IAF96_Pos (0U)
#define IAC_ISR3_IAF96_Msk (0x1UL << IAC_ISR3_IAF96_Pos) /*!< 0x00000001 */
#define IAC_ISR3_IAF96 IAC_ISR3_IAF96_Msk
#define IAC_ISR3_IAF97_Pos (1U)
#define IAC_ISR3_IAF97_Msk (0x1UL << IAC_ISR3_IAF97_Pos) /*!< 0x00000002 */
#define IAC_ISR3_IAF97 IAC_ISR3_IAF97_Msk
#define IAC_ISR3_IAF98_Pos (2U)
#define IAC_ISR3_IAF98_Msk (0x1UL << IAC_ISR3_IAF98_Pos) /*!< 0x00000004 */
#define IAC_ISR3_IAF98 IAC_ISR3_IAF98_Msk
#define IAC_ISR3_IAF99_Pos (3U)
#define IAC_ISR3_IAF99_Msk (0x1UL << IAC_ISR3_IAF99_Pos) /*!< 0x00000008 */
#define IAC_ISR3_IAF99 IAC_ISR3_IAF99_Msk
#define IAC_ISR3_IAF100_Pos (4U)
#define IAC_ISR3_IAF100_Msk (0x1UL << IAC_ISR3_IAF100_Pos) /*!< 0x00000010 */
#define IAC_ISR3_IAF100 IAC_ISR3_IAF100_Msk
#define IAC_ISR3_IAF101_Pos (5U)
#define IAC_ISR3_IAF101_Msk (0x1UL << IAC_ISR3_IAF101_Pos) /*!< 0x00000020 */
#define IAC_ISR3_IAF101 IAC_ISR3_IAF101_Msk
#define IAC_ISR3_IAF102_Pos (6U)
#define IAC_ISR3_IAF102_Msk (0x1UL << IAC_ISR3_IAF102_Pos) /*!< 0x00000040 */
#define IAC_ISR3_IAF102 IAC_ISR3_IAF102_Msk
#define IAC_ISR3_IAF103_Pos (7U)
#define IAC_ISR3_IAF103_Msk (0x1UL << IAC_ISR3_IAF103_Pos) /*!< 0x00000080 */
#define IAC_ISR3_IAF103 IAC_ISR3_IAF103_Msk
#define IAC_ISR3_IAF104_Pos (8U)
#define IAC_ISR3_IAF104_Msk (0x1UL << IAC_ISR3_IAF104_Pos) /*!< 0x00000100 */
#define IAC_ISR3_IAF104 IAC_ISR3_IAF104_Msk
#define IAC_ISR3_IAF106_Pos (10U)
#define IAC_ISR3_IAF106_Msk (0x1UL << IAC_ISR3_IAF106_Pos) /*!< 0x00000400 */
#define IAC_ISR3_IAF106 IAC_ISR3_IAF106_Msk
/******************* Bits definition for IAC_ISR4 register *******************/
#define IAC_ISR4_IAF128_Pos (0U)
#define IAC_ISR4_IAF128_Msk (0x1UL << IAC_ISR4_IAF128_Pos) /*!< 0x00000001 */
#define IAC_ISR4_IAF128 IAC_ISR4_IAF128_Msk
#define IAC_ISR4_IAF129_Pos (1U)
#define IAC_ISR4_IAF129_Msk (0x1UL << IAC_ISR4_IAF129_Pos) /*!< 0x00000002 */
#define IAC_ISR4_IAF129 IAC_ISR4_IAF129_Msk
#define IAC_ISR4_IAF130_Pos (2U)
#define IAC_ISR4_IAF130_Msk (0x1UL << IAC_ISR4_IAF130_Pos) /*!< 0x00000004 */
#define IAC_ISR4_IAF130 IAC_ISR4_IAF130_Msk
#define IAC_ISR4_IAF131_Pos (3U)
#define IAC_ISR4_IAF131_Msk (0x1UL << IAC_ISR4_IAF131_Pos) /*!< 0x00000008 */
#define IAC_ISR4_IAF131 IAC_ISR4_IAF131_Msk
#define IAC_ISR4_IAF133_Pos (5U)
#define IAC_ISR4_IAF133_Msk (0x1UL << IAC_ISR4_IAF133_Pos) /*!< 0x00000020 */
#define IAC_ISR4_IAF133 IAC_ISR4_IAF133_Msk
#define IAC_ISR4_IAF134_Pos (6U)
#define IAC_ISR4_IAF134_Msk (0x1UL << IAC_ISR4_IAF134_Pos) /*!< 0x00000040 */
#define IAC_ISR4_IAF134 IAC_ISR4_IAF134_Msk
#define IAC_ISR4_IAF135_Pos (7U)
#define IAC_ISR4_IAF135_Msk (0x1UL << IAC_ISR4_IAF135_Pos) /*!< 0x00000080 */
#define IAC_ISR4_IAF135 IAC_ISR4_IAF135_Msk
#define IAC_ISR4_IAF136_Pos (8U)
#define IAC_ISR4_IAF136_Msk (0x1UL << IAC_ISR4_IAF136_Pos) /*!< 0x00000100 */
#define IAC_ISR4_IAF136 IAC_ISR4_IAF136_Msk
#define IAC_ISR4_IAF137_Pos (9U)
#define IAC_ISR4_IAF137_Msk (0x1UL << IAC_ISR4_IAF137_Pos) /*!< 0x00000200 */
#define IAC_ISR4_IAF137 IAC_ISR4_IAF137_Msk
#define IAC_ISR4_IAF138_Pos (10U)
#define IAC_ISR4_IAF138_Msk (0x1UL << IAC_ISR4_IAF138_Pos) /*!< 0x00000400 */
#define IAC_ISR4_IAF138 IAC_ISR4_IAF138_Msk
#define IAC_ISR4_IAF139_Pos (11U)
#define IAC_ISR4_IAF139_Msk (0x1UL << IAC_ISR4_IAF139_Pos) /*!< 0x00000800 */
#define IAC_ISR4_IAF139 IAC_ISR4_IAF139_Msk
#define IAC_ISR4_IAF140_Pos (12U)
#define IAC_ISR4_IAF140_Msk (0x1UL << IAC_ISR4_IAF140_Pos) /*!< 0x00001000 */
#define IAC_ISR4_IAF140 IAC_ISR4_IAF140_Msk
#define IAC_ISR4_IAF141_Pos (13U)
#define IAC_ISR4_IAF141_Msk (0x1UL << IAC_ISR4_IAF141_Pos) /*!< 0x00002000 */
#define IAC_ISR4_IAF141 IAC_ISR4_IAF141_Msk
#define IAC_ISR4_IAF142_Pos (14U)
#define IAC_ISR4_IAF142_Msk (0x1UL << IAC_ISR4_IAF142_Pos) /*!< 0x00004000 */
#define IAC_ISR4_IAF142 IAC_ISR4_IAF142_Msk
#define IAC_ISR4_IAF143_Pos (15U)
#define IAC_ISR4_IAF143_Msk (0x1UL << IAC_ISR4_IAF143_Pos) /*!< 0x00008000 */
#define IAC_ISR4_IAF143 IAC_ISR4_IAF143_Msk
#define IAC_ISR4_IAF144_Pos (16U)
#define IAC_ISR4_IAF144_Msk (0x1UL << IAC_ISR4_IAF144_Pos) /*!< 0x00010000 */
#define IAC_ISR4_IAF144 IAC_ISR4_IAF144_Msk
#define IAC_ISR4_IAF145_Pos (17U)
#define IAC_ISR4_IAF145_Msk (0x1UL << IAC_ISR4_IAF145_Pos) /*!< 0x00020000 */
#define IAC_ISR4_IAF145 IAC_ISR4_IAF145_Msk
#define IAC_ISR4_IAF146_Pos (18U)
#define IAC_ISR4_IAF146_Msk (0x1UL << IAC_ISR4_IAF146_Pos) /*!< 0x00040000 */
#define IAC_ISR4_IAF146 IAC_ISR4_IAF146_Msk
#define IAC_ISR4_IAF147_Pos (19U)
#define IAC_ISR4_IAF147_Msk (0x1UL << IAC_ISR4_IAF147_Pos) /*!< 0x00080000 */
#define IAC_ISR4_IAF147 IAC_ISR4_IAF147_Msk
#define IAC_ISR4_IAF149_Pos (21U)
#define IAC_ISR4_IAF149_Msk (0x1UL << IAC_ISR4_IAF149_Pos) /*!< 0x00200000 */
#define IAC_ISR4_IAF149 IAC_ISR4_IAF149_Msk
#define IAC_ISR4_IAF150_Pos (22U)
#define IAC_ISR4_IAF150_Msk (0x1UL << IAC_ISR4_IAF150_Pos) /*!< 0x00400000 */
#define IAC_ISR4_IAF150 IAC_ISR4_IAF150_Msk
#define IAC_ISR4_IAF151_Pos (23U)
#define IAC_ISR4_IAF151_Msk (0x1UL << IAC_ISR4_IAF151_Pos) /*!< 0x00800000 */
#define IAC_ISR4_IAF151 IAC_ISR4_IAF151_Msk
#define IAC_ISR4_IAF152_Pos (24U)
#define IAC_ISR4_IAF152_Msk (0x1UL << IAC_ISR4_IAF152_Pos) /*!< 0x01000000 */
#define IAC_ISR4_IAF152 IAC_ISR4_IAF152_Msk
#define IAC_ISR4_IAF153_Pos (25U)
#define IAC_ISR4_IAF153_Msk (0x1UL << IAC_ISR4_IAF153_Pos) /*!< 0x02000000 */
#define IAC_ISR4_IAF153 IAC_ISR4_IAF153_Msk
#define IAC_ISR4_IAF155_Pos (27U)
#define IAC_ISR4_IAF155_Msk (0x1UL << IAC_ISR4_IAF155_Pos) /*!< 0x08000000 */
#define IAC_ISR4_IAF155 IAC_ISR4_IAF155_Msk
#define IAC_ISR4_IAF156_Pos (28U)
#define IAC_ISR4_IAF156_Msk (0x1UL << IAC_ISR4_IAF156_Pos) /*!< 0x10000000 */
#define IAC_ISR4_IAF156 IAC_ISR4_IAF156_Msk
#define IAC_ISR4_IAF157_Pos (29U)
#define IAC_ISR4_IAF157_Msk (0x1UL << IAC_ISR4_IAF157_Pos) /*!< 0x20000000 */
#define IAC_ISR4_IAF157 IAC_ISR4_IAF157_Msk
/******************* Bits definition for IAC_ICR0 register *******************/
#define IAC_ICR0_IACF0_Pos (0U)
#define IAC_ICR0_IACF0_Msk (0x1UL << IAC_ICR0_IACF0_Pos) /*!< 0x00000001 */
#define IAC_ICR0_IACF0 IAC_ICR0_IACF0_Msk
#define IAC_ICR0_IACF1_Pos (1U)
#define IAC_ICR0_IACF1_Msk (0x1UL << IAC_ICR0_IACF1_Pos) /*!< 0x00000002 */
#define IAC_ICR0_IACF1 IAC_ICR0_IACF1_Msk
#define IAC_ICR0_IACF2_Pos (2U)
#define IAC_ICR0_IACF2_Msk (0x1UL << IAC_ICR0_IACF2_Pos) /*!< 0x00000004 */
#define IAC_ICR0_IACF2 IAC_ICR0_IACF2_Msk
#define IAC_ICR0_IACF3_Pos (3U)
#define IAC_ICR0_IACF3_Msk (0x1UL << IAC_ICR0_IACF3_Pos) /*!< 0x00000008 */
#define IAC_ICR0_IACF3 IAC_ICR0_IACF3_Msk
#define IAC_ICR0_IACF4_Pos (4U)
#define IAC_ICR0_IACF4_Msk (0x1UL << IAC_ICR0_IACF4_Pos) /*!< 0x00000010 */
#define IAC_ICR0_IACF4 IAC_ICR0_IACF4_Msk
#define IAC_ICR0_IACF5_Pos (5U)
#define IAC_ICR0_IACF5_Msk (0x1UL << IAC_ICR0_IACF5_Pos) /*!< 0x00000020 */
#define IAC_ICR0_IACF5 IAC_ICR0_IACF5_Msk
#define IAC_ICR0_IACF6_Pos (6U)
#define IAC_ICR0_IACF6_Msk (0x1UL << IAC_ICR0_IACF6_Pos) /*!< 0x00000040 */
#define IAC_ICR0_IACF6 IAC_ICR0_IACF6_Msk
#define IAC_ICR0_IACF8_Pos (8U)
#define IAC_ICR0_IACF8_Msk (0x1UL << IAC_ICR0_IACF8_Pos) /*!< 0x00000100 */
#define IAC_ICR0_IACF8 IAC_ICR0_IACF8_Msk
#define IAC_ICR0_IACF9_Pos (9U)
#define IAC_ICR0_IACF9_Msk (0x1UL << IAC_ICR0_IACF9_Pos) /*!< 0x00000200 */
#define IAC_ICR0_IACF9 IAC_ICR0_IACF9_Msk
#define IAC_ICR0_IACF10_Pos (10U)
#define IAC_ICR0_IACF10_Msk (0x1UL << IAC_ICR0_IACF10_Pos) /*!< 0x00000400 */
#define IAC_ICR0_IACF10 IAC_ICR0_IACF10_Msk
#define IAC_ICR0_IACF11_Pos (11U)
#define IAC_ICR0_IACF11_Msk (0x1UL << IAC_ICR0_IACF11_Pos) /*!< 0x00000800 */
#define IAC_ICR0_IACF11 IAC_ICR0_IACF11_Msk
#define IAC_ICR0_IACF12_Pos (12U)
#define IAC_ICR0_IACF12_Msk (0x1UL << IAC_ICR0_IACF12_Pos) /*!< 0x00001000 */
#define IAC_ICR0_IACF12 IAC_ICR0_IACF12_Msk
#define IAC_ICR0_IACF13_Pos (13U)
#define IAC_ICR0_IACF13_Msk (0x1UL << IAC_ICR0_IACF13_Pos) /*!< 0x00002000 */
#define IAC_ICR0_IACF13 IAC_ICR0_IACF13_Msk
#define IAC_ICR0_IACF14_Pos (14U)
#define IAC_ICR0_IACF14_Msk (0x1UL << IAC_ICR0_IACF14_Pos) /*!< 0x00004000 */
#define IAC_ICR0_IACF14 IAC_ICR0_IACF14_Msk
#define IAC_ICR0_IACF15_Pos (15U)
#define IAC_ICR0_IACF15_Msk (0x1UL << IAC_ICR0_IACF15_Pos) /*!< 0x00008000 */
#define IAC_ICR0_IACF15 IAC_ICR0_IACF15_Msk
#define IAC_ICR0_IACF16_Pos (16U)
#define IAC_ICR0_IACF16_Msk (0x1UL << IAC_ICR0_IACF16_Pos) /*!< 0x00010000 */
#define IAC_ICR0_IACF16 IAC_ICR0_IACF16_Msk
#define IAC_ICR0_IACF17_Pos (17U)
#define IAC_ICR0_IACF17_Msk (0x1UL << IAC_ICR0_IACF17_Pos) /*!< 0x00020000 */
#define IAC_ICR0_IACF17 IAC_ICR0_IACF17_Msk
#define IAC_ICR0_IACF18_Pos (18U)
#define IAC_ICR0_IACF18_Msk (0x1UL << IAC_ICR0_IACF18_Pos) /*!< 0x00040000 */
#define IAC_ICR0_IACF18 IAC_ICR0_IACF18_Msk
#define IAC_ICR0_IACF19_Pos (19U)
#define IAC_ICR0_IACF19_Msk (0x1UL << IAC_ICR0_IACF19_Pos) /*!< 0x00080000 */
#define IAC_ICR0_IACF19 IAC_ICR0_IACF19_Msk
#define IAC_ICR0_IACF20_Pos (20U)
#define IAC_ICR0_IACF20_Msk (0x1UL << IAC_ICR0_IACF20_Pos) /*!< 0x00100000 */
#define IAC_ICR0_IACF20 IAC_ICR0_IACF20_Msk
#define IAC_ICR0_IACF21_Pos (21U)
#define IAC_ICR0_IACF21_Msk (0x1UL << IAC_ICR0_IACF21_Pos) /*!< 0x00200000 */
#define IAC_ICR0_IACF21 IAC_ICR0_IACF21_Msk
#define IAC_ICR0_IACF22_Pos (22U)
#define IAC_ICR0_IACF22_Msk (0x1UL << IAC_ICR0_IACF22_Pos) /*!< 0x00400000 */
#define IAC_ICR0_IACF22 IAC_ICR0_IACF22_Msk
#define IAC_ICR0_IACF23_Pos (23U)
#define IAC_ICR0_IACF23_Msk (0x1UL << IAC_ICR0_IACF23_Pos) /*!< 0x00800000 */
#define IAC_ICR0_IACF23 IAC_ICR0_IACF23_Msk
#define IAC_ICR0_IACF24_Pos (24U)
#define IAC_ICR0_IACF24_Msk (0x1UL << IAC_ICR0_IACF24_Pos) /*!< 0x01000000 */
#define IAC_ICR0_IACF24 IAC_ICR0_IACF24_Msk
#define IAC_ICR0_IACF25_Pos (25U)
#define IAC_ICR0_IACF25_Msk (0x1UL << IAC_ICR0_IACF25_Pos) /*!< 0x02000000 */
#define IAC_ICR0_IACF25 IAC_ICR0_IACF25_Msk
#define IAC_ICR0_IACF26_Pos (26U)
#define IAC_ICR0_IACF26_Msk (0x1UL << IAC_ICR0_IACF26_Pos) /*!< 0x04000000 */
#define IAC_ICR0_IACF26 IAC_ICR0_IACF26_Msk
#define IAC_ICR0_IACF27_Pos (27U)
#define IAC_ICR0_IACF27_Msk (0x1UL << IAC_ICR0_IACF27_Pos) /*!< 0x08000000 */
#define IAC_ICR0_IACF27 IAC_ICR0_IACF27_Msk
#define IAC_ICR0_IACF28_Pos (28U)
#define IAC_ICR0_IACF28_Msk (0x1UL << IAC_ICR0_IACF28_Pos) /*!< 0x10000000 */
#define IAC_ICR0_IACF28 IAC_ICR0_IACF28_Msk
#define IAC_ICR0_IACF29_Pos (29U)
#define IAC_ICR0_IACF29_Msk (0x1UL << IAC_ICR0_IACF29_Pos) /*!< 0x20000000 */
#define IAC_ICR0_IACF29 IAC_ICR0_IACF29_Msk
#define IAC_ICR0_IACF30_Pos (30U)
#define IAC_ICR0_IACF30_Msk (0x1UL << IAC_ICR0_IACF30_Pos) /*!< 0x40000000 */
#define IAC_ICR0_IACF30 IAC_ICR0_IACF30_Msk
#define IAC_ICR0_IACF31_Pos (31U)
#define IAC_ICR0_IACF31_Msk (0x1UL << IAC_ICR0_IACF31_Pos) /*!< 0x80000000 */
#define IAC_ICR0_IACF31 IAC_ICR0_IACF31_Msk
/******************* Bits definition for IAC_ICR1 register *******************/
#define IAC_ICR1_IACF32_Pos (0U)
#define IAC_ICR1_IACF32_Msk (0x1UL << IAC_ICR1_IACF32_Pos) /*!< 0x00000001 */
#define IAC_ICR1_IACF32 IAC_ICR1_IACF32_Msk
#define IAC_ICR1_IACF33_Pos (1U)
#define IAC_ICR1_IACF33_Msk (0x1UL << IAC_ICR1_IACF33_Pos) /*!< 0x00000002 */
#define IAC_ICR1_IACF33 IAC_ICR1_IACF33_Msk
#define IAC_ICR1_IACF34_Pos (2U)
#define IAC_ICR1_IACF34_Msk (0x1UL << IAC_ICR1_IACF34_Pos) /*!< 0x00000004 */
#define IAC_ICR1_IACF34 IAC_ICR1_IACF34_Msk
#define IAC_ICR1_IACF35_Pos (3U)
#define IAC_ICR1_IACF35_Msk (0x1UL << IAC_ICR1_IACF35_Pos) /*!< 0x00000008 */
#define IAC_ICR1_IACF35 IAC_ICR1_IACF35_Msk
#define IAC_ICR1_IACF36_Pos (4U)
#define IAC_ICR1_IACF36_Msk (0x1UL << IAC_ICR1_IACF36_Pos) /*!< 0x00000010 */
#define IAC_ICR1_IACF36 IAC_ICR1_IACF36_Msk
#define IAC_ICR1_IACF37_Pos (5U)
#define IAC_ICR1_IACF37_Msk (0x1UL << IAC_ICR1_IACF37_Pos) /*!< 0x00000020 */
#define IAC_ICR1_IACF37 IAC_ICR1_IACF37_Msk
#define IAC_ICR1_IACF38_Pos (6U)
#define IAC_ICR1_IACF38_Msk (0x1UL << IAC_ICR1_IACF38_Pos) /*!< 0x00000040 */
#define IAC_ICR1_IACF38 IAC_ICR1_IACF38_Msk
#define IAC_ICR1_IACF39_Pos (7U)
#define IAC_ICR1_IACF39_Msk (0x1UL << IAC_ICR1_IACF39_Pos) /*!< 0x00000080 */
#define IAC_ICR1_IACF39 IAC_ICR1_IACF39_Msk
#define IAC_ICR1_IACF40_Pos (8U)
#define IAC_ICR1_IACF40_Msk (0x1UL << IAC_ICR1_IACF40_Pos) /*!< 0x00000100 */
#define IAC_ICR1_IACF40 IAC_ICR1_IACF40_Msk
#define IAC_ICR1_IACF41_Pos (9U)
#define IAC_ICR1_IACF41_Msk (0x1UL << IAC_ICR1_IACF41_Pos) /*!< 0x00000200 */
#define IAC_ICR1_IACF41 IAC_ICR1_IACF41_Msk
#define IAC_ICR1_IACF42_Pos (10U)
#define IAC_ICR1_IACF42_Msk (0x1UL << IAC_ICR1_IACF42_Pos) /*!< 0x00000400 */
#define IAC_ICR1_IACF42 IAC_ICR1_IACF42_Msk
#define IAC_ICR1_IACF43_Pos (11U)
#define IAC_ICR1_IACF43_Msk (0x1UL << IAC_ICR1_IACF43_Pos) /*!< 0x00000800 */
#define IAC_ICR1_IACF43 IAC_ICR1_IACF43_Msk
#define IAC_ICR1_IACF44_Pos (12U)
#define IAC_ICR1_IACF44_Msk (0x1UL << IAC_ICR1_IACF44_Pos) /*!< 0x00001000 */
#define IAC_ICR1_IACF44 IAC_ICR1_IACF44_Msk
#define IAC_ICR1_IACF45_Pos (13U)
#define IAC_ICR1_IACF45_Msk (0x1UL << IAC_ICR1_IACF45_Pos) /*!< 0x00002000 */
#define IAC_ICR1_IACF45 IAC_ICR1_IACF45_Msk
#define IAC_ICR1_IACF46_Pos (14U)
#define IAC_ICR1_IACF46_Msk (0x1UL << IAC_ICR1_IACF46_Pos) /*!< 0x00004000 */
#define IAC_ICR1_IACF46 IAC_ICR1_IACF46_Msk
#define IAC_ICR1_IACF47_Pos (15U)
#define IAC_ICR1_IACF47_Msk (0x1UL << IAC_ICR1_IACF47_Pos) /*!< 0x00008000 */
#define IAC_ICR1_IACF47 IAC_ICR1_IACF47_Msk
#define IAC_ICR1_IACF48_Pos (16U)
#define IAC_ICR1_IACF48_Msk (0x1UL << IAC_ICR1_IACF48_Pos) /*!< 0x00010000 */
#define IAC_ICR1_IACF48 IAC_ICR1_IACF48_Msk
#define IAC_ICR1_IACF49_Pos (17U)
#define IAC_ICR1_IACF49_Msk (0x1UL << IAC_ICR1_IACF49_Pos) /*!< 0x00020000 */
#define IAC_ICR1_IACF49 IAC_ICR1_IACF49_Msk
#define IAC_ICR1_IACF50_Pos (18U)
#define IAC_ICR1_IACF50_Msk (0x1UL << IAC_ICR1_IACF50_Pos) /*!< 0x00040000 */
#define IAC_ICR1_IACF50 IAC_ICR1_IACF50_Msk
#define IAC_ICR1_IACF51_Pos (19U)
#define IAC_ICR1_IACF51_Msk (0x1UL << IAC_ICR1_IACF51_Pos) /*!< 0x00080000 */
#define IAC_ICR1_IACF51 IAC_ICR1_IACF51_Msk
#define IAC_ICR1_IACF52_Pos (20U)
#define IAC_ICR1_IACF52_Msk (0x1UL << IAC_ICR1_IACF52_Pos) /*!< 0x00100000 */
#define IAC_ICR1_IACF52 IAC_ICR1_IACF52_Msk
#define IAC_ICR1_IACF53_Pos (21U)
#define IAC_ICR1_IACF53_Msk (0x1UL << IAC_ICR1_IACF53_Pos) /*!< 0x00200000 */
#define IAC_ICR1_IACF53 IAC_ICR1_IACF53_Msk
#define IAC_ICR1_IACF54_Pos (22U)
#define IAC_ICR1_IACF54_Msk (0x1UL << IAC_ICR1_IACF54_Pos) /*!< 0x00400000 */
#define IAC_ICR1_IACF54 IAC_ICR1_IACF54_Msk
#define IAC_ICR1_IACF55_Pos (23U)
#define IAC_ICR1_IACF55_Msk (0x1UL << IAC_ICR1_IACF55_Pos) /*!< 0x00800000 */
#define IAC_ICR1_IACF55 IAC_ICR1_IACF55_Msk
#define IAC_ICR1_IACF56_Pos (24U)
#define IAC_ICR1_IACF56_Msk (0x1UL << IAC_ICR1_IACF56_Pos) /*!< 0x01000000 */
#define IAC_ICR1_IACF56 IAC_ICR1_IACF56_Msk
#define IAC_ICR1_IACF57_Pos (25U)
#define IAC_ICR1_IACF57_Msk (0x1UL << IAC_ICR1_IACF57_Pos) /*!< 0x02000000 */
#define IAC_ICR1_IACF57 IAC_ICR1_IACF57_Msk
#define IAC_ICR1_IACF58_Pos (26U)
#define IAC_ICR1_IACF58_Msk (0x1UL << IAC_ICR1_IACF58_Pos) /*!< 0x04000000 */
#define IAC_ICR1_IACF58 IAC_ICR1_IACF58_Msk
#define IAC_ICR1_IACF60_Pos (28U)
#define IAC_ICR1_IACF60_Msk (0x1UL << IAC_ICR1_IACF60_Pos) /*!< 0x10000000 */
#define IAC_ICR1_IACF60 IAC_ICR1_IACF60_Msk
#define IAC_ICR1_IACF61_Pos (29U)
#define IAC_ICR1_IACF61_Msk (0x1UL << IAC_ICR1_IACF61_Pos) /*!< 0x20000000 */
#define IAC_ICR1_IACF61 IAC_ICR1_IACF61_Msk
#define IAC_ICR1_IACF62_Pos (30U)
#define IAC_ICR1_IACF62_Msk (0x1UL << IAC_ICR1_IACF62_Pos) /*!< 0x40000000 */
#define IAC_ICR1_IACF62 IAC_ICR1_IACF62_Msk
/******************* Bits definition for IAC_ICR2 register *******************/
#define IAC_ICR2_IACF64_Pos (0U)
#define IAC_ICR2_IACF64_Msk (0x1UL << IAC_ICR2_IACF64_Pos) /*!< 0x00000001 */
#define IAC_ICR2_IACF64 IAC_ICR2_IACF64_Msk
#define IAC_ICR2_IACF65_Pos (1U)
#define IAC_ICR2_IACF65_Msk (0x1UL << IAC_ICR2_IACF65_Pos) /*!< 0x00000002 */
#define IAC_ICR2_IACF65 IAC_ICR2_IACF65_Msk
#define IAC_ICR2_IACF67_Pos (3U)
#define IAC_ICR2_IACF67_Msk (0x1UL << IAC_ICR2_IACF67_Pos) /*!< 0x00000008 */
#define IAC_ICR2_IACF67 IAC_ICR2_IACF67_Msk
#define IAC_ICR2_IACF68_Pos (4U)
#define IAC_ICR2_IACF68_Msk (0x1UL << IAC_ICR2_IACF68_Pos) /*!< 0x00000010 */
#define IAC_ICR2_IACF68 IAC_ICR2_IACF68_Msk
#define IAC_ICR2_IACF69_Pos (5U)
#define IAC_ICR2_IACF69_Msk (0x1UL << IAC_ICR2_IACF69_Pos) /*!< 0x00000020 */
#define IAC_ICR2_IACF69 IAC_ICR2_IACF69_Msk
#define IAC_ICR2_IACF76_Pos (12U)
#define IAC_ICR2_IACF76_Msk (0x1UL << IAC_ICR2_IACF76_Pos) /*!< 0x00001000 */
#define IAC_ICR2_IACF76 IAC_ICR2_IACF76_Msk
#define IAC_ICR2_IACF77_Pos (13U)
#define IAC_ICR2_IACF77_Msk (0x1UL << IAC_ICR2_IACF77_Pos) /*!< 0x00002000 */
#define IAC_ICR2_IACF77 IAC_ICR2_IACF77_Msk
#define IAC_ICR2_IACF78_Pos (14U)
#define IAC_ICR2_IACF78_Msk (0x1UL << IAC_ICR2_IACF78_Pos) /*!< 0x00004000 */
#define IAC_ICR2_IACF78 IAC_ICR2_IACF78_Msk
#define IAC_ICR2_IACF79_Pos (15U)
#define IAC_ICR2_IACF79_Msk (0x1UL << IAC_ICR2_IACF79_Pos) /*!< 0x00008000 */
#define IAC_ICR2_IACF79 IAC_ICR2_IACF79_Msk
#define IAC_ICR2_IACF80_Pos (16U)
#define IAC_ICR2_IACF80_Msk (0x1UL << IAC_ICR2_IACF80_Pos) /*!< 0x00010000 */
#define IAC_ICR2_IACF80 IAC_ICR2_IACF80_Msk
#define IAC_ICR2_IACF81_Pos (17U)
#define IAC_ICR2_IACF81_Msk (0x1UL << IAC_ICR2_IACF81_Pos) /*!< 0x00020000 */
#define IAC_ICR2_IACF81 IAC_ICR2_IACF81_Msk
#define IAC_ICR2_IACF82_Pos (18U)
#define IAC_ICR2_IACF82_Msk (0x1UL << IAC_ICR2_IACF82_Pos) /*!< 0x00040000 */
#define IAC_ICR2_IACF82 IAC_ICR2_IACF82_Msk
#define IAC_ICR2_IACF83_Pos (19U)
#define IAC_ICR2_IACF83_Msk (0x1UL << IAC_ICR2_IACF83_Pos) /*!< 0x00080000 */
#define IAC_ICR2_IACF83 IAC_ICR2_IACF83_Msk
#define IAC_ICR2_IACF84_Pos (20U)
#define IAC_ICR2_IACF84_Msk (0x1UL << IAC_ICR2_IACF84_Pos) /*!< 0x00100000 */
#define IAC_ICR2_IACF84 IAC_ICR2_IACF84_Msk
#define IAC_ICR2_IACF86_Pos (22U)
#define IAC_ICR2_IACF86_Msk (0x1UL << IAC_ICR2_IACF86_Pos) /*!< 0x00400000 */
#define IAC_ICR2_IACF86 IAC_ICR2_IACF86_Msk
#define IAC_ICR2_IACF87_Pos (23U)
#define IAC_ICR2_IACF87_Msk (0x1UL << IAC_ICR2_IACF87_Pos) /*!< 0x00800000 */
#define IAC_ICR2_IACF87 IAC_ICR2_IACF87_Msk
#define IAC_ICR2_IACF88_Pos (24U)
#define IAC_ICR2_IACF88_Msk (0x1UL << IAC_ICR2_IACF88_Pos) /*!< 0x01000000 */
#define IAC_ICR2_IACF88 IAC_ICR2_IACF88_Msk
#define IAC_ICR2_IACF89_Pos (25U)
#define IAC_ICR2_IACF89_Msk (0x1UL << IAC_ICR2_IACF89_Pos) /*!< 0x02000000 */
#define IAC_ICR2_IACF89 IAC_ICR2_IACF89_Msk
#define IAC_ICR2_IACF90_Pos (26U)
#define IAC_ICR2_IACF90_Msk (0x1UL << IAC_ICR2_IACF90_Pos) /*!< 0x04000000 */
#define IAC_ICR2_IACF90 IAC_ICR2_IACF90_Msk
#define IAC_ICR2_IACF92_Pos (28U)
#define IAC_ICR2_IACF92_Msk (0x1UL << IAC_ICR2_IACF92_Pos) /*!< 0x10000000 */
#define IAC_ICR2_IACF92 IAC_ICR2_IACF92_Msk
#define IAC_ICR2_IACF93_Pos (29U)
#define IAC_ICR2_IACF93_Msk (0x1UL << IAC_ICR2_IACF93_Pos) /*!< 0x20000000 */
#define IAC_ICR2_IACF93 IAC_ICR2_IACF93_Msk
#define IAC_ICR2_IACF94_Pos (30U)
#define IAC_ICR2_IACF94_Msk (0x1UL << IAC_ICR2_IACF94_Pos) /*!< 0x40000000 */
#define IAC_ICR2_IACF94 IAC_ICR2_IACF94_Msk
#define IAC_ICR2_IACF95_Pos (31U)
#define IAC_ICR2_IACF95_Msk (0x1UL << IAC_ICR2_IACF95_Pos) /*!< 0x80000000 */
#define IAC_ICR2_IACF95 IAC_ICR2_IACF95_Msk
/******************* Bits definition for IAC_ICR3 register *******************/
#define IAC_ICR3_IACF96_Pos (0U)
#define IAC_ICR3_IACF96_Msk (0x1UL << IAC_ICR3_IACF96_Pos) /*!< 0x00000001 */
#define IAC_ICR3_IACF96 IAC_ICR3_IACF96_Msk
#define IAC_ICR3_IACF97_Pos (1U)
#define IAC_ICR3_IACF97_Msk (0x1UL << IAC_ICR3_IACF97_Pos) /*!< 0x00000002 */
#define IAC_ICR3_IACF97 IAC_ICR3_IACF97_Msk
#define IAC_ICR3_IACF98_Pos (2U)
#define IAC_ICR3_IACF98_Msk (0x1UL << IAC_ICR3_IACF98_Pos) /*!< 0x00000004 */
#define IAC_ICR3_IACF98 IAC_ICR3_IACF98_Msk
#define IAC_ICR3_IACF99_Pos (3U)
#define IAC_ICR3_IACF99_Msk (0x1UL << IAC_ICR3_IACF99_Pos) /*!< 0x00000008 */
#define IAC_ICR3_IACF99 IAC_ICR3_IACF99_Msk
#define IAC_ICR3_IACF100_Pos (4U)
#define IAC_ICR3_IACF100_Msk (0x1UL << IAC_ICR3_IACF100_Pos) /*!< 0x00000010 */
#define IAC_ICR3_IACF100 IAC_ICR3_IACF100_Msk
#define IAC_ICR3_IACF101_Pos (5U)
#define IAC_ICR3_IACF101_Msk (0x1UL << IAC_ICR3_IACF101_Pos) /*!< 0x00000020 */
#define IAC_ICR3_IACF101 IAC_ICR3_IACF101_Msk
#define IAC_ICR3_IACF102_Pos (6U)
#define IAC_ICR3_IACF102_Msk (0x1UL << IAC_ICR3_IACF102_Pos) /*!< 0x00000040 */
#define IAC_ICR3_IACF102 IAC_ICR3_IACF102_Msk
#define IAC_ICR3_IACF103_Pos (7U)
#define IAC_ICR3_IACF103_Msk (0x1UL << IAC_ICR3_IACF103_Pos) /*!< 0x00000080 */
#define IAC_ICR3_IACF103 IAC_ICR3_IACF103_Msk
#define IAC_ICR3_IACF104_Pos (8U)
#define IAC_ICR3_IACF104_Msk (0x1UL << IAC_ICR3_IACF104_Pos) /*!< 0x00000100 */
#define IAC_ICR3_IACF104 IAC_ICR3_IACF104_Msk
#define IAC_ICR3_IACF106_Pos (10U)
#define IAC_ICR3_IACF106_Msk (0x1UL << IAC_ICR3_IACF106_Pos) /*!< 0x00000400 */
#define IAC_ICR3_IACF106 IAC_ICR3_IACF106_Msk
/******************* Bits definition for IAC_ICR4 register *******************/
#define IAC_ICR4_IACF128_Pos (0U)
#define IAC_ICR4_IACF128_Msk (0x1UL << IAC_ICR4_IACF128_Pos) /*!< 0x00000001 */
#define IAC_ICR4_IACF128 IAC_ICR4_IACF128_Msk
#define IAC_ICR4_IACF129_Pos (1U)
#define IAC_ICR4_IACF129_Msk (0x1UL << IAC_ICR4_IACF129_Pos) /*!< 0x00000002 */
#define IAC_ICR4_IACF129 IAC_ICR4_IACF129_Msk
#define IAC_ICR4_IACF130_Pos (2U)
#define IAC_ICR4_IACF130_Msk (0x1UL << IAC_ICR4_IACF130_Pos) /*!< 0x00000004 */
#define IAC_ICR4_IACF130 IAC_ICR4_IACF130_Msk
#define IAC_ICR4_IACF131_Pos (3U)
#define IAC_ICR4_IACF131_Msk (0x1UL << IAC_ICR4_IACF131_Pos) /*!< 0x00000008 */
#define IAC_ICR4_IACF131 IAC_ICR4_IACF131_Msk
#define IAC_ICR4_IACF133_Pos (5U)
#define IAC_ICR4_IACF133_Msk (0x1UL << IAC_ICR4_IACF133_Pos) /*!< 0x00000020 */
#define IAC_ICR4_IACF133 IAC_ICR4_IACF133_Msk
#define IAC_ICR4_IACF134_Pos (6U)
#define IAC_ICR4_IACF134_Msk (0x1UL << IAC_ICR4_IACF134_Pos) /*!< 0x00000040 */
#define IAC_ICR4_IACF134 IAC_ICR4_IACF134_Msk
#define IAC_ICR4_IACF135_Pos (7U)
#define IAC_ICR4_IACF135_Msk (0x1UL << IAC_ICR4_IACF135_Pos) /*!< 0x00000080 */
#define IAC_ICR4_IACF135 IAC_ICR4_IACF135_Msk
#define IAC_ICR4_IACF136_Pos (8U)
#define IAC_ICR4_IACF136_Msk (0x1UL << IAC_ICR4_IACF136_Pos) /*!< 0x00000100 */
#define IAC_ICR4_IACF136 IAC_ICR4_IACF136_Msk
#define IAC_ICR4_IACF137_Pos (9U)
#define IAC_ICR4_IACF137_Msk (0x1UL << IAC_ICR4_IACF137_Pos) /*!< 0x00000200 */
#define IAC_ICR4_IACF137 IAC_ICR4_IACF137_Msk
#define IAC_ICR4_IACF138_Pos (10U)
#define IAC_ICR4_IACF138_Msk (0x1UL << IAC_ICR4_IACF138_Pos) /*!< 0x00000400 */
#define IAC_ICR4_IACF138 IAC_ICR4_IACF138_Msk
#define IAC_ICR4_IACF139_Pos (11U)
#define IAC_ICR4_IACF139_Msk (0x1UL << IAC_ICR4_IACF139_Pos) /*!< 0x00000800 */
#define IAC_ICR4_IACF139 IAC_ICR4_IACF139_Msk
#define IAC_ICR4_IACF140_Pos (12U)
#define IAC_ICR4_IACF140_Msk (0x1UL << IAC_ICR4_IACF140_Pos) /*!< 0x00001000 */
#define IAC_ICR4_IACF140 IAC_ICR4_IACF140_Msk
#define IAC_ICR4_IACF141_Pos (13U)
#define IAC_ICR4_IACF141_Msk (0x1UL << IAC_ICR4_IACF141_Pos) /*!< 0x00002000 */
#define IAC_ICR4_IACF141 IAC_ICR4_IACF141_Msk
#define IAC_ICR4_IACF142_Pos (14U)
#define IAC_ICR4_IACF142_Msk (0x1UL << IAC_ICR4_IACF142_Pos) /*!< 0x00004000 */
#define IAC_ICR4_IACF142 IAC_ICR4_IACF142_Msk
#define IAC_ICR4_IACF143_Pos (15U)
#define IAC_ICR4_IACF143_Msk (0x1UL << IAC_ICR4_IACF143_Pos) /*!< 0x00008000 */
#define IAC_ICR4_IACF143 IAC_ICR4_IACF143_Msk
#define IAC_ICR4_IACF144_Pos (16U)
#define IAC_ICR4_IACF144_Msk (0x1UL << IAC_ICR4_IACF144_Pos) /*!< 0x00010000 */
#define IAC_ICR4_IACF144 IAC_ICR4_IACF144_Msk
#define IAC_ICR4_IACF145_Pos (17U)
#define IAC_ICR4_IACF145_Msk (0x1UL << IAC_ICR4_IACF145_Pos) /*!< 0x00020000 */
#define IAC_ICR4_IACF145 IAC_ICR4_IACF145_Msk
#define IAC_ICR4_IACF146_Pos (18U)
#define IAC_ICR4_IACF146_Msk (0x1UL << IAC_ICR4_IACF146_Pos) /*!< 0x00040000 */
#define IAC_ICR4_IACF146 IAC_ICR4_IACF146_Msk
#define IAC_ICR4_IACF147_Pos (19U)
#define IAC_ICR4_IACF147_Msk (0x1UL << IAC_ICR4_IACF147_Pos) /*!< 0x00080000 */
#define IAC_ICR4_IACF147 IAC_ICR4_IACF147_Msk
#define IAC_ICR4_IACF149_Pos (21U)
#define IAC_ICR4_IACF149_Msk (0x1UL << IAC_ICR4_IACF149_Pos) /*!< 0x00200000 */
#define IAC_ICR4_IACF149 IAC_ICR4_IACF149_Msk
#define IAC_ICR4_IACF150_Pos (22U)
#define IAC_ICR4_IACF150_Msk (0x1UL << IAC_ICR4_IACF150_Pos) /*!< 0x00400000 */
#define IAC_ICR4_IACF150 IAC_ICR4_IACF150_Msk
#define IAC_ICR4_IACF151_Pos (23U)
#define IAC_ICR4_IACF151_Msk (0x1UL << IAC_ICR4_IACF151_Pos) /*!< 0x00800000 */
#define IAC_ICR4_IACF151 IAC_ICR4_IACF151_Msk
#define IAC_ICR4_IACF152_Pos (24U)
#define IAC_ICR4_IACF152_Msk (0x1UL << IAC_ICR4_IACF152_Pos) /*!< 0x01000000 */
#define IAC_ICR4_IACF152 IAC_ICR4_IACF152_Msk
#define IAC_ICR4_IACF153_Pos (25U)
#define IAC_ICR4_IACF153_Msk (0x1UL << IAC_ICR4_IACF153_Pos) /*!< 0x02000000 */
#define IAC_ICR4_IACF153 IAC_ICR4_IACF153_Msk
#define IAC_ICR4_IACF155_Pos (27U)
#define IAC_ICR4_IACF155_Msk (0x1UL << IAC_ICR4_IACF155_Pos) /*!< 0x08000000 */
#define IAC_ICR4_IACF155 IAC_ICR4_IACF155_Msk
#define IAC_ICR4_IACF156_Pos (28U)
#define IAC_ICR4_IACF156_Msk (0x1UL << IAC_ICR4_IACF156_Pos) /*!< 0x10000000 */
#define IAC_ICR4_IACF156 IAC_ICR4_IACF156_Msk
#define IAC_ICR4_IACF157_Pos (29U)
#define IAC_ICR4_IACF157_Msk (0x1UL << IAC_ICR4_IACF157_Pos) /*!< 0x20000000 */
#define IAC_ICR4_IACF157 IAC_ICR4_IACF157_Msk
/******************************************************************************/
/* */
/* ICACHE */
/* */
/******************************************************************************/
/****************** Bit definition for ICACHE_CR register *******************/
#define ICACHE_CR_EN_Pos (0U)
#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */
#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */
#define ICACHE_CR_CACHEINV_Pos (1U)
#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */
#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */
#define ICACHE_CR_WAYSEL_Pos (2U)
#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */
#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */
#define ICACHE_CR_HITMEN_Pos (16U)
#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */
#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */
#define ICACHE_CR_MISSMEN_Pos (17U)
#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */
#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */
#define ICACHE_CR_HITMRST_Pos (18U)
#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */
#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */
#define ICACHE_CR_MISSMRST_Pos (19U)
#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */
#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */
/****************** Bit definition for ICACHE_SR register *******************/
#define ICACHE_SR_BUSYF_Pos (0U)
#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */
#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */
#define ICACHE_SR_BSYENDF_Pos (1U)
#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */
#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */
#define ICACHE_SR_ERRF_Pos (2U)
#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */
#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */
/****************** Bit definition for ICACHE_IER register ******************/
#define ICACHE_IER_BSYENDIE_Pos (1U)
#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */
#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */
#define ICACHE_IER_ERRIE_Pos (2U)
#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */
#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */
/****************** Bit definition for ICACHE_FCR register ******************/
#define ICACHE_FCR_CBSYENDF_Pos (1U)
#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */
#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */
#define ICACHE_FCR_CERRF_Pos (2U)
#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */
#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */
/****************** Bit definition for ICACHE_HMONR register ****************/
#define ICACHE_HMONR_HITMON_Pos (0U)
#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos)/*!< 0xFFFFFFFF */
#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */
/****************** Bit definition for ICACHE_MMONR register ****************/
#define ICACHE_MMONR_MISSMON_Pos (0U)
#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */
#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */
/******************************************************************************/
/* */
/* Independent Watchdog (IWDG) */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0x0000) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0xFUL << IWDG_PR_PR_Pos) /*!< 0x0000000F */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!< Prescaler divider */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
#define IWDG_PR_PR_3 (0x8UL << IWDG_PR_PR_Pos) /*!< 0x00000008 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
#define IWDG_SR_EWU_Pos (3U)
#define IWDG_SR_EWU_Msk (0x1UL << IWDG_SR_EWU_Pos) /*!< 0x00000008 */
#define IWDG_SR_EWU IWDG_SR_EWU_Msk /*!< Watchdog interrupt comparator value update */
#define IWDG_SR_ONF_Pos (8U)
#define IWDG_SR_ONF_Msk (0x1UL << IWDG_SR_ONF_Pos) /*!< 0x00000100 */
#define IWDG_SR_ONF IWDG_SR_ONF_Msk /*!< Watchdog Enable status bit */
#define IWDG_SR_EWIF_Pos (15U)
#define IWDG_SR_EWIF_Msk (0x1UL << IWDG_SR_EWIF_Pos) /*!< 0x00008000 */
#define IWDG_SR_EWIF IWDG_SR_EWIF_Msk /*!< Watchdog Early Interrupt flag */
/****************** Bit definition for IWDG_WINR register *******************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/****************** Bit definition for IWDG_EWCR register *******************/
#define IWDG_EWCR_EWIT_Pos (0U)
#define IWDG_EWCR_EWIT_Msk (0xFFFUL << IWDG_EWCR_EWIT_Pos) /*!< 0x00000FFF */
#define IWDG_EWCR_EWIT IWDG_EWCR_EWIT_Msk /*!< Watchdog counter window value */
#define IWDG_EWCR_EWIE_Pos (15U)
#define IWDG_EWCR_EWIE_Msk (0x1UL << IWDG_EWCR_EWIE_Pos) /*!< 0x00008000 */
#define IWDG_EWCR_EWIE IWDG_EWCR_EWIE_Msk /*!< Watchdog early interrupt enable */
/******************* Bit definition for IWDG_ICR register *******************/
#define IWDG_ICR_EWIC_Pos (15U)
#define IWDG_ICR_EWIC_Msk (0x1UL << IWDG_ICR_EWIC_Pos) /*!< 0x00008000 */
#define IWDG_ICR_EWIC IWDG_ICR_EWIC_Msk /*!< Watchdog early interrupt acknowledge */
/******************************************************************************/
/* */
/* JPEG Encoder/Decoder */
/* */
/******************************************************************************/
/******************** Bit definition for CONFR0 register ********************/
#define JPEG_CONFR0_START_Pos (0U)
#define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
#define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
/******************** Bit definition for CONFR1 register ********************/
#define JPEG_CONFR1_NF_Pos (0U)
#define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
#define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
#define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
#define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
#define JPEG_CONFR1_DE_Pos (3U)
#define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
#define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
#define JPEG_CONFR1_COLORSPACE_Pos (4U)
#define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
#define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
#define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
#define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
#define JPEG_CONFR1_NS_Pos (6U)
#define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
#define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
#define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
#define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
#define JPEG_CONFR1_HDR_Pos (8U)
#define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
#define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
#define JPEG_CONFR1_YSIZE_Pos (16U)
#define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
#define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
/******************** Bit definition for CONFR2 register ********************/
#define JPEG_CONFR2_NMCU_Pos (0U)
#define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
#define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
/******************** Bit definition for CONFR3 register ********************/
#define JPEG_CONFR3_XSIZE_Pos (16U)
#define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
#define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
/******************** Bit definition for CONFR4 register ********************/
#define JPEG_CONFR4_HD_Pos (0U)
#define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR4_HA_Pos (1U)
#define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR4_QT_Pos (2U)
#define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR4_NB_Pos (4U)
#define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR4_VSF_Pos (8U)
#define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
#define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR4_HSF_Pos (12U)
#define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
#define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CONFR5 register ********************/
#define JPEG_CONFR5_HD_Pos (0U)
#define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR5_HA_Pos (1U)
#define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR5_QT_Pos (2U)
#define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR5_NB_Pos (4U)
#define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR5_VSF_Pos (8U)
#define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR5_HSF_Pos (12U)
#define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CONFR6 register ********************/
#define JPEG_CONFR6_HD_Pos (0U)
#define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR6_HA_Pos (1U)
#define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR6_QT_Pos (2U)
#define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR6_NB_Pos (4U)
#define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR6_VSF_Pos (8U)
#define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR6_HSF_Pos (12U)
#define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CONFR7 register ********************/
#define JPEG_CONFR7_HD_Pos (0U)
#define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
#define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
#define JPEG_CONFR7_HA_Pos (1U)
#define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
#define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
#define JPEG_CONFR7_QT_Pos (2U)
#define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
#define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
#define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
#define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
#define JPEG_CONFR7_NB_Pos (4U)
#define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
#define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
#define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
#define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
#define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
#define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
#define JPEG_CONFR7_VSF_Pos (8U)
#define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
#define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
#define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
#define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
#define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
#define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
#define JPEG_CONFR7_HSF_Pos (12U)
#define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
#define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
#define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
#define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
#define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
#define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
/******************** Bit definition for CR register ********************/
#define JPEG_CR_JCEN_Pos (0U)
#define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
#define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
#define JPEG_CR_IFTIE_Pos (1U)
#define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
#define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
#define JPEG_CR_IFNFIE_Pos (2U)
#define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
#define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
#define JPEG_CR_OFTIE_Pos (3U)
#define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
#define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
#define JPEG_CR_OFNEIE_Pos (4U)
#define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
#define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
#define JPEG_CR_EOCIE_Pos (5U)
#define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
#define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
#define JPEG_CR_HPDIE_Pos (6U)
#define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
#define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
#define JPEG_CR_IDMAEN_Pos (11U)
#define JPEG_CR_IDMAEN_Msk (0x1UL << JPEG_CR_IDMAEN_Pos) /*!< 0x00000800 */
#define JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk /*!<Input DMA enable */
#define JPEG_CR_ODMAEN_Pos (12U)
#define JPEG_CR_ODMAEN_Msk (0x1UL << JPEG_CR_ODMAEN_Pos) /*!< 0x00001000 */
#define JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk /*!<Output DMA enable */
#define JPEG_CR_IFF_Pos (13U)
#define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
#define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
#define JPEG_CR_OFF_Pos (14U)
#define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
#define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
/******************** Bit definition for SR register ********************/
#define JPEG_SR_IFTF_Pos (1U)
#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
#define JPEG_SR_IFNFF_Pos (2U)
#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
#define JPEG_SR_OFTF_Pos (3U)
#define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
#define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
#define JPEG_SR_OFNEF_Pos (4U)
#define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
#define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
#define JPEG_SR_EOCF_Pos (5U)
#define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
#define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
#define JPEG_SR_HPDF_Pos (6U)
#define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
#define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
#define JPEG_SR_COF_Pos (7U)
#define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */
#define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
/******************** Bit definition for CFR register ********************/
#define JPEG_CFR_CEOCF_Pos (5U)
#define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000020 */
#define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
#define JPEG_CFR_CHPDF_Pos (6U)
#define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000040 */
#define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
/******************** Bit definition for DIR register ********************/
#define JPEG_DIR_DATAIN_Pos (0U)
#define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
#define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
/******************** Bit definition for DOR register ********************/
#define JPEG_DOR_DATAOUT_Pos (0U)
#define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
#define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CC1IF_Pos (0U)
#define LPTIM_ISR_CC1IF_Msk (0x1UL << LPTIM_ISR_CC1IF_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF_Msk /*!< Capture/Compare 1 interrupt flag */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMP1OK_Pos (3U)
#define LPTIM_ISR_CMP1OK_Msk (0x1UL << LPTIM_ISR_CMP1OK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK_Msk /*!< Compare register 1 update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
#define LPTIM_ISR_UE_Pos (7U)
#define LPTIM_ISR_UE_Msk (0x1UL << LPTIM_ISR_UE_Pos) /*!< 0x00000080 */
#define LPTIM_ISR_UE LPTIM_ISR_UE_Msk /*!< Update event occurrence */
#define LPTIM_ISR_REPOK_Pos (8U)
#define LPTIM_ISR_REPOK_Msk (0x1UL << LPTIM_ISR_REPOK_Pos) /*!< 0x00000100 */
#define LPTIM_ISR_REPOK LPTIM_ISR_REPOK_Msk /*!< Repetition register update OK */
#define LPTIM_ISR_CC2IF_Pos (9U)
#define LPTIM_ISR_CC2IF_Msk (0x1UL << LPTIM_ISR_CC2IF_Pos) /*!< 0x00000200 */
#define LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF_Msk /*!< Capture/Compare 2 interrupt flag */
#define LPTIM_ISR_CC1OF_Pos (12U)
#define LPTIM_ISR_CC1OF_Msk (0x1UL << LPTIM_ISR_CC1OF_Pos) /*!< 0x00001000 */
#define LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
#define LPTIM_ISR_CC2OF_Pos (13U)
#define LPTIM_ISR_CC2OF_Msk (0x1UL << LPTIM_ISR_CC2OF_Pos) /*!< 0x00002000 */
#define LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
#define LPTIM_ISR_CMP2OK_Pos (19U)
#define LPTIM_ISR_CMP2OK_Msk (0x1UL << LPTIM_ISR_CMP2OK_Pos) /*!< 0x00080000 */
#define LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK_Msk /*!< Compare register 2 update OK */
#define LPTIM_ISR_DIEROK_Pos (24U)
#define LPTIM_ISR_DIEROK_Msk (0x1UL << LPTIM_ISR_DIEROK_Pos) /*!< 0x01000000 */
#define LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK_Msk /*!< Interrupt enable register update OK */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CC1CF_Pos (0U)
#define LPTIM_ICR_CC1CF_Msk (0x1UL << LPTIM_ICR_CC1CF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CC1CF LPTIM_ICR_CC1CF_Msk /*!< Capture/Compare 1 clear flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMP1OKCF_Pos (3U)
#define LPTIM_ICR_CMP1OKCF_Msk (0x1UL << LPTIM_ICR_CMP1OKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMP1OKCF LPTIM_ICR_CMP1OKCF_Msk /*!< Compare register 1 update OK clear flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
#define LPTIM_ICR_UECF_Pos (7U)
#define LPTIM_ICR_UECF_Msk (0x1UL << LPTIM_ICR_UECF_Pos) /*!< 0x00000080 */
#define LPTIM_ICR_UECF LPTIM_ICR_UECF_Msk /*!< Update event Clear Flag */
#define LPTIM_ICR_REPOKCF_Pos (8U)
#define LPTIM_ICR_REPOKCF_Msk (0x1UL << LPTIM_ICR_REPOKCF_Pos) /*!< 0x00000100 */
#define LPTIM_ICR_REPOKCF LPTIM_ICR_REPOKCF_Msk /*!< Repetition register update OK Clear Flag */
#define LPTIM_ICR_CC2CF_Pos (9U)
#define LPTIM_ICR_CC2CF_Msk (0x1UL << LPTIM_ICR_CC2CF_Pos) /*!< 0x00000200 */
#define LPTIM_ICR_CC2CF LPTIM_ICR_CC2CF_Msk /*!< Capture/Compare 2 clear flag */
#define LPTIM_ICR_CC1OCF_Pos (12U)
#define LPTIM_ICR_CC1OCF_Msk (0x1UL << LPTIM_ICR_CC1OCF_Pos) /*!< 0x00001000 */
#define LPTIM_ICR_CC1OCF LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
#define LPTIM_ICR_CC2OCF_Pos (13U)
#define LPTIM_ICR_CC2OCF_Msk (0x1UL << LPTIM_ICR_CC2OCF_Pos) /*!< 0x00002000 */
#define LPTIM_ICR_CC2OCF LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
#define LPTIM_ICR_CMP2OKCF_Pos (19U)
#define LPTIM_ICR_CMP2OKCF_Msk (0x1UL << LPTIM_ICR_CMP2OKCF_Pos) /*!< 0x00080000 */
#define LPTIM_ICR_CMP2OKCF LPTIM_ICR_CMP2OKCF_Msk /*!< Compare register 2 update OK clear flag */
#define LPTIM_ICR_DIEROKCF_Pos (24U)
#define LPTIM_ICR_DIEROKCF_Msk (0x1UL << LPTIM_ICR_DIEROKCF_Pos) /*!< 0x01000000 */
#define LPTIM_ICR_DIEROKCF LPTIM_ICR_DIEROKCF_Msk /*!< Interrupt enable register update OK clear flag */
/****************** Bit definition for LPTIM_DIER register *******************/
#define LPTIM_DIER_CC1IE_Pos (0U)
#define LPTIM_DIER_CC1IE_Msk (0x1UL << LPTIM_DIER_CC1IE_Pos) /*!< 0x00000001 */
#define LPTIM_DIER_CC1IE LPTIM_DIER_CC1IE_Msk /*!< Compare/Compare interrupt enable */
#define LPTIM_DIER_ARRMIE_Pos (1U)
#define LPTIM_DIER_ARRMIE_Msk (0x1UL << LPTIM_DIER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_DIER_EXTTRIGIE_Pos (2U)
#define LPTIM_DIER_EXTTRIGIE_Msk (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_DIER_CMP1OKIE_Pos (3U)
#define LPTIM_DIER_CMP1OKIE_Msk (0x1UL << LPTIM_DIER_CMP1OKIE_Pos) /*!< 0x00000008 */
#define LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE_Msk /*!< Compare register 1 update OK interrupt enable */
#define LPTIM_DIER_ARROKIE_Pos (4U)
#define LPTIM_DIER_ARROKIE_Msk (0x1UL << LPTIM_DIER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_DIER_UPIE_Pos (5U)
#define LPTIM_DIER_UPIE_Msk (0x1UL << LPTIM_DIER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_DIER_UPIE LPTIM_DIER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_DIER_DOWNIE_Pos (6U)
#define LPTIM_DIER_DOWNIE_Msk (0x1UL << LPTIM_DIER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
#define LPTIM_DIER_UEIE_Pos (7U)
#define LPTIM_DIER_UEIE_Msk (0x1UL << LPTIM_DIER_UEIE_Pos) /*!< 0x00000080 */
#define LPTIM_DIER_UEIE LPTIM_DIER_UEIE_Msk /*!< Update event Interrupt Enable */
#define LPTIM_DIER_REPOKIE_Pos (8U)
#define LPTIM_DIER_REPOKIE_Msk (0x1UL << LPTIM_DIER_REPOKIE_Pos) /*!< 0x00000100 */
#define LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE_Msk /*!< Repetition register update OK Interrupt Enable */
#define LPTIM_DIER_CC2IE_Pos (9U)
#define LPTIM_DIER_CC2IE_Msk (0x1UL << LPTIM_DIER_CC2IE_Pos) /*!< 0x00000200 */
#define LPTIM_DIER_CC2IE LPTIM_DIER_CC2IE_Msk /*!< Capture/Compare 2 interrupt interrupt enable */
#define LPTIM_DIER_CC1OIE_Pos (12U)
#define LPTIM_DIER_CC1OIE_Msk (0x1UL << LPTIM_DIER_CC1OIE_Pos) /*!< 0x00001000 */
#define LPTIM_DIER_CC1OIE LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt enable */
#define LPTIM_DIER_CC2OIE_Pos (13U)
#define LPTIM_DIER_CC2OIE_Msk (0x1UL << LPTIM_DIER_CC2OIE_Pos) /*!< 0x00002000 */
#define LPTIM_DIER_CC2OIE LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt enable */
#define LPTIM_DIER_CC1DE_Pos (16U)
#define LPTIM_DIER_CC1DE_Msk (0x1UL << LPTIM_DIER_CC1DE_Pos) /*!< 0x00010000 */
#define LPTIM_DIER_CC1DE LPTIM_DIER_CC1DE_Msk /*!< Capture/Compare 1 DMA request enable */
#define LPTIM_DIER_CMP2OKIE_Pos (19U)
#define LPTIM_DIER_CMP2OKIE_Msk (0x1UL << LPTIM_DIER_CMP2OKIE_Pos) /*!< 0x00080000 */
#define LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE_Msk /*!< Compare register 2 update OK interrupt enable */
#define LPTIM_DIER_UEDE_Pos (23U)
#define LPTIM_DIER_UEDE_Msk (0x1UL << LPTIM_DIER_UEDE_Pos) /*!< 0x00800000 */
#define LPTIM_DIER_UEDE LPTIM_DIER_UEDE_Msk /*!< Update event DMA request enable */
#define LPTIM_DIER_CC2DE_Pos (25U)
#define LPTIM_DIER_CC2DE_Msk (0x1UL << LPTIM_DIER_CC2DE_Pos) /*!< 0x02000000 */
#define LPTIM_DIER_CC2DE LPTIM_DIER_CC2DE_Msk /*!< Capture/Compare 2 DMA request enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CCR1_CCR1_Pos (0U)
#define LPTIM_CCR1_CCR1_Msk (0xFFFFUL << LPTIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define LPTIM_CCR1_CCR1 LPTIM_CCR1_CCR1_Msk /*!< Compare register 1 */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_CFGR2 register *****************/
#define LPTIM_CFGR2_IN1SEL_Pos (0U)
#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR2_IN2SEL_Pos (4U)
#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
#define LPTIM_CFGR2_IC1SEL_Pos (16U)
#define LPTIM_CFGR2_IC1SEL_Msk (0x3UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00000003 */
#define LPTIM_CFGR2_IC1SEL LPTIM_CFGR2_IC1SEL_Msk /*!< IC1SEL[17:16] bits */
#define LPTIM_CFGR2_IC1SEL_0 (0x1UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00010000 */
#define LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR2_IC2SEL_Pos (20U)
#define LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00000030 */
#define LPTIM_CFGR2_IC2SEL LPTIM_CFGR2_IC2SEL_Msk /*!< IC2SEL[21:20] bits */
#define LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) /*!< 0x00200000 */
/****************** Bit definition for LPTIM_RCR register *******************/
#define LPTIM_RCR_REP_Pos (0U)
#define LPTIM_RCR_REP_Msk (0xFFUL << LPTIM_RCR_REP_Pos) /*!< 0x000000FF */
#define LPTIM_RCR_REP LPTIM_RCR_REP_Msk /*!< Repetition Counter Value */
/***************** Bit definition for LPTIM_CCMR1 register ******************/
#define LPTIM_CCMR1_CC1SEL_Pos (0U)
#define LPTIM_CCMR1_CC1SEL_Msk (0x1UL << LPTIM_CCMR1_CC1SEL_Pos) /*!< 0x00000001 */
#define LPTIM_CCMR1_CC1SEL LPTIM_CCMR1_CC1SEL_Msk /*!< Capture/Compare 1 selection */
#define LPTIM_CCMR1_CC1E_Pos (1U)
#define LPTIM_CCMR1_CC1E_Msk (0x1UL << LPTIM_CCMR1_CC1E_Pos) /*!< 0x00000002 */
#define LPTIM_CCMR1_CC1E LPTIM_CCMR1_CC1E_Msk /*!< Capture/Compare 1 output enable */
#define LPTIM_CCMR1_CC1P_Pos (2U)
#define LPTIM_CCMR1_CC1P_Msk (0x3UL << LPTIM_CCMR1_CC1P_Pos) /*!< 0x0000000C */
#define LPTIM_CCMR1_CC1P LPTIM_CCMR1_CC1P_Msk /*!< Capture/Compare 1 output polarity */
#define LPTIM_CCMR1_CC1P_0 (0x1UL << LPTIM_CCMR1_CC1P_Pos) /*!< 0x00000004 */
#define LPTIM_CCMR1_CC1P_1 (0x2UL << LPTIM_CCMR1_CC1P_Pos) /*!< 0x00000008 */
#define LPTIM_CCMR1_IC1PSC_Pos (8U)
#define LPTIM_CCMR1_IC1PSC_Msk (0x3UL << LPTIM_CCMR1_IC1PSC_Pos) /*!< 0x00000300 */
#define LPTIM_CCMR1_IC1PSC LPTIM_CCMR1_IC1PSC_Msk /*!< Input capture 1 prescaler */
#define LPTIM_CCMR1_IC1PSC_0 (0x1UL << LPTIM_CCMR1_IC1PSC_Pos) /*!< 0x00000100 */
#define LPTIM_CCMR1_IC1PSC_1 (0x2UL << LPTIM_CCMR1_IC1PSC_Pos) /*!< 0x00000200 */
#define LPTIM_CCMR1_IC1F_Pos (12U)
#define LPTIM_CCMR1_IC1F_Msk (0x3UL << LPTIM_CCMR1_IC1F_Pos) /*!< 0x00003000 */
#define LPTIM_CCMR1_IC1F LPTIM_CCMR1_IC1F_Msk /*!< Input capture 1 filter */
#define LPTIM_CCMR1_IC1F_0 (0x1UL << LPTIM_CCMR1_IC1F_Pos) /*!< 0x00001000 */
#define LPTIM_CCMR1_IC1F_1 (0x2UL << LPTIM_CCMR1_IC1F_Pos) /*!< 0x00002000 */
#define LPTIM_CCMR1_CC2SEL_Pos (16U)
#define LPTIM_CCMR1_CC2SEL_Msk (0x1UL << LPTIM_CCMR1_CC2SEL_Pos) /*!< 0x00010000 */
#define LPTIM_CCMR1_CC2SEL LPTIM_CCMR1_CC2SEL_Msk /*!< Capture/Compare 2 selection */
#define LPTIM_CCMR1_CC2E_Pos (17U)
#define LPTIM_CCMR1_CC2E_Msk (0x1UL << LPTIM_CCMR1_CC2E_Pos) /*!< 0x00020000 */
#define LPTIM_CCMR1_CC2E LPTIM_CCMR1_CC2E_Msk /*!< Capture/Compare 2 output enable */
#define LPTIM_CCMR1_CC2P_Pos (18U)
#define LPTIM_CCMR1_CC2P_Msk (0x3UL << LPTIM_CCMR1_CC2P_Pos) /*!< 0x000C0000 */
#define LPTIM_CCMR1_CC2P LPTIM_CCMR1_CC2P_Msk /*!< Capture/Compare 2 output polarity */
#define LPTIM_CCMR1_CC2P_0 (0x1UL << LPTIM_CCMR1_CC2P_Pos) /*!< 0x00040000 */
#define LPTIM_CCMR1_CC2P_1 (0x2UL << LPTIM_CCMR1_CC2P_Pos) /*!< 0x00080000 */
#define LPTIM_CCMR1_IC2PSC_Pos (24U)
#define LPTIM_CCMR1_IC2PSC_Msk (0x3UL << LPTIM_CCMR1_IC2PSC_Pos) /*!< 0x03000000 */
#define LPTIM_CCMR1_IC2PSC LPTIM_CCMR1_IC2PSC_Msk /*!< Input capture 2 prescaler */
#define LPTIM_CCMR1_IC2PSC_0 (0x1UL << LPTIM_CCMR1_IC2PSC_Pos) /*!< 0x01000000 */
#define LPTIM_CCMR1_IC2PSC_1 (0x2UL << LPTIM_CCMR1_IC2PSC_Pos) /*!< 0x02000000 */
#define LPTIM_CCMR1_IC2F_Pos (28U)
#define LPTIM_CCMR1_IC2F_Msk (0x3UL << LPTIM_CCMR1_IC2F_Pos) /*!< 0x30000000 */
#define LPTIM_CCMR1_IC2F LPTIM_CCMR1_IC2F_Msk /*!< Input capture 2 filter */
#define LPTIM_CCMR1_IC2F_0 (0x1UL << LPTIM_CCMR1_IC2F_Pos) /*!< 0x10000000 */
#define LPTIM_CCMR1_IC2F_1 (0x2UL << LPTIM_CCMR1_IC2F_Pos) /*!< 0x20000000 */
/****************** Bit definition for LPTIM_CCR2 register ******************/
#define LPTIM_CCR2_CCR2_Pos (0U)
#define LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk /*!< Compare register 2 */
/******************************************************************************/
/* */
/* LCD-TFT Display Controller (LTDC) */
/* */
/******************************************************************************/
/* Bit fields for LTDC_SSCR register */
#define LTDC_SSCR_VSH_Pos (0U)
#define LTDC_SSCR_VSH_Msk (0xffffUL << LTDC_SSCR_VSH_Pos)
#define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< vertical synchronization height (in units of horizontal scan line)These bits define the vertical Synchronization height minus 1. It represents the number of horizontal synchronization lines. */
#define LTDC_SSCR_HSW_Pos (16U)
#define LTDC_SSCR_HSW_Msk (0xffffUL << LTDC_SSCR_HSW_Pos)
#define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< horizontal synchronization width (in units of pixel clock period)These bits define the number of Horizontal Synchronization pixel minus 1. */
/* Bit fields for LTDC_BPCR register */
#define LTDC_BPCR_AVBP_Pos (0U)
#define LTDC_BPCR_AVBP_Msk (0xffffUL << LTDC_BPCR_AVBP_Pos)
#define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< accumulated Vertical back porch (in units of horizontal scan line)These bits define the accumulated vertical back porch width that includes the vertical synchronization and vertical back porch lines minus 1.The vertical back porch is the number of horizontal scan lines at a start of frame to the start of the first active scan line of the next frame. */
#define LTDC_BPCR_AHBP_Pos (16U)
#define LTDC_BPCR_AHBP_Msk (0xffffUL << LTDC_BPCR_AHBP_Pos)
#define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< accumulated horizontal back porch (in units of pixel clock period)These bits define the accumulated horizontal back porch width that includes the horizontal synchronization and horizontal back porch pixels minus 1.The horizontal back porch is the period between horizontal synchronization going inactive and the start of the active display part of the next scan line. */
/* Bit fields for LTDC_AWCR register */
#define LTDC_AWCR_AAH_Pos (0U)
#define LTDC_AWCR_AAH_Msk (0xffffUL << LTDC_AWCR_AAH_Pos)
#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< accumulated active height (in units of horizontal scan line)These bits define the accumulated height which includes the vertical synchronization, vertical back porch and the active height lines minus 1. The active height is the number of active lines in the panel.Refer to device datasheet for maximum active height supported following maximum pixel clock. */
#define LTDC_AWCR_AAW_Pos (16U)
#define LTDC_AWCR_AAW_Msk (0xffffUL << LTDC_AWCR_AAW_Pos)
#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< accumulated active width (in units of pixel clock period)These bits define the accumulated active width which includes the horizontal synchronization, horizontal back porch and active pixels minus 1.The active width is the number of pixels in active display area of the panel scan line.Refer to device datasheet for maximum active width supported following maximum pixel clock. */
/* Bit fields for LTDC_TWCR register */
#define LTDC_TWCR_TOTALH_Pos (0U)
#define LTDC_TWCR_TOTALH_Msk (0xffffUL << LTDC_TWCR_TOTALH_Pos)
#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< total height (in units of horizontal scan line)These bits defines the accumulated height which includes the vertical synchronization, vertical back porch, the active height and vertical front porch height lines minus 1. */
#define LTDC_TWCR_TOTALW_Pos (16U)
#define LTDC_TWCR_TOTALW_Msk (0xffffUL << LTDC_TWCR_TOTALW_Pos)
#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< total width (in units of pixel clock period)These bits defines the accumulated total width which includes the horizontal synchronization, horizontal back porch, active width and horizontal front porch pixels minus 1. */
/* Bit fields for LTDC_GCR register */
#define LTDC_GCR_LTDCEN_Pos (0U)
#define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos)
#define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: LTDC disable- 1: LTDC enable */
#define LTDC_GCR_GAMEN_Pos (1U)
#define LTDC_GCR_GAMEN_Msk (0x1UL << LTDC_GCR_GAMEN_Pos)
#define LTDC_GCR_GAMEN LTDC_GCR_GAMEN_Msk /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: GammaCorrection disable (pixels bypass the gamma operator)- 1: Gamma Correction enable */
#define LTDC_GCR_ROTEN_Pos (2U)
#define LTDC_GCR_ROTEN_Msk (0x1UL << LTDC_GCR_ROTEN_Pos)
#define LTDC_GCR_ROTEN LTDC_GCR_ROTEN_Msk /*!< LCD-TFT controller enableThis bit is set and cleared by software.- 0: Rotation disable- 1: Rotation enable (for a pure visual rotation, the mirroring has to be activated) */
#define LTDC_GCR_DBW_Pos (4U)
#define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos)
#define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< dither blue widthThese bits return the dither blue bits. */
#define LTDC_GCR_DGW_Pos (8U)
#define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos)
#define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< dither green widthThese bits return the dither green bits. */
#define LTDC_GCR_DRW_Pos (12U)
#define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos)
#define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< dither red widthThese bits return the Dither Red Bits. */
#define LTDC_GCR_DEN_Pos (16U)
#define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos)
#define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< dither enableThis bit is set and cleared by software.- 0: dither disable- 1: dither enable */
#define LTDC_GCR_BCKEN_Pos (17U)
#define LTDC_GCR_BCKEN_Msk (0x1UL << LTDC_GCR_BCKEN_Pos)
#define LTDC_GCR_BCKEN LTDC_GCR_BCKEN_Msk /*!< backgroundlayer enableThis bit is set and cleared by software.- 0: backgrounddisable- 1: background enable */
#define LTDC_GCR_CRCEN_Pos (19U)
#define LTDC_GCR_CRCEN_Msk (0x1UL << LTDC_GCR_CRCEN_Pos)
#define LTDC_GCR_CRCEN LTDC_GCR_CRCEN_Msk /*!< CRC enableThis bit is set and cleared by software.- 0: CRC disable- 1: CRC enable */
#define LTDC_GCR_SFEN_Pos (24U)
#define LTDC_GCR_SFEN_Msk (0x1UL << LTDC_GCR_SFEN_Pos)
#define LTDC_GCR_SFEN LTDC_GCR_SFEN_Msk /*!< single-frame mode: mode enableThis bit is set and cleared by software.- 0: single-frame disable:a trigger (on SFSW or External) will generate a continuous flow.- 1: single-frame enable: a trigger (on SFSW or External) will generate a single frame. */
#define LTDC_GCR_SFSWTR_Pos (25U)
#define LTDC_GCR_SFSWTR_Msk (0x1UL << LTDC_GCR_SFSWTR_Pos)
#define LTDC_GCR_SFSWTR LTDC_GCR_SFSWTR_Msk /*!< single-frame mode: software triggerThis bit is set by software and cleared by hardware.- 0: no action- 1: triggers one frame */
#define LTDC_GCR_SFEXEN_Pos (26U)
#define LTDC_GCR_SFEXEN_Msk (0x1UL << LTDC_GCR_SFEXEN_Pos)
#define LTDC_GCR_SFEXEN LTDC_GCR_SFEXEN_Msk /*!< single-frame mode: external trigger enableThis bit is set and cleared by software.- 0: external trigger disable- 1: external trigger enable: a trigger on the external trigger will generate one single frame. */
#define LTDC_GCR_PCPOL_Pos (28U)
#define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos)
#define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< pixel clock polarityThis bit is set and cleared by software.- 0: pixel clock polarity is active low.- 1: pixel clock is active high. */
#define LTDC_GCR_DEPOL_Pos (29U)
#define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos)
#define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< blanking (=no data/pixel) polarityThis bit is set and cleared by software.- 0: blanking (no data/pixel) polarity is active low.- 1: blanking (no data/pixel) polarity is active high. */
#define LTDC_GCR_VSPOL_Pos (30U)
#define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos)
#define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< vertical synchronization polarityThis bit is set and cleared by software.- 0: vertical synchronization is active low.- 1: vertical synchronization is active high. */
#define LTDC_GCR_HSPOL_Pos (31U)
#define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos)
#define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< horizontal synchronization polarityThis bit is set and cleared by software.- 0: horizontal synchronization polarity is active low.- 1: horizontal synchronization polarity is active high. */
/* Bit fields for LTDC_SRCR register */
#define LTDC_SRCR_IMR_Pos (0U)
#define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos)
#define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
#define LTDC_SRCR_VBR_Pos (1U)
#define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos)
#define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
/* Bit fields for LTDC_GCCR register */
#define LTDC_GCCR_ADDR_Pos (0U)
#define LTDC_GCCR_ADDR_Msk (0xffUL << LTDC_GCCR_ADDR_Pos)
#define LTDC_GCCR_ADDR LTDC_GCCR_ADDR_Msk /*!< address of the R,G,B table where the COMP component is written.When LTDC_GC1R.GCT=2, the gamma is implemented with 8 interpolated segment. In that case, the valid ADDR addresses are: 0, 32, 64, 96, 128, 160, 192, 224, 255.Note that for ADDR=255, the gamma interpolation hardware considers that the address is 256. */
#define LTDC_GCCR_COMP_Pos (8U)
#define LTDC_GCCR_COMP_Msk (0xffUL << LTDC_GCCR_COMP_Pos)
#define LTDC_GCCR_COMP LTDC_GCCR_COMP_Msk /*!< color component to be written, in either (or all) the R,G,B tables.. */
#define LTDC_GCCR_BEN_Pos (16U)
#define LTDC_GCCR_BEN_Msk (0x1UL << LTDC_GCCR_BEN_Pos)
#define LTDC_GCCR_BEN LTDC_GCCR_BEN_Msk /*!< write trigger to the blue table- 0: no action done- 1: COMP is written at ADDR in the Blue table. */
#define LTDC_GCCR_GEN_Pos (17U)
#define LTDC_GCCR_GEN_Msk (0x1UL << LTDC_GCCR_GEN_Pos)
#define LTDC_GCCR_GEN LTDC_GCCR_GEN_Msk /*!< write trigger to the green table- 0: no action done- 1: COMP is written at ADDR in the Green table. */
#define LTDC_GCCR_REN_Pos (18U)
#define LTDC_GCCR_REN_Msk (0x1UL << LTDC_GCCR_REN_Pos)
#define LTDC_GCCR_REN LTDC_GCCR_REN_Msk /*!< write trigger to the red table- 0: no action done- 1: COMP is written at ADDR in the Red table. */
/* Bit fields for LTDC_BCCR register */
#define LTDC_BCCR_BCBLUE_Pos (0U)
#define LTDC_BCCR_BCBLUE_Msk (0xffUL << LTDC_BCCR_BCBLUE_Pos)
#define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< background color blue valueThese bits configure the background blue value. */
#define LTDC_BCCR_BCGREEN_Pos (8U)
#define LTDC_BCCR_BCGREEN_Msk (0xffUL << LTDC_BCCR_BCGREEN_Pos)
#define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< background color green valueThese bits configure the background green value. */
#define LTDC_BCCR_BCRED_Pos (16U)
#define LTDC_BCCR_BCRED_Msk (0xffUL << LTDC_BCCR_BCRED_Pos)
#define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< background color red valueThese bits configure the background red value. */
/* Bit fields for LTDC_IER register */
#define LTDC_IER_LIE_Pos (0U)
#define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos)
#define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
#define LTDC_IER_FUWIE_Pos (1U)
#define LTDC_IER_FUWIE_Msk (0x1UL << LTDC_IER_FUWIE_Pos)
#define LTDC_IER_FUWIE LTDC_IER_FUWIE_Msk /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
#define LTDC_IER_TERRIE_Pos (2U)
#define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos)
#define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
#define LTDC_IER_RRIE_Pos (3U)
#define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos)
#define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
#define LTDC_IER_FUIE_Pos (6U)
#define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos)
#define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
#define LTDC_IER_CRCIE_Pos (7U)
#define LTDC_IER_CRCIE_Msk (0x1UL << LTDC_IER_CRCIE_Pos)
#define LTDC_IER_CRCIE LTDC_IER_CRCIE_Msk /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
#define LTDC_IER_FURIE_Pos (8U)
#define LTDC_IER_FURIE_Msk (0x1UL << LTDC_IER_FURIE_Pos)
#define LTDC_IER_FURIE LTDC_IER_FURIE_Msk /*!< FIFOunderrun at rotation interrupt enableThis bit is set and cleared by software.- 0: FIFOunderrun at rotation interrupt disable- 1: FIFO underrunat rotation interrupt enable */
/* Bit fields for LTDC_ISR register */
#define LTDC_ISR_LIF_Pos (0U)
#define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos)
#define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
#define LTDC_ISR_FUWIF_Pos (1U)
#define LTDC_ISR_FUWIF_Msk (0x1UL << LTDC_ISR_FUWIF_Pos)
#define LTDC_ISR_FUWIF LTDC_ISR_FUWIF_Msk /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
#define LTDC_ISR_TERRIF_Pos (2U)
#define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos)
#define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
#define LTDC_ISR_RRIF_Pos (3U)
#define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos)
#define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
#define LTDC_ISR_FUIF_Pos (6U)
#define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos)
#define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data is read from the FIFO */
#define LTDC_ISR_CRCIF_Pos (7U)
#define LTDC_ISR_CRCIF_Msk (0x1UL << LTDC_ISR_CRCIF_Pos)
#define LTDC_ISR_CRCIF LTDC_ISR_CRCIF_Msk /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when the computed CRC is different from the expected CRC. */
#define LTDC_ISR_FURIF_Pos (8U)
#define LTDC_ISR_FURIF_Msk (0x1UL << LTDC_ISR_FURIF_Pos)
#define LTDC_ISR_FURIF LTDC_ISR_FURIF_Msk /*!< FIFO underrun at rotation interrupt flag- 0: no FIFO underrun at rotation interrupt generated- 1: FIFO underrun at rotation interrupt generated */
/* Bit fields for LTDC_ICR register */
#define LTDC_ICR_CLIF_Pos (0U)
#define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos)
#define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
#define LTDC_ICR_CFUWIF_Pos (1U)
#define LTDC_ICR_CFUWIF_Msk (0x1UL << LTDC_ICR_CFUWIF_Pos)
#define LTDC_ICR_CFUWIF LTDC_ICR_CFUWIF_Msk /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
#define LTDC_ICR_CTERRIF_Pos (2U)
#define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos)
#define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
#define LTDC_ICR_CRRIF_Pos (3U)
#define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos)
#define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
#define LTDC_ICR_CFUIF_Pos (6U)
#define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos)
#define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
#define LTDC_ICR_CCRCIF_Pos (7U)
#define LTDC_ICR_CCRCIF_Msk (0x1UL << LTDC_ICR_CCRCIF_Pos)
#define LTDC_ICR_CCRCIF LTDC_ICR_CCRCIF_Msk /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
#define LTDC_ICR_CFURIF_Pos (8U)
#define LTDC_ICR_CFURIF_Msk (0x1UL << LTDC_ICR_CFURIF_Pos)
#define LTDC_ICR_CFURIF LTDC_ICR_CFURIF_Msk /*!< clears register reload interrupt flag- 0: no effect- 1: clears the FURIF flag in the LTDC_ISR register */
/* Bit fields for LTDC_LIPCR register */
#define LTDC_LIPCR_LIPOS_Pos (0U)
#define LTDC_LIPCR_LIPOS_Msk (0xffffUL << LTDC_LIPCR_LIPOS_Pos)
#define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< line interrupt positionThese bits configure the line interrupt position. */
/* Bit fields for LTDC_CPSR register */
#define LTDC_CPSR_CYPOS_Pos (0U)
#define LTDC_CPSR_CYPOS_Msk (0xffffUL << LTDC_CPSR_CYPOS_Pos)
#define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< current Y positionThese bits return the current Y position. */
#define LTDC_CPSR_CXPOS_Pos (16U)
#define LTDC_CPSR_CXPOS_Msk (0xffffUL << LTDC_CPSR_CXPOS_Pos)
#define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< current X positionThese bits return the current X position. */
/* Bit fields for LTDC_CDSR register */
#define LTDC_CDSR_VDES_Pos (0U)
#define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos)
#define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< vertical data enable display status- 0: active low- 1: active high */
#define LTDC_CDSR_HDES_Pos (1U)
#define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos)
#define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< horizontal data enable display status- 0: active low- 1: active high */
#define LTDC_CDSR_VSYNCS_Pos (2U)
#define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos)
#define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< vertical synchronization display status- 0: active low- 1: active high */
#define LTDC_CDSR_HSYNCS_Pos (3U)
#define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos)
#define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< horizontal synchronization display status- 0: active low- 1: active high */
/* Bit fields for LTDC_EDCR register */
#define LTDC_EDCR_OCYEN_Pos (25U)
#define LTDC_EDCR_OCYEN_Msk (0x1UL << LTDC_EDCR_OCYEN_Pos)
#define LTDC_EDCR_OCYEN LTDC_EDCR_OCYEN_Msk /*!< output conversion to YCbCr 422: Enable- 0: conversion is disabled- 1: conversion is enabled */
#define LTDC_EDCR_OCYSEL_Pos (26U)
#define LTDC_EDCR_OCYSEL_Msk (0x1UL << LTDC_EDCR_OCYSEL_Pos)
#define LTDC_EDCR_OCYSEL LTDC_EDCR_OCYSEL_Msk /*!< output conversion to YCbCr 422: selection of the CCIR hard-wired coefficients:- 0: use CCIR-BT601 set (for typically SDTV analog-like displays)- 1: use CCIR-BT709 set (for typically HDTV digital-like displays) */
#define LTDC_EDCR_OCYCO_Pos (27U)
#define LTDC_EDCR_OCYCO_Msk (0x1UL << LTDC_EDCR_OCYCO_Pos)
#define LTDC_EDCR_OCYCO LTDC_EDCR_OCYCO_Msk /*!< output conversion to YCbCr 422: chrominance order.- 0: Cb is output first (so: Y0Cb, then Y1Cr, Y2Cb, etc .. ).- 1: Cr is output first (so: Y0Cr, then Y1Cb, Y2Cr, etc ..). */
/* Bit fields for LTDC_IER2 register */
#define LTDC_IER2_LIE_Pos (0U)
#define LTDC_IER2_LIE_Msk (0x1UL << LTDC_IER2_LIE_Pos)
#define LTDC_IER2_LIE LTDC_IER2_LIE_Msk /*!< line interrupt enableThis bit is set and cleared by software.- 0: line interrupt disable- 1: line interrupt enable */
#define LTDC_IER2_FUWIE_Pos (1U)
#define LTDC_IER2_FUWIE_Msk (0x1UL << LTDC_IER2_FUWIE_Pos)
#define LTDC_IER2_FUWIE LTDC_IER2_FUWIE_Msk /*!< FIFO underrun warning interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun interrupt disable- 1: FIFO underrun Interrupt enable */
#define LTDC_IER2_TERRIE_Pos (2U)
#define LTDC_IER2_TERRIE_Msk (0x1UL << LTDC_IER2_TERRIE_Pos)
#define LTDC_IER2_TERRIE LTDC_IER2_TERRIE_Msk /*!< transfer error interrupt enableThis bit is set and cleared by software.- 0: transfer error interrupt disable- 1: transfer error interrupt enable */
#define LTDC_IER2_RRIE_Pos (3U)
#define LTDC_IER2_RRIE_Msk (0x1UL << LTDC_IER2_RRIE_Pos)
#define LTDC_IER2_RRIE LTDC_IER2_RRIE_Msk /*!< register reload interrupt enableThis bit is set and cleared by software.- 0: register reload interrupt disable- 1: register reload interrupt enable */
#define LTDC_IER2_FUIE_Pos (6U)
#define LTDC_IER2_FUIE_Msk (0x1UL << LTDC_IER2_FUIE_Pos)
#define LTDC_IER2_FUIE LTDC_IER2_FUIE_Msk /*!< FIFO underrun interrupt enableThis bit is set and cleared by software.- 0: FIFO underrun killing interrupt disable- 1: FIFO underrun killing Interrupt enable */
#define LTDC_IER2_CRCIE_Pos (7U)
#define LTDC_IER2_CRCIE_Msk (0x1UL << LTDC_IER2_CRCIE_Pos)
#define LTDC_IER2_CRCIE LTDC_IER2_CRCIE_Msk /*!< CRC error interrupt enableThis bit is set and cleared by software.- 0: crcerror disable- 1: crc error interrupt enable */
/* Bit fields for LTDC_ISR2 register */
#define LTDC_ISR2_LIF_Pos (0U)
#define LTDC_ISR2_LIF_Msk (0x1UL << LTDC_ISR2_LIF_Pos)
#define LTDC_ISR2_LIF LTDC_ISR2_LIF_Msk /*!< line interrupt flag- 0: no line interrupt generated- 1: line interrupt generated when a programmed line is reached */
#define LTDC_ISR2_FUWIF_Pos (1U)
#define LTDC_ISR2_FUWIF_Msk (0x1UL << LTDC_ISR2_FUWIF_Pos)
#define LTDC_ISR2_FUWIF LTDC_ISR2_FUWIF_Msk /*!< FIFO underrun warning interrupt flag- 0: no FIFO underrun warning interrupt generated.- 1: FIFO underrun warning interrupt generated, if one of the layer FIFOs is empty and pixel data is read from the FIFO */
#define LTDC_ISR2_TERRIF_Pos (2U)
#define LTDC_ISR2_TERRIF_Msk (0x1UL << LTDC_ISR2_TERRIF_Pos)
#define LTDC_ISR2_TERRIF LTDC_ISR2_TERRIF_Msk /*!< transfer error interrupt flag- 0: no transfer error interrupt generated- 1: transfer error interrupt generated when a bus error occurs */
#define LTDC_ISR2_RRIF_Pos (3U)
#define LTDC_ISR2_RRIF_Msk (0x1UL << LTDC_ISR2_RRIF_Pos)
#define LTDC_ISR2_RRIF LTDC_ISR2_RRIF_Msk /*!< register reload interrupt flag- 0: no register reload interrupt generated- 1: register reload interrupt generated when a vertical blanking reload occurs (and the first line after the active area is reached) */
#define LTDC_ISR2_FUIF_Pos (6U)
#define LTDC_ISR2_FUIF_Msk (0x1UL << LTDC_ISR2_FUIF_Pos)
#define LTDC_ISR2_FUIF LTDC_ISR2_FUIF_Msk /*!< FIFO underrun interrupt flag- 0: no FIFO underrun killing interrupt generated.- 1: FIFO underrun killing interrupt generated, if one of the layer FIFOs is empty and many pixel data are read from the FIFO */
#define LTDC_ISR2_CRCIF_Pos (7U)
#define LTDC_ISR2_CRCIF_Msk (0x1UL << LTDC_ISR2_CRCIF_Pos)
#define LTDC_ISR2_CRCIF LTDC_ISR2_CRCIF_Msk /*!< transfer error interrupt flag- 0: no CRC error interrupt generated- 1: CRC error interrupt generated when a bus error occurs */
/* Bit fields for LTDC_ICR2 register */
#define LTDC_ICR2_CLIF_Pos (0U)
#define LTDC_ICR2_CLIF_Msk (0x1UL << LTDC_ICR2_CLIF_Pos)
#define LTDC_ICR2_CLIF LTDC_ICR2_CLIF_Msk /*!< clears the line interrupt flag- 0: no effect- 1: clears the LIF flag in the LTDC_ISR register. */
#define LTDC_ICR2_CFUWIF_Pos (1U)
#define LTDC_ICR2_CFUWIF_Msk (0x1UL << LTDC_ICR2_CFUWIF_Pos)
#define LTDC_ICR2_CFUWIF LTDC_ICR2_CFUWIF_Msk /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUWIF flag in the LTDC_ISR register. */
#define LTDC_ICR2_CTERRIF_Pos (2U)
#define LTDC_ICR2_CTERRIF_Msk (0x1UL << LTDC_ICR2_CTERRIF_Pos)
#define LTDC_ICR2_CTERRIF LTDC_ICR2_CTERRIF_Msk /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the TERRIF flag in the LTDC_ISR register. */
#define LTDC_ICR2_CRRIF_Pos (3U)
#define LTDC_ICR2_CRRIF_Msk (0x1UL << LTDC_ICR2_CRRIF_Pos)
#define LTDC_ICR2_CRRIF LTDC_ICR2_CRRIF_Msk /*!< clears register reload interrupt flag- 0: no effect- 1: clears the RRIF flag in the LTDC_ISR register */
#define LTDC_ICR2_CFUIF_Pos (6U)
#define LTDC_ICR2_CFUIF_Msk (0x1UL << LTDC_ICR2_CFUIF_Pos)
#define LTDC_ICR2_CFUIF LTDC_ICR2_CFUIF_Msk /*!< clears the FIFO underrun warning interrupt flag- 0: no effect- 1: clears the FUKIF flag in the LTDC_ISR register. */
#define LTDC_ICR2_CCRCIF_Pos (7U)
#define LTDC_ICR2_CCRCIF_Msk (0x1UL << LTDC_ICR2_CCRCIF_Pos)
#define LTDC_ICR2_CCRCIF LTDC_ICR2_CCRCIF_Msk /*!< clears the transfer error interrupt flag- 0: no effect- 1: clears the CRCIF flag in the LTDC_ISR register. */
/* Bit fields for LTDC_LIPCR2 register */
#define LTDC_LIPCR2_LIPOS_Pos (0U)
#define LTDC_LIPCR2_LIPOS_Msk (0xffffUL << LTDC_LIPCR2_LIPOS_Pos)
#define LTDC_LIPCR2_LIPOS LTDC_LIPCR2_LIPOS_Msk /*!< line interrupt positionThese bits configure the line interrupt position. */
/* Bit fields for LTDC_CPSR2 register */
#define LTDC_CPSR2_CYPOS_Pos (0U)
#define LTDC_CPSR2_CYPOS_Msk (0xffffUL << LTDC_CPSR2_CYPOS_Pos)
#define LTDC_CPSR2_CYPOS LTDC_CPSR2_CYPOS_Msk /*!< current Y positionThese bits return the current Y position. */
#define LTDC_CPSR2_CXPOS_Pos (16U)
#define LTDC_CPSR2_CXPOS_Msk (0xffffUL << LTDC_CPSR2_CXPOS_Pos)
#define LTDC_CPSR2_CXPOS LTDC_CPSR2_CXPOS_Msk /*!< current X positionThese bits return the current X position. */
/* Bit fields for LTDC_ECRCR register */
#define LTDC_ECRCR_ECRC_Pos (0U)
#define LTDC_ECRCR_ECRC_Msk (0xffffUL << LTDC_ECRCR_ECRC_Pos)
#define LTDC_ECRCR_ECRC LTDC_ECRCR_ECRC_Msk /*!< expected CRC of frame */
/* Bit fields for LTDC_CCRCR register */
#define LTDC_CCRCR_CCRC_Pos (0U)
#define LTDC_CCRCR_CCRC_Msk (0xffffUL << LTDC_CCRCR_CCRC_Pos)
#define LTDC_CCRCR_CCRC LTDC_CCRCR_CCRC_Msk /*!< expected CRC of frame */
/* Bit fields for LTDC_FUTR register */
#define LTDC_FUTR_THRE_Pos (0U)
#define LTDC_FUTR_THRE_Msk (0xffffUL << LTDC_FUTR_THRE_Pos)
#define LTDC_FUTR_THRE LTDC_FUTR_THRE_Msk /*!< threshold to trigger a FIFO underrun killing interrupt (unit is per fifo word, 64bit) */
/* Bit fields for LTDC_LxC0R register */
#define LTDC_LxC0R_CKTA_Pos (0U)
#define LTDC_LxC0R_CKTA_Msk (0x1UL << LTDC_LxC0R_CKTA_Pos)
#define LTDC_LxC0R_CKTA LTDC_LxC0R_CKTA_Msk /*!< color key transparency Ability */
#define LTDC_LxC0R_CFBDA_Pos (1U)
#define LTDC_LxC0R_CFBDA_Msk (0x1UL << LTDC_LxC0R_CFBDA_Pos)
#define LTDC_LxC0R_CFBDA LTDC_LxC0R_CFBDA_Msk /*!< color frame buffer duplication ability */
#define LTDC_LxC0R_CFBPA_Pos (2U)
#define LTDC_LxC0R_CFBPA_Msk (0x1UL << LTDC_LxC0R_CFBPA_Pos)
#define LTDC_LxC0R_CFBPA LTDC_LxC0R_CFBPA_Msk /*!< color frame buffer pitch ability */
#define LTDC_LxC0R_APA_Pos (3U)
#define LTDC_LxC0R_APA_Msk (0x1UL << LTDC_LxC0R_APA_Pos)
#define LTDC_LxC0R_APA LTDC_LxC0R_APA_Msk /*!< alpha plane ability */
#define LTDC_LxC0R_DCP_Pos (4U)
#define LTDC_LxC0R_DCP_Msk (0x1UL << LTDC_LxC0R_DCP_Pos)
#define LTDC_LxC0R_DCP LTDC_LxC0R_DCP_Msk /*!< default color programmability */
#define LTDC_LxC0R_WINA_Pos (5U)
#define LTDC_LxC0R_WINA_Msk (0x1UL << LTDC_LxC0R_WINA_Pos)
#define LTDC_LxC0R_WINA LTDC_LxC0R_WINA_Msk /*!< windowing ability */
#define LTDC_LxC0R_CLUTA_Pos (6U)
#define LTDC_LxC0R_CLUTA_Msk (0x1UL << LTDC_LxC0R_CLUTA_Pos)
#define LTDC_LxC0R_CLUTA LTDC_LxC0R_CLUTA_Msk /*!< CLUT ability */
#define LTDC_LxC0R_CKRA_Pos (7U)
#define LTDC_LxC0R_CKRA_Msk (0x1UL << LTDC_LxC0R_CKRA_Pos)
#define LTDC_LxC0R_CKRA LTDC_LxC0R_CKRA_Msk /*!< color key replace ability */
#define LTDC_LxC0R_F21_Pos (8U)
#define LTDC_LxC0R_F21_Msk (0x1UL << LTDC_LxC0R_F21_Pos)
#define LTDC_LxC0R_F21 LTDC_LxC0R_F21_Msk /*!< blending factor 2, ability for: 1.0 */
#define LTDC_LxC0R_F20_Pos (9U)
#define LTDC_LxC0R_F20_Msk (0x1UL << LTDC_LxC0R_F20_Pos)
#define LTDC_LxC0R_F20 LTDC_LxC0R_F20_Msk /*!< blending factor 2, ability for: 0.0 */
#define LTDC_LxC0R_F2P_Pos (10U)
#define LTDC_LxC0R_F2P_Msk (0x1UL << LTDC_LxC0R_F2P_Pos)
#define LTDC_LxC0R_F2P LTDC_LxC0R_F2P_Msk /*!< blending factor 2, ability for: pixel_alpha */
#define LTDC_LxC0R_F21P_Pos (11U)
#define LTDC_LxC0R_F21P_Msk (0x1UL << LTDC_LxC0R_F21P_Pos)
#define LTDC_LxC0R_F21P LTDC_LxC0R_F21P_Msk /*!< blending factor 2, ability for: 1.0 - pixel_alpha */
#define LTDC_LxC0R_F2C_Pos (12U)
#define LTDC_LxC0R_F2C_Msk (0x1UL << LTDC_LxC0R_F2C_Pos)
#define LTDC_LxC0R_F2C LTDC_LxC0R_F2C_Msk /*!< blending factor 2, ability for: constant_alpha */
#define LTDC_LxC0R_F21C_Pos (13U)
#define LTDC_LxC0R_F21C_Msk (0x1UL << LTDC_LxC0R_F21C_Pos)
#define LTDC_LxC0R_F21C LTDC_LxC0R_F21C_Msk /*!< blending factor 2, ability for: 1.0 - constant_alpha */
#define LTDC_LxC0R_F2PC_Pos (14U)
#define LTDC_LxC0R_F2PC_Msk (0x1UL << LTDC_LxC0R_F2PC_Pos)
#define LTDC_LxC0R_F2PC LTDC_LxC0R_F2PC_Msk /*!< blending factor 2, ability for: pixel_alpha * constant_alpha */
#define LTDC_LxC0R_F21PC_Pos (15U)
#define LTDC_LxC0R_F21PC_Msk (0x1UL << LTDC_LxC0R_F21PC_Pos)
#define LTDC_LxC0R_F21PC LTDC_LxC0R_F21PC_Msk /*!< blending factor 2, ability for: 1.0 - (pixel_alpha * constant_alpha) */
#define LTDC_LxC0R_F11_Pos (16U)
#define LTDC_LxC0R_F11_Msk (0x1UL << LTDC_LxC0R_F11_Pos)
#define LTDC_LxC0R_F11 LTDC_LxC0R_F11_Msk /*!< blending factor 1, ability for: 1.0 */
#define LTDC_LxC0R_F10_Pos (17U)
#define LTDC_LxC0R_F10_Msk (0x1UL << LTDC_LxC0R_F10_Pos)
#define LTDC_LxC0R_F10 LTDC_LxC0R_F10_Msk /*!< blending factor 1,ability for: 0.0 */
#define LTDC_LxC0R_F1P_Pos (18U)
#define LTDC_LxC0R_F1P_Msk (0x1UL << LTDC_LxC0R_F1P_Pos)
#define LTDC_LxC0R_F1P LTDC_LxC0R_F1P_Msk /*!< blending factor 1, ability for: pixel_alpha */
#define LTDC_LxC0R_F11P_Pos (19U)
#define LTDC_LxC0R_F11P_Msk (0x1UL << LTDC_LxC0R_F11P_Pos)
#define LTDC_LxC0R_F11P LTDC_LxC0R_F11P_Msk /*!< blending factor 1, ability for: 1.0 - pixel_alpha */
#define LTDC_LxC0R_F1C_Pos (20U)
#define LTDC_LxC0R_F1C_Msk (0x1UL << LTDC_LxC0R_F1C_Pos)
#define LTDC_LxC0R_F1C LTDC_LxC0R_F1C_Msk /*!< blending factor 1, ability for: constant_alpha */
#define LTDC_LxC0R_F11C_Pos (21U)
#define LTDC_LxC0R_F11C_Msk (0x1UL << LTDC_LxC0R_F11C_Pos)
#define LTDC_LxC0R_F11C LTDC_LxC0R_F11C_Msk /*!< blending factor 1, ability for: 1.0 - constant_alpha */
#define LTDC_LxC0R_F1PC_Pos (22U)
#define LTDC_LxC0R_F1PC_Msk (0x1UL << LTDC_LxC0R_F1PC_Pos)
#define LTDC_LxC0R_F1PC LTDC_LxC0R_F1PC_Msk /*!< blending factor 1, ability for: pixel_alpha * constant_alpha */
#define LTDC_LxC0R_F11PC_Pos (23U)
#define LTDC_LxC0R_F11PC_Msk (0x1UL << LTDC_LxC0R_F11PC_Pos)
#define LTDC_LxC0R_F11PC LTDC_LxC0R_F11PC_Msk /*!< blending factor 1, ability for: 1.0 - (pixel_alpha * constant_alpha) */
#define LTDC_LxC0R_P88_Pos (24U)
#define LTDC_LxC0R_P88_Msk (0x1UL << LTDC_LxC0R_P88_Pos)
#define LTDC_LxC0R_P88 LTDC_LxC0R_P88_Msk /*!< pixel format, ability for: AL88. */
#define LTDC_LxC0R_P44_Pos (25U)
#define LTDC_LxC0R_P44_Msk (0x1UL << LTDC_LxC0R_P44_Pos)
#define LTDC_LxC0R_P44 LTDC_LxC0R_P44_Msk /*!< pixel format, ability for: AL44. */
#define LTDC_LxC0R_P8_Pos (26U)
#define LTDC_LxC0R_P8_Msk (0x1UL << LTDC_LxC0R_P8_Pos)
#define LTDC_LxC0R_P8 LTDC_LxC0R_P8_Msk /*!< pixel format, ability for: L8. */
#define LTDC_LxC0R_P4444_Pos (27U)
#define LTDC_LxC0R_P4444_Msk (0x1UL << LTDC_LxC0R_P4444_Pos)
#define LTDC_LxC0R_P4444 LTDC_LxC0R_P4444_Msk /*!< pixel format, ability for: ARGB4444. */
#define LTDC_LxC0R_P1555_Pos (28U)
#define LTDC_LxC0R_P1555_Msk (0x1UL << LTDC_LxC0R_P1555_Pos)
#define LTDC_LxC0R_P1555 LTDC_LxC0R_P1555_Msk /*!< pixel format, ability for: ARGB1555. */
#define LTDC_LxC0R_P565_Pos (29U)
#define LTDC_LxC0R_P565_Msk (0x1UL << LTDC_LxC0R_P565_Pos)
#define LTDC_LxC0R_P565 LTDC_LxC0R_P565_Msk /*!< pixel format, ability for: RGB565. */
#define LTDC_LxC0R_P888_Pos (30U)
#define LTDC_LxC0R_P888_Msk (0x1UL << LTDC_LxC0R_P888_Pos)
#define LTDC_LxC0R_P888 LTDC_LxC0R_P888_Msk /*!< pixel format, ability for: RGB888. */
#define LTDC_LxC0R_P8888_Pos (31U)
#define LTDC_LxC0R_P8888_Msk (0x1UL << LTDC_LxC0R_P8888_Pos)
#define LTDC_LxC0R_P8888 LTDC_LxC0R_P8888_Msk /*!< pixel format, ability for: ARGB8888. */
/* Bit fields for LTDC_LxC1R register */
#define LTDC_LxC1R_YIA_Pos (0U)
#define LTDC_LxC1R_YIA_Msk (0x1UL << LTDC_LxC1R_YIA_Pos)
#define LTDC_LxC1R_YIA LTDC_LxC1R_YIA_Msk /*!< YCbCr 422 interleaved ability for that layer.- 0: interleaved not available- 1: interleaved available */
#define LTDC_LxC1R_YSPA_Pos (1U)
#define LTDC_LxC1R_YSPA_Msk (0x1UL << LTDC_LxC1R_YSPA_Pos)
#define LTDC_LxC1R_YSPA LTDC_LxC1R_YSPA_Msk /*!< YCbCr 420 semi-planar ability for that layer.- 0: semiplanar not available- 1: semi-planar available */
#define LTDC_LxC1R_YFPA_Pos (2U)
#define LTDC_LxC1R_YFPA_Msk (0x1UL << LTDC_LxC1R_YFPA_Pos)
#define LTDC_LxC1R_YFPA LTDC_LxC1R_YFPA_Msk /*!< YCbCr 420 full-planar ability for that layer.- 0: full planar not available- 1: full planar available */
#define LTDC_LxC1R_SCA_Pos (31U)
#define LTDC_LxC1R_SCA_Msk (0x1UL << LTDC_LxC1R_SCA_Pos)
#define LTDC_LxC1R_SCA LTDC_LxC1R_SCA_Msk /*!< scaling ability for that layer.- 0: scaling not available- 1: scaling available */
/* Bit fields for LTDC_LxRCR register */
#define LTDC_LxRCR_IMR_Pos (0U)
#define LTDC_LxRCR_IMR_Msk (0x1UL << LTDC_LxRCR_IMR_Pos)
#define LTDC_LxRCR_IMR LTDC_LxRCR_IMR_Msk /*!< immediate reload triggerThis bit is set by software and cleared only by hardware after reload.- 0: no effect- 1: The shadow registers are reloaded immediately. */
#define LTDC_LxRCR_VBR_Pos (1U)
#define LTDC_LxRCR_VBR_Msk (0x1UL << LTDC_LxRCR_VBR_Pos)
#define LTDC_LxRCR_VBR LTDC_LxRCR_VBR_Msk /*!< vertical blanking reload requestThis bit is set by software and cleared only by hardware after reload (it cannot be cleared through register write once it is set).- 0: no effect- 1: The shadow registers are reloaded during the vertical blanking period (at the beginning of the first line after the active display area). */
#define LTDC_LxRCR_GRMSK_Pos (2U)
#define LTDC_LxRCR_GRMSK_Msk (0x1UL << LTDC_LxRCR_GRMSK_Pos)
#define LTDC_LxRCR_GRMSK LTDC_LxRCR_GRMSK_Msk /*!< shadow reload control: global (centralized) reload maskedThis bit is set and cleared by software.- 0: global reload active (the control from the LTDC_SRCR are enabled)- 1: global reload is masked (the control from the LTDC_SRCR are disabled) */
/* Bit fields for LTDC_LxCR register */
#define LTDC_LxCR_LEN_Pos (0U)
#define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos)
#define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< layer enable: the bit is used to enable/disable the presence of this whole layer.This bit is set and cleared by software.- 0: layer disabled- 1: layer enabled */
#define LTDC_LxCR_CKEN_Pos (1U)
#define LTDC_LxCR_CKEN_Msk (0x1UL << LTDC_LxCR_CKEN_Pos)
#define LTDC_LxCR_CKEN LTDC_LxCR_CKEN_Msk /*!< color keying enableThis bit is set and cleared by software.- 0: color keying disabled- 1: color keying enabled: if RGB matches, then the ARGB are set to 0. */
#define LTDC_LxCR_VPDEN_Pos (2U)
#define LTDC_LxCR_VPDEN_Msk (0x1UL << LTDC_LxCR_VPDEN_Pos)
#define LTDC_LxCR_VPDEN LTDC_LxCR_VPDEN_Msk /*!< vertical pixel duplication enableThis bit is set and cleared by software.- 0: duplication disabled- 1: duplication enabled */
#define LTDC_LxCR_CLUTEN_Pos (4U)
#define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos)
#define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< color look-up table enableThis bit is set and cleared by software.- 0: color look-up table disabled- 1: color look-up table enabledThe CLUT is only meaningful for L8, AL44 and AL88 pixel format. Refer to Color look-up table (CLUT) */
#define LTDC_LxCR_HMEN_Pos (8U)
#define LTDC_LxCR_HMEN_Msk (0x1UL << LTDC_LxCR_HMEN_Pos)
#define LTDC_LxCR_HMEN LTDC_LxCR_HMEN_Msk /*!< horizontal mirroring enableThis bit is set and cleared by software.- 0: mirror disabled- 1: mirror enabled (if so, the color frame buffer start address has to be set to the last byte of the first line, so for instannce: if line is 100 pixels, 24bpp, then address is set to 299) */
#define LTDC_LxCR_DCBEN_Pos (9U)
#define LTDC_LxCR_DCBEN_Msk (0x1UL << LTDC_LxCR_DCBEN_Pos)
#define LTDC_LxCR_DCBEN LTDC_LxCR_DCBEN_Msk /*!< default color blending enableThis bit is set and cleared by software.- 0: blending disabled- 1: blending enabled */
/* Bit fields for LTDC_LxWHPCR register */
#define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
#define LTDC_LxWHPCR_WHSTPOS_Msk (0xffffUL << LTDC_LxWHPCR_WHSTPOS_Pos)
#define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< window horizontal start positionThese bits configure the first visible pixel of a line of the layer window.WHSTPOS[15:0] must be >= AAW[15:0] bits (programmed in LTDC_AWCR register). */
#define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
#define LTDC_LxWHPCR_WHSPPOS_Msk (0xffffUL << LTDC_LxWHPCR_WHSPPOS_Pos)
#define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< window horizontal stop positionThese bits configure the last visible pixel of a line of the layer window.WHSPPOS[15:0] must be <= AHBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
/* Bit fields for LTDC_LxWVPCR register */
#define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
#define LTDC_LxWVPCR_WVSTPOS_Msk (0xffffUL << LTDC_LxWVPCR_WVSTPOS_Pos)
#define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< window vertical start positionThese bits configure the first visible line of the layer window.WVSTPOS[15:0] must be >= AAH[15:0] bits (programmed in LTDC_AWCR register). */
#define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
#define LTDC_LxWVPCR_WVSPPOS_Msk (0xffffUL << LTDC_LxWVPCR_WVSPPOS_Pos)
#define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< window vertical stop positionThese bits configure the last visible line of the layer window.WVSPPOS[11:0] must be <= AVBP[15:0] bits + 1 (programmed in LTDC_BPCR register). */
/* Bit fields for LTDC_LxCKCR register */
#define LTDC_LxCKCR_CKBLUE_Pos (0U)
#define LTDC_LxCKCR_CKBLUE_Msk (0xffUL << LTDC_LxCKCR_CKBLUE_Pos)
#define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< color key blue value */
#define LTDC_LxCKCR_CKGREEN_Pos (8U)
#define LTDC_LxCKCR_CKGREEN_Msk (0xffUL << LTDC_LxCKCR_CKGREEN_Pos)
#define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< color key green value */
#define LTDC_LxCKCR_CKRED_Pos (16U)
#define LTDC_LxCKCR_CKRED_Msk (0xffUL << LTDC_LxCKCR_CKRED_Pos)
#define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< color key red value */
/* Bit fields for LTDC_LxPFCR register */
#define LTDC_LxPFCR_PF_Pos (0U)
#define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos)
#define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< pixel formatThese bits configure the pixel format- 000: ARGB8888- 001: RGB888- 010: RGB565- 011: ARGB1555- 100: ARGB4444- 101: L8 (8-bit luminance)- 110: AL44 (4-bit alpha, 4-bit luminance)- 111: AL88 (8-bit alpha, 8-bit luminance) */
/* Bit fields for LTDC_LxCACR register */
#define LTDC_LxCACR_CONSTA_Pos (0U)
#define LTDC_LxCACR_CONSTA_Msk (0xffUL << LTDC_LxCACR_CONSTA_Pos)
#define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< constant alphaThese bits configure the constant alpha used for blending. The constant alpha is divided by 255 by hardware.Example: if the programmed constant alpha is 0xFF, the constant alpha value is 255 / 255 = 1. */
/* Bit fields for LTDC_LxDCCR register */
#define LTDC_LxDCCR_DCBLUE_Pos (0U)
#define LTDC_LxDCCR_DCBLUE_Msk (0xffUL << LTDC_LxDCCR_DCBLUE_Pos)
#define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< default color blueThese bits configure the default blue value. */
#define LTDC_LxDCCR_DCGREEN_Pos (8U)
#define LTDC_LxDCCR_DCGREEN_Msk (0xffUL << LTDC_LxDCCR_DCGREEN_Pos)
#define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< default color greenThese bits configure the default green value. */
#define LTDC_LxDCCR_DCRED_Pos (16U)
#define LTDC_LxDCCR_DCRED_Msk (0xffUL << LTDC_LxDCCR_DCRED_Pos)
#define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< default color redThese bits configure the default red value. */
#define LTDC_LxDCCR_DCALPHA_Pos (24U)
#define LTDC_LxDCCR_DCALPHA_Msk (0xffUL << LTDC_LxDCCR_DCALPHA_Pos)
#define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< default color alphaThese bits configure the default alpha value. */
/* Bit fields for LTDC_LxBFCR register */
#define LTDC_LxBFCR_BF2_Pos (0U)
#define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos)
#define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< blending factor 2These bits select the blending factor F2- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: reserved- 101: 1 - constant alpha- 110: reserved- 111: 1 - (pixel alpha x constant alpha) */
#define LTDC_LxBFCR_BF1_Pos (8U)
#define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos)
#define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< blending factor 1These bits select the blending factor F1.- 000: reserved- 001: reserved- 010: reserved- 011: reserved- 100: constant alpha- 101: reserved- 110: pixel alpha x constant alpha- 111: reserved */
#define LTDC_LxBFCR_BOR_Pos (16U)
#define LTDC_LxBFCR_BOR_Msk (0x1UL << LTDC_LxBFCR_BOR_Pos)
#define LTDC_LxBFCR_BOR LTDC_LxBFCR_BOR_Msk /*!< blending orderThese bits select the blending orderBOR.BOR= 0000 is for the most background layer (usually hidden behind others)BOR= 1111 is for the most foreground layer (always visible, never hidden by any other).In case of inconsistency, like two layers at same order, the blending engine reverses to BOR[LayerID] = LayerID-1, so that Layer3 is in foreground and Layer1 is in background.Note: if the Layer3 is set as secure, to guarantee it is on the foreground, it should be configured with BOR(Layer3)=1111. */
/* Bit fields for LTDC_LxBLCR register */
#define LTDC_LxBLCR_BL_Pos (0U)
#define LTDC_LxBLCR_BL_Msk (0xffUL << LTDC_LxBLCR_BL_Pos)
#define LTDC_LxBLCR_BL LTDC_LxBLCR_BL_Msk /*!< burst length- 0x00: maximum burst length (16 words 64bit, thus 128 Bytes)- 0x01: 1 word (of 64bit) per burst..- 0x10: 16 words (of 64bit) per burst- 0x11: reserved...- 0xFF: reserved. */
/* Bit fields for LTDC_LxPCR register */
#define LTDC_LxPCR_YCEN_Pos (3U)
#define LTDC_LxPCR_YCEN_Msk (0x1UL << LTDC_LxPCR_YCEN_Pos)
#define LTDC_LxPCR_YCEN LTDC_LxPCR_YCEN_Msk /*!< YCbCr-to-RGB Conversion Enable:- 0: conversion disabled.- 1: YCbCr conversion enabled, using the YCM setting above. */
#define LTDC_LxPCR_YCM_Pos (4U)
#define LTDC_LxPCR_YCM_Msk (0x3UL << LTDC_LxPCR_YCM_Pos)
#define LTDC_LxPCR_YCM LTDC_LxPCR_YCM_Msk /*!< YCbCr Conversion ModeDefined the type of input that is considered and converted to a YCbCr 444:- 00: interleaved 422 (Cb and Cr component are replicated horizontally for pixels P and P+1)- 01: semi-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 10: full-Planar 420: (Cb and Cr component are replicated horizontally and vertically. The layer main configuration defines the access to the Y buffer, and auxiliary registers define the access to the Cb and Cr buffers).- 11: reserved. */
#define LTDC_LxPCR_YF_Pos (6U)
#define LTDC_LxPCR_YF_Msk (0x1UL << LTDC_LxPCR_YF_Pos)
#define LTDC_LxPCR_YF LTDC_LxPCR_YF_Msk /*!< Y Component FirstDefines if the byte 0 of a word (in LSB) contains the Y component.- 0: Y component disabled (thus Cr or Cb component is on byte 0)- 1: Y component enabled (thus Y component is on byte 0) */
#define LTDC_LxPCR_CBF_Pos (7U)
#define LTDC_LxPCR_CBF_Msk (0x1UL << LTDC_LxPCR_CBF_Pos)
#define LTDC_LxPCR_CBF LTDC_LxPCR_CBF_Msk /*!< Cb Component FirstDefines if the byte 0 and 1 of a word (in LSB) contains the Cb component. The setting impacts only for interleaved and semi-planar modes, as it has no meaning in full-planar mode)- 0: Cb disabled (thus Cr component is on byte 0 and 1)- 1: Cb enabled (thus Cb component is on byte 0 and 1) */
#define LTDC_LxPCR_OF_Pos (8U)
#define LTDC_LxPCR_OF_Msk (0x1UL << LTDC_LxPCR_OF_Pos)
#define LTDC_LxPCR_OF LTDC_LxPCR_OF_Msk /*!< Odd Pixel FirstDefines if the byte 0 of a word (in LSB) contains the Odd pixel.- 0: odd pixel disabled (thus even pixel on byte 0)- 1: odd pixel enabled (thus odd pixel on byte 0) */
#define LTDC_LxPCR_YREN_Pos (9U)
#define LTDC_LxPCR_YREN_Msk (0x1UL << LTDC_LxPCR_YREN_Pos)
#define LTDC_LxPCR_YREN LTDC_LxPCR_YREN_Msk /*!< Y Rescale EnableWhen enabled, incoming Y values in range 16..235 are re-scaled to range 0..255, - 0: rescaling disabled.- 1: rescaling enabled. */
/* Bit fields for LTDC_LxCFBAR register */
#define LTDC_LxCFBAR_CFBADD_Pos (0U)
#define LTDC_LxCFBAR_CFBADD_Msk (0xffffffffUL << LTDC_LxCFBAR_CFBADD_Pos)
#define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
/* Bit fields for LTDC_LxCFBLR register */
#define LTDC_LxCFBLR_CFBLL_Pos (0U)
#define LTDC_LxCFBLR_CFBLL_Msk (0xffffUL << LTDC_LxCFBLR_CFBLL_Pos)
#define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
#define LTDC_LxCFBLR_CFBP_Pos (16U)
#define LTDC_LxCFBLR_CFBP_Msk (0xffffUL << LTDC_LxCFBLR_CFBP_Pos)
#define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
/* Bit fields for LTDC_LxCFBLNR register */
#define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
#define LTDC_LxCFBLNR_CFBLNBR_Msk (0xffffUL << LTDC_LxCFBLNR_CFBLNBR_Pos)
#define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
/* Bit fields for LTDC_L1AFBA0R register */
#define LTDC_L1AFBA0R_AFBADD0_Pos (0U)
#define LTDC_L1AFBA0R_AFBADD0_Msk (0xffffffffUL << LTDC_L1AFBA0R_AFBADD0_Pos)
#define LTDC_L1AFBA0R_AFBADD0 LTDC_L1AFBA0R_AFBADD0_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
/* Bit fields for LTDC_LxAFBA1R register */
#define LTDC_L1AFBA1R_AFBADD1_Pos (0U)
#define LTDC_L1AFBA1R_AFBADD1_Msk (0xffffffffUL << LTDC_L1AFBA1R_AFBADD1_Pos)
#define LTDC_L1AFBA1R_AFBADD1 LTDC_L1AFBA1R_AFBADD1_Msk /*!< color frame buffer start addressThese bits define the color frame buffer start address. */
/* Bit fields for LTDC_LxAFBLR register */
#define LTDC_L1AFBLR_AFBLL_Pos (0U)
#define LTDC_L1AFBLR_AFBLL_Msk (0xffffUL << LTDC_L1AFBLR_AFBLL_Pos)
#define LTDC_L1AFBLR_AFBLL LTDC_L1AFBLR_AFBLL_Msk /*!< color frame buffer line lengthThese bits define the length of one line of pixels in bytes + 7.The line length is computed as follows:active high width * number of bytes per pixel + 7. */
#define LTDC_L1AFBLR_AFBP_Pos (16U)
#define LTDC_L1AFBLR_AFBP_Msk (0xffffUL << LTDC_L1AFBLR_AFBP_Pos)
#define LTDC_L1AFBLR_AFBP LTDC_L1AFBLR_AFBP_Msk /*!< color frame buffer pitch in bytesThese bits define the pitch that is the increment from the start of one line of pixels to the start of the next line in bytes.Negative values (with msb bit = 1) are allowed, to read the buffer from bottom to top, and thus to flip is vertically. When vertically flipped, as the address register must provide the address of the first line to be read, the address register must point to the start of the bottom line of the buffer. */
/* Bit fields for LTDC_LxAFBLNR register */
#define LTDC_L1AFBLNR_AFBLNBR_Pos (0U)
#define LTDC_L1AFBLNR_AFBLNBR_Msk (0xffffUL << LTDC_L1AFBLNR_AFBLNBR_Pos)
#define LTDC_L1AFBLNR_AFBLNBR LTDC_L1AFBLNR_AFBLNBR_Msk /*!< frame buffer line numberThese bits define the number of lines in the frame buffer that corresponds to the active high width. */
/* Bit fields for LTDC_LxCLUTWR register */
#define LTDC_LxCLUTWR_BLUE_Pos (0U)
#define LTDC_LxCLUTWR_BLUE_Msk (0xffUL << LTDC_LxCLUTWR_BLUE_Pos)
#define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< blue valueThese bits configure the blue value. */
#define LTDC_LxCLUTWR_GREEN_Pos (8U)
#define LTDC_LxCLUTWR_GREEN_Msk (0xffUL << LTDC_LxCLUTWR_GREEN_Pos)
#define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< green valueThese bits configure the green value. */
#define LTDC_LxCLUTWR_RED_Pos (16U)
#define LTDC_LxCLUTWR_RED_Msk (0xffUL << LTDC_LxCLUTWR_RED_Pos)
#define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< red valueThese bits configure the red value. */
#define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
#define LTDC_LxCLUTWR_CLUTADD_Msk (0xffUL << LTDC_LxCLUTWR_CLUTADD_Pos)
#define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT addressThese bits configure the CLUT address (color position within the CLUT) of each RGB value. */
/* Bit fields for LTDC_LxCYR0R register */
#define LTDC_LxCYR0R_CR2R_Pos (0U)
#define LTDC_LxCYR0R_CR2R_Msk (0x3ffUL << LTDC_LxCYR0R_CR2R_Pos)
#define LTDC_LxCYR0R_CR2R LTDC_LxCYR0R_CR2R_Msk /*!< Cr-to-Red coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
#define LTDC_LxCYR0R_CB2B_Pos (16U)
#define LTDC_LxCYR0R_CB2B_Msk (0x3ffUL << LTDC_LxCYR0R_CB2B_Pos)
#define LTDC_LxCYR0R_CB2B LTDC_LxCYR0R_CB2B_Msk /*!< Cb-to-Blue coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
/* Bit fields for LTDC_LxCYR1R register */
#define LTDC_LxCYR1R_CR2G_Pos (0U)
#define LTDC_LxCYR1R_CR2G_Msk (0x3ffUL << LTDC_LxCYR1R_CR2G_Pos)
#define LTDC_LxCYR1R_CR2G LTDC_LxCYR1R_CR2G_Msk /*!< Cr-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
#define LTDC_LxCYR1R_CB2G_Pos (16U)
#define LTDC_LxCYR1R_CB2G_Msk (0x3ffUL << LTDC_LxCYR1R_CB2G_Pos)
#define LTDC_LxCYR1R_CB2G LTDC_LxCYR1R_CB2G_Msk /*!< Cb-to-Green coefficient, with bits 9:8 as positive integer and 7:0 as decimals. */
/* Bit fields for LTDC_LxFPF0R register */
#define LTDC_LxFPF0R_APOS_Pos (0U)
#define LTDC_LxFPF0R_APOS_Msk (0x1fUL << LTDC_LxFPF0R_APOS_Pos)
#define LTDC_LxFPF0R_APOS LTDC_LxFPF0R_APOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */
#define LTDC_LxFPF0R_ALEN_Pos (5U)
#define LTDC_LxFPF0R_ALEN_Msk (0x1fUL << LTDC_LxFPF0R_ALEN_Pos)
#define LTDC_LxFPF0R_ALEN LTDC_LxFPF0R_ALEN_Msk /*!< Width of the alpha component (in bits). */
#define LTDC_LxFPF0R_RPOS_Pos (9U)
#define LTDC_LxFPF0R_RPOS_Msk (0x1fUL << LTDC_LxFPF0R_RPOS_Pos)
#define LTDC_LxFPF0R_RPOS LTDC_LxFPF0R_RPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */
#define LTDC_LxFPF0R_RLEN_Pos (14U)
#define LTDC_LxFPF0R_RLEN_Msk (0x1fUL << LTDC_LxFPF0R_RLEN_Pos)
#define LTDC_LxFPF0R_RLEN LTDC_LxFPF0R_RLEN_Msk /*!< Width of the red component (in bits). */
/* Bit fields for LTDC_LxFPF1R register */
#define LTDC_LxFPF1R_GPOS_Pos (0U)
#define LTDC_LxFPF1R_GPOS_Msk (0x1fUL << LTDC_LxFPF1R_GPOS_Pos)
#define LTDC_LxFPF1R_GPOS LTDC_LxFPF1R_GPOS_Msk /*!< Location of the alpha component inside the pixel memory word (in bits). */
#define LTDC_LxFPF1R_GLEN_Pos (5U)
#define LTDC_LxFPF1R_GLEN_Msk (0x1fUL << LTDC_LxFPF1R_GLEN_Pos)
#define LTDC_LxFPF1R_GLEN LTDC_LxFPF1R_GLEN_Msk /*!< Width of the alpha component (in bits). */
#define LTDC_LxFPF1R_BPOS_Pos (9U)
#define LTDC_LxFPF1R_BPOS_Msk (0x1fUL << LTDC_LxFPF1R_BPOS_Pos)
#define LTDC_LxFPF1R_BPOS LTDC_LxFPF1R_BPOS_Msk /*!< Location of the red component inside the pixel memory word (in bits). */
#define LTDC_LxFPF1R_BLEN_Pos (14U)
#define LTDC_LxFPF1R_BLEN_Msk (0x1fUL << LTDC_LxFPF1R_BLEN_Pos)
#define LTDC_LxFPF1R_BLEN LTDC_LxFPF1R_BLEN_Msk /*!< Width of the red component (in bits). */
#define LTDC_LxFPF1R_PSIZE_Pos (18U)
#define LTDC_LxFPF1R_PSIZE_Msk (0x7UL << LTDC_LxFPF1R_PSIZE_Pos)
#define LTDC_LxFPF1R_PSIZE LTDC_LxFPF1R_PSIZE_Msk /*!< Width of the red component (in bits). */
/******************************************************************************/
/* */
/* Memory Cipher Engine (MCE) */
/* */
/******************************************************************************/
/******************** Bit definition for MCE_CR register ********************/
#define MCE_CR_GLOCK_Pos (0U)
#define MCE_CR_GLOCK_Msk (0x1UL << MCE_CR_GLOCK_Pos) /*!< 0x00000001 */
#define MCE_CR_GLOCK MCE_CR_GLOCK_Msk /*!< MCE global lock */
#define MCE_CR_MKLOCK_Pos (1U)
#define MCE_CR_MKLOCK_Msk (0x1UL << MCE_CR_MKLOCK_Pos) /*!< 0x00000002 */
#define MCE_CR_MKLOCK MCE_CR_MKLOCK_Msk /*!< MCE master and fast master keys lock */
#define MCE_CR_CIPHERSEL_Pos (4U)
#define MCE_CR_CIPHERSEL_Msk (0x3UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000030 */
#define MCE_CR_CIPHERSEL MCE_CR_CIPHERSEL_Msk /*!< MCE Cipher selection */
#define MCE_CR_CIPHERSEL_0 (0x1UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000010 */
#define MCE_CR_CIPHERSEL_1 (0x2UL << MCE_CR_CIPHERSEL_Pos) /*!< 0x00000020 */
/******************** Bit definition for MCE_SR register ********************/
#define MCE_SR_MKVALID_Pos (0U)
#define MCE_SR_MKVALID_Msk (0x1UL << MCE_SR_MKVALID_Pos) /*!< 0x00000001 */
#define MCE_SR_MKVALID MCE_SR_MKVALID_Msk /*!< MCE master key valid flag */
#define MCE_SR_FMKVALID_Pos (2U)
#define MCE_SR_FMKVALID_Msk (0x1UL << MCE_SR_FMKVALID_Pos) /*!< 0x00000004 */
#define MCE_SR_FMKVALID MCE_SR_FMKVALID_Msk /*!< MCE fast master key valid flag */
#define MCE_SR_ENCDIS_Pos (4U)
#define MCE_SR_ENCDIS_Msk (0x1UL << MCE_SR_ENCDIS_Pos) /*!< 0x00000010 */
#define MCE_SR_ENCDIS MCE_SR_ENCDIS_Msk /*!< MCE encryption disabled flag */
/******************** Bit definition for MCE_IASR register ******************/
#define MCE_IASR_IAEF_Pos (1U)
#define MCE_IASR_IAEF_Msk (0x1UL << MCE_IASR_IAEF_Pos) /*!< 0x00000002 */
#define MCE_IASR_IAEF MCE_IASR_IAEF_Msk /*!< MCE illegal access error flag */
/******************** Bit definition for MCE_IACR register ******************/
#define MCE_IACR_IAEF_Pos (1U)
#define MCE_IACR_IAEF_Msk (0x1UL << MCE_IACR_IAEF_Pos) /*!< 0x00000002 */
#define MCE_IACR_IAEF MCE_IACR_IAEF_Msk /*!< MCE illegal access error clear bit */
/******************** Bit definition for MCE_IAIER register *****************/
#define MCE_IAIER_IAEIE_Pos (1U)
#define MCE_IAIER_IAEIE_Msk (0x1UL << MCE_IAIER_IAEIE_Pos) /*!< 0x00000002 */
#define MCE_IAIER_IAEIE MCE_IAIER_IAEIE_Msk /*!< MCE illegal access error interrupt enable */
/******************** Bit definition for MCE_IADDR register *****************/
#define MCE_IADDR_IADD_Pos (0U)
#define MCE_IADDR_IADD_Msk (0xFFFFFFFFUL << MCE_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */
#define MCE_IADDR_IADD MCE_IADDR_IADD_Msk /*!< MCE illegal access */
/******************** Bit definition for MCE_REGCR register *****************/
#define MCE_REGCR_BREN_Pos (0U)
#define MCE_REGCR_BREN_Msk (0x1UL << MCE_REGCR_BREN_Pos) /*!< 0x00000001 */
#define MCE_REGCR_BREN MCE_REGCR_BREN_Msk /*!< MCE base region enable */
#define MCE_REGCR_CTXID_Pos (9U)
#define MCE_REGCR_CTXID_Msk (0x3UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000600 */
#define MCE_REGCR_CTXID MCE_REGCR_CTXID_Msk /*!< MCE context ID */
#define MCE_REGCR_CTXID_0 (0x1UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000200 */
#define MCE_REGCR_CTXID_1 (0x2UL << MCE_REGCR_CTXID_Pos) /*!< 0x00000400 */
#define MCE_REGCR_ENC_Pos (14U)
#define MCE_REGCR_ENC_Msk (0x3UL << MCE_REGCR_ENC_Pos) /*!< 0x0000C000 */
#define MCE_REGCR_ENC MCE_REGCR_ENC_Msk /*!< MCE encrypted region */
#define MCE_REGCR_ENC_0 (0x1UL << MCE_REGCR_ENC_Pos) /*!< 0x00004000 */
#define MCE_REGCR_ENC_1 (0x2UL << MCE_REGCR_ENC_Pos) /*!< 0x00008000 */
/******************** Bit definition for MCE_SADDR register *****************/
#define MCE_SADDR_BADDSTART_Pos (12U)
#define MCE_SADDR_BADDSTART_Msk (0xFFFFFUL << MCE_SADDR_BADDSTART_Pos) /*!< 0xFFFFF000 */
#define MCE_SADDR_BADDSTART MCE_SADDR_BADDSTART_Msk /*!< MCE region address start */
/******************** Bit definition for MCE_EADDR register *****************/
#define MCE_EADDR_BADDEND_Pos (12U)
#define MCE_EADDR_BADDEND_Msk (0xFFFFFUL << MCE_EADDR_BADDEND_Pos) /*!< 0xFFFFF000 */
#define MCE_EADDR_BADDEND MCE_EADDR_BADDEND_Msk /*!< MCE region address end */
/******************** Bit definition for MCE_MKEYR0 register ****************/
#define MCE_MKEYR0_MKEY_Pos (0U)
#define MCE_MKEYR0_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR0_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR0_MKEY MCE_MKEYR0_MKEY_Msk /*!< MCE master key, bits [31:0] */
/******************** Bit definition for MCE_MKEYR1 register ****************/
#define MCE_MKEYR1_MKEY_Pos (0U)
#define MCE_MKEYR1_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR1_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR1_MKEY MCE_MKEYR1_MKEY_Msk /*!< MCE master key, bits [63:32] */
/******************** Bit definition for MCE_MKEYR2 register ****************/
#define MCE_MKEYR2_MKEY_Pos (0U)
#define MCE_MKEYR2_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR2_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR2_MKEY MCE_MKEYR2_MKEY_Msk /*!< MCE master key, bits [95:64] */
/******************** Bit definition for MCE_MKEYR3 register ****************/
#define MCE_MKEYR3_MKEY_Pos (0U)
#define MCE_MKEYR3_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR3_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR3_MKEY MCE_MKEYR3_MKEY_Msk /*!< MCE master key, bits [127:96] */
/******************** Bit definition for MCE_MKEYR4 register ****************/
#define MCE_MKEYR4_MKEY_Pos (0U)
#define MCE_MKEYR4_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR4_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR4_MKEY MCE_MKEYR4_MKEY_Msk /*!< MCE master key, bits [159:128] */
/******************** Bit definition for MCE_MKEYR5 register ****************/
#define MCE_MKEYR5_MKEY_Pos (0U)
#define MCE_MKEYR5_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR5_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR5_MKEY MCE_MKEYR5_MKEY_Msk /*!< MCE master key, bits [191:160] */
/******************** Bit definition for MCE_MKEYR6 register ****************/
#define MCE_MKEYR6_MKEY_Pos (0U)
#define MCE_MKEYR6_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR6_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR6_MKEY MCE_MKEYR6_MKEY_Msk /*!< MCE master key, bits [223:192] */
/******************** Bit definition for MCE_MKEYR7 register ****************/
#define MCE_MKEYR7_MKEY_Pos (0U)
#define MCE_MKEYR7_MKEY_Msk (0xFFFFFFFFUL << MCE_MKEYR7_MKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_MKEYR7_MKEY MCE_MKEYR7_MKEY_Msk /*!< MCE master key, bits [255:224] */
/******************** Bit definition for MCE_FMKEYR0 register ***************/
#define MCE_FMKEYR0_FMKEY_Pos (0U)
#define MCE_FMKEYR0_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR0_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR0_FMKEY MCE_FMKEYR0_FMKEY_Msk /*!< MCE fast master key, bits [31:0] */
/******************** Bit definition for MCE_FMKEYR1 register ***************/
#define MCE_FMKEYR1_FMKEY_Pos (0U)
#define MCE_FMKEYR1_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR1_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR1_FMKEY MCE_FMKEYR1_FMKEY_Msk /*!< MCE fast master key, bits [63:32] */
/******************** Bit definition for MCE_FMKEYR2 register ***************/
#define MCE_FMKEYR2_FMKEY_Pos (0U)
#define MCE_FMKEYR2_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR2_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR2_FMKEY MCE_FMKEYR2_FMKEY_Msk /*!< MCE fast master key, bits [95:64] */
/******************** Bit definition for MCE_FMKEYR3 register ***************/
#define MCE_FMKEYR3_FMKEY_Pos (0U)
#define MCE_FMKEYR3_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR3_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR3_FMKEY MCE_FMKEYR3_FMKEY_Msk /*!< MCE fast master key, bits [127:96] */
/******************** Bit definition for MCE_FMKEYR4 register ****************/
#define MCE_FMKEYR4_FMKEY_Pos (0U)
#define MCE_FMKEYR4_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR4_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR4_FMKEY MCE_FMKEYR4_FMKEY_Msk /*!< MCE fast master key, bits [159:128] */
/******************** Bit definition for MCE_FMKEYR5 register ****************/
#define MCE_FMKEYR5_FMKEY_Pos (0U)
#define MCE_FMKEYR5_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR5_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR5_FMKEY MCE_FMKEYR5_FMKEY_Msk /*!< MCE fast master key, bits [191:160] */
/******************** Bit definition for MCE_FMKEYR6 register ****************/
#define MCE_FMKEYR6_FMKEY_Pos (0U)
#define MCE_FMKEYR6_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR6_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR6_FMKEY MCE_FMKEYR6_FMKEY_Msk /*!< MCE fast master key, bits [223:192] */
/******************** Bit definition for MCE_FMKEYR7 register ****************/
#define MCE_FMKEYR7_FMKEY_Pos (0U)
#define MCE_FMKEYR7_FMKEY_Msk (0xFFFFFFFFUL << MCE_FMKEYR7_FMKEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_FMKEYR7_FMKEY MCE_FMKEYR7_FMKEY_Msk /*!< MCE fast master key, bits [255:224] */
/******************** Bit definition for MCE_CCCFGR register ****************/
#define MCE_CCCFGR_CCEN_Pos (0U)
#define MCE_CCCFGR_CCEN_Msk (0x1UL << MCE_CCCFGR_CCEN_Pos) /*!< 0x00000001 */
#define MCE_CCCFGR_CCEN MCE_CCCFGR_CCEN_Msk /*!< MCE cipher context enable */
#define MCE_CCCFGR_CCLOCK_Pos (1U)
#define MCE_CCCFGR_CCLOCK_Msk (0x1UL << MCE_CCCFGR_CCLOCK_Pos) /*!< 0x00000002 */
#define MCE_CCCFGR_CCLOCK MCE_CCCFGR_CCLOCK_Msk /*!< MCE cipher context lock */
#define MCE_CCCFGR_KEYLOCK_Pos (2U)
#define MCE_CCCFGR_KEYLOCK_Msk (0x1UL << MCE_CCCFGR_KEYLOCK_Pos) /*!< 0x00000004 */
#define MCE_CCCFGR_KEYLOCK MCE_CCCFGR_KEYLOCK_Msk /*!< MCE cipher context key lock */
#define MCE_CCCFGR_MODE_Pos (4U)
#define MCE_CCCFGR_MODE_Msk (0x3UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000030 */
#define MCE_CCCFGR_MODE MCE_CCCFGR_MODE_Msk /*!< MCE authorized cipher mode */
#define MCE_CCCFGR_MODE_0 (0x1UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000010 */
#define MCE_CCCFGR_MODE_1 (0x2UL << MCE_CCCFGR_MODE_Pos) /*!< 0x00000020 */
#define MCE_CCCFGR_KEYCRC_Pos (8U)
#define MCE_CCCFGR_KEYCRC_Msk (0xFFUL << MCE_CCCFGR_KEYCRC_Pos) /*!< 0x0000FF00 */
#define MCE_CCCFGR_KEYCRC MCE_CCCFGR_KEYCRC_Msk /*!< MCE cipher context key CRC */
#define MCE_CCCFGR_VERSION_Pos (16U)
#define MCE_CCCFGR_VERSION_Msk (0xFFFFUL << MCE_CCCFGR_VERSION_Pos) /*!< 0xFFFF0000 */
#define MCE_CCCFGR_VERSION MCE_CCCFGR_VERSION_Msk /*!< MCE cipher context version */
/******************** Bit definition for MCE_CCNR0 register *****************/
#define MCE_CCNR0_SCNONCE_Pos (0U)
#define MCE_CCNR0_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR0_SCNONCE_Pos) /*!< 0xFFFFFFFF */
#define MCE_CCNR0_SCNONCE MCE_CCNR0_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [31:0] */
/******************** Bit definition for MCE_CCNR1 register ****************/
#define MCE_CCNR1_SCNONCE_Pos (0U)
#define MCE_CCNR1_SCNONCE_Msk (0xFFFFFFFFUL << MCE_CCNR1_SCNONCE_Pos) /*!< 0xFFFFFFFF */
#define MCE_CCNR1_SCNONCE MCE_CCNR1_SCNONCE_Msk /*!< MCE cipher context stream cipher nonce, bits [63:32] */
/******************** Bit definition for MCE_CCKEYR0 register ***************/
#define MCE_CCKEYR0_KEY_Pos (0U)
#define MCE_CCKEYR0_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR0_KEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_CCKEYR0_KEY MCE_CCKEYR0_KEY_Msk /*!< MCE cipher context key, bits [31:0] */
/******************** Bit definition for MCE_CCKEYR1 register ***************/
#define MCE_CCKEYR1_KEY_Pos (0U)
#define MCE_CCKEYR1_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR1_KEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_CCKEYR1_KEY MCE_CCKEYR1_KEY_Msk /*!< MCE fast master key, bits [63:32] */
/******************** Bit definition for MCE_CCKEYR2 register ***************/
#define MCE_CCKEYR2_KEY_Pos (0U)
#define MCE_CCKEYR2_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR2_KEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_CCKEYR2_KEY MCE_CCKEYR2_KEY_Msk /*!< MCE fast master key, bits [95:64] */
/******************** Bit definition for MCE_CCKEYR3 register ***************/
#define MCE_CCKEYR3_KEY_Pos (0U)
#define MCE_CCKEYR3_KEY_Msk (0xFFFFFFFFUL << MCE_CCKEYR3_KEY_Pos) /*!< 0xFFFFFFFF */
#define MCE_CCKEYR3_KEY MCE_CCKEYR3_KEY_Msk /*!< MCE fast master key, bits [127:96] */
/******************************************************************************/
/* */
/* MDF/ADF */
/* */
/******************************************************************************/
/******************* Bit definition for MDF/ADF_GCR register ****************/
#define MDF_GCR_TRGO_Pos (0U)
#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */
#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*!< Trigger output control */
#define MDF_GCR_ILVNB_Pos (4U)
#define MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) /*!< 0x000000F0 */
#define MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk /*!< Interleaved Number */
/******************* Bit definition for MDF/ADF_CKGCR register ********************/
#define MDF_CKGCR_CKDEN_Pos (0U)
#define MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) /*!< 0x00000001 */
#define MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk /*!<CKGEN diveders enable */
#define MDF_CKGCR_CCK0EN_Pos (1U)
#define MDF_CKGCR_CCK0EN_Msk (0x1UL << MDF_CKGCR_CCK0EN_Pos) /*!< 0x00000002 */
#define MDF_CKGCR_CCK0EN MDF_CKGCR_CCK0EN_Msk /*!<CCK0 clock enable */
#define MDF_CKGCR_CCK1EN_Pos (2U)
#define MDF_CKGCR_CCK1EN_Msk (0x1UL << MDF_CKGCR_CCK1EN_Pos) /*!< 0x00000004 */
#define MDF_CKGCR_CCK1EN MDF_CKGCR_CCK1EN_Msk /*!<CCK1 clock enable */
#define MDF_CKGCR_CKGMOD_Pos (4U)
#define MDF_CKGCR_CKGMOD_Msk (0x1UL << MDF_CKGCR_CKGMOD_Pos) /*!< 0x00000010 */
#define MDF_CKGCR_CKGMOD MDF_CKGCR_CKGMOD_Msk /*!<Clock genartor mode */
#define MDF_CKGCR_CCK0DIR_Pos (5U)
#define MDF_CKGCR_CCK0DIR_Msk (0x1UL << MDF_CKGCR_CCK0DIR_Pos) /*!< 0x00000020 */
#define MDF_CKGCR_CCK0DIR MDF_CKGCR_CCK0DIR_Msk /*!<CCK0 clock direction */
#define MDF_CKGCR_CCK1DIR_Pos (6U)
#define MDF_CKGCR_CCK1DIR_Msk (0x1UL << MDF_CKGCR_CCK1DIR_Pos) /*!< 0x00000040 */
#define MDF_CKGCR_CCK1DIR MDF_CKGCR_CCK1DIR_Msk /*!<CCK1 clock direction */
#define MDF_CKGCR_TRGSENS_Pos (8U)
#define MDF_CKGCR_TRGSENS_Msk (0x1UL << MDF_CKGCR_TRGSENS_Pos) /*!< 0x00000100 */
#define MDF_CKGCR_TRGSENS MDF_CKGCR_TRGSENS_Msk /*!<CKGEN trigger sensitivity selection */
#define MDF_CKGCR_TRGSRC_Pos (12U)
#define MDF_CKGCR_TRGSRC_Msk (0xFUL << MDF_CKGCR_TRGSRC_Pos) /*!< 0x0000F000 */
#define MDF_CKGCR_TRGSRC MDF_CKGCR_TRGSRC_Msk /*!<Digital Filter trigger signal selection */
#define MDF_CKGCR_TRGSRC_0 (0x1UL << MDF_CKGCR_TRGSRC_Pos) /*!< 0x00001000 */
#define MDF_CKGCR_TRGSRC_1 (0x2UL << MDF_CKGCR_TRGSRC_Pos) /*!< 0x00002000 */
#define MDF_CKGCR_TRGSRC_2 (0x4UL << MDF_CKGCR_TRGSRC_Pos) /*!< 0x00004000 */
#define MDF_CKGCR_TRGSRC_3 (0x8UL << MDF_CKGCR_TRGSRC_Pos) /*!< 0x00008000 */
#define MDF_CKGCR_CCKDIV_Pos (16U)
#define MDF_CKGCR_CCKDIV_Msk (0xFUL << MDF_CKGCR_CCKDIV_Pos) /*!< 0x000F0000 */
#define MDF_CKGCR_CCKDIV MDF_CKGCR_CCKDIV_Msk /*!<Divider to control the MDF_CCK clock */
#define MDF_CKGCR_PROCDIV_Pos (24U)
#define MDF_CKGCR_PROCDIV_Msk (0x7FUL << MDF_CKGCR_PROCDIV_Pos) /*!< 0x7F000000 */
#define MDF_CKGCR_PROCDIV MDF_CKGCR_PROCDIV_Msk /*!<Divider to control the serial interface clock */
#define MDF_CKGCR_CCKACTIVE_Pos (31U)
#define MDF_CKGCR_CCKACTIVE_Msk (0x1UL << MDF_CKGCR_CCKACTIVE_Pos) /*!< 0x80000000 */
#define MDF_CKGCR_CCKACTIVE MDF_CKGCR_CCKACTIVE_Msk /*!<Clock generator active flag */
/******************* Bit definition for MDF/ADF_OR register ********************/
#define MDF_OR_OPTION_Pos (0U)
#define MDF_OR_OPTION_Msk (0xFFFFFFFFUL << MDF_OR_OPTION_Pos) /*!< 0xFFFFFFFF */
#define MDF_OR_OPTION MDF_OR_OPTION_Msk /*!<Option Control Bits */
/******************* Bit definition for MDF/ADF_SITFxCR register ********************/
#define MDF_SITFCR_SITFEN_Pos (0U)
#define MDF_SITFCR_SITFEN_Msk (0x1UL << MDF_SITFCR_SITFEN_Pos) /*!< 0x00000001 */
#define MDF_SITFCR_SITFEN MDF_SITFCR_SITFEN_Msk /*!<Serial interface enable */
#define MDF_SITFCR_SCKSRC_Pos (1U)
#define MDF_SITFCR_SCKSRC_Msk (0x3UL << MDF_SITFCR_SCKSRC_Pos) /*!< 0x00000006 */
#define MDF_SITFCR_SCKSRC MDF_SITFCR_SCKSRC_Msk /*!<Serial clock source */
#define MDF_SITFCR_SCKSRC_0 (0x1UL << MDF_SITFCR_SCKSRC_Pos)
#define MDF_SITFCR_SCKSRC_1 (0x2UL << MDF_SITFCR_SCKSRC_Pos)
#define MDF_SITFCR_SITFMOD_Pos (4U)
#define MDF_SITFCR_SITFMOD_Msk (0x3UL << MDF_SITFCR_SITFMOD_Pos) /*!< 0x00000030 */
#define MDF_SITFCR_SITFMOD MDF_SITFCR_SITFMOD_Msk /*!<Serial interface type */
#define MDF_SITFCR_SITFMOD_0 (0x1UL << MDF_SITFCR_SITFMOD_Pos) /*!< 0x00000010 */
#define MDF_SITFCR_SITFMOD_1 (0x2UL << MDF_SITFCR_SITFMOD_Pos) /*!< 0x00000020 */
#define MDF_SITFCR_STH_Pos (8U)
#define MDF_SITFCR_STH_Msk (0x1FUL << MDF_SITFCR_STH_Pos) /*!< 0x00001F00 */
#define MDF_SITFCR_STH MDF_SITFCR_STH_Msk /*!<Manchester Symbol threshold / SPI threshold */
#define MDF_SITFCR_SITFACTIVE_Pos (31U)
#define MDF_SITFCR_SITFACTIVE_Msk (0x1UL << MDF_SITFCR_SITFACTIVE_Pos) /*!< 0x80000000 */
#define MDF_SITFCR_SITFACTIVE MDF_SITFCR_SITFACTIVE_Msk /*!<Serial interface active flag */
/******************* Bit definition for MDF/ADF_BSMXxCR register ********************/
#define MDF_BSMXCR_BSSEL_Pos (0U)
#define MDF_BSMXCR_BSSEL_Msk (0x1FUL << MDF_BSMXCR_BSSEL_Pos) /*!< 0x0000001F */
#define MDF_BSMXCR_BSSEL MDF_BSMXCR_BSSEL_Msk /*!<Bit Streal selection */
#define MDF_BSMXCR_BSSEL_0 (0x1UL << MDF_BSMXCR_BSSEL_Pos) /*!< 0x00000001 */
#define MDF_BSMXCR_BSSEL_1 (0x2UL << MDF_BSMXCR_BSSEL_Pos) /*!< 0x00000002 */
#define MDF_BSMXCR_BSSEL_2 (0x4UL << MDF_BSMXCR_BSSEL_Pos) /*!< 0x00000004 */
#define MDF_BSMXCR_BSSEL_3 (0x8UL << MDF_BSMXCR_BSSEL_Pos) /*!< 0x00000008 */
#define MDF_BSMXCR_BSSEL_4 (0x10UL << MDF_BSMXCR_BSSEL_Pos) /*!< 0x00000010 */
#define MDF_BSMXCR_BSMXACTIVATE_Pos (31U)
#define MDF_BSMXCR_BSMXACTIVATE_Msk (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos) /*!< 0x80000000 */
#define MDF_BSMXCR_BSMXACTIVATE MDF_BSMXCR_BSMXACTIVATE_Msk /*!<Bit Streal activation flag */
/******************* Bit definition for MDF/ADF_DFLTxCR register ********************/
#define MDF_DFLTCR_DFLTEN_Pos (0U)
#define MDF_DFLTCR_DFLTEN_Msk (0x1UL << MDF_DFLTCR_DFLTEN_Pos) /*!< 0x00000001 */
#define MDF_DFLTCR_DFLTEN MDF_DFLTCR_DFLTEN_Msk /*!<Digital filter enable */
#define MDF_DFLTCR_DMAEN_Pos (1U)
#define MDF_DFLTCR_DMAEN_Msk (0x1UL << MDF_DFLTCR_DMAEN_Pos) /*!< 0x00000002 */
#define MDF_DFLTCR_DMAEN MDF_DFLTCR_DMAEN_Msk /*!<DMA request enable */
#define MDF_DFLTCR_FTH_Pos (2U)
#define MDF_DFLTCR_FTH_Msk (0x1UL << MDF_DFLTCR_FTH_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_FTH MDF_DFLTCR_FTH_Msk /*!<RXFIFO Threshold selection */
#define MDF_DFLTCR_ACQMOD_Pos (4U)
#define MDF_DFLTCR_ACQMOD_Msk (0x7UL << MDF_DFLTCR_ACQMOD_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_ACQMOD MDF_DFLTCR_ACQMOD_Msk /*!<Digital filter trigger mode */
#define MDF_DFLTCR_ACQMOD_0 (0x1UL << MDF_DFLTCR_ACQMOD_Pos) /*!< 0x00000010 */
#define MDF_DFLTCR_ACQMOD_1 (0x2UL << MDF_DFLTCR_ACQMOD_Pos) /*!< 0x00000020 */
#define MDF_DFLTCR_ACQMOD_2 (0x4UL << MDF_DFLTCR_ACQMOD_Pos) /*!< 0x00000040 */
#define MDF_DFLTCR_TRGSENS_Pos (8U)
#define MDF_DFLTCR_TRGSENS_Msk (0x1UL << MDF_DFLTCR_TRGSENS_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_TRGSENS MDF_DFLTCR_TRGSENS_Msk /*!<Digital filter trigger sensitivity selection */
#define MDF_DFLTCR_TRGSRC_Pos (12U)
#define MDF_DFLTCR_TRGSRC_Msk (0xFUL << MDF_DFLTCR_TRGSRC_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_TRGSRC MDF_DFLTCR_TRGSRC_Msk /*!<Digital filter trigger signal selection */
#define MDF_DFLTCR_TRGSRC_0 (0x1UL << MDF_DFLTCR_TRGSRC_Pos) /*!< 0x00001000 */
#define MDF_DFLTCR_TRGSRC_1 (0x2UL << MDF_DFLTCR_TRGSRC_Pos) /*!< 0x00002000 */
#define MDF_DFLTCR_TRGSRC_2 (0x4UL << MDF_DFLTCR_TRGSRC_Pos) /*!< 0x00004000 */
#define MDF_DFLTCR_TRGSRC_3 (0x8UL << MDF_DFLTCR_TRGSRC_Pos) /*!< 0x00008000 */
#define MDF_DFLTCR_SNPSFMT_Pos (16U)
#define MDF_DFLTCR_SNPSFMT_Msk (0x1UL << MDF_DFLTCR_SNPSFMT_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_SNPSFMT MDF_DFLTCR_SNPSFMT_Msk /*!<SnapShot Data format */
#define MDF_DFLTCR_NBDIS_Pos (20U)
#define MDF_DFLTCR_NBDIS_Msk (0xFFUL << MDF_DFLTCR_NBDIS_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_NBDIS MDF_DFLTCR_NBDIS_Msk /*!<Number of samples to be discard */
#define MDF_DFLTCR_DFLTRUN_Pos (30U)
#define MDF_DFLTCR_DFLTRUN_Msk (0x1UL << MDF_DFLTCR_DFLTRUN_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_DFLTRUN MDF_DFLTCR_DFLTRUN_Msk /*!<Digital filter run status flag */
#define MDF_DFLTCR_DFLTACTIVE_Pos (31U)
#define MDF_DFLTCR_DFLTACTIVE_Msk (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos) /*!< 0x00000004 */
#define MDF_DFLTCR_DFLTACTIVE MDF_DFLTCR_DFLTACTIVE_Msk /*!<Digital filter active flag */
/******************* Bit definition for MDF/ADF_DFLTxCICR register ********************/
#define MDF_DFLTCICR_DATSRC_Pos (0U)
#define MDF_DFLTCICR_DATSRC_Msk (0x3UL << MDF_DFLTCICR_DATSRC_Pos) /*!< 0x00000003 */
#define MDF_DFLTCICR_DATSRC MDF_DFLTCICR_DATSRC_Msk /*!<Source Data for the digital filter */
#define MDF_DFLTCICR_DATSRC_0 (0x1UL << MDF_DFLTCICR_DATSRC_Pos) /*!< 0x00000001 */
#define MDF_DFLTCICR_DATSRC_1 (0x2UL << MDF_DFLTCICR_DATSRC_Pos) /*!< 0x00000002 */
#define MDF_DFLTCICR_CICMOD_Pos (4U)
#define MDF_DFLTCICR_CICMOD_Msk (0x7UL << MDF_DFLTCICR_CICMOD_Pos) /*!< 0x00000070 */
#define MDF_DFLTCICR_CICMOD MDF_DFLTCICR_CICMOD_Msk /*!<Select the CIC Mode*/
#define MDF_DFLTCICR_CICMOD_0 (0x1UL << MDF_DFLTCICR_CICMOD_Pos) /*!< 0x00000010 */
#define MDF_DFLTCICR_CICMOD_1 (0x2UL << MDF_DFLTCICR_CICMOD_Pos) /*!< 0x00000020 */
#define MDF_DFLTCICR_CICMOD_2 (0x4UL << MDF_DFLTCICR_CICMOD_Pos) /*!< 0x00000030 */
#define MDF_DFLTCICR_MCICD_Pos (8U)
#define MDF_DFLTCICR_MCICD_Msk (0x1FFUL << MDF_DFLTCICR_MCICD_Pos) /*!< 0x0001FF00 */
#define MDF_DFLTCICR_MCICD MDF_DFLTCICR_MCICD_Msk /*!<CIC decimation ratio selection*/
#define MDF_DFLTCICR_SCALE_Pos (20U)
#define MDF_DFLTCICR_SCALE_Msk (0x3FUL << MDF_DFLTCICR_SCALE_Pos) /*!< 0x03F00000 */
#define MDF_DFLTCICR_SCALE MDF_DFLTCICR_SCALE_Msk /*!<Scaling factor selection*/
/******************* Bit definition for MDF/ADF_DFLTxRSFR register ********************/
#define MDF_DFLTRSFR_RSFLTBYP_Pos (0U)
#define MDF_DFLTRSFR_RSFLTBYP_Msk (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos) /*!< 0x00000001 */
#define MDF_DFLTRSFR_RSFLTBYP MDF_DFLTRSFR_RSFLTBYP_Msk /*!<Reshape filter bypass*/
#define MDF_DFLTRSFR_RSFLTD_Pos (4U)
#define MDF_DFLTRSFR_RSFLTD_Msk (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos) /*!< 0x00000010 */
#define MDF_DFLTRSFR_RSFLTD MDF_DFLTRSFR_RSFLTD_Msk /*!<Reshape filter decimation ratio*/
#define MDF_DFLTRSFR_HPFBYP_Pos (7U)
#define MDF_DFLTRSFR_HPFBYP_Msk (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos) /*!< 0x00000080 */
#define MDF_DFLTRSFR_HPFBYP MDF_DFLTRSFR_HPFBYP_Msk /*!<High-pass filter bypass*/
#define MDF_DFLTRSFR_HPFC_Pos (8U)
#define MDF_DFLTRSFR_HPFC_Msk (0x3UL << MDF_DFLTRSFR_HPFC_Pos) /*!< 0x00000080 */
#define MDF_DFLTRSFR_HPFC MDF_DFLTRSFR_HPFC_Msk /*!<High-pass filter cut-off frequency*/
#define MDF_DFLTRSFR_HPFC_0 (0x1UL << MDF_DFLTRSFR_HPFC_Pos)
#define MDF_DFLTRSFR_HPFC_1 (0x2UL << MDF_DFLTRSFR_HPFC_Pos)
/******************* Bit definition for MDF/ADF_DFLTxINTR register ********************/
#define MDF_DFLTINTR_INTDIV_Pos (0U)
#define MDF_DFLTINTR_INTDIV_Msk (0x3UL << MDF_DFLTINTR_INTDIV_Pos) /*!< 0x00000003 */
#define MDF_DFLTINTR_INTDIV MDF_DFLTINTR_INTDIV_Msk /*!<Integrator output dividion*/
#define MDF_DFLTINTR_INTDIV_0 (0x1UL << MDF_DFLTINTR_INTDIV_Pos) /*!< 0x00000001 */
#define MDF_DFLTINTR_INTDIV_1 (0x2UL << MDF_DFLTINTR_INTDIV_Pos) /*!< 0x00000002 */
#define MDF_DFLTINTR_INTVAL_Pos (4U)
#define MDF_DFLTINTR_INTVAL_Msk (0x7FUL << MDF_DFLTINTR_INTVAL_Pos) /*!< 0x000007F0 */
#define MDF_DFLTINTR_INTVAL MDF_DFLTINTR_INTVAL_Msk /*!<Integrator value selection*/
/******************* Bit definition for MDF/ADF_OLDxCR register ********************/
#define MDF_OLDCR_OLDEN_Pos (0U)
#define MDF_OLDCR_OLDEN_Msk (0x1UL << MDF_OLDCR_OLDEN_Pos) /*!< 0x00000001 */
#define MDF_OLDCR_OLDEN MDF_OLDCR_OLDEN_Msk /*!<OLD enable*/
#define MDF_OLDCR_THINB_Pos (1U)
#define MDF_OLDCR_THINB_Msk (0x1UL << MDF_OLDCR_THINB_Pos) /*!< 0x00000002 */
#define MDF_OLDCR_THINB MDF_OLDCR_THINB_Msk /*!<OLD threshold in band*/
#define MDF_OLDCR_BKOLD_Pos (4U)
#define MDF_OLDCR_BKOLD_Msk (0xFUL << MDF_OLDCR_BKOLD_Pos) /*!< 0x000000F0 */
#define MDF_OLDCR_BKOLD MDF_OLDCR_BKOLD_Msk /*!<Bteak signal assignment for OLD*/
#define MDF_OLDCR_BKOLD_0 (0x1UL << MDF_OLDCR_BKOLD_Pos) /*!< 0x00000010 */
#define MDF_OLDCR_BKOLD_1 (0x2UL << MDF_OLDCR_BKOLD_Pos) /*!< 0x00000020 */
#define MDF_OLDCR_BKOLD_2 (0x4UL << MDF_OLDCR_BKOLD_Pos) /*!< 0x00000040 */
#define MDF_OLDCR_BKOLD_3 (0x8UL << MDF_OLDCR_BKOLD_Pos) /*!< 0x00000080 */
#define MDF_OLDCR_ACICN_Pos (12U)
#define MDF_OLDCR_ACICN_Msk (0x3UL << MDF_OLDCR_ACICN_Pos) /*!< 0x00003000 */
#define MDF_OLDCR_ACICN MDF_OLDCR_ACICN_Msk /*!<OLD CIC order selection*/
#define MDF_OLDCR_ACICN_0 (0x1UL << MDF_OLDCR_ACICN_Pos) /*!< 0x00001000 */
#define MDF_OLDCR_ACICN_1 (0x2UL << MDF_OLDCR_ACICN_Pos) /*!< 0x00002000 */
#define MDF_OLDCR_ACICD_Pos (17U)
#define MDF_OLDCR_ACICD_Msk (0x1FUL << MDF_OLDCR_ACICD_Pos) /*!< 0x003E0000 */
#define MDF_OLDCR_ACICD MDF_OLDCR_ACICD_Msk /*!<OLD CIC decimation ratio selection*/
#define MDF_OLDCR_OLDACTIVE_Pos (31U)
#define MDF_OLDCR_OLDACTIVE_Msk (0x1UL << MDF_OLDCR_OLDACTIVE_Pos) /*!< 0x80000000 */
#define MDF_OLDCR_OLDACTIVE MDF_OLDCR_OLDACTIVE_Msk /*!<OLD active flag*/
/******************* Bit definition for MDF/ADF_OLDxTHLR register ********************/
#define MDF_OLDTHLR_OLDTHL_Pos (0U)
#define MDF_OLDTHLR_OLDTHL_Msk (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) /*!< 0x03FFFFFF */
#define MDF_OLDTHLR_OLDTHL MDF_OLDTHLR_OLDTHL_Msk /*!<OLD Low threshold value*/
/******************* Bit definition for MDF/ADF_OLDxTHHR register ********************/
#define MDF_OLDTHHR_OLDTHH_Pos (0U)
#define MDF_OLDTHHR_OLDTHH_Msk (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) /*!< 0x03FFFFFF */
#define MDF_OLDTHHR_OLDTHH MDF_OLDTHHR_OLDTHH_Msk /*!<OLD High threshold value*/
/******************* Bit definition for MDF/ADF_DLYxCR register ********************/
#define MDF_DLYCR_SKPDLY_Pos (0U)
#define MDF_DLYCR_SKPDLY_Msk (0x7FUL << MDF_DLYCR_SKPDLY_Pos) /*!< 0x0000007F */
#define MDF_DLYCR_SKPDLY MDF_DLYCR_SKPDLY_Msk /*!<Delay to apply to a bitstream*/
#define MDF_DLYCR_SKPBF_Pos (31U)
#define MDF_DLYCR_SKPBF_Msk (0x1UL << MDF_DLYCR_SKPBF_Pos) /*!< 0x80000000 */
#define MDF_DLYCR_SKPBF MDF_DLYCR_SKPBF_Msk /*!<DSkip Busy Flag*/
/******************* Bit definition for MDF/ADF_SCDxCR register ********************/
#define MDF_SCDCR_SCDEN_Pos (0U)
#define MDF_SCDCR_SCDEN_Msk (0x1UL << MDF_SCDCR_SCDEN_Pos) /*!< 0x00000001 */
#define MDF_SCDCR_SCDEN MDF_SCDCR_SCDEN_Msk /*!<Short circuit detector enable*/
#define MDF_SCDCR_BKSCD_Pos (4U)
#define MDF_SCDCR_BKSCD_Msk (0xFUL << MDF_SCDCR_BKSCD_Pos) /*!< 0x000000F0 */
#define MDF_SCDCR_BKSCD MDF_SCDCR_BKSCD_Msk /*!<Break signal assignment to short circuit detector */
#define MDF_SCDCR_BKSCD_0 (0x1UL << MDF_SCDCR_BKSCD_Pos) /*!< 0x00000010 */
#define MDF_SCDCR_BKSCD_1 (0x2UL << MDF_SCDCR_BKSCD_Pos) /*!< 0x00000020 */
#define MDF_SCDCR_BKSCD_2 (0x4UL << MDF_SCDCR_BKSCD_Pos) /*!< 0x00000040 */
#define MDF_SCDCR_BKSCD_3 (0x8UL << MDF_SCDCR_BKSCD_Pos) /*!< 0x00000080 */
#define MDF_SCDCR_SCDT_Pos (12U)
#define MDF_SCDCR_SCDT_Msk (0xFFUL << MDF_SCDCR_SCDT_Pos) /*!< 0x00000FF00 */
#define MDF_SCDCR_SCDT MDF_SCDCR_SCDT_Msk /*!<Short circuit detector threshold*/
#define MDF_SCDCR_SCDACTIVE_Pos (31U)
#define MDF_SCDCR_SCDACTIVE_Msk (0x1UL << MDF_SCDCR_SCDACTIVE_Pos) /*!< 0x80000000 */
#define MDF_SCDCR_SCDACTIVE MDF_SCDCR_SCDACTIVE_Msk /*!<Short circuit detector active flag*/
/******************* Bit definition for MDF/ADF_DFLTIER register ********************/
#define MDF_DFLTIER_FTHIE_Pos (0U)
#define MDF_DFLTIER_FTHIE_Msk (0x1UL << MDF_DFLTIER_FTHIE_Pos) /*!< 0x00000001 */
#define MDF_DFLTIER_FTHIE MDF_DFLTIER_FTHIE_Msk /*!<RXFIFO threshold interrupt enable*/
#define MDF_DFLTIER_DOVRIE_Pos (1U)
#define MDF_DFLTIER_DOVRIE_Msk (0x1UL << MDF_DFLTIER_DOVRIE_Pos) /*!< 0x00000002 */
#define MDF_DFLTIER_DOVRIE MDF_DFLTIER_DOVRIE_Msk /*!<Data overflow interrupt enable*/
#define MDF_DFLTIER_SSDRIE_Pos (2U)
#define MDF_DFLTIER_SSDRIE_Msk (0x1UL << MDF_DFLTIER_SSDRIE_Pos) /*!< 0x00000004 */
#define MDF_DFLTIER_SSDRIE MDF_DFLTIER_SSDRIE_Msk /*!<Snapshot data ready interrupt enable*/
#define MDF_DFLTIER_OLDIE_Pos (4U)
#define MDF_DFLTIER_OLDIE_Msk (0x1UL << MDF_DFLTIER_OLDIE_Pos) /*!< 0x00000010 */
#define MDF_DFLTIER_OLDIE MDF_DFLTIER_OLDIE_Msk /*!<OLD interrupt enable*/
#define MDF_DFLTIER_SSOVRIE_Pos (7U)
#define MDF_DFLTIER_SSOVRIE_Msk (0x1UL << MDF_DFLTIER_SSOVRIE_Pos) /*!< 0x00000080 */
#define MDF_DFLTIER_SSOVRIE MDF_DFLTIER_SSOVRIE_Msk /*!<Snapshot overrun interrupt enable*/
#define MDF_DFLTIER_SCDIE_Pos (8U)
#define MDF_DFLTIER_SCDIE_Msk (0x1UL << MDF_DFLTIER_SCDIE_Pos) /*!< 0x00000100 */
#define MDF_DFLTIER_SCDIE MDF_DFLTIER_SCDIE_Msk /*!<Short circuit dtector interrupt enable*/
#define MDF_DFLTIER_SATIE_Pos (9U)
#define MDF_DFLTIER_SATIE_Msk (0x1UL << MDF_DFLTIER_SATIE_Pos) /*!< 0x00000200 */
#define MDF_DFLTIER_SATIE MDF_DFLTIER_SATIE_Msk /*!<Saturation detection interrupt enable*/
#define MDF_DFLTIER_CKABIE_Pos (10U)
#define MDF_DFLTIER_CKABIE_Msk (0x1UL << MDF_DFLTIER_CKABIE_Pos) /*!< 0x00000400 */
#define MDF_DFLTIER_CKABIE MDF_DFLTIER_CKABIE_Msk /*!<Clock absence detection interrupt enable*/
#define MDF_DFLTIER_RFOVRIE_Pos (11U)
#define MDF_DFLTIER_RFOVRIE_Msk (0x1UL << MDF_DFLTIER_RFOVRIE_Pos) /*!< 0x00000800 */
#define MDF_DFLTIER_RFOVRIE MDF_DFLTIER_RFOVRIE_Msk /*!<reshape filter overrun interrupt enable*/
#define MDF_DFLTIER_SDDETIE_Pos (12U)
#define MDF_DFLTIER_SDDETIE_Msk (0x1UL << MDF_DFLTIER_SDDETIE_Pos) /*!< 0x00001000 */
#define MDF_DFLTIER_SDDETIE MDF_DFLTIER_SDDETIE_Msk /*!<SAD interrupt enable*/
#define MDF_DFLTIER_SDLVLIE_Pos (13U)
#define MDF_DFLTIER_SDLVLIE_Msk (0x1UL << MDF_DFLTIER_SDLVLIE_Pos) /*!< 0x00002000 */
#define MDF_DFLTIER_SDLVLIE MDF_DFLTIER_SDLVLIE_Msk /*!<Sound level value ready interrupt enable*/
/******************* Bit definition for MDF/ADF_DFLTISR register ********************/
#define MDF_DFLTISR_FTHF_Pos (0U)
#define MDF_DFLTISR_FTHF_Msk (0x1UL << MDF_DFLTISR_FTHF_Pos) /*!< 0x00000001 */
#define MDF_DFLTISR_FTHF MDF_DFLTISR_FTHF_Msk /*!<RXFIFO threshold interrupt flag*/
#define MDF_DFLTISR_DOVRF_Pos (1U)
#define MDF_DFLTISR_DOVRF_Msk (0x1UL << MDF_DFLTISR_DOVRF_Pos) /*!< 0x00000002 */
#define MDF_DFLTISR_DOVRF MDF_DFLTISR_DOVRF_Msk /*!<Data overflow interrupt flag*/
#define MDF_DFLTISR_SSDRF_Pos (2U)
#define MDF_DFLTISR_SSDRF_Msk (0x1UL << MDF_DFLTISR_SSDRF_Pos) /*!< 0x00000004 */
#define MDF_DFLTISR_SSDRF MDF_DFLTISR_SSDRF_Msk /*!<Snapshot data ready interrupt flag*/
#define MDF_DFLTISR_RXNEF_Pos (3U)
#define MDF_DFLTISR_RXNEF_Msk (0x1UL << MDF_DFLTISR_RXNEF_Pos) /*!< 0x00000008 */
#define MDF_DFLTISR_RXNEF MDF_DFLTISR_RXNEF_Msk /*!<Snapshot data ready interrupt flag*/
#define MDF_DFLTISR_OLDF_Pos (4U)
#define MDF_DFLTISR_OLDF_Msk (0x1UL << MDF_DFLTISR_OLDF_Pos) /*!< 0x00000010 */
#define MDF_DFLTISR_OLDF MDF_DFLTISR_OLDF_Msk /*!<OLD interrupt flag*/
#define MDF_DFLTISR_THLF_Pos (5U)
#define MDF_DFLTISR_THLF_Msk (0x1UL << MDF_DFLTISR_THLF_Pos) /*!< 0x00000010 */
#define MDF_DFLTISR_THLF MDF_DFLTISR_THLF_Msk /*!<OLD interrupt flag*/
#define MDF_DFLTISR_THHF_Pos (6U)
#define MDF_DFLTISR_THHF_Msk (0x1UL << MDF_DFLTISR_THHF_Pos) /*!< 0x00000010 */
#define MDF_DFLTISR_THHF MDF_DFLTISR_THHF_Msk /*!<OLD interrupt flag*/
#define MDF_DFLTISR_SSOVRF_Pos (7U)
#define MDF_DFLTISR_SSOVRF_Msk (0x1UL << MDF_DFLTISR_SSOVRF_Pos) /*!< 0x00000080 */
#define MDF_DFLTISR_SSOVRF MDF_DFLTISR_SSOVRF_Msk /*!<Snapshot overrun interrupt flag*/
#define MDF_DFLTISR_SCDF_Pos (8U)
#define MDF_DFLTISR_SCDF_Msk (0x1UL << MDF_DFLTISR_SCDF_Pos) /*!< 0x00000100 */
#define MDF_DFLTISR_SCDF MDF_DFLTISR_SCDF_Msk /*!<Short circuit dtector interrupt flag*/
#define MDF_DFLTISR_SATF_Pos (9U)
#define MDF_DFLTISR_SATF_Msk (0x1UL << MDF_DFLTISR_SATF_Pos) /*!< 0x00000200 */
#define MDF_DFLTISR_SATF MDF_DFLTISR_SATF_Msk /*!<Saturation detection interrupt flag*/
#define MDF_DFLTISR_CKABF_Pos (10U)
#define MDF_DFLTISR_CKABF_Msk (0x1UL << MDF_DFLTISR_CKABF_Pos) /*!< 0x00000400 */
#define MDF_DFLTISR_CKABF MDF_DFLTISR_CKABF_Msk /*!<Clock absence detection interrupt flag*/
#define MDF_DFLTISR_RFOVRF_Pos (11U)
#define MDF_DFLTISR_RFOVRF_Msk (0x1UL << MDF_DFLTISR_RFOVRF_Pos) /*!< 0x00000800 */
#define MDF_DFLTISR_RFOVRF MDF_DFLTISR_RFOVRF_Msk /*!<reshape filter overrun interrupt flag*/
#define MDF_DFLTISR_SDDETF_Pos (12U)
#define MDF_DFLTISR_SDDETF_Msk (0x1UL << MDF_DFLTISR_SDDETF_Pos) /*!< 0x00001000 */
#define MDF_DFLTISR_SDDETF MDF_DFLTISR_SDDETF_Msk /*!<SAD interrupt flag*/
#define MDF_DFLTISR_SDLVLF_Pos (13U)
#define MDF_DFLTISR_SDLVLF_Msk (0x1UL << MDF_DFLTISR_SDLVLF_Pos) /*!< 0x00002000 */
#define MDF_DFLTISR_SDLVLF MDF_DFLTISR_SDLVLF_Msk /*!<Sound level value ready interrupt flag*/
/******************* Bit definition for MDF/ADF_OECCR register ********************/
#define MDF_OECCR_OFFSET_Pos (0U)
#define MDF_OECCR_OFFSET_Msk (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos) /*!< 0x03FFFFFF */
#define MDF_OECCR_OFFSET MDF_OECCR_OFFSET_Msk /*!<Short circuit detector enable*/
/******************* Bit definition for MDF/ADF_SADCR register ********************/
#define MDF_SADCR_SADEN_Pos (0U)
#define MDF_SADCR_SADEN_Msk (0x1UL << MDF_SADCR_SADEN_Pos) /*!< 0x00000001 */
#define MDF_SADCR_SADEN MDF_SADCR_SADEN_Msk /*!<SAD enable*/
#define MDF_SADCR_DATCAP_Pos (1U)
#define MDF_SADCR_DATCAP_Msk (0x3UL << MDF_SADCR_DATCAP_Pos) /*!< 0x00000003 */
#define MDF_SADCR_DATCAP MDF_SADCR_DATCAP_Msk /*!<SAD data capture mode*/
#define MDF_SADCR_DATCAP_0 (0x1UL << MDF_SADCR_DATCAP_Pos) /*!< 0x00000002 */
#define MDF_SADCR_DATCAP_1 (0x2UL << MDF_SADCR_DATCAP_Pos) /*!< 0x00000004 */
#define MDF_SADCR_DETCFG_Pos (3U)
#define MDF_SADCR_DETCFG_Msk (0x1UL << MDF_SADCR_DETCFG_Pos) /*!< 0x00000008 */
#define MDF_SADCR_DETCFG MDF_SADCR_DETCFG_Msk /*!<SAD trigger event configuration*/
#define MDF_SADCR_SADST_Pos (4U)
#define MDF_SADCR_SADST_Msk (0x3UL << MDF_SADCR_SADST_Pos) /*!< 0x00000030 */
#define MDF_SADCR_SADST MDF_SADCR_SADST_Msk /*!<SAD state*/
#define MDF_SADCR_HYSTEN_Pos (7U)
#define MDF_SADCR_HYSTEN_Msk (0x1UL << MDF_SADCR_HYSTEN_Pos) /*!< 0x00000080 */
#define MDF_SADCR_HYSTEN MDF_SADCR_HYSTEN_Msk /*!<Hysteresis enable*/
#define MDF_SADCR_FRSIZE_Pos (8U)
#define MDF_SADCR_FRSIZE_Msk (0x7UL << MDF_SADCR_FRSIZE_Pos) /*!< 0x00000700 */
#define MDF_SADCR_FRSIZE MDF_SADCR_FRSIZE_Msk /*!<Frame size*/
#define MDF_SADCR_FRSIZE_0 (0x1UL << MDF_SADCR_FRSIZE_Pos) /*!< 0x00000100 */
#define MDF_SADCR_FRSIZE_1 (0x2UL << MDF_SADCR_FRSIZE_Pos) /*!< 0x00000200 */
#define MDF_SADCR_FRSIZE_2 (0x4UL << MDF_SADCR_FRSIZE_Pos) /*!< 0x00000300 */
#define MDF_SADCR_SADMOD_Pos (12U)
#define MDF_SADCR_SADMOD_Msk (0x3UL << MDF_SADCR_SADMOD_Pos) /*!< 0x00003000 */
#define MDF_SADCR_SADMOD MDF_SADCR_SADMOD_Msk /*!<SAD working mode*/
#define MDF_SADCR_SADMOD_0 (0x1UL << MDF_SADCR_SADMOD_Pos) /*!< 0x00001000 */
#define MDF_SADCR_SADMOD_1 (0x2UL << MDF_SADCR_SADMOD_Pos) /*!< 0x00002000 */
#define MDF_SADCR_SADACTIVE_Pos (31U)
#define MDF_SADCR_SADACTIVE_Msk (0x1UL << MDF_SADCR_SADACTIVE_Pos) /*!< 0x80000000 */
#define MDF_SADCR_SADACTIVE MDF_SADCR_SADACTIVE_Msk /*!<SAD active flag*/
/******************* Bit definition for MDF/ADF_SADCFGR register ********************/
#define MDF_SADCFGR_SNTHR_Pos (0U)
#define MDF_SADCFGR_SNTHR_Msk (0xFUL << MDF_SADCFGR_SNTHR_Pos) /*!< 0x0000000F */
#define MDF_SADCFGR_SNTHR MDF_SADCFGR_SNTHR_Msk /*!<Signal to noise threshold*/
#define MDF_SADCFGR_SNTHR_0 (0x1UL << MDF_SADCFGR_SNTHR_Pos) /*!< 0x00000001 */
#define MDF_SADCFGR_SNTHR_1 (0x2UL << MDF_SADCFGR_SNTHR_Pos) /*!< 0x00000002 */
#define MDF_SADCFGR_SNTHR_2 (0x4UL << MDF_SADCFGR_SNTHR_Pos) /*!< 0x00000004 */
#define MDF_SADCFGR_SNTHR_3 (0x8UL << MDF_SADCFGR_SNTHR_Pos) /*!< 0x00000008 */
#define MDF_SADCFGR_ANSLP_Pos (4U)
#define MDF_SADCFGR_ANSLP_Msk (0x7UL << MDF_SADCFGR_ANSLP_Pos) /*!< 0x00000070 */
#define MDF_SADCFGR_ANSLP MDF_SADCFGR_ANSLP_Msk /*!<Ambiant noise slope control*/
#define MDF_SADCFGR_LFRNB_Pos (8U)
#define MDF_SADCFGR_LFRNB_Msk (0x7UL << MDF_SADCFGR_LFRNB_Pos) /*!< 0x00000700 */
#define MDF_SADCFGR_LFRNB MDF_SADCFGR_LFRNB_Msk /*!<Number of learning frames*/
#define MDF_SADCFGR_LFRNB_0 (0x1UL << MDF_SADCFGR_LFRNB_Pos) /*!< 0x00000100 */
#define MDF_SADCFGR_LFRNB_1 (0x2UL << MDF_SADCFGR_LFRNB_Pos) /*!< 0x00000200 */
#define MDF_SADCFGR_LFRNB_2 (0x4UL << MDF_SADCFGR_LFRNB_Pos) /*!< 0x00000400 */
#define MDF_SADCFGR_HGOVR_Pos (12U)
#define MDF_SADCFGR_HGOVR_Msk (0x7UL << MDF_SADCFGR_HGOVR_Pos) /*!< 0x00007000 */
#define MDF_SADCFGR_HGOVR MDF_SADCFGR_HGOVR_Msk /*!<Hangover time window*/
#define MDF_SADCFGR_HGOVR_0 (0x1UL << MDF_SADCFGR_HGOVR_Pos) /*!< 0x00001000 */
#define MDF_SADCFGR_HGOVR_1 (0x2UL << MDF_SADCFGR_HGOVR_Pos) /*!< 0x00002000 */
#define MDF_SADCFGR_HGOVR_2 (0x4UL << MDF_SADCFGR_HGOVR_Pos) /*!< 0x00004000 */
#define MDF_SADCFGR_ANMIN_Pos (16U)
#define MDF_SADCFGR_ANMIN_Msk (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos) /*!< 0x1FFF0000 */
#define MDF_SADCFGR_ANMIN MDF_SADCFGR_ANMIN_Msk /*!<Hangover time window*/
/******************* Bit definition for MDF/ADF_SADSDLVR register ********************/
#define MDF_SADSDLVR_SDLVL_Pos (0U)
#define MDF_SADSDLVR_SDLVL_Msk (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos) /*!< 0x00007FFF */
#define MDF_SADSDLVR_SDLVL MDF_SADSDLVR_SDLVL_Msk /*!<Short term sound level*/
/******************* Bit definition for MDF/ADF_SADANLVR register ********************/
#define MDF_SADANLVR_ANLVL_Pos (0U)
#define MDF_SADANLVR_ANLVL_Msk (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos) /*!< 0x00007FFF */
#define MDF_SADANLVR_ANLVL MDF_SADANLVR_ANLVL_Msk /*!<Ambiant noise level estimation*/
/******************* Bit definition for MDF/ADF_SNPSDR register ********************/
#define MDF_SNPSDR_MCICDC_Pos (0U)
#define MDF_SNPSDR_MCICDC_Msk (0x1FFUL << MDF_SNPSDR_MCICDC_Pos) /*!< 0x000001FF */
#define MDF_SNPSDR_MCICDC MDF_SNPSDR_MCICDC_Msk /*!<MCIC decimation counter*/
#define MDF_SNPSDR_EXTSDR_Pos (9U)
#define MDF_SNPSDR_EXTSDR_Msk (0x7FUL << MDF_SNPSDR_EXTSDR_Pos) /*!< 0x0000FE00 */
#define MDF_SNPSDR_EXTSDR MDF_SNPSDR_EXTSDR_Msk /*!<Extended data size*/
#define MDF_SNPSDR_SDR_Pos (16U)
#define MDF_SNPSDR_SDR_Msk (0xFFFFUL << MDF_SNPSDR_SDR_Pos) /*!< 0xFFFF0000 */
#define MDF_SNPSDR_SDR MDF_SNPSDR_SDR_Msk /*!<Extended data size*/
/******************* Bit definition for MDF/ADF_DFLTDR register ********************/
#define MDF_DFLTDR_DR_Pos (8U)
#define MDF_DFLTDR_DR_Msk (0xFFFFFFUL << MDF_DFLTDR_DR_Pos) /*!< 0xFFFFFF00 */
#define MDF_DFLTDR_DR MDF_DFLTDR_DR_Msk /*!<MCIC decimation counter*/
/******************************************************************************/
/* */
/* MDIOS */
/* */
/******************************************************************************/
/******************** Bit definition for MDIOS_CR register *******************/
#define MDIOS_CR_EN_Pos (0U)
#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
#define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
#define MDIOS_CR_WRIE_Pos (1U)
#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
#define MDIOS_CR_RDIE_Pos (2U)
#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
#define MDIOS_CR_EIE_Pos (3U)
#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
#define MDIOS_CR_DPC_Pos (7U)
#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
/******************** Bit definition for MDIOS_SR register *******************/
#define MDIOS_SR_PERF_Pos (0U)
#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
#define MDIOS_SR_SERF_Pos (1U)
#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
#define MDIOS_SR_TERF_Pos (2U)
#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
/******************** Bit definition for MDIOS_CLRFR register *******************/
#define MDIOS_SR_CPERF_Pos (0U)
#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
#define MDIOS_SR_CSERF_Pos (1U)
#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
#define MDIOS_SR_CTERF_Pos (2U)
#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
/******************************************************************************/
/* */
/* Public Key Accelerator (PKA) */
/* */
/******************************************************************************/
/******************* Bit definition for PKA_CR register *********************/
#define PKA_CR_EN_Pos (0U)
#define PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) /*!< 0x00000001 */
#define PKA_CR_EN PKA_CR_EN_Msk /*!< PKA enable */
#define PKA_CR_START_Pos (1U)
#define PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) /*!< 0x00000002 */
#define PKA_CR_START PKA_CR_START_Msk /*!< Start operation */
#define PKA_CR_MODE_Pos (8U)
#define PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) /*!< 0x00003F00 */
#define PKA_CR_MODE PKA_CR_MODE_Msk /*!< MODE[5:0] PKA operation code */
#define PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) /*!< 0x00000100 */
#define PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) /*!< 0x00000200 */
#define PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) /*!< 0x00000400 */
#define PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) /*!< 0x00000800 */
#define PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) /*!< 0x00001000 */
#define PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) /*!< 0x00002000 */
#define PKA_CR_PROCENDIE_Pos (17U)
#define PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) /*!< 0x00020000 */
#define PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk /*!< End of operation interrupt enable */
#define PKA_CR_RAMERRIE_Pos (19U)
#define PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) /*!< 0x00080000 */
#define PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk /*!< RAM error interrupt enable */
#define PKA_CR_ADDRERRIE_Pos (20U)
#define PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) /*!< 0x00100000 */
#define PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk /*!< Address error interrupt enable */
#define PKA_CR_OPERRIE_Pos (21U)
#define PKA_CR_OPERRIE_Msk (0x1UL << PKA_CR_OPERRIE_Pos) /*!< 0x00200000 */
#define PKA_CR_OPERRIE PKA_CR_OPERRIE_Msk /*!< Operation Error interrupt enable */
/******************* Bit definition for PKA_SR register *********************/
#define PKA_SR_INITOK_Pos (0U)
#define PKA_SR_INITOK_Msk (0x1UL << PKA_SR_INITOK_Pos) /*!< 0x00000001 */
#define PKA_SR_INITOK PKA_SR_INITOK_Msk /*!< PKA initialisation flag */
#define PKA_SR_BUSY_Pos (16U)
#define PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) /*!< 0x00010000 */
#define PKA_SR_BUSY PKA_SR_BUSY_Msk /*!< PKA operation is in progress */
#define PKA_SR_PROCENDF_Pos (17U)
#define PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) /*!< 0x00020000 */
#define PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk /*!< PKA end of operation flag */
#define PKA_SR_RAMERRF_Pos (19U)
#define PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) /*!< 0x00080000 */
#define PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk /*!< PKA RAM error flag */
#define PKA_SR_ADDRERRF_Pos (20U)
#define PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) /*!< 0x00100000 */
#define PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk /*!< Address error flag */
#define PKA_SR_OPERRF_Pos (21U)
#define PKA_SR_OPERRF_Msk (0x1UL << PKA_SR_OPERRF_Pos) /*!< 0x00200000 */
#define PKA_SR_OPERRF PKA_SR_OPERRF_Msk /*!< PKA operation Error flag*/
/******************* Bit definition for PKA_CLRFR register ******************/
#define PKA_CLRFR_PROCENDFC_Pos (17U)
#define PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) /*!< 0x00020000 */
#define PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk /*!< Clear PKA end of operation flag */
#define PKA_CLRFR_RAMERRFC_Pos (19U)
#define PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) /*!< 0x00080000 */
#define PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk /*!< Clear PKA RAM error flag */
#define PKA_CLRFR_ADDRERRFC_Pos (20U)
#define PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) /*!< 0x00100000 */
#define PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk /*!< Clear address error flag */
#define PKA_CLRFR_OPERRFC_Pos (21U)
#define PKA_CLRFR_OPERRFC_Msk (0x1UL << PKA_CLRFR_OPERRFC_Pos) /*!< 0x00200000 */
#define PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC_Msk /*!< Clear PKA operation Error flag*/
/******************* Bits definition for PKA RAM *************************/
#define PKA_RAM_OFFSET (0x0400UL) /*!< PKA RAM address offset */
/* Compute Montgomery parameter input data */
#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
/* Compute Montgomery parameter output data */
#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */
/* Compute modular exponentiation input data */
#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */
#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */
#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */
#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/
#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */
#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */
/* Compute modular exponentiation output data */
#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */
#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */
#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */
#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */
/* Compute ECC scalar multiplication input data */
#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */
#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */
/* Compute ECC scalar multiplication output data */
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
/* Point check input data */
#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
/* Point check output data */
#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
/* ECDSA signature input data */
#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */
#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */
#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
/* ECDSA signature output data */
#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */
#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */
#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */
/* ECDSA verification input data */
#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */
#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */
#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */
#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */
#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */
#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */
#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */
#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */
#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
/* ECDSA verification output data */
#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* RSA CRT exponentiation input data */
#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */
#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */
#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */
#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */
#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */
#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */
#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */
/* RSA CRT exponentiation output data */
#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Modular reduction input data */
#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */
#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */
#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */
#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
/* Modular reduction output data */
#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic addition input data */
#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
/* Arithmetic addition output data */
#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic subtraction input data */
#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
/* Arithmetic subtraction output data */
#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Arithmetic multiplication input data */
#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
/* Arithmetic multiplication output data */
#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Comparison input data */
#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
/* Comparison output data */
#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Modular addition input data */
#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */
/* Modular addition output data */
#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Modular inversion input data */
#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */
/* Modular inversion output data */
#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Modular subtraction input data */
#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */
/* Modular subtraction output data */
#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Montgomery multiplication input data */
#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */
/* Montgomery multiplication output data */
#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */
/* Generic Arithmetic input data */
#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */
/* Generic Arithmetic output data */
#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */
/* Compute ECC complete addition input data */
#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
/* Compute ECC complete addition output data */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */
#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */
/* Compute ECC double base ladder input data */
#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */
#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */
/* Compute ECC double base ladder output data */
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */
#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */
#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
/* Compute ECC projective to affine conversion input data */
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */
#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */
#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */
/* Compute ECC projective to affine conversion output data */
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */
#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */
#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */
/******************************************************************************/
/* */
/* Parallel Synchronous Slave Interface (PSSI ) */
/* */
/******************************************************************************/
/******************** Bit definition for PSSI_CR register *******************/
#define PSSI_CR_CKPOL_Pos (5U)
#define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000020 */
#define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */
#define PSSI_CR_DEPOL_Pos (6U)
#define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000040 */
#define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */
#define PSSI_CR_RDYPOL_Pos (8U)
#define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000100 */
#define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */
#define PSSI_CR_EDM_Pos (10U)
#define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */
#define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */
#define PSSI_CR_ENABLE_Pos (14U)
#define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */
#define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */
#define PSSI_CR_DERDYCFG_Pos (18U)
#define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */
#define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */
#define PSSI_CR_CKSRC_Pos (29U)
#define PSSI_CR_CKSRC_Msk (0x1UL << PSSI_CR_CKSRC_Pos) /*!< 0x20000000 */
#define PSSI_CR_CKSRC PSSI_CR_CKSRC_Msk /*!< Clock source */
#define PSSI_CR_DMAEN_Pos (30U)
#define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */
#define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */
#define PSSI_CR_OUTEN_Pos (31U)
#define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */
#define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */
/******************** Bit definition for PSSI_SR register *******************/
#define PSSI_SR_RTT4B_Pos (2U)
#define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */
#define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */
#define PSSI_SR_RTT1B_Pos (3U)
#define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */
#define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */
/******************** Bit definition for PSSI_RIS register *******************/
#define PSSI_RIS_OVR_RIS_Pos (1U)
#define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
#define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */
/******************** Bit definition for PSSI_IER register *******************/
#define PSSI_IER_OVR_IE_Pos (1U)
#define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */
#define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */
/******************** Bit definition for PSSI_MIS register *******************/
#define PSSI_MIS_OVR_MIS_Pos (1U)
#define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
#define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */
/******************** Bit definition for PSSI_ICR register *******************/
#define PSSI_ICR_OVR_ISC_Pos (1U)
#define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
#define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */
/******************** Bit definition for PSSI_DR register *******************/
#define PSSI_DR_DR_Pos (0U)
#define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */
#define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************* Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_SDEN_Pos (2U)
#define PWR_CR1_SDEN_Msk (0x1UL << PWR_CR1_SDEN_Pos) /*!< 0x00000004 */
#define PWR_CR1_SDEN PWR_CR1_SDEN_Msk /*!< SMPS step-down converter enable */
#define PWR_CR1_MODE_PDN_Pos (4U)
#define PWR_CR1_MODE_PDN_Msk (0x1UL << PWR_CR1_MODE_PDN_Pos) /*!< 0x00000010 */
#define PWR_CR1_MODE_PDN PWR_CR1_MODE_PDN_Msk /*!< Pull down on output voltage during power down mode */
#define PWR_CR1_LPDS08V_Pos (5U)
#define PWR_CR1_LPDS08V_Msk (0x1UL << PWR_CR1_LPDS08V_Pos) /*!< 0x00000020 */
#define PWR_CR1_LPDS08V PWR_CR1_LPDS08V_Msk /*!< SMPS Low power mode enable (SVOS high only) */
#define PWR_CR1_VDD18SMPSVMEN_Pos (8U)
#define PWR_CR1_VDD18SMPSVMEN_Msk (0x1UL << PWR_CR1_VDD18SMPSVMEN_Pos) /*!< 0x00000100 */
#define PWR_CR1_VDD18SMPSVMEN PWR_CR1_VDD18SMPSVMEN_Msk /*!< VDD18SMPS voltage monitor enable */
#define PWR_CR1_VDD18SMPSRDY_Pos (15U)
#define PWR_CR1_VDD18SMPSRDY_Msk (0x1UL << PWR_CR1_VDD18SMPSRDY_Pos) /*!< 0x00008000 */
#define PWR_CR1_VDD18SMPSRDY PWR_CR1_VDD18SMPSRDY_Msk /*!< VDD18SMPS ready */
#define PWR_CR1_POPL_Pos (16U)
#define PWR_CR1_POPL_Msk (0x1FUL << PWR_CR1_POPL_Pos) /*!< 0x001F0000 */
#define PWR_CR1_POPL PWR_CR1_POPL_Msk /*!< pwr_on pulse low configuration */
#define PWR_CR1_POPL_0 (0x1UL << PWR_CR1_POPL_Pos) /*!< 0x00010000 */
#define PWR_CR1_POPL_1 (0x2UL << PWR_CR1_POPL_Pos) /*!< 0x00020000 */
#define PWR_CR1_POPL_2 (0x4UL << PWR_CR1_POPL_Pos) /*!< 0x00040000 */
#define PWR_CR1_POPL_3 (0x8UL << PWR_CR1_POPL_Pos) /*!< 0x00080000 */
#define PWR_CR1_POPL_4 (0x10UL << PWR_CR1_POPL_Pos) /*!< 0x00100000 */
/******************* Bit definition for PWR_CR2 register ********************/
#define PWR_CR2_PVDEN_Pos (0U)
#define PWR_CR2_PVDEN_Msk (0x1UL << PWR_CR2_PVDEN_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDEN PWR_CR2_PVDEN_Msk /*!< Programmable Voltage detector enable */
#define PWR_CR2_PVDO_Pos (8U)
#define PWR_CR2_PVDO_Msk (0x1UL << PWR_CR2_PVDO_Pos) /*!< 0x00000100 */
#define PWR_CR2_PVDO PWR_CR2_PVDO_Msk /*!< Programmable Voltage Detect Output */
/******************* Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_VCOREMONEN_Pos (0U)
#define PWR_CR3_VCOREMONEN_Msk (0x1UL << PWR_CR3_VCOREMONEN_Pos) /*!< 0x00000001 */
#define PWR_CR3_VCOREMONEN PWR_CR3_VCOREMONEN_Msk /*!< VDDCORE monitoring enable */
#define PWR_CR3_VCORELLS_Pos (4U)
#define PWR_CR3_VCORELLS_Msk (0x1UL << PWR_CR3_VCORELLS_Pos) /*!< 0x00000010 */
#define PWR_CR3_VCORELLS PWR_CR3_VCORELLS_Msk /*!< VDDCORE Voltage Detector low level selection */
#define PWR_CR3_VCOREL_Pos (8U)
#define PWR_CR3_VCOREL_Msk (0x1UL << PWR_CR3_VCOREL_Pos) /*!< 0x00000100 */
#define PWR_CR3_VCOREL PWR_CR3_VCOREL_Msk /*!< Monitored VDDCORE level above low threshold */
#define PWR_CR3_VCOREH_Pos (9U)
#define PWR_CR3_VCOREH_Msk (0x1UL << PWR_CR3_VCOREH_Pos) /*!< 0x00000200 */
#define PWR_CR3_VCOREH PWR_CR3_VCOREH_Msk /*!< Monitored VDDCORE level above high threshold */
/******************* Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_TCMRBSEN_Pos (0U)
#define PWR_CR4_TCMRBSEN_Msk (0x1UL << PWR_CR4_TCMRBSEN_Pos) /*!< 0x00000001 */
#define PWR_CR4_TCMRBSEN PWR_CR4_TCMRBSEN_Msk /*!< I-TCM and D-TCM RAMs backup supply enable (used to maintain TCM RAMs content in Standby mode) */
#define PWR_CR4_TCMFLXRBSEN_Pos (4U)
#define PWR_CR4_TCMFLXRBSEN_Msk (0x1UL << PWR_CR4_TCMFLXRBSEN_Pos) /*!< 0x00000010 */
#define PWR_CR4_TCMFLXRBSEN PWR_CR4_TCMFLXRBSEN_Msk /*!< I-TCM FLEX MEM backup supply enable (used to maintain I-TCM FLEX MEM content in Standby mode) */
/****************** Bit definition for PWR_VOSCR register *******************/
#define PWR_VOSCR_VOS_Pos (0U)
#define PWR_VOSCR_VOS_Msk (0x1UL << PWR_VOSCR_VOS_Pos) /*!< 0x00000001 */
#define PWR_VOSCR_VOS PWR_VOSCR_VOS_Msk /*!< Voltage scaling selection according to performance */
#define PWR_VOSCR_VOSRDY_Pos (1U)
#define PWR_VOSCR_VOSRDY_Msk (0x1UL << PWR_VOSCR_VOSRDY_Pos) /*!< 0x00000002 */
#define PWR_VOSCR_VOSRDY PWR_VOSCR_VOSRDY_Msk /*!< VOS Ready bit for VCORE voltage scaling output selection */
#define PWR_VOSCR_ACTVOS_Pos (16U)
#define PWR_VOSCR_ACTVOS_Msk (0x1UL << PWR_VOSCR_ACTVOS_Pos) /*!< 0x00010000 */
#define PWR_VOSCR_ACTVOS PWR_VOSCR_ACTVOS_Msk /*!< VOS currently applied for VCORE voltage scaling selection */
#define PWR_VOSCR_ACTVOSRDY_Pos (17U)
#define PWR_VOSCR_ACTVOSRDY_Msk (0x1UL << PWR_VOSCR_ACTVOSRDY_Pos) /*!< 0x00020000 */
#define PWR_VOSCR_ACTVOSRDY PWR_VOSCR_ACTVOSRDY_Msk /*!< Voltage levels ready bit for currently used ACTVOS */
/****************** Bit definition for PWR_BDCR1 register *******************/
#define PWR_BDCR1_MONEN_Pos (0U)
#define PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) /*!< 0x00000001 */
#define PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk /*!< VBAT and temperature monitoring enable */
#define PWR_BDCR1_VBATL_Pos (16U)
#define PWR_BDCR1_VBATL_Msk (0x1UL << PWR_BDCR1_VBATL_Pos) /*!< 0x00010000 */
#define PWR_BDCR1_VBATL PWR_BDCR1_VBATL_Msk /*!< VBAT level monitoring versus low threshold */
#define PWR_BDCR1_VBATH_Pos (17U)
#define PWR_BDCR1_VBATH_Msk (0x1UL << PWR_BDCR1_VBATH_Pos) /*!< 0x00020000 */
#define PWR_BDCR1_VBATH PWR_BDCR1_VBATH_Msk /*!< VBAT level monitoring versus high threshold */
#define PWR_BDCR1_TEMPL_Pos (18U)
#define PWR_BDCR1_TEMPL_Msk (0x1UL << PWR_BDCR1_TEMPL_Pos) /*!< 0x00040000 */
#define PWR_BDCR1_TEMPL PWR_BDCR1_TEMPL_Msk /*!< Temperature level monitoring versus low threshold */
#define PWR_BDCR1_TEMPH_Pos (19U)
#define PWR_BDCR1_TEMPH_Msk (0x1UL << PWR_BDCR1_TEMPH_Pos) /*!< 0x00080000 */
#define PWR_BDCR1_TEMPH PWR_BDCR1_TEMPH_Msk /*!< Temperature level monitoring versus high threshold */
/****************** Bit definition for PWR_BDCR2 register *******************/
#define PWR_BDCR2_BKPRBSEN_Pos (0U)
#define PWR_BDCR2_BKPRBSEN_Msk (0x1UL << PWR_BDCR2_BKPRBSEN_Pos) /*!< 0x00000001 */
#define PWR_BDCR2_BKPRBSEN PWR_BDCR2_BKPRBSEN_Msk /*!< Backup RAM backup supply enable (used to maintain BKP RAM content in Standby and VBAT modes) */
/****************** Bit definition for PWR_DBPCR register *******************/
#define PWR_DBPCR_DBP_Pos (0U)
#define PWR_DBPCR_DBP_Msk (0x1UL << PWR_DBPCR_DBP_Pos) /*!< 0x00000001 */
#define PWR_DBPCR_DBP PWR_DBPCR_DBP_Msk /*!< Disable backup domain write protection */
/****************** Bit definition for PWR_CPUCR register *******************/
#define PWR_CPUCR_PDDS_Pos (0U)
#define PWR_CPUCR_PDDS_Msk (0x1UL << PWR_CPUCR_PDDS_Pos) /*!< 0x00000001 */
#define PWR_CPUCR_PDDS PWR_CPUCR_PDDS_Msk /*!< Power Down Deepsleep selection */
#define PWR_CPUCR_CSSF_Pos (1U)
#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000002 */
#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear Standby and Stop flags (always read as 0) */
#define PWR_CPUCR_STOPF_Pos (8U)
#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000100 */
#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP flag */
#define PWR_CPUCR_SBF_Pos (9U)
#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000200 */
#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System Standby flag */
#define PWR_CPUCR_SVOS_Pos (16U)
#define PWR_CPUCR_SVOS_Msk (0x1UL << PWR_CPUCR_SVOS_Pos) /*!< 0x00010000 */
#define PWR_CPUCR_SVOS PWR_CPUCR_SVOS_Msk /*!< System Stop mode voltage scaling selection */
/****************** Bit definition for PWR_SVMCR1 register ******************/
#define PWR_SVMCR1_VDDIO4VMEN_Pos (0U)
#define PWR_SVMCR1_VDDIO4VMEN_Msk (0x1UL << PWR_SVMCR1_VDDIO4VMEN_Pos) /*!< 0x00000001 */
#define PWR_SVMCR1_VDDIO4VMEN PWR_SVMCR1_VDDIO4VMEN_Msk /*!< VDDOI4 Independent I/Os voltage monitor enable */
#define PWR_SVMCR1_VDDIO4SV_Pos (8U)
#define PWR_SVMCR1_VDDIO4SV_Msk (0x1UL << PWR_SVMCR1_VDDIO4SV_Pos) /*!< 0x00000100 */
#define PWR_SVMCR1_VDDIO4SV PWR_SVMCR1_VDDIO4SV_Msk /*!< VDDIO4 Independent I/Os supply valid */
#define PWR_SVMCR1_VDDIO4RDY_Pos (16U)
#define PWR_SVMCR1_VDDIO4RDY_Msk (0x1UL << PWR_SVMCR1_VDDIO4RDY_Pos) /*!< 0x00010000 */
#define PWR_SVMCR1_VDDIO4RDY PWR_SVMCR1_VDDIO4RDY_Msk /*!< VDDIO4 ready */
#define PWR_SVMCR1_VDDIO4VRSEL_Pos (24U)
#define PWR_SVMCR1_VDDIO4VRSEL_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSEL_Pos) /*!< 0x01000000 */
#define PWR_SVMCR1_VDDIO4VRSEL PWR_SVMCR1_VDDIO4VRSEL_Msk /*!< VDDIO4 IO voltage range selection */
#define PWR_SVMCR1_VDDIO4VRSTBY_Pos (25U)
#define PWR_SVMCR1_VDDIO4VRSTBY_Msk (0x1UL << PWR_SVMCR1_VDDIO4VRSTBY_Pos) /*!< 0x04000000 */
#define PWR_SVMCR1_VDDIO4VRSTBY PWR_SVMCR1_VDDIO4VRSTBY_Msk /*!< VDDIO4 IO voltage range standby mode */
/****************** Bit definition for PWR_SVMCR2 register ******************/
#define PWR_SVMCR2_VDDIO5VMEN_Pos (0U)
#define PWR_SVMCR2_VDDIO5VMEN_Msk (0x1UL << PWR_SVMCR2_VDDIO5VMEN_Pos) /*!< 0x00000001 */
#define PWR_SVMCR2_VDDIO5VMEN PWR_SVMCR2_VDDIO5VMEN_Msk /*!< VDDIO5 Independent voltage monitor enable */
#define PWR_SVMCR2_VDDIO5SV_Pos (8U)
#define PWR_SVMCR2_VDDIO5SV_Msk (0x1UL << PWR_SVMCR2_VDDIO5SV_Pos) /*!< 0x00000100 */
#define PWR_SVMCR2_VDDIO5SV PWR_SVMCR2_VDDIO5SV_Msk /*!< VDDIO5 Independent supply valid */
#define PWR_SVMCR2_VDDIO5RDY_Pos (16U)
#define PWR_SVMCR2_VDDIO5RDY_Msk (0x1UL << PWR_SVMCR2_VDDIO5RDY_Pos) /*!< 0x00010000 */
#define PWR_SVMCR2_VDDIO5RDY PWR_SVMCR2_VDDIO5RDY_Msk /*!< VDDIO5 ready */
#define PWR_SVMCR2_VDDIO5VRSEL_Pos (24U)
#define PWR_SVMCR2_VDDIO5VRSEL_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSEL_Pos) /*!< 0x01000000 */
#define PWR_SVMCR2_VDDIO5VRSEL PWR_SVMCR2_VDDIO5VRSEL_Msk /*!< VDDIO5 IO voltage range selection */
#define PWR_SVMCR2_VDDIO5VRSTBY_Pos (25U)
#define PWR_SVMCR2_VDDIO5VRSTBY_Msk (0x1UL << PWR_SVMCR2_VDDIO5VRSTBY_Pos) /*!< 0x02000000 */
#define PWR_SVMCR2_VDDIO5VRSTBY PWR_SVMCR2_VDDIO5VRSTBY_Msk /*!< VDDIO5 IO voltage range standby mode */
/****************** Bit definition for PWR_SVMCR3 register ******************/
#define PWR_SVMCR3_VDDIO2VMEN_Pos (0U)
#define PWR_SVMCR3_VDDIO2VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO2VMEN_Pos) /*!< 0x00000001 */
#define PWR_SVMCR3_VDDIO2VMEN PWR_SVMCR3_VDDIO2VMEN_Msk /*!< VDDIO2 Independent voltage monitor enable */
#define PWR_SVMCR3_VDDIO3VMEN_Pos (1U)
#define PWR_SVMCR3_VDDIO3VMEN_Msk (0x1UL << PWR_SVMCR3_VDDIO3VMEN_Pos) /*!< 0x00000002 */
#define PWR_SVMCR3_VDDIO3VMEN PWR_SVMCR3_VDDIO3VMEN_Msk /*!< VDDIO3 Independent voltage monitor enable */
#define PWR_SVMCR3_USB33VMEN_Pos (2U)
#define PWR_SVMCR3_USB33VMEN_Msk (0x1UL << PWR_SVMCR3_USB33VMEN_Pos) /*!< 0x00000004 */
#define PWR_SVMCR3_USB33VMEN PWR_SVMCR3_USB33VMEN_Msk /*!< VDD33USB Independent USB 33 voltage monitor enable */
#define PWR_SVMCR3_AVMEN_Pos (4U)
#define PWR_SVMCR3_AVMEN_Msk (0x1UL << PWR_SVMCR3_AVMEN_Pos) /*!< 0x00000010 */
#define PWR_SVMCR3_AVMEN PWR_SVMCR3_AVMEN_Msk /*!< VDDA18ADC Independent ADC voltage monitor enable */
#define PWR_SVMCR3_VDDIO2SV_Pos (8U)
#define PWR_SVMCR3_VDDIO2SV_Msk (0x1UL << PWR_SVMCR3_VDDIO2SV_Pos) /*!< 0x00000100 */
#define PWR_SVMCR3_VDDIO2SV PWR_SVMCR3_VDDIO2SV_Msk /*!< VDDIO2 Independent supply valid */
#define PWR_SVMCR3_VDDIO3SV_Pos (9U)
#define PWR_SVMCR3_VDDIO3SV_Msk (0x1UL << PWR_SVMCR3_VDDIO3SV_Pos) /*!< 0x00000200 */
#define PWR_SVMCR3_VDDIO3SV PWR_SVMCR3_VDDIO3SV_Msk /*!< VDDIO3 Independent supply valid */
#define PWR_SVMCR3_USB33SV_Pos (10U)
#define PWR_SVMCR3_USB33SV_Msk (0x1UL << PWR_SVMCR3_USB33SV_Pos) /*!< 0x00000400 */
#define PWR_SVMCR3_USB33SV PWR_SVMCR3_USB33SV_Msk /*!< VDD33USB Independent supply valid */
#define PWR_SVMCR3_ASV_Pos (12U)
#define PWR_SVMCR3_ASV_Msk (0x1UL << PWR_SVMCR3_ASV_Pos) /*!< 0x00001000 */
#define PWR_SVMCR3_ASV PWR_SVMCR3_ASV_Msk /*!< VDDA18ADC Independent supply valid */
#define PWR_SVMCR3_VDDIO2RDY_Pos (16U)
#define PWR_SVMCR3_VDDIO2RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO2RDY_Pos) /*!< 0x00010000 */
#define PWR_SVMCR3_VDDIO2RDY PWR_SVMCR3_VDDIO2RDY_Msk /*!< VDDIO2 ready */
#define PWR_SVMCR3_VDDIO3RDY_Pos (17U)
#define PWR_SVMCR3_VDDIO3RDY_Msk (0x1UL << PWR_SVMCR3_VDDIO3RDY_Pos) /*!< 0x00020000 */
#define PWR_SVMCR3_VDDIO3RDY PWR_SVMCR3_VDDIO3RDY_Msk /*!< VDDIO3 ready */
#define PWR_SVMCR3_USB33RDY_Pos (18U)
#define PWR_SVMCR3_USB33RDY_Msk (0x1UL << PWR_SVMCR3_USB33RDY_Pos) /*!< 0x00040000 */
#define PWR_SVMCR3_USB33RDY PWR_SVMCR3_USB33RDY_Msk /*!< VDD33USB ready */
#define PWR_SVMCR3_ARDY_Pos (20U)
#define PWR_SVMCR3_ARDY_Msk (0x1UL << PWR_SVMCR3_ARDY_Pos) /*!< 0x00100000 */
#define PWR_SVMCR3_ARDY PWR_SVMCR3_ARDY_Msk /*!< VDDA18ADC ready */
#define PWR_SVMCR3_VDDIOVRSEL_Pos (24U)
#define PWR_SVMCR3_VDDIOVRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIOVRSEL_Pos) /*!< 0x01000000 */
#define PWR_SVMCR3_VDDIOVRSEL PWR_SVMCR3_VDDIOVRSEL_Msk /*!< VDD IO voltage range selection */
#define PWR_SVMCR3_VDDIO2VRSEL_Pos (25U)
#define PWR_SVMCR3_VDDIO2VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO2VRSEL_Pos) /*!< 0x02000000 */
#define PWR_SVMCR3_VDDIO2VRSEL PWR_SVMCR3_VDDIO2VRSEL_Msk /*!< VDDIO2 IO voltage range selection */
#define PWR_SVMCR3_VDDIO3VRSEL_Pos (26U)
#define PWR_SVMCR3_VDDIO3VRSEL_Msk (0x1UL << PWR_SVMCR3_VDDIO3VRSEL_Pos) /*!< 0x04000000 */
#define PWR_SVMCR3_VDDIO3VRSEL PWR_SVMCR3_VDDIO3VRSEL_Msk /*!< VDDIO3 IO voltage range selection */
/***************** Bit definition for PWR_WKUPCR register *******************/
#define PWR_WKUPCR_WKUPC1_Pos (0U)
#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Flag for WKUP1 pin */
#define PWR_WKUPCR_WKUPC2_Pos (1U)
#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Flag for WKUP2 pin */
#define PWR_WKUPCR_WKUPC3_Pos (2U)
#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Flag for WKUP3 pin */
#define PWR_WKUPCR_WKUPC4_Pos (3U)
#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Flag for WKUP4 pin */
#define PWR_WKUPCR_WKUPC_Pos (0U)
#define PWR_WKUPCR_WKUPC_Msk (0xFUL << PWR_WKUPCR_WKUPC_Pos) /*!< 0x0000000F */
#define PWR_WKUPCR_WKUPC PWR_WKUPCR_WKUPC_Msk /*!< Clear Wakeup Flag 1 to 4 */
/***************** Bit definition for PWR_WKUPSR register *******************/
#define PWR_WKUPSR_WKUPF1_Pos (0U)
#define PWR_WKUPSR_WKUPF1_Msk (0x1UL << PWR_WKUPSR_WKUPF1_Pos) /*!< 0x00000001 */
#define PWR_WKUPSR_WKUPF1 PWR_WKUPSR_WKUPF1_Msk /*!< Wakeup Flag for WKUP1 pin */
#define PWR_WKUPSR_WKUPF2_Pos (1U)
#define PWR_WKUPSR_WKUPF2_Msk (0x1UL << PWR_WKUPSR_WKUPF2_Pos) /*!< 0x00000002 */
#define PWR_WKUPSR_WKUPF2 PWR_WKUPSR_WKUPF2_Msk /*!< Wakeup Flag for WKUP2 pin */
#define PWR_WKUPSR_WKUPF3_Pos (2U)
#define PWR_WKUPSR_WKUPF3_Msk (0x1UL << PWR_WKUPSR_WKUPF3_Pos) /*!< 0x00000004 */
#define PWR_WKUPSR_WKUPF3 PWR_WKUPSR_WKUPF3_Msk /*!< Wakeup Flag for WKUP3 pin */
#define PWR_WKUPSR_WKUPF4_Pos (3U)
#define PWR_WKUPSR_WKUPF4_Msk (0x1UL << PWR_WKUPSR_WKUPF4_Pos) /*!< 0x00000008 */
#define PWR_WKUPSR_WKUPF4 PWR_WKUPSR_WKUPF4_Msk /*!< Wakeup Flag for WKUP4 pin */
/***************** Bit definition for PWR_WKUPEPR register *******************/
#define PWR_WKUPEPR_WKUPEN1_Pos (0U)
#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup pin WKUP1 */
#define PWR_WKUPEPR_WKUPEN2_Pos (1U)
#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup pin WKUP2 */
#define PWR_WKUPEPR_WKUPEN3_Pos (2U)
#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup pin WKUP3 */
#define PWR_WKUPEPR_WKUPEN4_Pos (3U)
#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup pin WKUP4 */
#define PWR_WKUPEPR_WKUPP1_Pos (8U)
#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Polarity bit for WKUP1 pin */
#define PWR_WKUPEPR_WKUPP2_Pos (9U)
#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Polarity bit for WKUP2 pin */
#define PWR_WKUPEPR_WKUPP3_Pos (10U)
#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Polarity bit for WKUP3 pin */
#define PWR_WKUPEPR_WKUPP4_Pos (11U)
#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Polarity bit for WKUP4 pin */
#define PWR_WKUPEPR_WKUPP_Pos (8U)
#define PWR_WKUPEPR_WKUPP_Msk (0x0FUL << PWR_WKUPEPR_WKUPP_Pos) /*!< 0x0000300F */
#define PWR_WKUPEPR_WKUPP PWR_WKUPEPR_WKUPP_Msk /*!< Wakeup Pin Polarity for WKUP1 to WKUP4 */
#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup pull configuration for WKUP1 pin */
#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup pull configuration for WKUP2 pin */
#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup pull configuration for WKUP3 pin */
#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup pull configuration for WKUP4 pin */
#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
#define PWR_WKUPEPR_WKUPEN_Pos (0U)
#define PWR_WKUPEPR_WKUPEN_Msk (0x0FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
/***************** Bit definition for PWR_SECCFGR register ******************/
#define PWR_SECCFGR_SEC0_Pos (0U)
#define PWR_SECCFGR_SEC0_Msk (0x1UL << PWR_SECCFGR_SEC0_Pos) /*!< 0x00000001 */
#define PWR_SECCFGR_SEC0 PWR_SECCFGR_SEC0_Msk /*!< System supply configuration secure protection */
#define PWR_SECCFGR_SEC1_Pos (1U)
#define PWR_SECCFGR_SEC1_Msk (0x1UL << PWR_SECCFGR_SEC1_Pos) /*!< 0x00000002 */
#define PWR_SECCFGR_SEC1 PWR_SECCFGR_SEC1_Msk /*!< Programmable voltage detector secure protection */
#define PWR_SECCFGR_SEC2_Pos (2U)
#define PWR_SECCFGR_SEC2_Msk (0x1UL << PWR_SECCFGR_SEC2_Pos) /*!< 0x00000004 */
#define PWR_SECCFGR_SEC2 PWR_SECCFGR_SEC2_Msk /*!< VDDCORE monitor secure protection */
#define PWR_SECCFGR_SEC3_Pos (3U)
#define PWR_SECCFGR_SEC3_Msk (0x1UL << PWR_SECCFGR_SEC3_Pos) /*!< 0x00000008 */
#define PWR_SECCFGR_SEC3 PWR_SECCFGR_SEC3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control secure protection */
#define PWR_SECCFGR_SEC4_Pos (4U)
#define PWR_SECCFGR_SEC4_Msk (0x1UL << PWR_SECCFGR_SEC4_Pos) /*!< 0x00000010 */
#define PWR_SECCFGR_SEC4 PWR_SECCFGR_SEC4_Msk /*!< Voltage scaling selection secure protection */
#define PWR_SECCFGR_SEC5_Pos (5U)
#define PWR_SECCFGR_SEC5_Msk (0x1UL << PWR_SECCFGR_SEC5_Pos) /*!< 0x00000020 */
#define PWR_SECCFGR_SEC5 PWR_SECCFGR_SEC5_Msk /*!< Backup domain secure protection */
#define PWR_SECCFGR_SEC6_Pos (6U)
#define PWR_SECCFGR_SEC6_Msk (0x1UL << PWR_SECCFGR_SEC6_Pos) /*!< 0x00000040 */
#define PWR_SECCFGR_SEC6 PWR_SECCFGR_SEC6_Msk /*!< CPU power control secure protection */
#define PWR_SECCFGR_SEC7_Pos (7U)
#define PWR_SECCFGR_SEC7_Msk (0x1UL << PWR_SECCFGR_SEC7_Pos) /*!< 0x00000080 */
#define PWR_SECCFGR_SEC7 PWR_SECCFGR_SEC7_Msk /*!< Peripheral voltage monitor secure protection */
#define PWR_SECCFGR_WKUPSEC1_Pos (16U)
#define PWR_SECCFGR_WKUPSEC1_Msk (0x1UL << PWR_SECCFGR_WKUPSEC1_Pos) /*!< 0x00010000 */
#define PWR_SECCFGR_WKUPSEC1 PWR_SECCFGR_WKUPSEC1_Msk /*!< WKUP1 secure protection */
#define PWR_SECCFGR_WKUPSEC2_Pos (17U)
#define PWR_SECCFGR_WKUPSEC2_Msk (0x1UL << PWR_SECCFGR_WKUPSEC2_Pos) /*!< 0x00020000 */
#define PWR_SECCFGR_WKUPSEC2 PWR_SECCFGR_WKUPSEC2_Msk /*!< WKUP2 secure protection */
#define PWR_SECCFGR_WKUPSEC3_Pos (18U)
#define PWR_SECCFGR_WKUPSEC3_Msk (0x1UL << PWR_SECCFGR_WKUPSEC3_Pos) /*!< 0x00040000 */
#define PWR_SECCFGR_WKUPSEC3 PWR_SECCFGR_WKUPSEC3_Msk /*!< WKUP3 secure protection */
#define PWR_SECCFGR_WKUPSEC4_Pos (19U)
#define PWR_SECCFGR_WKUPSEC4_Msk (0x1UL << PWR_SECCFGR_WKUPSEC4_Pos) /*!< 0x00080000 */
#define PWR_SECCFGR_WKUPSEC4 PWR_SECCFGR_WKUPSEC4_Msk /*!< WKUP4 secure protection */
/***************** Bit definition for PWR_PRIVCFGR register *****************/
#define PWR_PRIVCFGR_PRIV0_Pos (0U)
#define PWR_PRIVCFGR_PRIV0_Msk (0x1UL << PWR_PRIVCFGR_PRIV0_Pos) /*!< 0x00000001 */
#define PWR_PRIVCFGR_PRIV0 PWR_PRIVCFGR_PRIV0_Msk /*!< System supply configuration privileged protection */
#define PWR_PRIVCFGR_PRIV1_Pos (1U)
#define PWR_PRIVCFGR_PRIV1_Msk (0x1UL << PWR_PRIVCFGR_PRIV1_Pos) /*!< 0x00000002 */
#define PWR_PRIVCFGR_PRIV1 PWR_PRIVCFGR_PRIV1_Msk /*!< Programmable voltage detector privileged protection */
#define PWR_PRIVCFGR_PRIV2_Pos (2U)
#define PWR_PRIVCFGR_PRIV2_Msk (0x1UL << PWR_PRIVCFGR_PRIV2_Pos) /*!< 0x00000004 */
#define PWR_PRIVCFGR_PRIV2 PWR_PRIVCFGR_PRIV2_Msk /*!< VDDCORE monitor privileged protection */
#define PWR_PRIVCFGR_PRIV3_Pos (3U)
#define PWR_PRIVCFGR_PRIV3_Msk (0x1UL << PWR_PRIVCFGR_PRIV3_Pos) /*!< 0x00000008 */
#define PWR_PRIVCFGR_PRIV3 PWR_PRIVCFGR_PRIV3_Msk /*!< I-TCM/D-TCM and I-TCM FLEX MEM low power control privileged protection */
#define PWR_PRIVCFGR_PRIV4_Pos (4U)
#define PWR_PRIVCFGR_PRIV4_Msk (0x1UL << PWR_PRIVCFGR_PRIV4_Pos) /*!< 0x00000010 */
#define PWR_PRIVCFGR_PRIV4 PWR_PRIVCFGR_PRIV4_Msk /*!< Voltage scaling selection privileged protection */
#define PWR_PRIVCFGR_PRIV5_Pos (5U)
#define PWR_PRIVCFGR_PRIV5_Msk (0x1UL << PWR_PRIVCFGR_PRIV5_Pos) /*!< 0x00000020 */
#define PWR_PRIVCFGR_PRIV5 PWR_PRIVCFGR_PRIV5_Msk /*!< Backup domain privileged protection */
#define PWR_PRIVCFGR_PRIV6_Pos (6U)
#define PWR_PRIVCFGR_PRIV6_Msk (0x1UL << PWR_PRIVCFGR_PRIV6_Pos) /*!< 0x00000040 */
#define PWR_PRIVCFGR_PRIV6 PWR_PRIVCFGR_PRIV6_Msk /*!< CPU power control privileged protection */
#define PWR_PRIVCFGR_PRIV7_Pos (7U)
#define PWR_PRIVCFGR_PRIV7_Msk (0x1UL << PWR_PRIVCFGR_PRIV7_Pos) /*!< 0x00000080 */
#define PWR_PRIVCFGR_PRIV7 PWR_PRIVCFGR_PRIV7_Msk /*!< Peripheral voltage monitor privileged protection */
#define PWR_PRIVCFGR_WKUPPRIV1_Pos (16U)
#define PWR_PRIVCFGR_WKUPPRIV1_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV1_Pos) /*!< 0x00010000 */
#define PWR_PRIVCFGR_WKUPPRIV1 PWR_PRIVCFGR_WKUPPRIV1_Msk /*!< WKUP1 privileged protection */
#define PWR_PRIVCFGR_WKUPPRIV2_Pos (17U)
#define PWR_PRIVCFGR_WKUPPRIV2_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV2_Pos) /*!< 0x00020000 */
#define PWR_PRIVCFGR_WKUPPRIV2 PWR_PRIVCFGR_WKUPPRIV2_Msk /*!< WKUP2 privileged protection */
#define PWR_PRIVCFGR_WKUPPRIV3_Pos (18U)
#define PWR_PRIVCFGR_WKUPPRIV3_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV3_Pos) /*!< 0x00040000 */
#define PWR_PRIVCFGR_WKUPPRIV3 PWR_PRIVCFGR_WKUPPRIV3_Msk /*!< WKUP3 privileged protection */
#define PWR_PRIVCFGR_WKUPPRIV4_Pos (19U)
#define PWR_PRIVCFGR_WKUPPRIV4_Msk (0x1UL << PWR_PRIVCFGR_WKUPPRIV4_Pos) /*!< 0x00080000 */
#define PWR_PRIVCFGR_WKUPPRIV4 PWR_PRIVCFGR_WKUPPRIV4_Msk /*!< WKUP4 privileged protection */
/******************************************************************************/
/* */
/* RAMs configuration controller */
/* */
/******************************************************************************/
/******************* Bit definition for RAMCFG_CR register ******************/
#define RAMCFG_CR_ECCE_Pos (0U)
#define RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) /*!< 0x00000001 */
#define RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk /*!< ECC Enable */
#define RAMCFG_CR_ALE_Pos (4U)
#define RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) /*!< 0x00000010 */
#define RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk /*!< Address Latching Enable */
#define RAMCFG_CR_SRAMER_Pos (8U)
#define RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) /*!< 0x00000100 */
#define RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk /*!< Start Erase */
#define RAMCFG_CR_SRAMHWERDIS_Pos (12U)
#define RAMCFG_CR_SRAMHWERDIS_Msk (0x1UL << RAMCFG_CR_SRAMHWERDIS_Pos) /*!< 0x00001000 */
#define RAMCFG_CR_SRAMHWERDIS RAMCFG_CR_SRAMHWERDIS_Msk /*!< SRAM hardware erase disable */
#define RAMCFG_CR_ITCMCFG_Pos (16U)
#define RAMCFG_CR_ITCMCFG_Msk (0x3UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00030000 */
#define RAMCFG_CR_ITCMCFG RAMCFG_CR_ITCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */
#define RAMCFG_CR_ITCMCFG_0 (0x1UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00010000 */
#define RAMCFG_CR_ITCMCFG_1 (0x2UL << RAMCFG_CR_ITCMCFG_Pos) /*!< 0x00020000 */
#define RAMCFG_CR_SRAMSD_Pos (20U)
#define RAMCFG_CR_SRAMSD_Msk (0x1UL << RAMCFG_CR_SRAMSD_Pos) /*!< 0x00100000 */
#define RAMCFG_CR_SRAMSD RAMCFG_CR_SRAMSD_Msk /*!< Shutdown AXISRAMx */
#define RAMCFG_CR_DTCMCFG_Pos (24U)
#define RAMCFG_CR_DTCMCFG_Msk (0x1UL << RAMCFG_CR_DTCMCFG_Pos) /*!< 0x01000000 */
#define RAMCFG_CR_DTCMCFG RAMCFG_CR_DTCMCFG_Msk /*!< Configuration of the FLEXMEM D-TCM extension */
/******************* Bit definition for RAMCFG_IER register *****************/
#define RAMCFG_IER_SEIE_Pos (0U)
#define RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) /*!< 0x00000001 */
#define RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk /*!< Single Error Interrupt Enable */
#define RAMCFG_IER_DEIE_Pos (1U)
#define RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) /*!< 0x00000002 */
#define RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk /*!< Double Error Interrupt Enable */
/******************* Bit definition for RAMCFG_ISR register *****************/
#define RAMCFG_ISR_SEDC_Pos (0U)
#define RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) /*!< 0x00000001 */
#define RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk /*!< Single Error Detected and Corrected flag */
#define RAMCFG_ISR_DED_Pos (1U)
#define RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) /*!< 0x00000002 */
#define RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk /*!< Double Error Detected flag */
#define RAMCFG_ISR_SRAMBUSY_Pos (8U)
#define RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) /*!< 0x00000100 */
#define RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk /*!< SRAM busy flag */
/******************* Bit definition for RAMCFG_ESEAR register ****************/
#define RAMCFG_ESEAR_ESEA_Pos (0U)
#define RAMCFG_ESEAR_ESEA_Msk (0x7FFUL << RAMCFG_ESEAR_ESEA_Pos) /*!< 0x000007FF */
#define RAMCFG_ESEAR_ESEA RAMCFG_ESEAR_ESEA_Msk /*!< ECC Single Error Address */
/******************* Bit definition for RAMCFG_EDEAR register ****************/
#define RAMCFG_EDEAR_EDEA_Pos (0U)
#define RAMCFG_EDEAR_EDEA_Msk (0x7FFUL << RAMCFG_EDEAR_EDEA_Pos) /*!< 0x000007FF */
#define RAMCFG_EDEAR_EDEA RAMCFG_EDEAR_EDEA_Msk /*!< ECC Double Error Address */
/******************* Bit definition for RAMCFG_ICR register *****************/
#define RAMCFG_ICR_CSEDC_Pos (0U)
#define RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) /*!< 0x00000001 */
#define RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk /*!< Clear ECC Single Error Detected and Corrected Flag */
#define RAMCFG_ICR_CDED_Pos (1U)
#define RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) /*!< 0x00000002 */
#define RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk /*!< Clear ECC Double Error Detected Flag*/
/***************** Bit definition for RAMCFG_ECCKEYR register ***************/
#define RAMCFG_ECCKEYR_ECCKEY_Pos (0U)
#define RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) /*!< 0x000000FF */
#define RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk /*!< ECC Write Protection Key */
/***************** Bit definition for RAMCFG_ERKEYR register ****************/
#define RAMCFG_ERKEYR_ERASEKEY_Pos (0U)
#define RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) /*!< 0x000000FF */
#define RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk /*!< Erase Write Protection Key */
/******************************************************************************/
/* */
/* (RCC) */
/* */
/******************************************************************************/
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_LSION_Pos (0U)
#define RCC_CR_LSION_Msk (0x1UL << RCC_CR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CR_LSION RCC_CR_LSION_Msk /*!< LSI oscillator enable */
#define RCC_CR_LSEON_Pos (1U)
#define RCC_CR_LSEON_Msk (0x1UL << RCC_CR_LSEON_Pos) /*!< 0x00000002 */
#define RCC_CR_LSEON RCC_CR_LSEON_Msk /*!< LSE oscillator enable */
#define RCC_CR_MSION_Pos (2U)
#define RCC_CR_MSION_Msk (0x1UL << RCC_CR_MSION_Pos) /*!< 0x00000004 */
#define RCC_CR_MSION RCC_CR_MSION_Msk /*!< MSI oscillator enable */
#define RCC_CR_HSION_Pos (3U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000008 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< HSI oscillator enable */
#define RCC_CR_HSEON_Pos (4U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00000010 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< HSE oscillator enable */
#define RCC_CR_PLL1ON_Pos (8U)
#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x00000100 */
#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< PLL1 enable */
#define RCC_CR_PLL2ON_Pos (9U)
#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x00000200 */
#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */
#define RCC_CR_PLL3ON_Pos (10U)
#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x00000400 */
#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */
#define RCC_CR_PLL4ON_Pos (11U)
#define RCC_CR_PLL4ON_Msk (0x1UL << RCC_CR_PLL4ON_Pos) /*!< 0x00000800 */
#define RCC_CR_PLL4ON RCC_CR_PLL4ON_Msk /*!< PLL4 enable */
/******************** Bit definition for RCC_SR register ********************/
#define RCC_SR_LSIRDY_Pos (0U)
#define RCC_SR_LSIRDY_Msk (0x1UL << RCC_SR_LSIRDY_Pos) /*!< 0x00000001 */
#define RCC_SR_LSIRDY RCC_SR_LSIRDY_Msk /*!< LSI clock ready flag */
#define RCC_SR_LSERDY_Pos (1U)
#define RCC_SR_LSERDY_Msk (0x1UL << RCC_SR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_SR_LSERDY RCC_SR_LSERDY_Msk /*!< LSE clock ready flag */
#define RCC_SR_MSIRDY_Pos (2U)
#define RCC_SR_MSIRDY_Msk (0x1UL << RCC_SR_MSIRDY_Pos) /*!< 0x00000004 */
#define RCC_SR_MSIRDY RCC_SR_MSIRDY_Msk /*!< MSI clock ready flag */
#define RCC_SR_HSIRDY_Pos (3U)
#define RCC_SR_HSIRDY_Msk (0x1UL << RCC_SR_HSIRDY_Pos) /*!< 0x00000008 */
#define RCC_SR_HSIRDY RCC_SR_HSIRDY_Msk /*!< HSI clock ready flag */
#define RCC_SR_HSERDY_Pos (4U)
#define RCC_SR_HSERDY_Msk (0x1UL << RCC_SR_HSERDY_Pos) /*!< 0x00000010 */
#define RCC_SR_HSERDY RCC_SR_HSERDY_Msk /*!< HSE clock ready flag */
#define RCC_SR_PLL1RDY_Pos (8U)
#define RCC_SR_PLL1RDY_Msk (0x1UL << RCC_SR_PLL1RDY_Pos) /*!< 0x00000100 */
#define RCC_SR_PLL1RDY RCC_SR_PLL1RDY_Msk /*!< PLL1 clock ready flag */
#define RCC_SR_PLL2RDY_Pos (9U)
#define RCC_SR_PLL2RDY_Msk (0x1UL << RCC_SR_PLL2RDY_Pos) /*!< 0x00000200 */
#define RCC_SR_PLL2RDY RCC_SR_PLL2RDY_Msk /*!< PLL2 clock ready flag */
#define RCC_SR_PLL3RDY_Pos (10U)
#define RCC_SR_PLL3RDY_Msk (0x1UL << RCC_SR_PLL3RDY_Pos) /*!< 0x00000400 */
#define RCC_SR_PLL3RDY RCC_SR_PLL3RDY_Msk /*!< PLL3 clock ready flag */
#define RCC_SR_PLL4RDY_Pos (11U)
#define RCC_SR_PLL4RDY_Msk (0x1UL << RCC_SR_PLL4RDY_Pos) /*!< 0x00000800 */
#define RCC_SR_PLL4RDY RCC_SR_PLL4RDY_Msk /*!< PLL4 clock ready flag */
/****************** Bit definition for RCC_STOPCR register ******************/
#define RCC_STOPCR_MSISTOPEN_Pos (0U)
#define RCC_STOPCR_MSISTOPEN_Msk (0x1UL << RCC_STOPCR_MSISTOPEN_Pos) /*!< 0x00000001 */
#define RCC_STOPCR_MSISTOPEN RCC_STOPCR_MSISTOPEN_Msk /*!< MSI oscillator enable */
#define RCC_STOPCR_HSISTOPEN_Pos (1U)
#define RCC_STOPCR_HSISTOPEN_Msk (0x1UL << RCC_STOPCR_HSISTOPEN_Pos) /*!< 0x00000002 */
#define RCC_STOPCR_HSISTOPEN RCC_STOPCR_HSISTOPEN_Msk /*!< HSI oscillator enable */
/****************** Bit definition for RCC_CFGR1 register *******************/
#define RCC_CFGR1_STOPWUCK_Pos (0U)
#define RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) /*!< 0x00000001 */
#define RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk /*!< System clock selection after a wake up from system stop */
#define RCC_CFGR1_CPUSW_Pos (16U)
#define RCC_CFGR1_CPUSW_Msk (0x3UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00030000 */
#define RCC_CFGR1_CPUSW RCC_CFGR1_CPUSW_Msk /*!< CPU clock switch selection */
#define RCC_CFGR1_CPUSW_0 (0x1UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00010000 */
#define RCC_CFGR1_CPUSW_1 (0x2UL << RCC_CFGR1_CPUSW_Pos) /*!< 0x00020000 */
#define RCC_CFGR1_CPUSWS_Pos (20U)
#define RCC_CFGR1_CPUSWS_Msk (0x3UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00300000 */
#define RCC_CFGR1_CPUSWS RCC_CFGR1_CPUSWS_Msk /*!< CPU clock switch status */
#define RCC_CFGR1_CPUSWS_0 (0x1UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00100000 */
#define RCC_CFGR1_CPUSWS_1 (0x2UL << RCC_CFGR1_CPUSWS_Pos) /*!< 0x00200000 */
#define RCC_CFGR1_SYSSW_Pos (24U)
#define RCC_CFGR1_SYSSW_Msk (0x3UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x03000000 */
#define RCC_CFGR1_SYSSW RCC_CFGR1_SYSSW_Msk /*!< System clock switch selection */
#define RCC_CFGR1_SYSSW_0 (0x1UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x01000000 */
#define RCC_CFGR1_SYSSW_1 (0x2UL << RCC_CFGR1_SYSSW_Pos) /*!< 0x02000000 */
#define RCC_CFGR1_SYSSWS_Pos (28U)
#define RCC_CFGR1_SYSSWS_Msk (0x3UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x30000000 */
#define RCC_CFGR1_SYSSWS RCC_CFGR1_SYSSWS_Msk /*!< System clock switch status */
#define RCC_CFGR1_SYSSWS_0 (0x1UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x10000000 */
#define RCC_CFGR1_SYSSWS_1 (0x2UL << RCC_CFGR1_SYSSWS_Pos) /*!< 0x20000000 */
/****************** Bit definition for RCC_CFGR2 register *******************/
#define RCC_CFGR2_PPRE1_Pos (0U)
#define RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000007 */
#define RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk /*!< CPU domain APB1 prescaler */
#define RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000001 */
#define RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000002 */
#define RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) /*!< 0x00000004 */
#define RCC_CFGR2_PPRE2_Pos (4U)
#define RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000070 */
#define RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk /*!< CPU domain APB2 prescaler */
#define RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000010 */
#define RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000020 */
#define RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) /*!< 0x00000040 */
#define RCC_CFGR2_PPRE4_Pos (12U)
#define RCC_CFGR2_PPRE4_Msk (0x7UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00007000 */
#define RCC_CFGR2_PPRE4 RCC_CFGR2_PPRE4_Msk /*!< CPU domain APB4 prescaler */
#define RCC_CFGR2_PPRE4_0 (0x1UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00001000 */
#define RCC_CFGR2_PPRE4_1 (0x2UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00002000 */
#define RCC_CFGR2_PPRE4_2 (0x4UL << RCC_CFGR2_PPRE4_Pos) /*!< 0x00004000 */
#define RCC_CFGR2_PPRE5_Pos (16U)
#define RCC_CFGR2_PPRE5_Msk (0x7UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00070000 */
#define RCC_CFGR2_PPRE5 RCC_CFGR2_PPRE5_Msk /*!< CPU domain APB5 prescaler */
#define RCC_CFGR2_PPRE5_0 (0x1UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00010000 */
#define RCC_CFGR2_PPRE5_1 (0x2UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00020000 */
#define RCC_CFGR2_PPRE5_2 (0x4UL << RCC_CFGR2_PPRE5_Pos) /*!< 0x00040000 */
#define RCC_CFGR2_HPRE_Pos (20U)
#define RCC_CFGR2_HPRE_Msk (0x7UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00700000 */
#define RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk /*!< AHB clock prescaler */
#define RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00100000 */
#define RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00200000 */
#define RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) /*!< 0x00400000 */
#define RCC_CFGR2_TIMPRE_Pos (24U)
#define RCC_CFGR2_TIMPRE_Msk (0x3UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x03000000 */
#define RCC_CFGR2_TIMPRE RCC_CFGR2_TIMPRE_Msk /*!< Timer clock prescaler selection */
#define RCC_CFGR2_TIMPRE_0 (0x1UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x01000000 */
#define RCC_CFGR2_TIMPRE_1 (0x2UL << RCC_CFGR2_TIMPRE_Pos) /*!< 0x02000000 */
/******************* Bit definition for RCC_BDCR register *******************/
#define RCC_BDCR_VSWRST_Pos (31U)
#define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x80000000 */
#define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk /*!< Vswitch (VSW) domain software reset */
/****************** Bit definition for RCC_HWRSR register *******************/
#define RCC_HWRSR_RMVF_Pos (16U)
#define RCC_HWRSR_RMVF_Msk (0x1UL << RCC_HWRSR_RMVF_Pos) /*!< 0x00010000 */
#define RCC_HWRSR_RMVF RCC_HWRSR_RMVF_Msk /*!< Remove reset flag */
#define RCC_HWRSR_LCKRSTF_Pos (17U)
#define RCC_HWRSR_LCKRSTF_Msk (0x1UL << RCC_HWRSR_LCKRSTF_Pos) /*!< 0x00020000 */
#define RCC_HWRSR_LCKRSTF RCC_HWRSR_LCKRSTF_Msk /*!< CPU lockup reset flag */
#define RCC_HWRSR_BORRSTF_Pos (21U)
#define RCC_HWRSR_BORRSTF_Msk (0x1UL << RCC_HWRSR_BORRSTF_Pos) /*!< 0x00200000 */
#define RCC_HWRSR_BORRSTF RCC_HWRSR_BORRSTF_Msk /*!< BOR reset flag */
#define RCC_HWRSR_PINRSTF_Pos (22U)
#define RCC_HWRSR_PINRSTF_Msk (0x1UL << RCC_HWRSR_PINRSTF_Pos) /*!< 0x00400000 */
#define RCC_HWRSR_PINRSTF RCC_HWRSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */
#define RCC_HWRSR_PORRSTF_Pos (23U)
#define RCC_HWRSR_PORRSTF_Msk (0x1UL << RCC_HWRSR_PORRSTF_Pos) /*!< 0x00800000 */
#define RCC_HWRSR_PORRSTF RCC_HWRSR_PORRSTF_Msk /*!< POR/PDR reset flag */
#define RCC_HWRSR_SFTRSTF_Pos (24U)
#define RCC_HWRSR_SFTRSTF_Msk (0x1UL << RCC_HWRSR_SFTRSTF_Pos) /*!< 0x01000000 */
#define RCC_HWRSR_SFTRSTF RCC_HWRSR_SFTRSTF_Msk /*!< Software system reset flag */
#define RCC_HWRSR_IWDGRSTF_Pos (26U)
#define RCC_HWRSR_IWDGRSTF_Msk (0x1UL << RCC_HWRSR_IWDGRSTF_Pos) /*!< 0x04000000 */
#define RCC_HWRSR_IWDGRSTF RCC_HWRSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */
#define RCC_HWRSR_WWDGRSTF_Pos (28U)
#define RCC_HWRSR_WWDGRSTF_Msk (0x1UL << RCC_HWRSR_WWDGRSTF_Pos) /*!< 0x10000000 */
#define RCC_HWRSR_WWDGRSTF RCC_HWRSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
#define RCC_HWRSR_LPWRRSTF_Pos (30U)
#define RCC_HWRSR_LPWRRSTF_Msk (0x1UL << RCC_HWRSR_LPWRRSTF_Pos) /*!< 0x40000000 */
#define RCC_HWRSR_LPWRRSTF RCC_HWRSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */
/******************* Bit definition for RCC_RSR register ********************/
#define RCC_RSR_RMVF_Pos (16U)
#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk /*!< Remove reset flag */
#define RCC_RSR_LCKRSTF_Pos (17U)
#define RCC_RSR_LCKRSTF_Msk (0x1UL << RCC_RSR_LCKRSTF_Pos) /*!< 0x00020000 */
#define RCC_RSR_LCKRSTF RCC_RSR_LCKRSTF_Msk /*!< CPU lockup reset flag */
#define RCC_RSR_BORRSTF_Pos (21U)
#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk /*!< BOR reset flag */
#define RCC_RSR_PINRSTF_Pos (22U)
#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk /*!< Pin reset flag (NRST) */
#define RCC_RSR_PORRSTF_Pos (23U)
#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk /*!< POR/PDR reset flag */
#define RCC_RSR_SFTRSTF_Pos (24U)
#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */
#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk /*!< Software system reset flag */
#define RCC_RSR_IWDGRSTF_Pos (26U)
#define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */
#define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk /*!< Independent watchdog reset flag */
#define RCC_RSR_WWDGRSTF_Pos (28U)
#define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */
#define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
#define RCC_RSR_LPWRRSTF_Pos (30U)
#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk /*!< Illegal Stop or Standby flag */
/***************** Bit definition for RCC_LSECFGR register ******************/
#define RCC_LSECFGR_LSECSSON_Pos (7U)
#define RCC_LSECFGR_LSECSSON_Msk (0x1UL << RCC_LSECFGR_LSECSSON_Pos) /*!< 0x00000080 */
#define RCC_LSECFGR_LSECSSON RCC_LSECFGR_LSECSSON_Msk /*!< LSE clock security system (CSS) enable */
#define RCC_LSECFGR_LSECSSRA_Pos (8U)
#define RCC_LSECFGR_LSECSSRA_Msk (0x1UL << RCC_LSECFGR_LSECSSRA_Pos) /*!< 0x00000100 */
#define RCC_LSECFGR_LSECSSRA RCC_LSECFGR_LSECSSRA_Msk /*!< LSE clock security system (CSS) rearm function */
#define RCC_LSECFGR_LSECSSD_Pos (9U)
#define RCC_LSECFGR_LSECSSD_Msk (0x1UL << RCC_LSECFGR_LSECSSD_Pos) /*!< 0x00000200 */
#define RCC_LSECFGR_LSECSSD RCC_LSECFGR_LSECSSD_Msk /*!< LSE clock security system (CSS) failure detection */
#define RCC_LSECFGR_LSEBYP_Pos (15U)
#define RCC_LSECFGR_LSEBYP_Msk (0x1UL << RCC_LSECFGR_LSEBYP_Pos) /*!< 0x00008000 */
#define RCC_LSECFGR_LSEBYP RCC_LSECFGR_LSEBYP_Msk /*!< LSE clock bypass */
#define RCC_LSECFGR_LSEEXT_Pos (16U)
#define RCC_LSECFGR_LSEEXT_Msk (0x1UL << RCC_LSECFGR_LSEEXT_Pos) /*!< 0x00010000 */
#define RCC_LSECFGR_LSEEXT RCC_LSECFGR_LSEEXT_Msk /*!< LSE clock type in bypass mode */
#define RCC_LSECFGR_LSEGFON_Pos (17U)
#define RCC_LSECFGR_LSEGFON_Msk (0x1UL << RCC_LSECFGR_LSEGFON_Pos) /*!< 0x00020000 */
#define RCC_LSECFGR_LSEGFON RCC_LSECFGR_LSEGFON_Msk /*!< LSE clock glitch filter enable */
#define RCC_LSECFGR_LSEDRV_Pos (18U)
#define RCC_LSECFGR_LSEDRV_Msk (0x3UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x000C0000 */
#define RCC_LSECFGR_LSEDRV RCC_LSECFGR_LSEDRV_Msk /*!< LSE oscillator driving capability */
#define RCC_LSECFGR_LSEDRV_0 (0x1UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00040000 */
#define RCC_LSECFGR_LSEDRV_1 (0x2UL << RCC_LSECFGR_LSEDRV_Pos) /*!< 0x00080000 */
/***************** Bit definition for RCC_MSICFGR register ******************/
#define RCC_MSICFGR_MSIFREQSEL_Pos (9U)
#define RCC_MSICFGR_MSIFREQSEL_Msk (0x1UL << RCC_MSICFGR_MSIFREQSEL_Pos) /*!< 0x00000200 */
#define RCC_MSICFGR_MSIFREQSEL RCC_MSICFGR_MSIFREQSEL_Msk /*!< MSI oscillator frequency selection */
#define RCC_MSICFGR_MSITRIM_Pos (16U)
#define RCC_MSICFGR_MSITRIM_Msk (0x1FUL << RCC_MSICFGR_MSITRIM_Pos) /*!< 0x001F0000 */
#define RCC_MSICFGR_MSITRIM RCC_MSICFGR_MSITRIM_Msk /*!< MSI clock trimming */
#define RCC_MSICFGR_MSICAL_Pos (23U)
#define RCC_MSICFGR_MSICAL_Msk (0xFFUL << RCC_MSICFGR_MSICAL_Pos) /*!< 0x7F800000 */
#define RCC_MSICFGR_MSICAL RCC_MSICFGR_MSICAL_Msk /*!< MSI clock calibration */
/***************** Bit definition for RCC_HSICFGR register ******************/
#define RCC_HSICFGR_HSIDIV_Pos (7U)
#define RCC_HSICFGR_HSIDIV_Msk (0x3UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000180 */
#define RCC_HSICFGR_HSIDIV RCC_HSICFGR_HSIDIV_Msk /*!< HSI clock divider */
#define RCC_HSICFGR_HSIDIV_0 (0x1UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000080 */
#define RCC_HSICFGR_HSIDIV_1 (0x2UL << RCC_HSICFGR_HSIDIV_Pos) /*!< 0x00000100 */
#define RCC_HSICFGR_HSITRIM_Pos (16U)
#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x007F0000 */
#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSI clock trimming */
#define RCC_HSICFGR_HSICAL_Pos (23U)
#define RCC_HSICFGR_HSICAL_Msk (0x1FFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0xFF800000 */
#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSI clock calibration */
/****************** Bit definition for RCC_HSIMCR register ******************/
#define RCC_HSIMCR_HSIREF_Pos (0U)
#define RCC_HSIMCR_HSIREF_Msk (0x7FFUL << RCC_HSIMCR_HSIREF_Pos) /*!< 0x000007FF */
#define RCC_HSIMCR_HSIREF RCC_HSIMCR_HSIREF_Msk /*!< HSI clock-cycle counter reference value */
#define RCC_HSIMCR_HSIDEV_Pos (16U)
#define RCC_HSIMCR_HSIDEV_Msk (0x3FUL << RCC_HSIMCR_HSIDEV_Pos) /*!< 0x003F0000 */
#define RCC_HSIMCR_HSIDEV RCC_HSIMCR_HSIDEV_Msk /*!< HSI clock count deviation value */
#define RCC_HSIMCR_HSIMONEN_Pos (31U)
#define RCC_HSIMCR_HSIMONEN_Msk (0x1UL << RCC_HSIMCR_HSIMONEN_Pos) /*!< 0x80000000 */
#define RCC_HSIMCR_HSIMONEN RCC_HSIMCR_HSIMONEN_Msk /*!< HSI clock period monitor enable */
/****************** Bit definition for RCC_HSIMSR register ******************/
#define RCC_HSIMSR_HSIVAL_Pos (0U)
#define RCC_HSIMSR_HSIVAL_Msk (0x7FFUL << RCC_HSIMSR_HSIVAL_Pos) /*!< 0x000007FF */
#define RCC_HSIMSR_HSIVAL RCC_HSIMSR_HSIVAL_Msk /*!< HSI clock-cycle counter measured value */
/***************** Bit definition for RCC_HSECFGR register ******************/
#define RCC_HSECFGR_HSEDIV2SEL_Pos (6U)
#define RCC_HSECFGR_HSEDIV2SEL_Msk (0x1UL << RCC_HSECFGR_HSEDIV2SEL_Pos) /*!< 0x00000040 */
#define RCC_HSECFGR_HSEDIV2SEL RCC_HSECFGR_HSEDIV2SEL_Msk /*!< HSE div2 clock source select */
#define RCC_HSECFGR_HSECSSON_Pos (7U)
#define RCC_HSECFGR_HSECSSON_Msk (0x1UL << RCC_HSECFGR_HSECSSON_Pos) /*!< 0x00000080 */
#define RCC_HSECFGR_HSECSSON RCC_HSECFGR_HSECSSON_Msk /*!< HSE CSS enable */
#define RCC_HSECFGR_HSECSSD_Pos (9U)
#define RCC_HSECFGR_HSECSSD_Msk (0x1UL << RCC_HSECFGR_HSECSSD_Pos) /*!< 0x00000200 */
#define RCC_HSECFGR_HSECSSD RCC_HSECFGR_HSECSSD_Msk /*!< HSE CSS failure detection */
#define RCC_HSECFGR_HSECSSBYP_Pos (10U)
#define RCC_HSECFGR_HSECSSBYP_Msk (0x1UL << RCC_HSECFGR_HSECSSBYP_Pos) /*!< 0x00000400 */
#define RCC_HSECFGR_HSECSSBYP RCC_HSECFGR_HSECSSBYP_Msk /*!< HSE CSS bypass enable */
#define RCC_HSECFGR_HSECSSBPRE_Pos (11U)
#define RCC_HSECFGR_HSECSSBPRE_Msk (0xFUL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00007800 */
#define RCC_HSECFGR_HSECSSBPRE RCC_HSECFGR_HSECSSBPRE_Msk /*!< HSE CSS bypass divider */
#define RCC_HSECFGR_HSECSSBPRE_0 (0x1UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00000800 */
#define RCC_HSECFGR_HSECSSBPRE_1 (0x2UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00001000 */
#define RCC_HSECFGR_HSECSSBPRE_2 (0x4UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00002000 */
#define RCC_HSECFGR_HSECSSBPRE_3 (0x8UL << RCC_HSECFGR_HSECSSBPRE_Pos) /*!< 0x00004000 */
#define RCC_HSECFGR_HSEBYP_Pos (15U)
#define RCC_HSECFGR_HSEBYP_Msk (0x1UL << RCC_HSECFGR_HSEBYP_Pos) /*!< 0x00008000 */
#define RCC_HSECFGR_HSEBYP RCC_HSECFGR_HSEBYP_Msk /*!< HSE clock bypass */
#define RCC_HSECFGR_HSEEXT_Pos (16U)
#define RCC_HSECFGR_HSEEXT_Msk (0x1UL << RCC_HSECFGR_HSEEXT_Pos) /*!< 0x00010000 */
#define RCC_HSECFGR_HSEEXT RCC_HSECFGR_HSEEXT_Msk /*!< HSE clock type in bypass mode */
/**************** Bit definition for RCC_PLL1CFGR1 register *****************/
#define RCC_PLL1CFGR1_PLL1DIVN_Pos (8U)
#define RCC_PLL1CFGR1_PLL1DIVN_Msk (0xFFFUL << RCC_PLL1CFGR1_PLL1DIVN_Pos) /*!< 0x000FFF00 */
#define RCC_PLL1CFGR1_PLL1DIVN RCC_PLL1CFGR1_PLL1DIVN_Msk /*!< PLL1 integer part for the VCO multiplication factor */
#define RCC_PLL1CFGR1_PLL1DIVM_Pos (20U)
#define RCC_PLL1CFGR1_PLL1DIVM_Msk (0x3FUL << RCC_PLL1CFGR1_PLL1DIVM_Pos)/*!< 0x03F00000 */
#define RCC_PLL1CFGR1_PLL1DIVM RCC_PLL1CFGR1_PLL1DIVM_Msk /*!< PLL1 reference input clock divide frequency ratio */
#define RCC_PLL1CFGR1_PLL1BYP_Pos (27U)
#define RCC_PLL1CFGR1_PLL1BYP_Msk (0x1UL << RCC_PLL1CFGR1_PLL1BYP_Pos) /*!< 0x08000000 */
#define RCC_PLL1CFGR1_PLL1BYP RCC_PLL1CFGR1_PLL1BYP_Msk /*!< PLL1 bypass */
#define RCC_PLL1CFGR1_PLL1SEL_Pos (28U)
#define RCC_PLL1CFGR1_PLL1SEL_Msk (0x7UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x70000000 */
#define RCC_PLL1CFGR1_PLL1SEL RCC_PLL1CFGR1_PLL1SEL_Msk /*!< PLL1 source selection of the reference clock */
#define RCC_PLL1CFGR1_PLL1SEL_0 (0x1UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x10000000 */
#define RCC_PLL1CFGR1_PLL1SEL_1 (0x2UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x20000000 */
#define RCC_PLL1CFGR1_PLL1SEL_2 (0x4UL << RCC_PLL1CFGR1_PLL1SEL_Pos) /*!< 0x40000000 */
/**************** Bit definition for RCC_PLL1CFGR2 register *****************/
#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos (0U)
#define RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL1CFGR2_PLL1DIVNFRAC_Pos) /*!< 0x00FFFFFF */
#define RCC_PLL1CFGR2_PLL1DIVNFRAC RCC_PLL1CFGR2_PLL1DIVNFRAC_Msk /*!< PLL1 fractional part of the VCO multiplication factor */
/**************** Bit definition for RCC_PLL1CFGR3 register *****************/
#define RCC_PLL1CFGR3_PLL1MODSSRST_Pos (0U)
#define RCC_PLL1CFGR3_PLL1MODSSRST_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSRST_Pos) /*!< 0x00000001 */
#define RCC_PLL1CFGR3_PLL1MODSSRST RCC_PLL1CFGR3_PLL1MODSSRST_Msk /*!< PLL1 modulation spread spectrum reset */
#define RCC_PLL1CFGR3_PLL1DACEN_Pos (1U)
#define RCC_PLL1CFGR3_PLL1DACEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1DACEN_Pos)/*!< 0x00000002 */
#define RCC_PLL1CFGR3_PLL1DACEN RCC_PLL1CFGR3_PLL1DACEN_Msk /*!< PLL1 noise canceling DAC enable in fractional mode */
#define RCC_PLL1CFGR3_PLL1MODSSDIS_Pos (2U)
#define RCC_PLL1CFGR3_PLL1MODSSDIS_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSSDIS_Pos) /*!< 0x00000004 */
#define RCC_PLL1CFGR3_PLL1MODSSDIS RCC_PLL1CFGR3_PLL1MODSSDIS_Msk /*!< PLL1 modulation spread spectrum disable */
#define RCC_PLL1CFGR3_PLL1MODDSEN_Pos (3U)
#define RCC_PLL1CFGR3_PLL1MODDSEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODDSEN_Pos) /*!< 0x00000008 */
#define RCC_PLL1CFGR3_PLL1MODDSEN RCC_PLL1CFGR3_PLL1MODDSEN_Msk /*!< PLL1 modulation spread spectrum (and fractional divide) enable */
#define RCC_PLL1CFGR3_PLL1MODSPRDW_Pos (4U)
#define RCC_PLL1CFGR3_PLL1MODSPRDW_Msk (0x1UL << RCC_PLL1CFGR3_PLL1MODSPRDW_Pos) /*!< 0x00000010 */
#define RCC_PLL1CFGR3_PLL1MODSPRDW RCC_PLL1CFGR3_PLL1MODSPRDW_Msk /*!< PLL1 modulation spread spectrum down */
#define RCC_PLL1CFGR3_PLL1MODDIV_Pos (8U)
#define RCC_PLL1CFGR3_PLL1MODDIV_Msk (0xFUL << RCC_PLL1CFGR3_PLL1MODDIV_Pos) /*!< 0x00000F00 */
#define RCC_PLL1CFGR3_PLL1MODDIV RCC_PLL1CFGR3_PLL1MODDIV_Msk /*!< PLL1 modulation division frequency adjustment */
#define RCC_PLL1CFGR3_PLL1MODSPR_Pos (16U)
#define RCC_PLL1CFGR3_PLL1MODSPR_Msk (0x1FUL << RCC_PLL1CFGR3_PLL1MODSPR_Pos) /*!< 0x001F0000 */
#define RCC_PLL1CFGR3_PLL1MODSPR RCC_PLL1CFGR3_PLL1MODSPR_Msk /*!< PLL1 modulation spread depth adjustment */
#define RCC_PLL1CFGR3_PLL1PDIV2_Pos (24U)
#define RCC_PLL1CFGR3_PLL1PDIV2_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV2_Pos)/*!< 0x07000000 */
#define RCC_PLL1CFGR3_PLL1PDIV2 RCC_PLL1CFGR3_PLL1PDIV2_Msk /*!< PLL1 VCO frequency divider level 2 */
#define RCC_PLL1CFGR3_PLL1PDIV1_Pos (27U)
#define RCC_PLL1CFGR3_PLL1PDIV1_Msk (0x7UL << RCC_PLL1CFGR3_PLL1PDIV1_Pos)/*!< 0x38000000 */
#define RCC_PLL1CFGR3_PLL1PDIV1 RCC_PLL1CFGR3_PLL1PDIV1_Msk /*!< PLL1 VCO frequency divider level 1 */
#define RCC_PLL1CFGR3_PLL1PDIVEN_Pos (30U)
#define RCC_PLL1CFGR3_PLL1PDIVEN_Msk (0x1UL << RCC_PLL1CFGR3_PLL1PDIVEN_Pos) /*!< 0x40000000 */
#define RCC_PLL1CFGR3_PLL1PDIVEN RCC_PLL1CFGR3_PLL1PDIVEN_Msk /*!< PLL1 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
/**************** Bit definition for RCC_PLL2CFGR1 register *****************/
#define RCC_PLL2CFGR1_PLL2DIVN_Pos (8U)
#define RCC_PLL2CFGR1_PLL2DIVN_Msk (0xFFFUL << RCC_PLL2CFGR1_PLL2DIVN_Pos) /*!< 0x000FFF00 */
#define RCC_PLL2CFGR1_PLL2DIVN RCC_PLL2CFGR1_PLL2DIVN_Msk /*!< PLL2 integer part for the VCO multiplication factor */
#define RCC_PLL2CFGR1_PLL2DIVM_Pos (20U)
#define RCC_PLL2CFGR1_PLL2DIVM_Msk (0x3FUL << RCC_PLL2CFGR1_PLL2DIVM_Pos)/*!< 0x03F00000 */
#define RCC_PLL2CFGR1_PLL2DIVM RCC_PLL2CFGR1_PLL2DIVM_Msk /*!< PLL2 reference input clock divide frequency ratio */
#define RCC_PLL2CFGR1_PLL2BYP_Pos (27U)
#define RCC_PLL2CFGR1_PLL2BYP_Msk (0x1UL << RCC_PLL2CFGR1_PLL2BYP_Pos) /*!< 0x08000000 */
#define RCC_PLL2CFGR1_PLL2BYP RCC_PLL2CFGR1_PLL2BYP_Msk /*!< PLL2 bypass */
#define RCC_PLL2CFGR1_PLL2SEL_Pos (28U)
#define RCC_PLL2CFGR1_PLL2SEL_Msk (0x7UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x70000000 */
#define RCC_PLL2CFGR1_PLL2SEL RCC_PLL2CFGR1_PLL2SEL_Msk /*!< PLL2 source selection of the reference clock */
#define RCC_PLL2CFGR1_PLL2SEL_0 (0x1UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x10000000 */
#define RCC_PLL2CFGR1_PLL2SEL_1 (0x2UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x20000000 */
#define RCC_PLL2CFGR1_PLL2SEL_2 (0x4UL << RCC_PLL2CFGR1_PLL2SEL_Pos) /*!< 0x40000000 */
/**************** Bit definition for RCC_PLL2CFGR2 register *****************/
#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos (0U)
#define RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL2CFGR2_PLL2DIVNFRAC_Pos) /*!< 0x00FFFFFF */
#define RCC_PLL2CFGR2_PLL2DIVNFRAC RCC_PLL2CFGR2_PLL2DIVNFRAC_Msk /*!< PLL2 fractional part of the VCO multiplication factor */
/**************** Bit definition for RCC_PLL2CFGR3 register *****************/
#define RCC_PLL2CFGR3_PLL2MODSSRST_Pos (0U)
#define RCC_PLL2CFGR3_PLL2MODSSRST_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSRST_Pos) /*!< 0x00000001 */
#define RCC_PLL2CFGR3_PLL2MODSSRST RCC_PLL2CFGR3_PLL2MODSSRST_Msk /*!< PLL2 modulation spread spectrum reset */
#define RCC_PLL2CFGR3_PLL2DACEN_Pos (1U)
#define RCC_PLL2CFGR3_PLL2DACEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2DACEN_Pos)/*!< 0x00000002 */
#define RCC_PLL2CFGR3_PLL2DACEN RCC_PLL2CFGR3_PLL2DACEN_Msk /*!< PLL2 noise canceling DAC enable in fractional mode */
#define RCC_PLL2CFGR3_PLL2MODSSDIS_Pos (2U)
#define RCC_PLL2CFGR3_PLL2MODSSDIS_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSSDIS_Pos) /*!< 0x00000004 */
#define RCC_PLL2CFGR3_PLL2MODSSDIS RCC_PLL2CFGR3_PLL2MODSSDIS_Msk /*!< PLL2 modulation spread spectrum disable */
#define RCC_PLL2CFGR3_PLL2MODDSEN_Pos (3U)
#define RCC_PLL2CFGR3_PLL2MODDSEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODDSEN_Pos) /*!< 0x00000008 */
#define RCC_PLL2CFGR3_PLL2MODDSEN RCC_PLL2CFGR3_PLL2MODDSEN_Msk /*!< PLL2 modulation spread spectrum (and fractional divide) enable */
#define RCC_PLL2CFGR3_PLL2MODSPRDW_Pos (4U)
#define RCC_PLL2CFGR3_PLL2MODSPRDW_Msk (0x1UL << RCC_PLL2CFGR3_PLL2MODSPRDW_Pos) /*!< 0x00000010 */
#define RCC_PLL2CFGR3_PLL2MODSPRDW RCC_PLL2CFGR3_PLL2MODSPRDW_Msk /*!< PLL2 modulation down spread */
#define RCC_PLL2CFGR3_PLL2MODDIV_Pos (8U)
#define RCC_PLL2CFGR3_PLL2MODDIV_Msk (0xFUL << RCC_PLL2CFGR3_PLL2MODDIV_Pos) /*!< 0x00000F00 */
#define RCC_PLL2CFGR3_PLL2MODDIV RCC_PLL2CFGR3_PLL2MODDIV_Msk /*!< PLL2 modulation division frequency adjustment */
#define RCC_PLL2CFGR3_PLL2MODSPR_Pos (16U)
#define RCC_PLL2CFGR3_PLL2MODSPR_Msk (0x1FUL << RCC_PLL2CFGR3_PLL2MODSPR_Pos) /*!< 0x001F0000 */
#define RCC_PLL2CFGR3_PLL2MODSPR RCC_PLL2CFGR3_PLL2MODSPR_Msk /*!< PLL2 modulation spread depth adjustment */
#define RCC_PLL2CFGR3_PLL2PDIV2_Pos (24U)
#define RCC_PLL2CFGR3_PLL2PDIV2_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV2_Pos)/*!< 0x07000000 */
#define RCC_PLL2CFGR3_PLL2PDIV2 RCC_PLL2CFGR3_PLL2PDIV2_Msk /*!< PLL2 VCO frequency divider level 2 */
#define RCC_PLL2CFGR3_PLL2PDIV1_Pos (27U)
#define RCC_PLL2CFGR3_PLL2PDIV1_Msk (0x7UL << RCC_PLL2CFGR3_PLL2PDIV1_Pos)/*!< 0x38000000 */
#define RCC_PLL2CFGR3_PLL2PDIV1 RCC_PLL2CFGR3_PLL2PDIV1_Msk /*!< PLL2 VCO frequency divider level 1 */
#define RCC_PLL2CFGR3_PLL2PDIVEN_Pos (30U)
#define RCC_PLL2CFGR3_PLL2PDIVEN_Msk (0x1UL << RCC_PLL2CFGR3_PLL2PDIVEN_Pos) /*!< 0x40000000 */
#define RCC_PLL2CFGR3_PLL2PDIVEN RCC_PLL2CFGR3_PLL2PDIVEN_Msk /*!< PLL2 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
/**************** Bit definition for RCC_PLL3CFGR1 register *****************/
#define RCC_PLL3CFGR1_PLL3DIVN_Pos (8U)
#define RCC_PLL3CFGR1_PLL3DIVN_Msk (0xFFFUL << RCC_PLL3CFGR1_PLL3DIVN_Pos) /*!< 0x000FFF00 */
#define RCC_PLL3CFGR1_PLL3DIVN RCC_PLL3CFGR1_PLL3DIVN_Msk /*!< PLL3 Integer part for the VCO multiplication factor */
#define RCC_PLL3CFGR1_PLL3DIVM_Pos (20U)
#define RCC_PLL3CFGR1_PLL3DIVM_Msk (0x3FUL << RCC_PLL3CFGR1_PLL3DIVM_Pos)/*!< 0x03F00000 */
#define RCC_PLL3CFGR1_PLL3DIVM RCC_PLL3CFGR1_PLL3DIVM_Msk /*!< PLL3 reference input clock divide frequency ratio */
#define RCC_PLL3CFGR1_PLL3BYP_Pos (27U)
#define RCC_PLL3CFGR1_PLL3BYP_Msk (0x1UL << RCC_PLL3CFGR1_PLL3BYP_Pos) /*!< 0x08000000 */
#define RCC_PLL3CFGR1_PLL3BYP RCC_PLL3CFGR1_PLL3BYP_Msk /*!< PLL3 bypass */
#define RCC_PLL3CFGR1_PLL3SEL_Pos (28U)
#define RCC_PLL3CFGR1_PLL3SEL_Msk (0x7UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x70000000 */
#define RCC_PLL3CFGR1_PLL3SEL RCC_PLL3CFGR1_PLL3SEL_Msk /*!< PLL3 source selection of the reference clock */
#define RCC_PLL3CFGR1_PLL3SEL_0 (0x1UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x10000000 */
#define RCC_PLL3CFGR1_PLL3SEL_1 (0x2UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x20000000 */
#define RCC_PLL3CFGR1_PLL3SEL_2 (0x4UL << RCC_PLL3CFGR1_PLL3SEL_Pos) /*!< 0x40000000 */
/**************** Bit definition for RCC_PLL3CFGR2 register *****************/
#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos (0U)
#define RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL3CFGR2_PLL3DIVNFRAC_Pos) /*!< 0x00FFFFFF */
#define RCC_PLL3CFGR2_PLL3DIVNFRAC RCC_PLL3CFGR2_PLL3DIVNFRAC_Msk /*!< PLL3 fractional part of the VCO multiplication factor */
/**************** Bit definition for RCC_PLL3CFGR3 register *****************/
#define RCC_PLL3CFGR3_PLL3MODSSRST_Pos (0U)
#define RCC_PLL3CFGR3_PLL3MODSSRST_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSRST_Pos) /*!< 0x00000001 */
#define RCC_PLL3CFGR3_PLL3MODSSRST RCC_PLL3CFGR3_PLL3MODSSRST_Msk /*!< PLL3 modulation spread spectrum reset */
#define RCC_PLL3CFGR3_PLL3DACEN_Pos (1U)
#define RCC_PLL3CFGR3_PLL3DACEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3DACEN_Pos)/*!< 0x00000002 */
#define RCC_PLL3CFGR3_PLL3DACEN RCC_PLL3CFGR3_PLL3DACEN_Msk /*!< PLL3 noise canceling DAC enable in fractional mode */
#define RCC_PLL3CFGR3_PLL3MODSSDIS_Pos (2U)
#define RCC_PLL3CFGR3_PLL3MODSSDIS_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSSDIS_Pos) /*!< 0x00000004 */
#define RCC_PLL3CFGR3_PLL3MODSSDIS RCC_PLL3CFGR3_PLL3MODSSDIS_Msk /*!< PLL3 modulation spread spectrum disable */
#define RCC_PLL3CFGR3_PLL3MODDSEN_Pos (3U)
#define RCC_PLL3CFGR3_PLL3MODDSEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODDSEN_Pos) /*!< 0x00000008 */
#define RCC_PLL3CFGR3_PLL3MODDSEN RCC_PLL3CFGR3_PLL3MODDSEN_Msk /*!< PLL3 modulation spread spectrum (and fractional divide) enable */
#define RCC_PLL3CFGR3_PLL3MODSPRDW_Pos (4U)
#define RCC_PLL3CFGR3_PLL3MODSPRDW_Msk (0x1UL << RCC_PLL3CFGR3_PLL3MODSPRDW_Pos) /*!< 0x00000010 */
#define RCC_PLL3CFGR3_PLL3MODSPRDW RCC_PLL3CFGR3_PLL3MODSPRDW_Msk /*!< PLL3 modulation down spread */
#define RCC_PLL3CFGR3_PLL3MODDIV_Pos (8U)
#define RCC_PLL3CFGR3_PLL3MODDIV_Msk (0xFUL << RCC_PLL3CFGR3_PLL3MODDIV_Pos) /*!< 0x00000F00 */
#define RCC_PLL3CFGR3_PLL3MODDIV RCC_PLL3CFGR3_PLL3MODDIV_Msk /*!< PLL3 modulation division frequency adjustment */
#define RCC_PLL3CFGR3_PLL3MODSPR_Pos (16U)
#define RCC_PLL3CFGR3_PLL3MODSPR_Msk (0x1FUL << RCC_PLL3CFGR3_PLL3MODSPR_Pos) /*!< 0x001F0000 */
#define RCC_PLL3CFGR3_PLL3MODSPR RCC_PLL3CFGR3_PLL3MODSPR_Msk /*!< PLL3 modulation spread depth adjustment */
#define RCC_PLL3CFGR3_PLL3PDIV2_Pos (24U)
#define RCC_PLL3CFGR3_PLL3PDIV2_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV2_Pos)/*!< 0x07000000 */
#define RCC_PLL3CFGR3_PLL3PDIV2 RCC_PLL3CFGR3_PLL3PDIV2_Msk /*!< PLL3 VCO frequency divider level 2 */
#define RCC_PLL3CFGR3_PLL3PDIV1_Pos (27U)
#define RCC_PLL3CFGR3_PLL3PDIV1_Msk (0x7UL << RCC_PLL3CFGR3_PLL3PDIV1_Pos)/*!< 0x38000000 */
#define RCC_PLL3CFGR3_PLL3PDIV1 RCC_PLL3CFGR3_PLL3PDIV1_Msk /*!< PLL3 VCO frequency divider level 1 */
#define RCC_PLL3CFGR3_PLL3PDIVEN_Pos (30U)
#define RCC_PLL3CFGR3_PLL3PDIVEN_Msk (0x1UL << RCC_PLL3CFGR3_PLL3PDIVEN_Pos) /*!< 0x40000000 */
#define RCC_PLL3CFGR3_PLL3PDIVEN RCC_PLL3CFGR3_PLL3PDIVEN_Msk /*!< PLL3 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
/**************** Bit definition for RCC_PLL4CFGR1 register *****************/
#define RCC_PLL4CFGR1_PLL4DIVN_Pos (8U)
#define RCC_PLL4CFGR1_PLL4DIVN_Msk (0xFFFUL << RCC_PLL4CFGR1_PLL4DIVN_Pos) /*!< 0x000FFF00 */
#define RCC_PLL4CFGR1_PLL4DIVN RCC_PLL4CFGR1_PLL4DIVN_Msk /*!< PLL4 integer part for the VCO multiplication factor */
#define RCC_PLL4CFGR1_PLL4DIVM_Pos (20U)
#define RCC_PLL4CFGR1_PLL4DIVM_Msk (0x3FUL << RCC_PLL4CFGR1_PLL4DIVM_Pos)/*!< 0x03F00000 */
#define RCC_PLL4CFGR1_PLL4DIVM RCC_PLL4CFGR1_PLL4DIVM_Msk /*!< PLL4 reference input clock divide frequency ratio */
#define RCC_PLL4CFGR1_PLL4BYP_Pos (27U)
#define RCC_PLL4CFGR1_PLL4BYP_Msk (0x1UL << RCC_PLL4CFGR1_PLL4BYP_Pos) /*!< 0x08000000 */
#define RCC_PLL4CFGR1_PLL4BYP RCC_PLL4CFGR1_PLL4BYP_Msk /*!< PLL4 bypass */
#define RCC_PLL4CFGR1_PLL4SEL_Pos (28U)
#define RCC_PLL4CFGR1_PLL4SEL_Msk (0x7UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x70000000 */
#define RCC_PLL4CFGR1_PLL4SEL RCC_PLL4CFGR1_PLL4SEL_Msk /*!< PLL4 source selection of the reference clock */
#define RCC_PLL4CFGR1_PLL4SEL_0 (0x1UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x10000000 */
#define RCC_PLL4CFGR1_PLL4SEL_1 (0x2UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x20000000 */
#define RCC_PLL4CFGR1_PLL4SEL_2 (0x4UL << RCC_PLL4CFGR1_PLL4SEL_Pos) /*!< 0x40000000 */
/**************** Bit definition for RCC_PLL4CFGR2 register *****************/
#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos (0U)
#define RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk (0xFFFFFFUL << RCC_PLL4CFGR2_PLL4DIVNFRAC_Pos) /*!< 0x00FFFFFF */
#define RCC_PLL4CFGR2_PLL4DIVNFRAC RCC_PLL4CFGR2_PLL4DIVNFRAC_Msk /*!< PLL4 fractional part of the VCO multiplication factor */
/**************** Bit definition for RCC_PLL4CFGR3 register *****************/
#define RCC_PLL4CFGR3_PLL4MODSSRST_Pos (0U)
#define RCC_PLL4CFGR3_PLL4MODSSRST_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSRST_Pos) /*!< 0x00000001 */
#define RCC_PLL4CFGR3_PLL4MODSSRST RCC_PLL4CFGR3_PLL4MODSSRST_Msk /*!< PLL4 modulation spread spectrum reset */
#define RCC_PLL4CFGR3_PLL4DACEN_Pos (1U)
#define RCC_PLL4CFGR3_PLL4DACEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4DACEN_Pos)/*!< 0x00000002 */
#define RCC_PLL4CFGR3_PLL4DACEN RCC_PLL4CFGR3_PLL4DACEN_Msk /*!< PLL4 noise canceling DAC enable in fractional mode */
#define RCC_PLL4CFGR3_PLL4MODSSDIS_Pos (2U)
#define RCC_PLL4CFGR3_PLL4MODSSDIS_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSSDIS_Pos) /*!< 0x00000004 */
#define RCC_PLL4CFGR3_PLL4MODSSDIS RCC_PLL4CFGR3_PLL4MODSSDIS_Msk /*!< PLL4 modulation spread spectrum disable */
#define RCC_PLL4CFGR3_PLL4MODDSEN_Pos (3U)
#define RCC_PLL4CFGR3_PLL4MODDSEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODDSEN_Pos) /*!< 0x00000008 */
#define RCC_PLL4CFGR3_PLL4MODDSEN RCC_PLL4CFGR3_PLL4MODDSEN_Msk /*!< PLL4 modulation spread spectrum (and fractional divide) enable */
#define RCC_PLL4CFGR3_PLL4MODSPRDW_Pos (4U)
#define RCC_PLL4CFGR3_PLL4MODSPRDW_Msk (0x1UL << RCC_PLL4CFGR3_PLL4MODSPRDW_Pos) /*!< 0x00000010 */
#define RCC_PLL4CFGR3_PLL4MODSPRDW RCC_PLL4CFGR3_PLL4MODSPRDW_Msk /*!< PLL4 modulation down spread */
#define RCC_PLL4CFGR3_PLL4MODDIV_Pos (8U)
#define RCC_PLL4CFGR3_PLL4MODDIV_Msk (0xFUL << RCC_PLL4CFGR3_PLL4MODDIV_Pos) /*!< 0x00000F00 */
#define RCC_PLL4CFGR3_PLL4MODDIV RCC_PLL4CFGR3_PLL4MODDIV_Msk /*!< PLL4 modulation division frequency adjustment */
#define RCC_PLL4CFGR3_PLL4MODSPR_Pos (16U)
#define RCC_PLL4CFGR3_PLL4MODSPR_Msk (0x1FUL << RCC_PLL4CFGR3_PLL4MODSPR_Pos) /*!< 0x001F0000 */
#define RCC_PLL4CFGR3_PLL4MODSPR RCC_PLL4CFGR3_PLL4MODSPR_Msk /*!< PLL4 modulation spread depth adjustment */
#define RCC_PLL4CFGR3_PLL4PDIV2_Pos (24U)
#define RCC_PLL4CFGR3_PLL4PDIV2_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV2_Pos)/*!< 0x07000000 */
#define RCC_PLL4CFGR3_PLL4PDIV2 RCC_PLL4CFGR3_PLL4PDIV2_Msk /*!< PLL4 VCO frequency divider level 2 */
#define RCC_PLL4CFGR3_PLL4PDIV1_Pos (27U)
#define RCC_PLL4CFGR3_PLL4PDIV1_Msk (0x7UL << RCC_PLL4CFGR3_PLL4PDIV1_Pos)/*!< 0x38000000 */
#define RCC_PLL4CFGR3_PLL4PDIV1 RCC_PLL4CFGR3_PLL4PDIV1_Msk /*!< PLL4 VCO frequency divider level 1 */
#define RCC_PLL4CFGR3_PLL4PDIVEN_Pos (30U)
#define RCC_PLL4CFGR3_PLL4PDIVEN_Msk (0x1UL << RCC_PLL4CFGR3_PLL4PDIVEN_Pos) /*!< 0x40000000 */
#define RCC_PLL4CFGR3_PLL4PDIVEN RCC_PLL4CFGR3_PLL4PDIVEN_Msk /*!< PLL4 post divider POSTDIV1, POSTDIV2, and PLL clock output enable */
/***************** Bit definition for RCC_IC1CFGR register ******************/
#define RCC_IC1CFGR_IC1INT_Pos (16U)
#define RCC_IC1CFGR_IC1INT_Msk (0xFFUL << RCC_IC1CFGR_IC1INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC1CFGR_IC1INT RCC_IC1CFGR_IC1INT_Msk /*!< Divider IC1 integer division factor */
#define RCC_IC1CFGR_IC1SEL_Pos (28U)
#define RCC_IC1CFGR_IC1SEL_Msk (0x3UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x30000000 */
#define RCC_IC1CFGR_IC1SEL RCC_IC1CFGR_IC1SEL_Msk /*!< Divider IC1 source selection */
#define RCC_IC1CFGR_IC1SEL_0 (0x1UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x10000000 */
#define RCC_IC1CFGR_IC1SEL_1 (0x2UL << RCC_IC1CFGR_IC1SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC2CFGR register ******************/
#define RCC_IC2CFGR_IC2INT_Pos (16U)
#define RCC_IC2CFGR_IC2INT_Msk (0xFFUL << RCC_IC2CFGR_IC2INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC2CFGR_IC2INT RCC_IC2CFGR_IC2INT_Msk /*!< Divider IC2 integer division factor */
#define RCC_IC2CFGR_IC2SEL_Pos (28U)
#define RCC_IC2CFGR_IC2SEL_Msk (0x3UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x30000000 */
#define RCC_IC2CFGR_IC2SEL RCC_IC2CFGR_IC2SEL_Msk /*!< Divider IC2 source selection */
#define RCC_IC2CFGR_IC2SEL_0 (0x1UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x10000000 */
#define RCC_IC2CFGR_IC2SEL_1 (0x2UL << RCC_IC2CFGR_IC2SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC3CFGR register ******************/
#define RCC_IC3CFGR_IC3INT_Pos (16U)
#define RCC_IC3CFGR_IC3INT_Msk (0xFFUL << RCC_IC3CFGR_IC3INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC3CFGR_IC3INT RCC_IC3CFGR_IC3INT_Msk /*!< Divider IC3 integer division factor */
#define RCC_IC3CFGR_IC3SEL_Pos (28U)
#define RCC_IC3CFGR_IC3SEL_Msk (0x3UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x30000000 */
#define RCC_IC3CFGR_IC3SEL RCC_IC3CFGR_IC3SEL_Msk /*!< Divider IC3 source selection */
#define RCC_IC3CFGR_IC3SEL_0 (0x1UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x10000000 */
#define RCC_IC3CFGR_IC3SEL_1 (0x2UL << RCC_IC3CFGR_IC3SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC4CFGR register ******************/
#define RCC_IC4CFGR_IC4INT_Pos (16U)
#define RCC_IC4CFGR_IC4INT_Msk (0xFFUL << RCC_IC4CFGR_IC4INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC4CFGR_IC4INT RCC_IC4CFGR_IC4INT_Msk /*!< Divider IC4 integer division factor */
#define RCC_IC4CFGR_IC4SEL_Pos (28U)
#define RCC_IC4CFGR_IC4SEL_Msk (0x3UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x30000000 */
#define RCC_IC4CFGR_IC4SEL RCC_IC4CFGR_IC4SEL_Msk /*!< Divider IC4 source selection */
#define RCC_IC4CFGR_IC4SEL_0 (0x1UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x10000000 */
#define RCC_IC4CFGR_IC4SEL_1 (0x2UL << RCC_IC4CFGR_IC4SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC5CFGR register ******************/
#define RCC_IC5CFGR_IC5INT_Pos (16U)
#define RCC_IC5CFGR_IC5INT_Msk (0xFFUL << RCC_IC5CFGR_IC5INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC5CFGR_IC5INT RCC_IC5CFGR_IC5INT_Msk /*!< Divider IC5 integer division factor */
#define RCC_IC5CFGR_IC5SEL_Pos (28U)
#define RCC_IC5CFGR_IC5SEL_Msk (0x3UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x30000000 */
#define RCC_IC5CFGR_IC5SEL RCC_IC5CFGR_IC5SEL_Msk /*!< Divider IC5 source selection */
#define RCC_IC5CFGR_IC5SEL_0 (0x1UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x10000000 */
#define RCC_IC5CFGR_IC5SEL_1 (0x2UL << RCC_IC5CFGR_IC5SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC6CFGR register ******************/
#define RCC_IC6CFGR_IC6INT_Pos (16U)
#define RCC_IC6CFGR_IC6INT_Msk (0xFFUL << RCC_IC6CFGR_IC6INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC6CFGR_IC6INT RCC_IC6CFGR_IC6INT_Msk /*!< Divider IC6 integer division factor */
#define RCC_IC6CFGR_IC6SEL_Pos (28U)
#define RCC_IC6CFGR_IC6SEL_Msk (0x3UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x30000000 */
#define RCC_IC6CFGR_IC6SEL RCC_IC6CFGR_IC6SEL_Msk /*!< Divider IC6 source selection */
#define RCC_IC6CFGR_IC6SEL_0 (0x1UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x10000000 */
#define RCC_IC6CFGR_IC6SEL_1 (0x2UL << RCC_IC6CFGR_IC6SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC7CFGR register ******************/
#define RCC_IC7CFGR_IC7INT_Pos (16U)
#define RCC_IC7CFGR_IC7INT_Msk (0xFFUL << RCC_IC7CFGR_IC7INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC7CFGR_IC7INT RCC_IC7CFGR_IC7INT_Msk /*!< Divider IC7 integer division factor */
#define RCC_IC7CFGR_IC7SEL_Pos (28U)
#define RCC_IC7CFGR_IC7SEL_Msk (0x3UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x30000000 */
#define RCC_IC7CFGR_IC7SEL RCC_IC7CFGR_IC7SEL_Msk /*!< Divider IC7 source selection */
#define RCC_IC7CFGR_IC7SEL_0 (0x1UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x10000000 */
#define RCC_IC7CFGR_IC7SEL_1 (0x2UL << RCC_IC7CFGR_IC7SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC8CFGR register ******************/
#define RCC_IC8CFGR_IC8INT_Pos (16U)
#define RCC_IC8CFGR_IC8INT_Msk (0xFFUL << RCC_IC8CFGR_IC8INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC8CFGR_IC8INT RCC_IC8CFGR_IC8INT_Msk /*!< Divider IC8 integer division factor */
#define RCC_IC8CFGR_IC8SEL_Pos (28U)
#define RCC_IC8CFGR_IC8SEL_Msk (0x3UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x30000000 */
#define RCC_IC8CFGR_IC8SEL RCC_IC8CFGR_IC8SEL_Msk /*!< Divider IC8 source selection */
#define RCC_IC8CFGR_IC8SEL_0 (0x1UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x10000000 */
#define RCC_IC8CFGR_IC8SEL_1 (0x2UL << RCC_IC8CFGR_IC8SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC9CFGR register ******************/
#define RCC_IC9CFGR_IC9INT_Pos (16U)
#define RCC_IC9CFGR_IC9INT_Msk (0xFFUL << RCC_IC9CFGR_IC9INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC9CFGR_IC9INT RCC_IC9CFGR_IC9INT_Msk /*!< Divider IC9 integer division factor */
#define RCC_IC9CFGR_IC9SEL_Pos (28U)
#define RCC_IC9CFGR_IC9SEL_Msk (0x3UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x30000000 */
#define RCC_IC9CFGR_IC9SEL RCC_IC9CFGR_IC9SEL_Msk /*!< Divider IC9 source selection */
#define RCC_IC9CFGR_IC9SEL_0 (0x1UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x10000000 */
#define RCC_IC9CFGR_IC9SEL_1 (0x2UL << RCC_IC9CFGR_IC9SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC10CFGR register *****************/
#define RCC_IC10CFGR_IC10INT_Pos (16U)
#define RCC_IC10CFGR_IC10INT_Msk (0xFFUL << RCC_IC10CFGR_IC10INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC10CFGR_IC10INT RCC_IC10CFGR_IC10INT_Msk /*!< Divider IC10 integer division factor */
#define RCC_IC10CFGR_IC10SEL_Pos (28U)
#define RCC_IC10CFGR_IC10SEL_Msk (0x3UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x30000000 */
#define RCC_IC10CFGR_IC10SEL RCC_IC10CFGR_IC10SEL_Msk /*!< Divider IC10 source selection */
#define RCC_IC10CFGR_IC10SEL_0 (0x1UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x10000000 */
#define RCC_IC10CFGR_IC10SEL_1 (0x2UL << RCC_IC10CFGR_IC10SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC11CFGR register *****************/
#define RCC_IC11CFGR_IC11INT_Pos (16U)
#define RCC_IC11CFGR_IC11INT_Msk (0xFFUL << RCC_IC11CFGR_IC11INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC11CFGR_IC11INT RCC_IC11CFGR_IC11INT_Msk /*!< Divider IC11 integer division factor */
#define RCC_IC11CFGR_IC11SEL_Pos (28U)
#define RCC_IC11CFGR_IC11SEL_Msk (0x3UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x30000000 */
#define RCC_IC11CFGR_IC11SEL RCC_IC11CFGR_IC11SEL_Msk /*!< Divider IC11 source selection */
#define RCC_IC11CFGR_IC11SEL_0 (0x1UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x10000000 */
#define RCC_IC11CFGR_IC11SEL_1 (0x2UL << RCC_IC11CFGR_IC11SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC12CFGR register *****************/
#define RCC_IC12CFGR_IC12INT_Pos (16U)
#define RCC_IC12CFGR_IC12INT_Msk (0xFFUL << RCC_IC12CFGR_IC12INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC12CFGR_IC12INT RCC_IC12CFGR_IC12INT_Msk /*!< Divider IC12 integer division factor */
#define RCC_IC12CFGR_IC12SEL_Pos (28U)
#define RCC_IC12CFGR_IC12SEL_Msk (0x3UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x30000000 */
#define RCC_IC12CFGR_IC12SEL RCC_IC12CFGR_IC12SEL_Msk /*!< Divider IC12 source selection */
#define RCC_IC12CFGR_IC12SEL_0 (0x1UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x10000000 */
#define RCC_IC12CFGR_IC12SEL_1 (0x2UL << RCC_IC12CFGR_IC12SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC13CFGR register *****************/
#define RCC_IC13CFGR_IC13INT_Pos (16U)
#define RCC_IC13CFGR_IC13INT_Msk (0xFFUL << RCC_IC13CFGR_IC13INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC13CFGR_IC13INT RCC_IC13CFGR_IC13INT_Msk /*!< Divider IC13 integer division factor */
#define RCC_IC13CFGR_IC13SEL_Pos (28U)
#define RCC_IC13CFGR_IC13SEL_Msk (0x3UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x30000000 */
#define RCC_IC13CFGR_IC13SEL RCC_IC13CFGR_IC13SEL_Msk /*!< Divider IC13 source selection */
#define RCC_IC13CFGR_IC13SEL_0 (0x1UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x10000000 */
#define RCC_IC13CFGR_IC13SEL_1 (0x2UL << RCC_IC13CFGR_IC13SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC14CFGR register *****************/
#define RCC_IC14CFGR_IC14INT_Pos (16U)
#define RCC_IC14CFGR_IC14INT_Msk (0xFFUL << RCC_IC14CFGR_IC14INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC14CFGR_IC14INT RCC_IC14CFGR_IC14INT_Msk /*!< Divider IC14 integer division factor */
#define RCC_IC14CFGR_IC14SEL_Pos (28U)
#define RCC_IC14CFGR_IC14SEL_Msk (0x3UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x30000000 */
#define RCC_IC14CFGR_IC14SEL RCC_IC14CFGR_IC14SEL_Msk /*!< Divider IC14 source selection */
#define RCC_IC14CFGR_IC14SEL_0 (0x1UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x10000000 */
#define RCC_IC14CFGR_IC14SEL_1 (0x2UL << RCC_IC14CFGR_IC14SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC15CFGR register *****************/
#define RCC_IC15CFGR_IC15INT_Pos (16U)
#define RCC_IC15CFGR_IC15INT_Msk (0xFFUL << RCC_IC15CFGR_IC15INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC15CFGR_IC15INT RCC_IC15CFGR_IC15INT_Msk /*!< Divider IC15 integer division factor */
#define RCC_IC15CFGR_IC15SEL_Pos (28U)
#define RCC_IC15CFGR_IC15SEL_Msk (0x3UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x30000000 */
#define RCC_IC15CFGR_IC15SEL RCC_IC15CFGR_IC15SEL_Msk /*!< Divider IC15 source selection */
#define RCC_IC15CFGR_IC15SEL_0 (0x1UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x10000000 */
#define RCC_IC15CFGR_IC15SEL_1 (0x2UL << RCC_IC15CFGR_IC15SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC16CFGR register *****************/
#define RCC_IC16CFGR_IC16INT_Pos (16U)
#define RCC_IC16CFGR_IC16INT_Msk (0xFFUL << RCC_IC16CFGR_IC16INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC16CFGR_IC16INT RCC_IC16CFGR_IC16INT_Msk /*!< Divider IC16 integer division factor */
#define RCC_IC16CFGR_IC16SEL_Pos (28U)
#define RCC_IC16CFGR_IC16SEL_Msk (0x3UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x30000000 */
#define RCC_IC16CFGR_IC16SEL RCC_IC16CFGR_IC16SEL_Msk /*!< Divider IC16 source selection */
#define RCC_IC16CFGR_IC16SEL_0 (0x1UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x10000000 */
#define RCC_IC16CFGR_IC16SEL_1 (0x2UL << RCC_IC16CFGR_IC16SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC17CFGR register *****************/
#define RCC_IC17CFGR_IC17INT_Pos (16U)
#define RCC_IC17CFGR_IC17INT_Msk (0xFFUL << RCC_IC17CFGR_IC17INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC17CFGR_IC17INT RCC_IC17CFGR_IC17INT_Msk /*!< Divider IC17 integer division factor */
#define RCC_IC17CFGR_IC17SEL_Pos (28U)
#define RCC_IC17CFGR_IC17SEL_Msk (0x3UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x30000000 */
#define RCC_IC17CFGR_IC17SEL RCC_IC17CFGR_IC17SEL_Msk /*!< Divider IC17 source selection */
#define RCC_IC17CFGR_IC17SEL_0 (0x1UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x10000000 */
#define RCC_IC17CFGR_IC17SEL_1 (0x2UL << RCC_IC17CFGR_IC17SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC18CFGR register *****************/
#define RCC_IC18CFGR_IC18INT_Pos (16U)
#define RCC_IC18CFGR_IC18INT_Msk (0xFFUL << RCC_IC18CFGR_IC18INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC18CFGR_IC18INT RCC_IC18CFGR_IC18INT_Msk /*!< Divider IC18 integer division factor */
#define RCC_IC18CFGR_IC18SEL_Pos (28U)
#define RCC_IC18CFGR_IC18SEL_Msk (0x3UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x30000000 */
#define RCC_IC18CFGR_IC18SEL RCC_IC18CFGR_IC18SEL_Msk /*!< Divider IC18 source selection */
#define RCC_IC18CFGR_IC18SEL_0 (0x1UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x10000000 */
#define RCC_IC18CFGR_IC18SEL_1 (0x2UL << RCC_IC18CFGR_IC18SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC19CFGR register *****************/
#define RCC_IC19CFGR_IC19INT_Pos (16U)
#define RCC_IC19CFGR_IC19INT_Msk (0xFFUL << RCC_IC19CFGR_IC19INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC19CFGR_IC19INT RCC_IC19CFGR_IC19INT_Msk /*!< Divider IC19 integer division factor */
#define RCC_IC19CFGR_IC19SEL_Pos (28U)
#define RCC_IC19CFGR_IC19SEL_Msk (0x3UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x30000000 */
#define RCC_IC19CFGR_IC19SEL RCC_IC19CFGR_IC19SEL_Msk /*!< Divider IC19 source selection */
#define RCC_IC19CFGR_IC19SEL_0 (0x1UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x10000000 */
#define RCC_IC19CFGR_IC19SEL_1 (0x2UL << RCC_IC19CFGR_IC19SEL_Pos) /*!< 0x20000000 */
/***************** Bit definition for RCC_IC20CFGR register *****************/
#define RCC_IC20CFGR_IC20INT_Pos (16U)
#define RCC_IC20CFGR_IC20INT_Msk (0xFFUL << RCC_IC20CFGR_IC20INT_Pos) /*!< 0x00FF0000 */
#define RCC_IC20CFGR_IC20INT RCC_IC20CFGR_IC20INT_Msk /*!< Divider IC20 integer division factor */
#define RCC_IC20CFGR_IC20SEL_Pos (28U)
#define RCC_IC20CFGR_IC20SEL_Msk (0x3UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x30000000 */
#define RCC_IC20CFGR_IC20SEL RCC_IC20CFGR_IC20SEL_Msk /*!< Divider IC20 source selection */
#define RCC_IC20CFGR_IC20SEL_0 (0x1UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x10000000 */
#define RCC_IC20CFGR_IC20SEL_1 (0x2UL << RCC_IC20CFGR_IC20SEL_Pos) /*!< 0x20000000 */
/******************* Bit definition for RCC_CIER register *******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI ready interrupt enable */
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE ready interrupt enable */
#define RCC_CIER_MSIRDYIE_Pos (2U)
#define RCC_CIER_MSIRDYIE_Msk (0x1UL << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000004 */
#define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI ready interrupt enable */
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI ready interrupt enable */
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE ready interrupt enable */
#define RCC_CIER_PLL1RDYIE_Pos (8U)
#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000100 */
#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk /*!< PLL1 ready interrupt enable */
#define RCC_CIER_PLL2RDYIE_Pos (9U)
#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk /*!< PLL2 ready interrupt enable */
#define RCC_CIER_PLL3RDYIE_Pos (10U)
#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000400 */
#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk /*!< PLL3 ready interrupt enable */
#define RCC_CIER_PLL4RDYIE_Pos (11U)
#define RCC_CIER_PLL4RDYIE_Msk (0x1UL << RCC_CIER_PLL4RDYIE_Pos) /*!< 0x00000800 */
#define RCC_CIER_PLL4RDYIE RCC_CIER_PLL4RDYIE_Msk /*!< PLL4 ready interrupt enable */
#define RCC_CIER_LSECSSIE_Pos (16U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00010000 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk /*!< LSE CSS interrupt enable */
#define RCC_CIER_HSECSSIE_Pos (17U)
#define RCC_CIER_HSECSSIE_Msk (0x1UL << RCC_CIER_HSECSSIE_Pos) /*!< 0x00020000 */
#define RCC_CIER_HSECSSIE RCC_CIER_HSECSSIE_Msk /*!< HSE CSS interrupt enable */
#define RCC_CIER_WKUPIE_Pos (24U)
#define RCC_CIER_WKUPIE_Msk (0x1UL << RCC_CIER_WKUPIE_Pos) /*!< 0x01000000 */
#define RCC_CIER_WKUPIE RCC_CIER_WKUPIE_Msk /*!< CPU wake-up from Stop interrupt enable */
/******************* Bit definition for RCC_CIFR register *******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI ready interrupt flag */
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE ready interrupt flag */
#define RCC_CIFR_MSIRDYF_Pos (2U)
#define RCC_CIFR_MSIRDYF_Msk (0x1UL << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000004 */
#define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI ready interrupt flag */
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI ready interrupt flag */
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE ready interrupt flag */
#define RCC_CIFR_PLL1RDYF_Pos (8U)
#define RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk /*!< PLL1 ready interrupt flag */
#define RCC_CIFR_PLL2RDYF_Pos (9U)
#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk /*!< PLL2 ready interrupt flag */
#define RCC_CIFR_PLL3RDYF_Pos (10U)
#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk /*!< PLL3 ready interrupt flag */
#define RCC_CIFR_PLL4RDYF_Pos (11U)
#define RCC_CIFR_PLL4RDYF_Msk (0x1UL << RCC_CIFR_PLL4RDYF_Pos) /*!< 0x00000800 */
#define RCC_CIFR_PLL4RDYF RCC_CIFR_PLL4RDYF_Msk /*!< PLL4 ready interrupt flag */
#define RCC_CIFR_LSECSSF_Pos (16U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00010000 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk /*!< LSE ready interrupt flag */
#define RCC_CIFR_HSECSSF_Pos (17U)
#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00020000 */
#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk /*!< HSE ready interrupt flag */
#define RCC_CIFR_WKUPF_Pos (24U)
#define RCC_CIFR_WKUPF_Msk (0x1UL << RCC_CIFR_WKUPF_Pos) /*!< 0x01000000 */
#define RCC_CIFR_WKUPF RCC_CIFR_WKUPF_Msk /*!< CPU wake-up from Stop interrupt flag */
/******************* Bit definition for RCC_CICR register *******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI ready interrupt clear */
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE ready interrupt clear */
#define RCC_CICR_MSIRDYC_Pos (2U)
#define RCC_CICR_MSIRDYC_Msk (0x1UL << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000004 */
#define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI ready interrupt clear */
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI ready interrupt clear */
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE ready interrupt clear */
#define RCC_CICR_PLL1RDYC_Pos (8U)
#define RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) /*!< 0x00000100 */
#define RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk /*!< PLL1 ready interrupt clear */
#define RCC_CICR_PLL2RDYC_Pos (9U)
#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000200 */
#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk /*!< PLL2 ready interrupt clear */
#define RCC_CICR_PLL3RDYC_Pos (10U)
#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk /*!< PLL3 ready interrupt clear */
#define RCC_CICR_PLL4RDYC_Pos (11U)
#define RCC_CICR_PLL4RDYC_Msk (0x1UL << RCC_CICR_PLL4RDYC_Pos) /*!< 0x00000800 */
#define RCC_CICR_PLL4RDYC RCC_CICR_PLL4RDYC_Msk /*!< PLL4 ready interrupt clear */
#define RCC_CICR_LSECSSC_Pos (16U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00010000 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk /*!< LSE ready interrupt clear */
#define RCC_CICR_HSECSSC_Pos (17U)
#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00020000 */
#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk /*!< HSE ready interrupt clear */
#define RCC_CICR_WKUPFC_Pos (24U)
#define RCC_CICR_WKUPFC_Msk (0x1UL << RCC_CICR_WKUPFC_Pos) /*!< 0x01000000 */
#define RCC_CICR_WKUPFC RCC_CICR_WKUPFC_Msk /*!< CPU wake-up ready interrupt clear */
/****************** Bit definition for RCC_CCIPR1 register ******************/
#define RCC_CCIPR1_ADF1SEL_Pos (0U)
#define RCC_CCIPR1_ADF1SEL_Msk (0x7UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR1_ADF1SEL RCC_CCIPR1_ADF1SEL_Msk /*!< Source selection for the ADF1 kernel clock */
#define RCC_CCIPR1_ADF1SEL_0 (0x1UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR1_ADF1SEL_1 (0x2UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR1_ADF1SEL_2 (0x4UL << RCC_CCIPR1_ADF1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR1_ADC12SEL_Pos (4U)
#define RCC_CCIPR1_ADC12SEL_Msk (0x7UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000070 */
#define RCC_CCIPR1_ADC12SEL RCC_CCIPR1_ADC12SEL_Msk /*!< Source selection for the ADC12 kernel clock */
#define RCC_CCIPR1_ADC12SEL_0 (0x1UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR1_ADC12SEL_1 (0x2UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR1_ADC12SEL_2 (0x4UL << RCC_CCIPR1_ADC12SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR1_ADCPRE_Pos (8U)
#define RCC_CCIPR1_ADCPRE_Msk (0xFFUL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x0000FF00 */
#define RCC_CCIPR1_ADCPRE RCC_CCIPR1_ADCPRE_Msk /*!< ADC12 Bus Slave clock divider selection (for clock ck_icn_s_vencram) */
#define RCC_CCIPR1_ADCPRE_0 (0x1UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000100 */
#define RCC_CCIPR1_ADCPRE_1 (0x2UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000200 */
#define RCC_CCIPR1_ADCPRE_2 (0x4UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000400 */
#define RCC_CCIPR1_ADCPRE_3 (0x8UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00000800 */
#define RCC_CCIPR1_ADCPRE_4 (0x10UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00001000 */
#define RCC_CCIPR1_ADCPRE_5 (0x20UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00002000 */
#define RCC_CCIPR1_ADCPRE_6 (0x40UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00004000 */
#define RCC_CCIPR1_ADCPRE_7 (0x80UL << RCC_CCIPR1_ADCPRE_Pos) /*!< 0x00008000 */
#define RCC_CCIPR1_DCMIPPSEL_Pos (20U)
#define RCC_CCIPR1_DCMIPPSEL_Msk (0x3UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00300000 */
#define RCC_CCIPR1_DCMIPPSEL RCC_CCIPR1_DCMIPPSEL_Msk /*!< Source selection for the DCMIPP kernel clock */
#define RCC_CCIPR1_DCMIPPSEL_0 (0x1UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR1_DCMIPPSEL_1 (0x2UL << RCC_CCIPR1_DCMIPPSEL_Pos) /*!< 0x00200000 */
/****************** Bit definition for RCC_CCIPR2 register ******************/
#define RCC_CCIPR2_ETH1PTPSEL_Pos (0U)
#define RCC_CCIPR2_ETH1PTPSEL_Msk (0x3UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000003 */
#define RCC_CCIPR2_ETH1PTPSEL RCC_CCIPR2_ETH1PTPSEL_Msk /*!< Source selection for the ETH1 kernel clock */
#define RCC_CCIPR2_ETH1PTPSEL_0 (0x1UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR2_ETH1PTPSEL_1 (0x2UL << RCC_CCIPR2_ETH1PTPSEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR2_ETH1PTPDIV_Pos (4U)
#define RCC_CCIPR2_ETH1PTPDIV_Msk (0xFUL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x000000F0 */
#define RCC_CCIPR2_ETH1PTPDIV RCC_CCIPR2_ETH1PTPDIV_Msk /*!< ETH1 Kernel clock divider selection (for clock ck_ker_eth1ptp) */
#define RCC_CCIPR2_ETH1PTPDIV_0 (0x1UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000010 */
#define RCC_CCIPR2_ETH1PTPDIV_1 (0x2UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000020 */
#define RCC_CCIPR2_ETH1PTPDIV_2 (0x4UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000040 */
#define RCC_CCIPR2_ETH1PTPDIV_3 (0x8UL << RCC_CCIPR2_ETH1PTPDIV_Pos) /*!< 0x00000080 */
#define RCC_CCIPR2_ETH1PWRDOWNACK_Pos (8U)
#define RCC_CCIPR2_ETH1PWRDOWNACK_Msk (0x1UL << RCC_CCIPR2_ETH1PWRDOWNACK_Pos) /*!< 0x00000100 */
#define RCC_CCIPR2_ETH1PWRDOWNACK RCC_CCIPR2_ETH1PWRDOWNACK_Msk /*!< Set and reset by software */
#define RCC_CCIPR2_ETH1CLKSEL_Pos (12U)
#define RCC_CCIPR2_ETH1CLKSEL_Msk (0x3UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR2_ETH1CLKSEL RCC_CCIPR2_ETH1CLKSEL_Msk /*!< Source selection for the ETH1 kernel clock */
#define RCC_CCIPR2_ETH1CLKSEL_0 (0x1UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR2_ETH1CLKSEL_1 (0x2UL << RCC_CCIPR2_ETH1CLKSEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR2_ETH1SEL_Pos (16U)
#define RCC_CCIPR2_ETH1SEL_Msk (0x7UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00070000 */
#define RCC_CCIPR2_ETH1SEL RCC_CCIPR2_ETH1SEL_Msk /*!< Set and reset by software */
#define RCC_CCIPR2_ETH1SEL_0 (0x1UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR2_ETH1SEL_1 (0x2UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR2_ETH1SEL_2 (0x4UL << RCC_CCIPR2_ETH1SEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR2_ETH1REFCLKSEL_Pos (20U)
#define RCC_CCIPR2_ETH1REFCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1REFCLKSEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR2_ETH1REFCLKSEL RCC_CCIPR2_ETH1REFCLKSEL_Msk /*!< Set and reset by software */
#define RCC_CCIPR2_ETH1GTXCLKSEL_Pos (24U)
#define RCC_CCIPR2_ETH1GTXCLKSEL_Msk (0x1UL << RCC_CCIPR2_ETH1GTXCLKSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR2_ETH1GTXCLKSEL RCC_CCIPR2_ETH1GTXCLKSEL_Msk /*!< Set and reset by software */
/****************** Bit definition for RCC_CCIPR3 register ******************/
#define RCC_CCIPR3_FDCANSEL_Pos (0U)
#define RCC_CCIPR3_FDCANSEL_Msk (0x3UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000003 */
#define RCC_CCIPR3_FDCANSEL RCC_CCIPR3_FDCANSEL_Msk /*!< Source selection for the FDCAN kernel clock */
#define RCC_CCIPR3_FDCANSEL_0 (0x1UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR3_FDCANSEL_1 (0x2UL << RCC_CCIPR3_FDCANSEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR3_FMCSEL_Pos (4U)
#define RCC_CCIPR3_FMCSEL_Msk (0x3UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000030 */
#define RCC_CCIPR3_FMCSEL RCC_CCIPR3_FMCSEL_Msk /*!< Source selection for the FMC kernel clock */
#define RCC_CCIPR3_FMCSEL_0 (0x1UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR3_FMCSEL_1 (0x2UL << RCC_CCIPR3_FMCSEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR3_DFTSEL_Pos (8U)
#define RCC_CCIPR3_DFTSEL_Msk (0x1UL << RCC_CCIPR3_DFTSEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR3_DFTSEL RCC_CCIPR3_DFTSEL_Msk /*!< Source selection for the DFT kernel clock */
/****************** Bit definition for RCC_CCIPR4 register ******************/
#define RCC_CCIPR4_I2C1SEL_Pos (0U)
#define RCC_CCIPR4_I2C1SEL_Msk (0x7UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR4_I2C1SEL RCC_CCIPR4_I2C1SEL_Msk /*!< Source selection for the I2C1 kernel clock */
#define RCC_CCIPR4_I2C1SEL_0 (0x1UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR4_I2C1SEL_1 (0x2UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR4_I2C1SEL_2 (0x4UL << RCC_CCIPR4_I2C1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR4_I2C2SEL_Pos (4U)
#define RCC_CCIPR4_I2C2SEL_Msk (0x7UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000070 */
#define RCC_CCIPR4_I2C2SEL RCC_CCIPR4_I2C2SEL_Msk /*!< Source selection for the I2C2 kernel clock */
#define RCC_CCIPR4_I2C2SEL_0 (0x1UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR4_I2C2SEL_1 (0x2UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR4_I2C2SEL_2 (0x4UL << RCC_CCIPR4_I2C2SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR4_I2C3SEL_Pos (8U)
#define RCC_CCIPR4_I2C3SEL_Msk (0x7UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000700 */
#define RCC_CCIPR4_I2C3SEL RCC_CCIPR4_I2C3SEL_Msk /*!< Source selection for the I2C3 kernel clock */
#define RCC_CCIPR4_I2C3SEL_0 (0x1UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR4_I2C3SEL_1 (0x2UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR4_I2C3SEL_2 (0x4UL << RCC_CCIPR4_I2C3SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR4_I2C4SEL_Pos (12U)
#define RCC_CCIPR4_I2C4SEL_Msk (0x7UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00007000 */
#define RCC_CCIPR4_I2C4SEL RCC_CCIPR4_I2C4SEL_Msk /*!< Source selection for the I2C4 kernel clock */
#define RCC_CCIPR4_I2C4SEL_0 (0x1UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR4_I2C4SEL_1 (0x2UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR4_I2C4SEL_2 (0x4UL << RCC_CCIPR4_I2C4SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR4_I3C1SEL_Pos (16U)
#define RCC_CCIPR4_I3C1SEL_Msk (0x7UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00070000 */
#define RCC_CCIPR4_I3C1SEL RCC_CCIPR4_I3C1SEL_Msk /*!< Source selection for the I3C1 kernel clock */
#define RCC_CCIPR4_I3C1SEL_0 (0x1UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR4_I3C1SEL_1 (0x2UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR4_I3C1SEL_2 (0x4UL << RCC_CCIPR4_I3C1SEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR4_I3C2SEL_Pos (20U)
#define RCC_CCIPR4_I3C2SEL_Msk (0x7UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00700000 */
#define RCC_CCIPR4_I3C2SEL RCC_CCIPR4_I3C2SEL_Msk /*!< Source selection for the I3C2 kernel clock */
#define RCC_CCIPR4_I3C2SEL_0 (0x1UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR4_I3C2SEL_1 (0x2UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR4_I3C2SEL_2 (0x4UL << RCC_CCIPR4_I3C2SEL_Pos) /*!< 0x00400000 */
#define RCC_CCIPR4_LTDCSEL_Pos (24U)
#define RCC_CCIPR4_LTDCSEL_Msk (0x3UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR4_LTDCSEL RCC_CCIPR4_LTDCSEL_Msk /*!< Source selection for the LTDC kernel clock */
#define RCC_CCIPR4_LTDCSEL_0 (0x1UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR4_LTDCSEL_1 (0x2UL << RCC_CCIPR4_LTDCSEL_Pos) /*!< 0x02000000 */
/****************** Bit definition for RCC_CCIPR5 register ******************/
#define RCC_CCIPR5_MCO1SEL_Pos (0U)
#define RCC_CCIPR5_MCO1SEL_Msk (0x7UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR5_MCO1SEL RCC_CCIPR5_MCO1SEL_Msk /*!< Source selection for the MCO1 kernel clock */
#define RCC_CCIPR5_MCO1SEL_0 (0x1UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR5_MCO1SEL_1 (0x2UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR5_MCO1SEL_2 (0x4UL << RCC_CCIPR5_MCO1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR5_MCO1PRE_Pos (4U)
#define RCC_CCIPR5_MCO1PRE_Msk (0xFUL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x000000F0 */
#define RCC_CCIPR5_MCO1PRE RCC_CCIPR5_MCO1PRE_Msk /*!< MCO1 Kernel clock divider selection (for clock MCO1) */
#define RCC_CCIPR5_MCO1PRE_0 (0x1UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000010 */
#define RCC_CCIPR5_MCO1PRE_1 (0x2UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000020 */
#define RCC_CCIPR5_MCO1PRE_2 (0x4UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000040 */
#define RCC_CCIPR5_MCO1PRE_3 (0x8UL << RCC_CCIPR5_MCO1PRE_Pos) /*!< 0x00000080 */
#define RCC_CCIPR5_MCO2SEL_Pos (8U)
#define RCC_CCIPR5_MCO2SEL_Msk (0x7UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000700 */
#define RCC_CCIPR5_MCO2SEL RCC_CCIPR5_MCO2SEL_Msk /*!< Source selection for the MCO2 kernel clock */
#define RCC_CCIPR5_MCO2SEL_0 (0x1UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR5_MCO2SEL_1 (0x2UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR5_MCO2SEL_2 (0x4UL << RCC_CCIPR5_MCO2SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR5_MCO2PRE_Pos (12U)
#define RCC_CCIPR5_MCO2PRE_Msk (0xFUL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x0000F000 */
#define RCC_CCIPR5_MCO2PRE RCC_CCIPR5_MCO2PRE_Msk /*!< MCO2 Kernel clock divider selection (for clock MCO2) */
#define RCC_CCIPR5_MCO2PRE_0 (0x1UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00001000 */
#define RCC_CCIPR5_MCO2PRE_1 (0x2UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00002000 */
#define RCC_CCIPR5_MCO2PRE_2 (0x4UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00004000 */
#define RCC_CCIPR5_MCO2PRE_3 (0x8UL << RCC_CCIPR5_MCO2PRE_Pos) /*!< 0x00008000 */
#define RCC_CCIPR5_MDF1SEL_Pos (16U)
#define RCC_CCIPR5_MDF1SEL_Msk (0x7UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00070000 */
#define RCC_CCIPR5_MDF1SEL RCC_CCIPR5_MDF1SEL_Msk /*!< Source selection for the MDF1 kernel clock */
#define RCC_CCIPR5_MDF1SEL_0 (0x1UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR5_MDF1SEL_1 (0x2UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR5_MDF1SEL_2 (0x4UL << RCC_CCIPR5_MDF1SEL_Pos) /*!< 0x00040000 */
/****************** Bit definition for RCC_CCIPR6 register ******************/
#define RCC_CCIPR6_XSPI1SEL_Pos (0U)
#define RCC_CCIPR6_XSPI1SEL_Msk (0x3UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000003 */
#define RCC_CCIPR6_XSPI1SEL RCC_CCIPR6_XSPI1SEL_Msk /*!< Source selection for the XSPI1 kernel clock */
#define RCC_CCIPR6_XSPI1SEL_0 (0x1UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR6_XSPI1SEL_1 (0x2UL << RCC_CCIPR6_XSPI1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR6_XSPI2SEL_Pos (4U)
#define RCC_CCIPR6_XSPI2SEL_Msk (0x3UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000030 */
#define RCC_CCIPR6_XSPI2SEL RCC_CCIPR6_XSPI2SEL_Msk /*!< Source selection for the XSPI2 kernel clock */
#define RCC_CCIPR6_XSPI2SEL_0 (0x1UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR6_XSPI2SEL_1 (0x2UL << RCC_CCIPR6_XSPI2SEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR6_XSPI3SEL_Pos (8U)
#define RCC_CCIPR6_XSPI3SEL_Msk (0x3UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR6_XSPI3SEL RCC_CCIPR6_XSPI3SEL_Msk /*!< Source selection for the XSPI3 kernel clock */
#define RCC_CCIPR6_XSPI3SEL_0 (0x1UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR6_XSPI3SEL_1 (0x2UL << RCC_CCIPR6_XSPI3SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR6_OTGPHY1SEL_Pos (12U)
#define RCC_CCIPR6_OTGPHY1SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR6_OTGPHY1SEL RCC_CCIPR6_OTGPHY1SEL_Msk /*!< Source selection for the OTGPHY1 kernel clock */
#define RCC_CCIPR6_OTGPHY1SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR6_OTGPHY1SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR6_OTGPHY1CKREFSEL_Pos (16U)
#define RCC_CCIPR6_OTGPHY1CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY1CKREFSEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR6_OTGPHY1CKREFSEL RCC_CCIPR6_OTGPHY1CKREFSEL_Msk /*!< Set and reset by software */
#define RCC_CCIPR6_OTGPHY2SEL_Pos (20U)
#define RCC_CCIPR6_OTGPHY2SEL_Msk (0x3UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00300000 */
#define RCC_CCIPR6_OTGPHY2SEL RCC_CCIPR6_OTGPHY2SEL_Msk /*!< Source selection for the OTGPHY2 kernel clock */
#define RCC_CCIPR6_OTGPHY2SEL_0 (0x1UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR6_OTGPHY2SEL_1 (0x2UL << RCC_CCIPR6_OTGPHY2SEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR6_OTGPHY2CKREFSEL_Pos (24U)
#define RCC_CCIPR6_OTGPHY2CKREFSEL_Msk (0x1UL << RCC_CCIPR6_OTGPHY2CKREFSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR6_OTGPHY2CKREFSEL RCC_CCIPR6_OTGPHY2CKREFSEL_Msk /*!< Set and reset by software */
/****************** Bit definition for RCC_CCIPR7 register ******************/
#define RCC_CCIPR7_PERSEL_Pos (0U)
#define RCC_CCIPR7_PERSEL_Msk (0x7UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR7_PERSEL RCC_CCIPR7_PERSEL_Msk /*!< Source selection for the PER kernel clock */
#define RCC_CCIPR7_PERSEL_0 (0x1UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR7_PERSEL_1 (0x2UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR7_PERSEL_2 (0x4UL << RCC_CCIPR7_PERSEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR7_PSSISEL_Pos (4U)
#define RCC_CCIPR7_PSSISEL_Msk (0x3UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000030 */
#define RCC_CCIPR7_PSSISEL RCC_CCIPR7_PSSISEL_Msk /*!< Source selection for the PSSI kernel clock */
#define RCC_CCIPR7_PSSISEL_0 (0x1UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR7_PSSISEL_1 (0x2UL << RCC_CCIPR7_PSSISEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR7_RTCSEL_Pos (8U)
#define RCC_CCIPR7_RTCSEL_Msk (0x3UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR7_RTCSEL RCC_CCIPR7_RTCSEL_Msk /*!< Source selection for the RTC kernel clock */
#define RCC_CCIPR7_RTCSEL_0 (0x1UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR7_RTCSEL_1 (0x2UL << RCC_CCIPR7_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR7_RTCPRE_Pos (12U)
#define RCC_CCIPR7_RTCPRE_Msk (0x3FUL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x0003F000 */
#define RCC_CCIPR7_RTCPRE RCC_CCIPR7_RTCPRE_Msk /*!< RTC OSC clock divider selection (for clock hse_ck) */
#define RCC_CCIPR7_RTCPRE_0 (0x1UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00001000 */
#define RCC_CCIPR7_RTCPRE_1 (0x2UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00002000 */
#define RCC_CCIPR7_RTCPRE_2 (0x4UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00004000 */
#define RCC_CCIPR7_RTCPRE_3 (0x8UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00008000 */
#define RCC_CCIPR7_RTCPRE_4 (0x10UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00010000 */
#define RCC_CCIPR7_RTCPRE_5 (0x20UL << RCC_CCIPR7_RTCPRE_Pos) /*!< 0x00020000 */
#define RCC_CCIPR7_SAI1SEL_Pos (20U)
#define RCC_CCIPR7_SAI1SEL_Msk (0x7UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00700000 */
#define RCC_CCIPR7_SAI1SEL RCC_CCIPR7_SAI1SEL_Msk /*!< Source selection for the SAI1 kernel clock */
#define RCC_CCIPR7_SAI1SEL_0 (0x1UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR7_SAI1SEL_1 (0x2UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR7_SAI1SEL_2 (0x4UL << RCC_CCIPR7_SAI1SEL_Pos) /*!< 0x00400000 */
#define RCC_CCIPR7_SAI2SEL_Pos (24U)
#define RCC_CCIPR7_SAI2SEL_Msk (0x7UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x07000000 */
#define RCC_CCIPR7_SAI2SEL RCC_CCIPR7_SAI2SEL_Msk /*!< Source selection for the SAI2 kernel clock */
#define RCC_CCIPR7_SAI2SEL_0 (0x1UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR7_SAI2SEL_1 (0x2UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR7_SAI2SEL_2 (0x4UL << RCC_CCIPR7_SAI2SEL_Pos) /*!< 0x04000000 */
/****************** Bit definition for RCC_CCIPR8 register ******************/
#define RCC_CCIPR8_SDMMC1SEL_Pos (0U)
#define RCC_CCIPR8_SDMMC1SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000003 */
#define RCC_CCIPR8_SDMMC1SEL RCC_CCIPR8_SDMMC1SEL_Msk /*!< Source selection for the SDMMC1 kernel clock */
#define RCC_CCIPR8_SDMMC1SEL_0 (0x1UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR8_SDMMC1SEL_1 (0x2UL << RCC_CCIPR8_SDMMC1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR8_SDMMC2SEL_Pos (4U)
#define RCC_CCIPR8_SDMMC2SEL_Msk (0x3UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000030 */
#define RCC_CCIPR8_SDMMC2SEL RCC_CCIPR8_SDMMC2SEL_Msk /*!< Source selection for the SDMMC2 kernel clock */
#define RCC_CCIPR8_SDMMC2SEL_0 (0x1UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR8_SDMMC2SEL_1 (0x2UL << RCC_CCIPR8_SDMMC2SEL_Pos) /*!< 0x00000020 */
/****************** Bit definition for RCC_CCIPR9 register ******************/
#define RCC_CCIPR9_SPDIFRX1SEL_Pos (0U)
#define RCC_CCIPR9_SPDIFRX1SEL_Msk (0x7UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR9_SPDIFRX1SEL RCC_CCIPR9_SPDIFRX1SEL_Msk /*!< Source selection for the SPDIFRX1 kernel clock */
#define RCC_CCIPR9_SPDIFRX1SEL_0 (0x1UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR9_SPDIFRX1SEL_1 (0x2UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR9_SPDIFRX1SEL_2 (0x4UL << RCC_CCIPR9_SPDIFRX1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR9_SPI1SEL_Pos (4U)
#define RCC_CCIPR9_SPI1SEL_Msk (0x7UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000070 */
#define RCC_CCIPR9_SPI1SEL RCC_CCIPR9_SPI1SEL_Msk /*!< Source selection for the SPI1 kernel clock */
#define RCC_CCIPR9_SPI1SEL_0 (0x1UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR9_SPI1SEL_1 (0x2UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR9_SPI1SEL_2 (0x4UL << RCC_CCIPR9_SPI1SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR9_SPI2SEL_Pos (8U)
#define RCC_CCIPR9_SPI2SEL_Msk (0x7UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000700 */
#define RCC_CCIPR9_SPI2SEL RCC_CCIPR9_SPI2SEL_Msk /*!< Source selection for the SPI2 kernel clock */
#define RCC_CCIPR9_SPI2SEL_0 (0x1UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR9_SPI2SEL_1 (0x2UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR9_SPI2SEL_2 (0x4UL << RCC_CCIPR9_SPI2SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR9_SPI3SEL_Pos (12U)
#define RCC_CCIPR9_SPI3SEL_Msk (0x7UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00007000 */
#define RCC_CCIPR9_SPI3SEL RCC_CCIPR9_SPI3SEL_Msk /*!< Source selection for the SPI3 kernel clock */
#define RCC_CCIPR9_SPI3SEL_0 (0x1UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR9_SPI3SEL_1 (0x2UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR9_SPI3SEL_2 (0x4UL << RCC_CCIPR9_SPI3SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR9_SPI4SEL_Pos (16U)
#define RCC_CCIPR9_SPI4SEL_Msk (0x7UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00070000 */
#define RCC_CCIPR9_SPI4SEL RCC_CCIPR9_SPI4SEL_Msk /*!< Source selection for the SPI4 kernel clock */
#define RCC_CCIPR9_SPI4SEL_0 (0x1UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR9_SPI4SEL_1 (0x2UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR9_SPI4SEL_2 (0x4UL << RCC_CCIPR9_SPI4SEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR9_SPI5SEL_Pos (20U)
#define RCC_CCIPR9_SPI5SEL_Msk (0x7UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00700000 */
#define RCC_CCIPR9_SPI5SEL RCC_CCIPR9_SPI5SEL_Msk /*!< Source selection for the SPI5 kernel clock */
#define RCC_CCIPR9_SPI5SEL_0 (0x1UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR9_SPI5SEL_1 (0x2UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR9_SPI5SEL_2 (0x4UL << RCC_CCIPR9_SPI5SEL_Pos) /*!< 0x00400000 */
#define RCC_CCIPR9_SPI6SEL_Pos (24U)
#define RCC_CCIPR9_SPI6SEL_Msk (0x7UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x07000000 */
#define RCC_CCIPR9_SPI6SEL RCC_CCIPR9_SPI6SEL_Msk /*!< Source selection for the SPI6 kernel clock */
#define RCC_CCIPR9_SPI6SEL_0 (0x1UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR9_SPI6SEL_1 (0x2UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR9_SPI6SEL_2 (0x4UL << RCC_CCIPR9_SPI6SEL_Pos) /*!< 0x04000000 */
/***************** Bit definition for RCC_CCIPR12 register ******************/
#define RCC_CCIPR12_LPTIM1SEL_Pos (8U)
#define RCC_CCIPR12_LPTIM1SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000700 */
#define RCC_CCIPR12_LPTIM1SEL RCC_CCIPR12_LPTIM1SEL_Msk /*!< Source selection for the LPTIM1 kernel clock */
#define RCC_CCIPR12_LPTIM1SEL_0 (0x1UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR12_LPTIM1SEL_1 (0x2UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR12_LPTIM1SEL_2 (0x4UL << RCC_CCIPR12_LPTIM1SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR12_LPTIM2SEL_Pos (12U)
#define RCC_CCIPR12_LPTIM2SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00007000 */
#define RCC_CCIPR12_LPTIM2SEL RCC_CCIPR12_LPTIM2SEL_Msk /*!< Source selection for the LPTIM2 kernel clock */
#define RCC_CCIPR12_LPTIM2SEL_0 (0x1UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR12_LPTIM2SEL_1 (0x2UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR12_LPTIM2SEL_2 (0x4UL << RCC_CCIPR12_LPTIM2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR12_LPTIM3SEL_Pos (16U)
#define RCC_CCIPR12_LPTIM3SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00070000 */
#define RCC_CCIPR12_LPTIM3SEL RCC_CCIPR12_LPTIM3SEL_Msk /*!< Source selection for the LPTIM3 kernel clock */
#define RCC_CCIPR12_LPTIM3SEL_0 (0x1UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR12_LPTIM3SEL_1 (0x2UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR12_LPTIM3SEL_2 (0x4UL << RCC_CCIPR12_LPTIM3SEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR12_LPTIM4SEL_Pos (20U)
#define RCC_CCIPR12_LPTIM4SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00700000 */
#define RCC_CCIPR12_LPTIM4SEL RCC_CCIPR12_LPTIM4SEL_Msk /*!< Source selection for the LPTIM4 kernel clock */
#define RCC_CCIPR12_LPTIM4SEL_0 (0x1UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR12_LPTIM4SEL_1 (0x2UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR12_LPTIM4SEL_2 (0x4UL << RCC_CCIPR12_LPTIM4SEL_Pos) /*!< 0x00400000 */
#define RCC_CCIPR12_LPTIM5SEL_Pos (24U)
#define RCC_CCIPR12_LPTIM5SEL_Msk (0x7UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x07000000 */
#define RCC_CCIPR12_LPTIM5SEL RCC_CCIPR12_LPTIM5SEL_Msk /*!< Source selection for the LPTIM5 kernel clock */
#define RCC_CCIPR12_LPTIM5SEL_0 (0x1UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR12_LPTIM5SEL_1 (0x2UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR12_LPTIM5SEL_2 (0x4UL << RCC_CCIPR12_LPTIM5SEL_Pos) /*!< 0x04000000 */
/***************** Bit definition for RCC_CCIPR13 register ******************/
#define RCC_CCIPR13_USART1SEL_Pos (0U)
#define RCC_CCIPR13_USART1SEL_Msk (0x7UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR13_USART1SEL RCC_CCIPR13_USART1SEL_Msk /*!< Source selection for the USART1 kernel clock */
#define RCC_CCIPR13_USART1SEL_0 (0x1UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR13_USART1SEL_1 (0x2UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR13_USART1SEL_2 (0x4UL << RCC_CCIPR13_USART1SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR13_USART2SEL_Pos (4U)
#define RCC_CCIPR13_USART2SEL_Msk (0x7UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000070 */
#define RCC_CCIPR13_USART2SEL RCC_CCIPR13_USART2SEL_Msk /*!< Source selection for the USART2 kernel clock */
#define RCC_CCIPR13_USART2SEL_0 (0x1UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR13_USART2SEL_1 (0x2UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR13_USART2SEL_2 (0x4UL << RCC_CCIPR13_USART2SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR13_USART3SEL_Pos (8U)
#define RCC_CCIPR13_USART3SEL_Msk (0x7UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000700 */
#define RCC_CCIPR13_USART3SEL RCC_CCIPR13_USART3SEL_Msk /*!< Source selection for the USART3 kernel clock */
#define RCC_CCIPR13_USART3SEL_0 (0x1UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR13_USART3SEL_1 (0x2UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR13_USART3SEL_2 (0x4UL << RCC_CCIPR13_USART3SEL_Pos) /*!< 0x00000400 */
#define RCC_CCIPR13_UART4SEL_Pos (12U)
#define RCC_CCIPR13_UART4SEL_Msk (0x7UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00007000 */
#define RCC_CCIPR13_UART4SEL RCC_CCIPR13_UART4SEL_Msk /*!< Source selection for the UART4 kernel clock */
#define RCC_CCIPR13_UART4SEL_0 (0x1UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR13_UART4SEL_1 (0x2UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR13_UART4SEL_2 (0x4UL << RCC_CCIPR13_UART4SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR13_UART5SEL_Pos (16U)
#define RCC_CCIPR13_UART5SEL_Msk (0x7UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00070000 */
#define RCC_CCIPR13_UART5SEL RCC_CCIPR13_UART5SEL_Msk /*!< Source selection for the UART5 kernel clock */
#define RCC_CCIPR13_UART5SEL_0 (0x1UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR13_UART5SEL_1 (0x2UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR13_UART5SEL_2 (0x4UL << RCC_CCIPR13_UART5SEL_Pos) /*!< 0x00040000 */
#define RCC_CCIPR13_USART6SEL_Pos (20U)
#define RCC_CCIPR13_USART6SEL_Msk (0x7UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00700000 */
#define RCC_CCIPR13_USART6SEL RCC_CCIPR13_USART6SEL_Msk /*!< Source selection for the USART6 kernel clock */
#define RCC_CCIPR13_USART6SEL_0 (0x1UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00100000 */
#define RCC_CCIPR13_USART6SEL_1 (0x2UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00200000 */
#define RCC_CCIPR13_USART6SEL_2 (0x4UL << RCC_CCIPR13_USART6SEL_Pos) /*!< 0x00400000 */
#define RCC_CCIPR13_UART7SEL_Pos (24U)
#define RCC_CCIPR13_UART7SEL_Msk (0x7UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x07000000 */
#define RCC_CCIPR13_UART7SEL RCC_CCIPR13_UART7SEL_Msk /*!< Source selection for the UART7 kernel clock */
#define RCC_CCIPR13_UART7SEL_0 (0x1UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR13_UART7SEL_1 (0x2UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR13_UART7SEL_2 (0x4UL << RCC_CCIPR13_UART7SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR13_UART8SEL_Pos (28U)
#define RCC_CCIPR13_UART8SEL_Msk (0x7UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x70000000 */
#define RCC_CCIPR13_UART8SEL RCC_CCIPR13_UART8SEL_Msk /*!< Source selection for the UART8 kernel clock */
#define RCC_CCIPR13_UART8SEL_0 (0x1UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR13_UART8SEL_1 (0x2UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x20000000 */
#define RCC_CCIPR13_UART8SEL_2 (0x4UL << RCC_CCIPR13_UART8SEL_Pos) /*!< 0x40000000 */
/***************** Bit definition for RCC_CCIPR14 register ******************/
#define RCC_CCIPR14_UART9SEL_Pos (0U)
#define RCC_CCIPR14_UART9SEL_Msk (0x7UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000007 */
#define RCC_CCIPR14_UART9SEL RCC_CCIPR14_UART9SEL_Msk /*!< Source selection for the UART9 kernel clock */
#define RCC_CCIPR14_UART9SEL_0 (0x1UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR14_UART9SEL_1 (0x2UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR14_UART9SEL_2 (0x4UL << RCC_CCIPR14_UART9SEL_Pos) /*!< 0x00000004 */
#define RCC_CCIPR14_USART10SEL_Pos (4U)
#define RCC_CCIPR14_USART10SEL_Msk (0x7UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000070 */
#define RCC_CCIPR14_USART10SEL RCC_CCIPR14_USART10SEL_Msk /*!< Source selection for the USART10 kernel clock */
#define RCC_CCIPR14_USART10SEL_0 (0x1UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000010 */
#define RCC_CCIPR14_USART10SEL_1 (0x2UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000020 */
#define RCC_CCIPR14_USART10SEL_2 (0x4UL << RCC_CCIPR14_USART10SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR14_LPUART1SEL_Pos (8U)
#define RCC_CCIPR14_LPUART1SEL_Msk (0x7UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000700 */
#define RCC_CCIPR14_LPUART1SEL RCC_CCIPR14_LPUART1SEL_Msk /*!< Source selection for the LPUART1 kernel clock */
#define RCC_CCIPR14_LPUART1SEL_0 (0x1UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR14_LPUART1SEL_1 (0x2UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR14_LPUART1SEL_2 (0x4UL << RCC_CCIPR14_LPUART1SEL_Pos) /*!< 0x00000400 */
/***************** Bit definition for RCC_MISCRSTR register *****************/
#define RCC_MISCRSTR_DBGRST_Pos (0U)
#define RCC_MISCRSTR_DBGRST_Msk (0x1UL << RCC_MISCRSTR_DBGRST_Pos) /*!< 0x00000001 */
#define RCC_MISCRSTR_DBGRST RCC_MISCRSTR_DBGRST_Msk /*!< DBG reset */
#define RCC_MISCRSTR_XSPIPHY1RST_Pos (4U)
#define RCC_MISCRSTR_XSPIPHY1RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY1RST_Pos) /*!< 0x00000010 */
#define RCC_MISCRSTR_XSPIPHY1RST RCC_MISCRSTR_XSPIPHY1RST_Msk /*!< XSPIPHY1 reset */
#define RCC_MISCRSTR_XSPIPHY2RST_Pos (5U)
#define RCC_MISCRSTR_XSPIPHY2RST_Msk (0x1UL << RCC_MISCRSTR_XSPIPHY2RST_Pos) /*!< 0x00000020 */
#define RCC_MISCRSTR_XSPIPHY2RST RCC_MISCRSTR_XSPIPHY2RST_Msk /*!< XSPIPHY2 reset */
#define RCC_MISCRSTR_SDMMC1DLLRST_Pos (7U)
#define RCC_MISCRSTR_SDMMC1DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC1DLLRST_Pos) /*!< 0x00000080 */
#define RCC_MISCRSTR_SDMMC1DLLRST RCC_MISCRSTR_SDMMC1DLLRST_Msk /*!< SDMMC1DLL reset */
#define RCC_MISCRSTR_SDMMC2DLLRST_Pos (8U)
#define RCC_MISCRSTR_SDMMC2DLLRST_Msk (0x1UL << RCC_MISCRSTR_SDMMC2DLLRST_Pos) /*!< 0x00000100 */
#define RCC_MISCRSTR_SDMMC2DLLRST RCC_MISCRSTR_SDMMC2DLLRST_Msk /*!< SDMMC2DLL reset */
/***************** Bit definition for RCC_MEMRSTR register ******************/
#define RCC_MEMRSTR_AXISRAM3RST_Pos (0U)
#define RCC_MEMRSTR_AXISRAM3RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM3RST_Pos)/*!< 0x00000001 */
#define RCC_MEMRSTR_AXISRAM3RST RCC_MEMRSTR_AXISRAM3RST_Msk /*!< AXISRAM3 reset */
#define RCC_MEMRSTR_AXISRAM4RST_Pos (1U)
#define RCC_MEMRSTR_AXISRAM4RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM4RST_Pos)/*!< 0x00000002 */
#define RCC_MEMRSTR_AXISRAM4RST RCC_MEMRSTR_AXISRAM4RST_Msk /*!< AXISRAM4 reset */
#define RCC_MEMRSTR_AXISRAM5RST_Pos (2U)
#define RCC_MEMRSTR_AXISRAM5RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM5RST_Pos)/*!< 0x00000004 */
#define RCC_MEMRSTR_AXISRAM5RST RCC_MEMRSTR_AXISRAM5RST_Msk /*!< AXISRAM5 reset */
#define RCC_MEMRSTR_AXISRAM6RST_Pos (3U)
#define RCC_MEMRSTR_AXISRAM6RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM6RST_Pos)/*!< 0x00000008 */
#define RCC_MEMRSTR_AXISRAM6RST RCC_MEMRSTR_AXISRAM6RST_Msk /*!< AXISRAM6 reset */
#define RCC_MEMRSTR_AHBSRAM1RST_Pos (4U)
#define RCC_MEMRSTR_AHBSRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM1RST_Pos)/*!< 0x00000010 */
#define RCC_MEMRSTR_AHBSRAM1RST RCC_MEMRSTR_AHBSRAM1RST_Msk /*!< AHBSRAM1 reset */
#define RCC_MEMRSTR_AHBSRAM2RST_Pos (5U)
#define RCC_MEMRSTR_AHBSRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AHBSRAM2RST_Pos)/*!< 0x00000020 */
#define RCC_MEMRSTR_AHBSRAM2RST RCC_MEMRSTR_AHBSRAM2RST_Msk /*!< AHBSRAM2 reset */
#define RCC_MEMRSTR_AXISRAM1RST_Pos (7U)
#define RCC_MEMRSTR_AXISRAM1RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM1RST_Pos)/*!< 0x00000080 */
#define RCC_MEMRSTR_AXISRAM1RST RCC_MEMRSTR_AXISRAM1RST_Msk /*!< AXISRAM1 reset */
#define RCC_MEMRSTR_AXISRAM2RST_Pos (8U)
#define RCC_MEMRSTR_AXISRAM2RST_Msk (0x1UL << RCC_MEMRSTR_AXISRAM2RST_Pos)/*!< 0x00000100 */
#define RCC_MEMRSTR_AXISRAM2RST RCC_MEMRSTR_AXISRAM2RST_Msk /*!< AXISRAM2 reset */
#define RCC_MEMRSTR_FLEXRAMRST_Pos (9U)
#define RCC_MEMRSTR_FLEXRAMRST_Msk (0x1UL << RCC_MEMRSTR_FLEXRAMRST_Pos) /*!< 0x00000200 */
#define RCC_MEMRSTR_FLEXRAMRST RCC_MEMRSTR_FLEXRAMRST_Msk /*!< FLEXRAM reset */
#define RCC_MEMRSTR_CACHEAXIRAMRST_Pos (10U)
#define RCC_MEMRSTR_CACHEAXIRAMRST_Msk (0x1UL << RCC_MEMRSTR_CACHEAXIRAMRST_Pos) /*!< 0x00000400 */
#define RCC_MEMRSTR_CACHEAXIRAMRST RCC_MEMRSTR_CACHEAXIRAMRST_Msk /*!< CACHEAXIRAM reset */
#define RCC_MEMRSTR_VENCRAMRST_Pos (11U)
#define RCC_MEMRSTR_VENCRAMRST_Msk (0x1UL << RCC_MEMRSTR_VENCRAMRST_Pos) /*!< 0x00000800 */
#define RCC_MEMRSTR_VENCRAMRST RCC_MEMRSTR_VENCRAMRST_Msk /*!< VENCRAM reset */
#define RCC_MEMRSTR_BOOTROMRST_Pos (12U)
#define RCC_MEMRSTR_BOOTROMRST_Msk (0x1UL << RCC_MEMRSTR_BOOTROMRST_Pos) /*!< 0x00001000 */
#define RCC_MEMRSTR_BOOTROMRST RCC_MEMRSTR_BOOTROMRST_Msk /*!< Boot ROM reset */
/***************** Bit definition for RCC_AHB1RSTR register *****************/
#define RCC_AHB1RSTR_GPDMA1RST_Pos (4U)
#define RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk /*!< GPDMA1 reset */
#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk /*!< ADC12 reset */
/***************** Bit definition for RCC_AHB2RSTR register *****************/
#define RCC_AHB2RSTR_RAMCFGRST_Pos (12U)
#define RCC_AHB2RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB2RSTR_RAMCFGRST_Pos) /*!< 0x00001000 */
#define RCC_AHB2RSTR_RAMCFGRST RCC_AHB2RSTR_RAMCFGRST_Msk /*!< RAMCFG reset */
#define RCC_AHB2RSTR_MDF1RST_Pos (16U)
#define RCC_AHB2RSTR_MDF1RST_Msk (0x1UL << RCC_AHB2RSTR_MDF1RST_Pos) /*!< 0x00010000 */
#define RCC_AHB2RSTR_MDF1RST RCC_AHB2RSTR_MDF1RST_Msk /*!< MDF1 reset */
#define RCC_AHB2RSTR_ADF1RST_Pos (17U)
#define RCC_AHB2RSTR_ADF1RST_Msk (0x1UL << RCC_AHB2RSTR_ADF1RST_Pos) /*!< 0x00020000 */
#define RCC_AHB2RSTR_ADF1RST RCC_AHB2RSTR_ADF1RST_Msk /*!< ADF1 reset */
/***************** Bit definition for RCC_AHB3RSTR register *****************/
#define RCC_AHB3RSTR_RNGRST_Pos (0U)
#define RCC_AHB3RSTR_RNGRST_Msk (0x1UL << RCC_AHB3RSTR_RNGRST_Pos) /*!< 0x00000001 */
#define RCC_AHB3RSTR_RNGRST RCC_AHB3RSTR_RNGRST_Msk /*!< RNG reset */
#define RCC_AHB3RSTR_HASHRST_Pos (1U)
#define RCC_AHB3RSTR_HASHRST_Msk (0x1UL << RCC_AHB3RSTR_HASHRST_Pos) /*!< 0x00000002 */
#define RCC_AHB3RSTR_HASHRST RCC_AHB3RSTR_HASHRST_Msk /*!< HASH reset */
#define RCC_AHB3RSTR_CRYPRST_Pos (2U)
#define RCC_AHB3RSTR_CRYPRST_Msk (0x1UL << RCC_AHB3RSTR_CRYPRST_Pos) /*!< 0x00000004 */
#define RCC_AHB3RSTR_CRYPRST RCC_AHB3RSTR_CRYPRST_Msk /*!< CRYP reset */
#define RCC_AHB3RSTR_SAESRST_Pos (4U)
#define RCC_AHB3RSTR_SAESRST_Msk (0x1UL << RCC_AHB3RSTR_SAESRST_Pos) /*!< 0x00000010 */
#define RCC_AHB3RSTR_SAESRST RCC_AHB3RSTR_SAESRST_Msk /*!< SAES reset */
#define RCC_AHB3RSTR_PKARST_Pos (8U)
#define RCC_AHB3RSTR_PKARST_Msk (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00000100 */
#define RCC_AHB3RSTR_PKARST RCC_AHB3RSTR_PKARST_Msk /*!< PKA reset */
#define RCC_AHB3RSTR_IACRST_Pos (10U)
#define RCC_AHB3RSTR_IACRST_Msk (0x1UL << RCC_AHB3RSTR_IACRST_Pos) /*!< 0x00000400 */
#define RCC_AHB3RSTR_IACRST RCC_AHB3RSTR_IACRST_Msk /*!< IAC reset */
/***************** Bit definition for RCC_AHB4RSTR register *****************/
#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk /*!< GPIO A reset */
#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk /*!< GPIO B reset */
#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk /*!< GPIO C reset */
#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk /*!< GPIO D reset */
#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk /*!< GPIO E reset */
#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk /*!< GPIO F reset */
#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk /*!< GPIO G reset */
#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk /*!< GPIO H reset */
#define RCC_AHB4RSTR_GPIONRST_Pos (13U)
#define RCC_AHB4RSTR_GPIONRST_Msk (0x1UL << RCC_AHB4RSTR_GPIONRST_Pos) /*!< 0x00002000 */
#define RCC_AHB4RSTR_GPIONRST RCC_AHB4RSTR_GPIONRST_Msk /*!< GPIO N reset */
#define RCC_AHB4RSTR_GPIOORST_Pos (14U)
#define RCC_AHB4RSTR_GPIOORST_Msk (0x1UL << RCC_AHB4RSTR_GPIOORST_Pos) /*!< 0x00004000 */
#define RCC_AHB4RSTR_GPIOORST RCC_AHB4RSTR_GPIOORST_Msk /*!< GPIO O reset */
#define RCC_AHB4RSTR_GPIOPRST_Pos (15U)
#define RCC_AHB4RSTR_GPIOPRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOPRST_Pos) /*!< 0x00008000 */
#define RCC_AHB4RSTR_GPIOPRST RCC_AHB4RSTR_GPIOPRST_Msk /*!< GPIO P reset */
#define RCC_AHB4RSTR_GPIOQRST_Pos (16U)
#define RCC_AHB4RSTR_GPIOQRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOQRST_Pos) /*!< 0x00010000 */
#define RCC_AHB4RSTR_GPIOQRST RCC_AHB4RSTR_GPIOQRST_Msk /*!< GPIO Q reset */
#define RCC_AHB4RSTR_PWRRST_Pos (18U)
#define RCC_AHB4RSTR_PWRRST_Msk (0x1UL << RCC_AHB4RSTR_PWRRST_Pos) /*!< 0x00040000 */
#define RCC_AHB4RSTR_PWRRST RCC_AHB4RSTR_PWRRST_Msk /*!< PWR reset */
#define RCC_AHB4RSTR_CRCRST_Pos (19U)
#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */
#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk /*!< CRC reset */
/***************** Bit definition for RCC_AHB5RSTR register *****************/
#define RCC_AHB5RSTR_HPDMA1RST_Pos (0U)
#define RCC_AHB5RSTR_HPDMA1RST_Msk (0x1UL << RCC_AHB5RSTR_HPDMA1RST_Pos) /*!< 0x00000001 */
#define RCC_AHB5RSTR_HPDMA1RST RCC_AHB5RSTR_HPDMA1RST_Msk /*!< HPDMA1 reset */
#define RCC_AHB5RSTR_DMA2DRST_Pos (1U)
#define RCC_AHB5RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB5RSTR_DMA2DRST_Pos) /*!< 0x00000002 */
#define RCC_AHB5RSTR_DMA2DRST RCC_AHB5RSTR_DMA2DRST_Msk /*!< DMA2D reset */
#define RCC_AHB5RSTR_JPEGRST_Pos (3U)
#define RCC_AHB5RSTR_JPEGRST_Msk (0x1UL << RCC_AHB5RSTR_JPEGRST_Pos) /*!< 0x00000008 */
#define RCC_AHB5RSTR_JPEGRST RCC_AHB5RSTR_JPEGRST_Msk /*!< JPEG reset */
#define RCC_AHB5RSTR_FMCRST_Pos (4U)
#define RCC_AHB5RSTR_FMCRST_Msk (0x1UL << RCC_AHB5RSTR_FMCRST_Pos) /*!< 0x00000010 */
#define RCC_AHB5RSTR_FMCRST RCC_AHB5RSTR_FMCRST_Msk /*!< FMC reset */
#define RCC_AHB5RSTR_XSPI1RST_Pos (5U)
#define RCC_AHB5RSTR_XSPI1RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI1RST_Pos) /*!< 0x00000020 */
#define RCC_AHB5RSTR_XSPI1RST RCC_AHB5RSTR_XSPI1RST_Msk /*!< XSPI1 reset */
#define RCC_AHB5RSTR_PSSIRST_Pos (6U)
#define RCC_AHB5RSTR_PSSIRST_Msk (0x1UL << RCC_AHB5RSTR_PSSIRST_Pos) /*!< 0x00000040 */
#define RCC_AHB5RSTR_PSSIRST RCC_AHB5RSTR_PSSIRST_Msk /*!< PSSI reset */
#define RCC_AHB5RSTR_SDMMC2RST_Pos (7U)
#define RCC_AHB5RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */
#define RCC_AHB5RSTR_SDMMC2RST RCC_AHB5RSTR_SDMMC2RST_Msk /*!< SDMMC2 reset */
#define RCC_AHB5RSTR_SDMMC1RST_Pos (8U)
#define RCC_AHB5RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB5RSTR_SDMMC1RST_Pos) /*!< 0x00000100 */
#define RCC_AHB5RSTR_SDMMC1RST RCC_AHB5RSTR_SDMMC1RST_Msk /*!< SDMMC1 reset */
#define RCC_AHB5RSTR_XSPI2RST_Pos (12U)
#define RCC_AHB5RSTR_XSPI2RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI2RST_Pos) /*!< 0x00001000 */
#define RCC_AHB5RSTR_XSPI2RST RCC_AHB5RSTR_XSPI2RST_Msk /*!< XSPI2 reset */
#define RCC_AHB5RSTR_XSPIMRST_Pos (13U)
#define RCC_AHB5RSTR_XSPIMRST_Msk (0x1UL << RCC_AHB5RSTR_XSPIMRST_Pos) /*!< 0x00002000 */
#define RCC_AHB5RSTR_XSPIMRST RCC_AHB5RSTR_XSPIMRST_Msk /*!< XSPIM reset */
#define RCC_AHB5RSTR_XSPI3RST_Pos (17U)
#define RCC_AHB5RSTR_XSPI3RST_Msk (0x1UL << RCC_AHB5RSTR_XSPI3RST_Pos) /*!< 0x00020000 */
#define RCC_AHB5RSTR_XSPI3RST RCC_AHB5RSTR_XSPI3RST_Msk /*!< XSPI3 reset */
#define RCC_AHB5RSTR_GFXMMURST_Pos (19U)
#define RCC_AHB5RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB5RSTR_GFXMMURST_Pos) /*!< 0x00080000 */
#define RCC_AHB5RSTR_GFXMMURST RCC_AHB5RSTR_GFXMMURST_Msk /*!< GFXMMU reset */
#define RCC_AHB5RSTR_GPU2DRST_Pos (20U)
#define RCC_AHB5RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB5RSTR_GPU2DRST_Pos) /*!< 0x00100000 */
#define RCC_AHB5RSTR_GPU2DRST RCC_AHB5RSTR_GPU2DRST_Msk /*!< GPU2D reset */
#define RCC_AHB5RSTR_OTG1PHYCTLRST_Pos (23U)
#define RCC_AHB5RSTR_OTG1PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG1PHYCTLRST_Pos) /*!< 0x00800000 */
#define RCC_AHB5RSTR_OTG1PHYCTLRST RCC_AHB5RSTR_OTG1PHYCTLRST_Msk /*!< OTG1PHYCTL reset */
#define RCC_AHB5RSTR_OTG2PHYCTLRST_Pos (24U)
#define RCC_AHB5RSTR_OTG2PHYCTLRST_Msk (0x1UL << RCC_AHB5RSTR_OTG2PHYCTLRST_Pos) /*!< 0x01000000 */
#define RCC_AHB5RSTR_OTG2PHYCTLRST RCC_AHB5RSTR_OTG2PHYCTLRST_Msk /*!< OTG2PHYCTL reset */
#define RCC_AHB5RSTR_ETH1RST_Pos (25U)
#define RCC_AHB5RSTR_ETH1RST_Msk (0x1UL << RCC_AHB5RSTR_ETH1RST_Pos) /*!< 0x02000000 */
#define RCC_AHB5RSTR_ETH1RST RCC_AHB5RSTR_ETH1RST_Msk /*!< ETH1 reset */
#define RCC_AHB5RSTR_OTG1RST_Pos (26U)
#define RCC_AHB5RSTR_OTG1RST_Msk (0x1UL << RCC_AHB5RSTR_OTG1RST_Pos) /*!< 0x04000000 */
#define RCC_AHB5RSTR_OTG1RST RCC_AHB5RSTR_OTG1RST_Msk /*!< OTG1 reset */
#define RCC_AHB5RSTR_OTGPHY1RST_Pos (27U)
#define RCC_AHB5RSTR_OTGPHY1RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY1RST_Pos)/*!< 0x08000000 */
#define RCC_AHB5RSTR_OTGPHY1RST RCC_AHB5RSTR_OTGPHY1RST_Msk /*!< OTGPHY1 reset */
#define RCC_AHB5RSTR_OTGPHY2RST_Pos (28U)
#define RCC_AHB5RSTR_OTGPHY2RST_Msk (0x1UL << RCC_AHB5RSTR_OTGPHY2RST_Pos)/*!< 0x10000000 */
#define RCC_AHB5RSTR_OTGPHY2RST RCC_AHB5RSTR_OTGPHY2RST_Msk /*!< OTGPHY2 reset */
#define RCC_AHB5RSTR_OTG2RST_Pos (29U)
#define RCC_AHB5RSTR_OTG2RST_Msk (0x1UL << RCC_AHB5RSTR_OTG2RST_Pos) /*!< 0x20000000 */
#define RCC_AHB5RSTR_OTG2RST RCC_AHB5RSTR_OTG2RST_Msk /*!< OTG2 reset */
#define RCC_AHB5RSTR_CACHEAXIRST_Pos (30U)
#define RCC_AHB5RSTR_CACHEAXIRST_Msk (0x1UL << RCC_AHB5RSTR_CACHEAXIRST_Pos) /*!< 0x40000000 */
#define RCC_AHB5RSTR_CACHEAXIRST RCC_AHB5RSTR_CACHEAXIRST_Msk /*!< CACHEAXI reset */
#define RCC_AHB5RSTR_NPURST_Pos (31U)
#define RCC_AHB5RSTR_NPURST_Msk (0x1UL << RCC_AHB5RSTR_NPURST_Pos) /*!< 0x80000000 */
#define RCC_AHB5RSTR_NPURST RCC_AHB5RSTR_NPURST_Msk /*!< NPU reset */
/**************** Bit definition for RCC_APB1RSTR1 register *****************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) /*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk /*!< TIM2 reset */
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) /*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk /*!< TIM3 reset */
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) /*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk /*!< TIM4 reset */
#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) /*!< 0x00000008 */
#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk /*!< TIM5 reset */
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) /*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk /*!< TIM6 reset */
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) /*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk /*!< TIM7 reset */
#define RCC_APB1RSTR1_TIM12RST_Pos (6U)
#define RCC_APB1RSTR1_TIM12RST_Msk (0x1UL << RCC_APB1RSTR1_TIM12RST_Pos) /*!< 0x00000040 */
#define RCC_APB1RSTR1_TIM12RST RCC_APB1RSTR1_TIM12RST_Msk /*!< TIM12 reset */
#define RCC_APB1RSTR1_TIM13RST_Pos (7U)
#define RCC_APB1RSTR1_TIM13RST_Msk (0x1UL << RCC_APB1RSTR1_TIM13RST_Pos) /*!< 0x00000080 */
#define RCC_APB1RSTR1_TIM13RST RCC_APB1RSTR1_TIM13RST_Msk /*!< TIM13 reset */
#define RCC_APB1RSTR1_TIM14RST_Pos (8U)
#define RCC_APB1RSTR1_TIM14RST_Msk (0x1UL << RCC_APB1RSTR1_TIM14RST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR1_TIM14RST RCC_APB1RSTR1_TIM14RST_Msk /*!< TIM14 reset */
#define RCC_APB1RSTR1_LPTIM1RST_Pos (9U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x00000200 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk /*!< LPTIM1 reset */
#define RCC_APB1RSTR1_WWDGRST_Pos (11U)
#define RCC_APB1RSTR1_WWDGRST_Msk (0x1UL << RCC_APB1RSTR1_WWDGRST_Pos) /*!< 0x00000800 */
#define RCC_APB1RSTR1_WWDGRST RCC_APB1RSTR1_WWDGRST_Msk /*!< WWDG reset */
#define RCC_APB1RSTR1_TIM10RST_Pos (12U)
#define RCC_APB1RSTR1_TIM10RST_Msk (0x1UL << RCC_APB1RSTR1_TIM10RST_Pos) /*!< 0x00001000 */
#define RCC_APB1RSTR1_TIM10RST RCC_APB1RSTR1_TIM10RST_Msk /*!< TIM10 reset */
#define RCC_APB1RSTR1_TIM11RST_Pos (13U)
#define RCC_APB1RSTR1_TIM11RST_Msk (0x1UL << RCC_APB1RSTR1_TIM11RST_Pos) /*!< 0x00002000 */
#define RCC_APB1RSTR1_TIM11RST RCC_APB1RSTR1_TIM11RST_Msk /*!< TIM11 reset */
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) /*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk /*!< SPI2 reset */
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos) /*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk /*!< SPI3 reset */
#define RCC_APB1RSTR1_SPDIFRX1RST_Pos (16U)
#define RCC_APB1RSTR1_SPDIFRX1RST_Msk (0x1UL << RCC_APB1RSTR1_SPDIFRX1RST_Pos) /*!< 0x00010000 */
#define RCC_APB1RSTR1_SPDIFRX1RST RCC_APB1RSTR1_SPDIFRX1RST_Msk /*!< SPDIFRX1 reset */
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk /*!< USART2 reset */
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk /*!< USART3 reset */
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) /*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk /*!< UART4 reset */
#define RCC_APB1RSTR1_UART5RST_Pos (20U)
#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) /*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk /*!< UART5 reset */
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) /*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk /*!< I2C1 reset */
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) /*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk /*!< I2C2 reset */
#define RCC_APB1RSTR1_I2C3RST_Pos (23U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos) /*!< 0x00800000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk /*!< I2C3 reset */
#define RCC_APB1RSTR1_I3C1RST_Pos (24U)
#define RCC_APB1RSTR1_I3C1RST_Msk (0x1UL << RCC_APB1RSTR1_I3C1RST_Pos) /*!< 0x01000000 */
#define RCC_APB1RSTR1_I3C1RST RCC_APB1RSTR1_I3C1RST_Msk /*!< I3C1 reset */
#define RCC_APB1RSTR1_I3C2RST_Pos (25U)
#define RCC_APB1RSTR1_I3C2RST_Msk (0x1UL << RCC_APB1RSTR1_I3C2RST_Pos) /*!< 0x02000000 */
#define RCC_APB1RSTR1_I3C2RST RCC_APB1RSTR1_I3C2RST_Msk /*!< I3C2 reset */
#define RCC_APB1RSTR1_UART7RST_Pos (30U)
#define RCC_APB1RSTR1_UART7RST_Msk (0x1UL << RCC_APB1RSTR1_UART7RST_Pos) /*!< 0x40000000 */
#define RCC_APB1RSTR1_UART7RST RCC_APB1RSTR1_UART7RST_Msk /*!< UART7 reset */
#define RCC_APB1RSTR1_UART8RST_Pos (31U)
#define RCC_APB1RSTR1_UART8RST_Msk (0x1UL << RCC_APB1RSTR1_UART8RST_Pos) /*!< 0x80000000 */
#define RCC_APB1RSTR1_UART8RST RCC_APB1RSTR1_UART8RST_Msk /*!< UART8 reset */
/**************** Bit definition for RCC_APB1RSTR2 register *****************/
#define RCC_APB1RSTR2_MDIOSRST_Pos (5U)
#define RCC_APB1RSTR2_MDIOSRST_Msk (0x1UL << RCC_APB1RSTR2_MDIOSRST_Pos) /*!< 0x00000020 */
#define RCC_APB1RSTR2_MDIOSRST RCC_APB1RSTR2_MDIOSRST_Msk /*!< MDIOS reset */
#define RCC_APB1RSTR2_FDCANRST_Pos (8U)
#define RCC_APB1RSTR2_FDCANRST_Msk (0x1UL << RCC_APB1RSTR2_FDCANRST_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTR2_FDCANRST RCC_APB1RSTR2_FDCANRST_Msk /*!< FDCAN reset */
#define RCC_APB1RSTR2_UCPD1RST_Pos (18U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk /*!< UCPD1 reset */
/***************** Bit definition for RCC_APB2RSTR register *****************/
#define RCC_APB2RSTR_TIM1RST_Pos (0U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
#define RCC_APB2RSTR_TIM8RST_Pos (1U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk /*!< TIM8 reset */
#define RCC_APB2RSTR_USART1RST_Pos (4U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
#define RCC_APB2RSTR_USART6RST_Pos (5U)
#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk /*!< USART6 reset */
#define RCC_APB2RSTR_UART9RST_Pos (6U)
#define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
#define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk /*!< UART9 reset */
#define RCC_APB2RSTR_USART10RST_Pos (7U)
#define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos)/*!< 0x00000080 */
#define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk /*!< USART10 reset */
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
#define RCC_APB2RSTR_SPI4RST_Pos (13U)
#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk /*!< SPI4 reset */
#define RCC_APB2RSTR_TIM18RST_Pos (15U)
#define RCC_APB2RSTR_TIM18RST_Msk (0x1UL << RCC_APB2RSTR_TIM18RST_Pos) /*!< 0x00008000 */
#define RCC_APB2RSTR_TIM18RST RCC_APB2RSTR_TIM18RST_Msk /*!< TIM18 reset */
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk /*!< TIM15 reset */
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
#define RCC_APB2RSTR_TIM9RST_Pos (19U)
#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00080000 */
#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */
#define RCC_APB2RSTR_SPI5RST_Pos (20U)
#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk /*!< SPI5 reset */
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk /*!< SAI1 reset */
#define RCC_APB2RSTR_SAI2RST_Pos (22U)
#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk /*!< SAI2 reset */
/**************** Bit definition for RCC_APB4RSTR1 register *****************/
#define RCC_APB4RSTR1_HDPRST_Pos (2U)
#define RCC_APB4RSTR1_HDPRST_Msk (0x1UL << RCC_APB4RSTR1_HDPRST_Pos) /*!< 0x00000004 */
#define RCC_APB4RSTR1_HDPRST RCC_APB4RSTR1_HDPRST_Msk /*!< HDP reset */
#define RCC_APB4RSTR1_LPUART1RST_Pos (3U)
#define RCC_APB4RSTR1_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR1_LPUART1RST_Pos) /*!< 0x00000008 */
#define RCC_APB4RSTR1_LPUART1RST RCC_APB4RSTR1_LPUART1RST_Msk /*!< LPUART1 reset */
#define RCC_APB4RSTR1_SPI6RST_Pos (5U)
#define RCC_APB4RSTR1_SPI6RST_Msk (0x1UL << RCC_APB4RSTR1_SPI6RST_Pos) /*!< 0x00000020 */
#define RCC_APB4RSTR1_SPI6RST RCC_APB4RSTR1_SPI6RST_Msk /*!< SPI6 reset */
#define RCC_APB4RSTR1_I2C4RST_Pos (7U)
#define RCC_APB4RSTR1_I2C4RST_Msk (0x1UL << RCC_APB4RSTR1_I2C4RST_Pos) /*!< 0x00000080 */
#define RCC_APB4RSTR1_I2C4RST RCC_APB4RSTR1_I2C4RST_Msk /*!< I2C4 reset */
#define RCC_APB4RSTR1_LPTIM2RST_Pos (9U)
#define RCC_APB4RSTR1_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM2RST_Pos)/*!< 0x00000200 */
#define RCC_APB4RSTR1_LPTIM2RST RCC_APB4RSTR1_LPTIM2RST_Msk /*!< LPTIM2 reset */
#define RCC_APB4RSTR1_LPTIM3RST_Pos (10U)
#define RCC_APB4RSTR1_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM3RST_Pos)/*!< 0x00000400 */
#define RCC_APB4RSTR1_LPTIM3RST RCC_APB4RSTR1_LPTIM3RST_Msk /*!< LPTIM3 reset */
#define RCC_APB4RSTR1_LPTIM4RST_Pos (11U)
#define RCC_APB4RSTR1_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM4RST_Pos)/*!< 0x00000800 */
#define RCC_APB4RSTR1_LPTIM4RST RCC_APB4RSTR1_LPTIM4RST_Msk /*!< LPTIM4 reset */
#define RCC_APB4RSTR1_LPTIM5RST_Pos (12U)
#define RCC_APB4RSTR1_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR1_LPTIM5RST_Pos)/*!< 0x00001000 */
#define RCC_APB4RSTR1_LPTIM5RST RCC_APB4RSTR1_LPTIM5RST_Msk /*!< LPTIM5 reset */
#define RCC_APB4RSTR1_VREFBUFRST_Pos (15U)
#define RCC_APB4RSTR1_VREFBUFRST_Msk (0x1UL << RCC_APB4RSTR1_VREFBUFRST_Pos) /*!< 0x00008000 */
#define RCC_APB4RSTR1_VREFBUFRST RCC_APB4RSTR1_VREFBUFRST_Msk /*!< VREFBUF reset */
#define RCC_APB4RSTR1_RTCRST_Pos (16U)
#define RCC_APB4RSTR1_RTCRST_Msk (0x1UL << RCC_APB4RSTR1_RTCRST_Pos) /*!< 0x00010000 */
#define RCC_APB4RSTR1_RTCRST RCC_APB4RSTR1_RTCRST_Msk /*!< RTC reset */
/**************** Bit definition for RCC_APB4RSTR2 register *****************/
#define RCC_APB4RSTR2_SYSCFGRST_Pos (0U)
#define RCC_APB4RSTR2_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR2_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB4RSTR2_SYSCFGRST RCC_APB4RSTR2_SYSCFGRST_Msk /*!< SYSCFG reset */
#define RCC_APB4RSTR2_DTSRST_Pos (2U)
#define RCC_APB4RSTR2_DTSRST_Msk (0x1UL << RCC_APB4RSTR2_DTSRST_Pos) /*!< 0x00000004 */
#define RCC_APB4RSTR2_DTSRST RCC_APB4RSTR2_DTSRST_Msk /*!< DTS reset */
/***************** Bit definition for RCC_APB5RSTR register *****************/
#define RCC_APB5RSTR_LTDCRST_Pos (1U)
#define RCC_APB5RSTR_LTDCRST_Msk (0x1UL << RCC_APB5RSTR_LTDCRST_Pos) /*!< 0x00000002 */
#define RCC_APB5RSTR_LTDCRST RCC_APB5RSTR_LTDCRST_Msk /*!< LTDC reset */
#define RCC_APB5RSTR_DCMIPPRST_Pos (2U)
#define RCC_APB5RSTR_DCMIPPRST_Msk (0x1UL << RCC_APB5RSTR_DCMIPPRST_Pos) /*!< 0x00000004 */
#define RCC_APB5RSTR_DCMIPPRST RCC_APB5RSTR_DCMIPPRST_Msk /*!< DCMIPP reset */
#define RCC_APB5RSTR_GFXTIMRST_Pos (4U)
#define RCC_APB5RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB5RSTR_GFXTIMRST_Pos) /*!< 0x00000010 */
#define RCC_APB5RSTR_GFXTIMRST RCC_APB5RSTR_GFXTIMRST_Msk /*!< GFXTIM reset */
#define RCC_APB5RSTR_VENCRST_Pos (5U)
#define RCC_APB5RSTR_VENCRST_Msk (0x1UL << RCC_APB5RSTR_VENCRST_Pos) /*!< 0x00000020 */
#define RCC_APB5RSTR_VENCRST RCC_APB5RSTR_VENCRST_Msk /*!< VENC reset */
#define RCC_APB5RSTR_CSIRST_Pos (6U)
#define RCC_APB5RSTR_CSIRST_Msk (0x1UL << RCC_APB5RSTR_CSIRST_Pos) /*!< 0x00000040 */
#define RCC_APB5RSTR_CSIRST RCC_APB5RSTR_CSIRST_Msk /*!< CSI reset */
/****************** Bit definition for RCC_DIVENR register ******************/
#define RCC_DIVENR_IC1EN_Pos (0U)
#define RCC_DIVENR_IC1EN_Msk (0x1UL << RCC_DIVENR_IC1EN_Pos) /*!< 0x00000001 */
#define RCC_DIVENR_IC1EN RCC_DIVENR_IC1EN_Msk /*!< IC1 enable */
#define RCC_DIVENR_IC2EN_Pos (1U)
#define RCC_DIVENR_IC2EN_Msk (0x1UL << RCC_DIVENR_IC2EN_Pos) /*!< 0x00000002 */
#define RCC_DIVENR_IC2EN RCC_DIVENR_IC2EN_Msk /*!< IC2 enable */
#define RCC_DIVENR_IC3EN_Pos (2U)
#define RCC_DIVENR_IC3EN_Msk (0x1UL << RCC_DIVENR_IC3EN_Pos) /*!< 0x00000004 */
#define RCC_DIVENR_IC3EN RCC_DIVENR_IC3EN_Msk /*!< IC3 enable */
#define RCC_DIVENR_IC4EN_Pos (3U)
#define RCC_DIVENR_IC4EN_Msk (0x1UL << RCC_DIVENR_IC4EN_Pos) /*!< 0x00000008 */
#define RCC_DIVENR_IC4EN RCC_DIVENR_IC4EN_Msk /*!< IC4 enable */
#define RCC_DIVENR_IC5EN_Pos (4U)
#define RCC_DIVENR_IC5EN_Msk (0x1UL << RCC_DIVENR_IC5EN_Pos) /*!< 0x00000010 */
#define RCC_DIVENR_IC5EN RCC_DIVENR_IC5EN_Msk /*!< IC5 enable */
#define RCC_DIVENR_IC6EN_Pos (5U)
#define RCC_DIVENR_IC6EN_Msk (0x1UL << RCC_DIVENR_IC6EN_Pos) /*!< 0x00000020 */
#define RCC_DIVENR_IC6EN RCC_DIVENR_IC6EN_Msk /*!< IC6 enable */
#define RCC_DIVENR_IC7EN_Pos (6U)
#define RCC_DIVENR_IC7EN_Msk (0x1UL << RCC_DIVENR_IC7EN_Pos) /*!< 0x00000040 */
#define RCC_DIVENR_IC7EN RCC_DIVENR_IC7EN_Msk /*!< IC7 enable */
#define RCC_DIVENR_IC8EN_Pos (7U)
#define RCC_DIVENR_IC8EN_Msk (0x1UL << RCC_DIVENR_IC8EN_Pos) /*!< 0x00000080 */
#define RCC_DIVENR_IC8EN RCC_DIVENR_IC8EN_Msk /*!< IC8 enable */
#define RCC_DIVENR_IC9EN_Pos (8U)
#define RCC_DIVENR_IC9EN_Msk (0x1UL << RCC_DIVENR_IC9EN_Pos) /*!< 0x00000100 */
#define RCC_DIVENR_IC9EN RCC_DIVENR_IC9EN_Msk /*!< IC9 enable */
#define RCC_DIVENR_IC10EN_Pos (9U)
#define RCC_DIVENR_IC10EN_Msk (0x1UL << RCC_DIVENR_IC10EN_Pos) /*!< 0x00000200 */
#define RCC_DIVENR_IC10EN RCC_DIVENR_IC10EN_Msk /*!< IC10 enable */
#define RCC_DIVENR_IC11EN_Pos (10U)
#define RCC_DIVENR_IC11EN_Msk (0x1UL << RCC_DIVENR_IC11EN_Pos) /*!< 0x00000400 */
#define RCC_DIVENR_IC11EN RCC_DIVENR_IC11EN_Msk /*!< IC11 enable */
#define RCC_DIVENR_IC12EN_Pos (11U)
#define RCC_DIVENR_IC12EN_Msk (0x1UL << RCC_DIVENR_IC12EN_Pos) /*!< 0x00000800 */
#define RCC_DIVENR_IC12EN RCC_DIVENR_IC12EN_Msk /*!< IC12 enable */
#define RCC_DIVENR_IC13EN_Pos (12U)
#define RCC_DIVENR_IC13EN_Msk (0x1UL << RCC_DIVENR_IC13EN_Pos) /*!< 0x00001000 */
#define RCC_DIVENR_IC13EN RCC_DIVENR_IC13EN_Msk /*!< IC13 enable */
#define RCC_DIVENR_IC14EN_Pos (13U)
#define RCC_DIVENR_IC14EN_Msk (0x1UL << RCC_DIVENR_IC14EN_Pos) /*!< 0x00002000 */
#define RCC_DIVENR_IC14EN RCC_DIVENR_IC14EN_Msk /*!< IC14 enable */
#define RCC_DIVENR_IC15EN_Pos (14U)
#define RCC_DIVENR_IC15EN_Msk (0x1UL << RCC_DIVENR_IC15EN_Pos) /*!< 0x00004000 */
#define RCC_DIVENR_IC15EN RCC_DIVENR_IC15EN_Msk /*!< IC15 enable */
#define RCC_DIVENR_IC16EN_Pos (15U)
#define RCC_DIVENR_IC16EN_Msk (0x1UL << RCC_DIVENR_IC16EN_Pos) /*!< 0x00008000 */
#define RCC_DIVENR_IC16EN RCC_DIVENR_IC16EN_Msk /*!< IC16 enable */
#define RCC_DIVENR_IC17EN_Pos (16U)
#define RCC_DIVENR_IC17EN_Msk (0x1UL << RCC_DIVENR_IC17EN_Pos) /*!< 0x00010000 */
#define RCC_DIVENR_IC17EN RCC_DIVENR_IC17EN_Msk /*!< IC17 enable */
#define RCC_DIVENR_IC18EN_Pos (17U)
#define RCC_DIVENR_IC18EN_Msk (0x1UL << RCC_DIVENR_IC18EN_Pos) /*!< 0x00020000 */
#define RCC_DIVENR_IC18EN RCC_DIVENR_IC18EN_Msk /*!< IC18 enable */
#define RCC_DIVENR_IC19EN_Pos (18U)
#define RCC_DIVENR_IC19EN_Msk (0x1UL << RCC_DIVENR_IC19EN_Pos) /*!< 0x00040000 */
#define RCC_DIVENR_IC19EN RCC_DIVENR_IC19EN_Msk /*!< IC19 enable */
#define RCC_DIVENR_IC20EN_Pos (19U)
#define RCC_DIVENR_IC20EN_Msk (0x1UL << RCC_DIVENR_IC20EN_Pos) /*!< 0x00080000 */
#define RCC_DIVENR_IC20EN RCC_DIVENR_IC20EN_Msk /*!< IC20 enable */
/****************** Bit definition for RCC_BUSENR register ******************/
#define RCC_BUSENR_ACLKNEN_Pos (0U)
#define RCC_BUSENR_ACLKNEN_Msk (0x1UL << RCC_BUSENR_ACLKNEN_Pos) /*!< 0x00000001 */
#define RCC_BUSENR_ACLKNEN RCC_BUSENR_ACLKNEN_Msk /*!< ACLKN enable */
#define RCC_BUSENR_ACLKNCEN_Pos (1U)
#define RCC_BUSENR_ACLKNCEN_Msk (0x1UL << RCC_BUSENR_ACLKNCEN_Pos) /*!< 0x00000002 */
#define RCC_BUSENR_ACLKNCEN RCC_BUSENR_ACLKNCEN_Msk /*!< ACLKNC enable */
#define RCC_BUSENR_AHBMEN_Pos (2U)
#define RCC_BUSENR_AHBMEN_Msk (0x1UL << RCC_BUSENR_AHBMEN_Pos) /*!< 0x00000004 */
#define RCC_BUSENR_AHBMEN RCC_BUSENR_AHBMEN_Msk /*!< AHBM enable */
#define RCC_BUSENR_AHB1EN_Pos (3U)
#define RCC_BUSENR_AHB1EN_Msk (0x1UL << RCC_BUSENR_AHB1EN_Pos) /*!< 0x00000008 */
#define RCC_BUSENR_AHB1EN RCC_BUSENR_AHB1EN_Msk /*!< AHB1 enable */
#define RCC_BUSENR_AHB2EN_Pos (4U)
#define RCC_BUSENR_AHB2EN_Msk (0x1UL << RCC_BUSENR_AHB2EN_Pos) /*!< 0x00000010 */
#define RCC_BUSENR_AHB2EN RCC_BUSENR_AHB2EN_Msk /*!< AHB2 enable */
#define RCC_BUSENR_AHB3EN_Pos (5U)
#define RCC_BUSENR_AHB3EN_Msk (0x1UL << RCC_BUSENR_AHB3EN_Pos) /*!< 0x00000020 */
#define RCC_BUSENR_AHB3EN RCC_BUSENR_AHB3EN_Msk /*!< AHB3 enable */
#define RCC_BUSENR_AHB4EN_Pos (6U)
#define RCC_BUSENR_AHB4EN_Msk (0x1UL << RCC_BUSENR_AHB4EN_Pos) /*!< 0x00000040 */
#define RCC_BUSENR_AHB4EN RCC_BUSENR_AHB4EN_Msk /*!< AHB4 enable */
#define RCC_BUSENR_AHB5EN_Pos (7U)
#define RCC_BUSENR_AHB5EN_Msk (0x1UL << RCC_BUSENR_AHB5EN_Pos) /*!< 0x00000080 */
#define RCC_BUSENR_AHB5EN RCC_BUSENR_AHB5EN_Msk /*!< AHB5 enable */
#define RCC_BUSENR_APB1EN_Pos (8U)
#define RCC_BUSENR_APB1EN_Msk (0x1UL << RCC_BUSENR_APB1EN_Pos) /*!< 0x00000100 */
#define RCC_BUSENR_APB1EN RCC_BUSENR_APB1EN_Msk /*!< APB1 enable */
#define RCC_BUSENR_APB2EN_Pos (9U)
#define RCC_BUSENR_APB2EN_Msk (0x1UL << RCC_BUSENR_APB2EN_Pos) /*!< 0x00000200 */
#define RCC_BUSENR_APB2EN RCC_BUSENR_APB2EN_Msk /*!< APB2 enable */
#define RCC_BUSENR_APB3EN_Pos (10U)
#define RCC_BUSENR_APB3EN_Msk (0x1UL << RCC_BUSENR_APB3EN_Pos) /*!< 0x00000400 */
#define RCC_BUSENR_APB3EN RCC_BUSENR_APB3EN_Msk /*!< APB3 enable */
#define RCC_BUSENR_APB4EN_Pos (11U)
#define RCC_BUSENR_APB4EN_Msk (0x1UL << RCC_BUSENR_APB4EN_Pos) /*!< 0x00000800 */
#define RCC_BUSENR_APB4EN RCC_BUSENR_APB4EN_Msk /*!< APB4 enable */
#define RCC_BUSENR_APB5EN_Pos (12U)
#define RCC_BUSENR_APB5EN_Msk (0x1UL << RCC_BUSENR_APB5EN_Pos) /*!< 0x00001000 */
#define RCC_BUSENR_APB5EN RCC_BUSENR_APB5EN_Msk /*!< APB5 enable */
/***************** Bit definition for RCC_MISCENR register ******************/
#define RCC_MISCENR_DBGEN_Pos (0U)
#define RCC_MISCENR_DBGEN_Msk (0x1UL << RCC_MISCENR_DBGEN_Pos) /*!< 0x00000001 */
#define RCC_MISCENR_DBGEN RCC_MISCENR_DBGEN_Msk /*!< DBG enable */
#define RCC_MISCENR_MCO1EN_Pos (1U)
#define RCC_MISCENR_MCO1EN_Msk (0x1UL << RCC_MISCENR_MCO1EN_Pos) /*!< 0x00000002 */
#define RCC_MISCENR_MCO1EN RCC_MISCENR_MCO1EN_Msk /*!< MCO1 enable */
#define RCC_MISCENR_MCO2EN_Pos (2U)
#define RCC_MISCENR_MCO2EN_Msk (0x1UL << RCC_MISCENR_MCO2EN_Pos) /*!< 0x00000004 */
#define RCC_MISCENR_MCO2EN RCC_MISCENR_MCO2EN_Msk /*!< MCO2 enable */
#define RCC_MISCENR_XSPIPHYCOMPEN_Pos (3U)
#define RCC_MISCENR_XSPIPHYCOMPEN_Msk (0x1UL << RCC_MISCENR_XSPIPHYCOMPEN_Pos) /*!< 0x00000008 */
#define RCC_MISCENR_XSPIPHYCOMPEN RCC_MISCENR_XSPIPHYCOMPEN_Msk /*!< XSPIPHYCOMP enable */
#define RCC_MISCENR_PEREN_Pos (6U)
#define RCC_MISCENR_PEREN_Msk (0x1UL << RCC_MISCENR_PEREN_Pos) /*!< 0x00000040 */
#define RCC_MISCENR_PEREN RCC_MISCENR_PEREN_Msk /*!< PER enable */
/****************** Bit definition for RCC_MEMENR register ******************/
#define RCC_MEMENR_AXISRAM3EN_Pos (0U)
#define RCC_MEMENR_AXISRAM3EN_Msk (0x1UL << RCC_MEMENR_AXISRAM3EN_Pos) /*!< 0x00000001 */
#define RCC_MEMENR_AXISRAM3EN RCC_MEMENR_AXISRAM3EN_Msk /*!< AXISRAM3 enable */
#define RCC_MEMENR_AXISRAM4EN_Pos (1U)
#define RCC_MEMENR_AXISRAM4EN_Msk (0x1UL << RCC_MEMENR_AXISRAM4EN_Pos) /*!< 0x00000002 */
#define RCC_MEMENR_AXISRAM4EN RCC_MEMENR_AXISRAM4EN_Msk /*!< AXISRAM4 enable */
#define RCC_MEMENR_AXISRAM5EN_Pos (2U)
#define RCC_MEMENR_AXISRAM5EN_Msk (0x1UL << RCC_MEMENR_AXISRAM5EN_Pos) /*!< 0x00000004 */
#define RCC_MEMENR_AXISRAM5EN RCC_MEMENR_AXISRAM5EN_Msk /*!< AXISRAM5 enable */
#define RCC_MEMENR_AXISRAM6EN_Pos (3U)
#define RCC_MEMENR_AXISRAM6EN_Msk (0x1UL << RCC_MEMENR_AXISRAM6EN_Pos) /*!< 0x00000008 */
#define RCC_MEMENR_AXISRAM6EN RCC_MEMENR_AXISRAM6EN_Msk /*!< AXISRAM6 enable */
#define RCC_MEMENR_AHBSRAM1EN_Pos (4U)
#define RCC_MEMENR_AHBSRAM1EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM1EN_Pos) /*!< 0x00000010 */
#define RCC_MEMENR_AHBSRAM1EN RCC_MEMENR_AHBSRAM1EN_Msk /*!< AHBSRAM1 enable */
#define RCC_MEMENR_AHBSRAM2EN_Pos (5U)
#define RCC_MEMENR_AHBSRAM2EN_Msk (0x1UL << RCC_MEMENR_AHBSRAM2EN_Pos) /*!< 0x00000020 */
#define RCC_MEMENR_AHBSRAM2EN RCC_MEMENR_AHBSRAM2EN_Msk /*!< AHBSRAM2 enable */
#define RCC_MEMENR_BKPSRAMEN_Pos (6U)
#define RCC_MEMENR_BKPSRAMEN_Msk (0x1UL << RCC_MEMENR_BKPSRAMEN_Pos) /*!< 0x00000040 */
#define RCC_MEMENR_BKPSRAMEN RCC_MEMENR_BKPSRAMEN_Msk /*!< BKPSRAM enable */
#define RCC_MEMENR_AXISRAM1EN_Pos (7U)
#define RCC_MEMENR_AXISRAM1EN_Msk (0x1UL << RCC_MEMENR_AXISRAM1EN_Pos) /*!< 0x00000080 */
#define RCC_MEMENR_AXISRAM1EN RCC_MEMENR_AXISRAM1EN_Msk /*!< AXISRAM1 enable */
#define RCC_MEMENR_AXISRAM2EN_Pos (8U)
#define RCC_MEMENR_AXISRAM2EN_Msk (0x1UL << RCC_MEMENR_AXISRAM2EN_Pos) /*!< 0x00000100 */
#define RCC_MEMENR_AXISRAM2EN RCC_MEMENR_AXISRAM2EN_Msk /*!< AXISRAM2 enable */
#define RCC_MEMENR_FLEXRAMEN_Pos (9U)
#define RCC_MEMENR_FLEXRAMEN_Msk (0x1UL << RCC_MEMENR_FLEXRAMEN_Pos) /*!< 0x00000200 */
#define RCC_MEMENR_FLEXRAMEN RCC_MEMENR_FLEXRAMEN_Msk /*!< FLEXRAM enable */
#define RCC_MEMENR_CACHEAXIRAMEN_Pos (10U)
#define RCC_MEMENR_CACHEAXIRAMEN_Msk (0x1UL << RCC_MEMENR_CACHEAXIRAMEN_Pos) /*!< 0x00000400 */
#define RCC_MEMENR_CACHEAXIRAMEN RCC_MEMENR_CACHEAXIRAMEN_Msk /*!< CACHEAXIRAM enable */
#define RCC_MEMENR_VENCRAMEN_Pos (11U)
#define RCC_MEMENR_VENCRAMEN_Msk (0x1UL << RCC_MEMENR_VENCRAMEN_Pos) /*!< 0x00000800 */
#define RCC_MEMENR_VENCRAMEN RCC_MEMENR_VENCRAMEN_Msk /*!< VENCRAM enable */
#define RCC_MEMENR_BOOTROMEN_Pos (12U)
#define RCC_MEMENR_BOOTROMEN_Msk (0x1UL << RCC_MEMENR_BOOTROMEN_Pos) /*!< 0x00001000 */
#define RCC_MEMENR_BOOTROMEN RCC_MEMENR_BOOTROMEN_Msk /*!< Boot ROM enable */
/***************** Bit definition for RCC_AHB1ENR register ******************/
#define RCC_AHB1ENR_GPDMA1EN_Pos (4U)
#define RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk /*!< GPDMA1 enable */
#define RCC_AHB1ENR_ADC12EN_Pos (5U)
#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk /*!< ADC12 enable */
/***************** Bit definition for RCC_AHB2ENR register ******************/
#define RCC_AHB2ENR_RAMCFGEN_Pos (12U)
#define RCC_AHB2ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB2ENR_RAMCFGEN_Pos) /*!< 0x00001000 */
#define RCC_AHB2ENR_RAMCFGEN RCC_AHB2ENR_RAMCFGEN_Msk /*!< RAMCFG enable */
#define RCC_AHB2ENR_MDF1EN_Pos (16U)
#define RCC_AHB2ENR_MDF1EN_Msk (0x1UL << RCC_AHB2ENR_MDF1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_MDF1EN RCC_AHB2ENR_MDF1EN_Msk /*!< MDF1 enable */
#define RCC_AHB2ENR_ADF1EN_Pos (17U)
#define RCC_AHB2ENR_ADF1EN_Msk (0x1UL << RCC_AHB2ENR_ADF1EN_Pos) /*!< 0x00020000 */
#define RCC_AHB2ENR_ADF1EN RCC_AHB2ENR_ADF1EN_Msk /*!< ADF1 enable */
/***************** Bit definition for RCC_AHB3ENR register ******************/
#define RCC_AHB3ENR_RNGEN_Pos (0U)
#define RCC_AHB3ENR_RNGEN_Msk (0x1UL << RCC_AHB3ENR_RNGEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENR_RNGEN RCC_AHB3ENR_RNGEN_Msk /*!< RNG enable */
#define RCC_AHB3ENR_HASHEN_Pos (1U)
#define RCC_AHB3ENR_HASHEN_Msk (0x1UL << RCC_AHB3ENR_HASHEN_Pos) /*!< 0x00000002 */
#define RCC_AHB3ENR_HASHEN RCC_AHB3ENR_HASHEN_Msk /*!< HASH enable */
#define RCC_AHB3ENR_CRYPEN_Pos (2U)
#define RCC_AHB3ENR_CRYPEN_Msk (0x1UL << RCC_AHB3ENR_CRYPEN_Pos) /*!< 0x00000004 */
#define RCC_AHB3ENR_CRYPEN RCC_AHB3ENR_CRYPEN_Msk /*!< CRYP enable */
#define RCC_AHB3ENR_SAESEN_Pos (4U)
#define RCC_AHB3ENR_SAESEN_Msk (0x1UL << RCC_AHB3ENR_SAESEN_Pos) /*!< 0x00000010 */
#define RCC_AHB3ENR_SAESEN RCC_AHB3ENR_SAESEN_Msk /*!< SAES enable */
#define RCC_AHB3ENR_PKAEN_Pos (8U)
#define RCC_AHB3ENR_PKAEN_Msk (0x1UL << RCC_AHB3ENR_PKAEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_PKAEN RCC_AHB3ENR_PKAEN_Msk /*!< PKA enable */
#define RCC_AHB3ENR_RIFSCEN_Pos (9U)
#define RCC_AHB3ENR_RIFSCEN_Msk (0x1UL << RCC_AHB3ENR_RIFSCEN_Pos) /*!< 0x00000200 */
#define RCC_AHB3ENR_RIFSCEN RCC_AHB3ENR_RIFSCEN_Msk /*!< RIFSC enable */
#define RCC_AHB3ENR_IACEN_Pos (10U)
#define RCC_AHB3ENR_IACEN_Msk (0x1UL << RCC_AHB3ENR_IACEN_Pos) /*!< 0x00000400 */
#define RCC_AHB3ENR_IACEN RCC_AHB3ENR_IACEN_Msk /*!< IAC enable */
#define RCC_AHB3ENR_RISAFEN_Pos (14U)
#define RCC_AHB3ENR_RISAFEN_Msk (0x1UL << RCC_AHB3ENR_RISAFEN_Pos) /*!< 0x00004000 */
#define RCC_AHB3ENR_RISAFEN RCC_AHB3ENR_RISAFEN_Msk /*!< RISAF enable */
/***************** Bit definition for RCC_AHB4ENR register ******************/
#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk /*!< GPIO A enable */
#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk /*!< GPIO B enable */
#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk /*!< GPIO C enable */
#define RCC_AHB4ENR_GPIODEN_Pos (3U)
#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk /*!< GPIO D enable */
#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk /*!< GPIO E enable */
#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk /*!< GPIO F enable */
#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk /*!< GPIO G enable */
#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk /*!< GPIO H enable */
#define RCC_AHB4ENR_GPIONEN_Pos (13U)
#define RCC_AHB4ENR_GPIONEN_Msk (0x1UL << RCC_AHB4ENR_GPIONEN_Pos) /*!< 0x00002000 */
#define RCC_AHB4ENR_GPIONEN RCC_AHB4ENR_GPIONEN_Msk /*!< GPIO N enable */
#define RCC_AHB4ENR_GPIOOEN_Pos (14U)
#define RCC_AHB4ENR_GPIOOEN_Msk (0x1UL << RCC_AHB4ENR_GPIOOEN_Pos) /*!< 0x00004000 */
#define RCC_AHB4ENR_GPIOOEN RCC_AHB4ENR_GPIOOEN_Msk /*!< GPIO O enable */
#define RCC_AHB4ENR_GPIOPEN_Pos (15U)
#define RCC_AHB4ENR_GPIOPEN_Msk (0x1UL << RCC_AHB4ENR_GPIOPEN_Pos) /*!< 0x00008000 */
#define RCC_AHB4ENR_GPIOPEN RCC_AHB4ENR_GPIOPEN_Msk /*!< GPIO P enable */
#define RCC_AHB4ENR_GPIOQEN_Pos (16U)
#define RCC_AHB4ENR_GPIOQEN_Msk (0x1UL << RCC_AHB4ENR_GPIOQEN_Pos) /*!< 0x00010000 */
#define RCC_AHB4ENR_GPIOQEN RCC_AHB4ENR_GPIOQEN_Msk /*!< GPIO Q enable */
#define RCC_AHB4ENR_PWREN_Pos (18U)
#define RCC_AHB4ENR_PWREN_Msk (0x1UL << RCC_AHB4ENR_PWREN_Pos) /*!< 0x00040000 */
#define RCC_AHB4ENR_PWREN RCC_AHB4ENR_PWREN_Msk /*!< PWR enable */
#define RCC_AHB4ENR_CRCEN_Pos (19U)
#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */
#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk /*!< CRC enable */
/***************** Bit definition for RCC_AHB5ENR register ******************/
#define RCC_AHB5ENR_HPDMA1EN_Pos (0U)
#define RCC_AHB5ENR_HPDMA1EN_Msk (0x1UL << RCC_AHB5ENR_HPDMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB5ENR_HPDMA1EN RCC_AHB5ENR_HPDMA1EN_Msk /*!< HPDMA1 enable */
#define RCC_AHB5ENR_DMA2DEN_Pos (1U)
#define RCC_AHB5ENR_DMA2DEN_Msk (0x1UL << RCC_AHB5ENR_DMA2DEN_Pos) /*!< 0x00000002 */
#define RCC_AHB5ENR_DMA2DEN RCC_AHB5ENR_DMA2DEN_Msk /*!< DMA2D enable */
#define RCC_AHB5ENR_JPEGEN_Pos (3U)
#define RCC_AHB5ENR_JPEGEN_Msk (0x1UL << RCC_AHB5ENR_JPEGEN_Pos) /*!< 0x00000008 */
#define RCC_AHB5ENR_JPEGEN RCC_AHB5ENR_JPEGEN_Msk /*!< JPEG enable */
#define RCC_AHB5ENR_FMCEN_Pos (4U)
#define RCC_AHB5ENR_FMCEN_Msk (0x1UL << RCC_AHB5ENR_FMCEN_Pos) /*!< 0x00000010 */
#define RCC_AHB5ENR_FMCEN RCC_AHB5ENR_FMCEN_Msk /*!< FMC enable */
#define RCC_AHB5ENR_XSPI1EN_Pos (5U)
#define RCC_AHB5ENR_XSPI1EN_Msk (0x1UL << RCC_AHB5ENR_XSPI1EN_Pos) /*!< 0x00000020 */
#define RCC_AHB5ENR_XSPI1EN RCC_AHB5ENR_XSPI1EN_Msk /*!< XSPI1 enable */
#define RCC_AHB5ENR_PSSIEN_Pos (6U)
#define RCC_AHB5ENR_PSSIEN_Msk (0x1UL << RCC_AHB5ENR_PSSIEN_Pos) /*!< 0x00000040 */
#define RCC_AHB5ENR_PSSIEN RCC_AHB5ENR_PSSIEN_Msk /*!< PSSI enable */
#define RCC_AHB5ENR_SDMMC2EN_Pos (7U)
#define RCC_AHB5ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC2EN_Pos) /*!< 0x00000080 */
#define RCC_AHB5ENR_SDMMC2EN RCC_AHB5ENR_SDMMC2EN_Msk /*!< SDMMC2 enable */
#define RCC_AHB5ENR_SDMMC1EN_Pos (8U)
#define RCC_AHB5ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB5ENR_SDMMC1EN_Pos) /*!< 0x00000100 */
#define RCC_AHB5ENR_SDMMC1EN RCC_AHB5ENR_SDMMC1EN_Msk /*!< SDMMC1 enable */
#define RCC_AHB5ENR_XSPI2EN_Pos (12U)
#define RCC_AHB5ENR_XSPI2EN_Msk (0x1UL << RCC_AHB5ENR_XSPI2EN_Pos) /*!< 0x00001000 */
#define RCC_AHB5ENR_XSPI2EN RCC_AHB5ENR_XSPI2EN_Msk /*!< XSPI2 enable */
#define RCC_AHB5ENR_XSPIMEN_Pos (13U)
#define RCC_AHB5ENR_XSPIMEN_Msk (0x1UL << RCC_AHB5ENR_XSPIMEN_Pos) /*!< 0x00002000 */
#define RCC_AHB5ENR_XSPIMEN RCC_AHB5ENR_XSPIMEN_Msk /*!< XSPIM enable */
#define RCC_AHB5ENR_MCE1EN_Pos (14U)
#define RCC_AHB5ENR_MCE1EN_Msk (0x1UL << RCC_AHB5ENR_MCE1EN_Pos) /*!< 0x00004000 */
#define RCC_AHB5ENR_MCE1EN RCC_AHB5ENR_MCE1EN_Msk /*!< MCE1 enable */
#define RCC_AHB5ENR_MCE2EN_Pos (15U)
#define RCC_AHB5ENR_MCE2EN_Msk (0x1UL << RCC_AHB5ENR_MCE2EN_Pos) /*!< 0x00008000 */
#define RCC_AHB5ENR_MCE2EN RCC_AHB5ENR_MCE2EN_Msk /*!< MCE2 enable */
#define RCC_AHB5ENR_MCE3EN_Pos (16U)
#define RCC_AHB5ENR_MCE3EN_Msk (0x1UL << RCC_AHB5ENR_MCE3EN_Pos) /*!< 0x00010000 */
#define RCC_AHB5ENR_MCE3EN RCC_AHB5ENR_MCE3EN_Msk /*!< MCE3 enable */
#define RCC_AHB5ENR_XSPI3EN_Pos (17U)
#define RCC_AHB5ENR_XSPI3EN_Msk (0x1UL << RCC_AHB5ENR_XSPI3EN_Pos) /*!< 0x00020000 */
#define RCC_AHB5ENR_XSPI3EN RCC_AHB5ENR_XSPI3EN_Msk /*!< XSPI3 enable */
#define RCC_AHB5ENR_MCE4EN_Pos (18U)
#define RCC_AHB5ENR_MCE4EN_Msk (0x1UL << RCC_AHB5ENR_MCE4EN_Pos) /*!< 0x00040000 */
#define RCC_AHB5ENR_MCE4EN RCC_AHB5ENR_MCE4EN_Msk /*!< MCE4 enable */
#define RCC_AHB5ENR_GFXMMUEN_Pos (19U)
#define RCC_AHB5ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB5ENR_GFXMMUEN_Pos) /*!< 0x00080000 */
#define RCC_AHB5ENR_GFXMMUEN RCC_AHB5ENR_GFXMMUEN_Msk /*!< GFXMMU enable */
#define RCC_AHB5ENR_GPU2DEN_Pos (20U)
#define RCC_AHB5ENR_GPU2DEN_Msk (0x1UL << RCC_AHB5ENR_GPU2DEN_Pos) /*!< 0x00100000 */
#define RCC_AHB5ENR_GPU2DEN RCC_AHB5ENR_GPU2DEN_Msk /*!< GPU2D enable */
#define RCC_AHB5ENR_ETH1MACEN_Pos (22U)
#define RCC_AHB5ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB5ENR_ETH1MACEN_Pos) /*!< 0x00400000 */
#define RCC_AHB5ENR_ETH1MACEN RCC_AHB5ENR_ETH1MACEN_Msk /*!< ETH1MAC enable */
#define RCC_AHB5ENR_ETH1TXEN_Pos (23U)
#define RCC_AHB5ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1TXEN_Pos) /*!< 0x00800000 */
#define RCC_AHB5ENR_ETH1TXEN RCC_AHB5ENR_ETH1TXEN_Msk /*!< ETH1TX enable */
#define RCC_AHB5ENR_ETH1RXEN_Pos (24U)
#define RCC_AHB5ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB5ENR_ETH1RXEN_Pos) /*!< 0x01000000 */
#define RCC_AHB5ENR_ETH1RXEN RCC_AHB5ENR_ETH1RXEN_Msk /*!< ETH1RX enable */
#define RCC_AHB5ENR_ETH1EN_Pos (25U)
#define RCC_AHB5ENR_ETH1EN_Msk (0x1UL << RCC_AHB5ENR_ETH1EN_Pos) /*!< 0x02000000 */
#define RCC_AHB5ENR_ETH1EN RCC_AHB5ENR_ETH1EN_Msk /*!< ETH1 enable */
#define RCC_AHB5ENR_OTG1EN_Pos (26U)
#define RCC_AHB5ENR_OTG1EN_Msk (0x1UL << RCC_AHB5ENR_OTG1EN_Pos) /*!< 0x04000000 */
#define RCC_AHB5ENR_OTG1EN RCC_AHB5ENR_OTG1EN_Msk /*!< OTG1 enable */
#define RCC_AHB5ENR_OTGPHY1EN_Pos (27U)
#define RCC_AHB5ENR_OTGPHY1EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY1EN_Pos) /*!< 0x08000000 */
#define RCC_AHB5ENR_OTGPHY1EN RCC_AHB5ENR_OTGPHY1EN_Msk /*!< OTGPHY1 enable */
#define RCC_AHB5ENR_OTGPHY2EN_Pos (28U)
#define RCC_AHB5ENR_OTGPHY2EN_Msk (0x1UL << RCC_AHB5ENR_OTGPHY2EN_Pos) /*!< 0x10000000 */
#define RCC_AHB5ENR_OTGPHY2EN RCC_AHB5ENR_OTGPHY2EN_Msk /*!< OTGPHY2 enable */
#define RCC_AHB5ENR_OTG2EN_Pos (29U)
#define RCC_AHB5ENR_OTG2EN_Msk (0x1UL << RCC_AHB5ENR_OTG2EN_Pos) /*!< 0x20000000 */
#define RCC_AHB5ENR_OTG2EN RCC_AHB5ENR_OTG2EN_Msk /*!< OTG2 enable */
#define RCC_AHB5ENR_CACHEAXIEN_Pos (30U)
#define RCC_AHB5ENR_CACHEAXIEN_Msk (0x1UL << RCC_AHB5ENR_CACHEAXIEN_Pos) /*!< 0x40000000 */
#define RCC_AHB5ENR_CACHEAXIEN RCC_AHB5ENR_CACHEAXIEN_Msk /*!< CACHEAXI enable */
#define RCC_AHB5ENR_NPUEN_Pos (31U)
#define RCC_AHB5ENR_NPUEN_Msk (0x1UL << RCC_AHB5ENR_NPUEN_Pos) /*!< 0x80000000 */
#define RCC_AHB5ENR_NPUEN RCC_AHB5ENR_NPUEN_Msk /*!< NPU enable */
/***************** Bit definition for RCC_APB1ENR1 register *****************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk /*!< TIM2 enable */
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) /*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk /*!< TIM3 enable */
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) /*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk /*!< TIM4 enable */
#define RCC_APB1ENR1_TIM5EN_Pos (3U)
#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) /*!< 0x00000008 */
#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk /*!< TIM5 enable */
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) /*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk /*!< TIM6 enable */
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) /*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk /*!< TIM7 enable */
#define RCC_APB1ENR1_TIM12EN_Pos (6U)
#define RCC_APB1ENR1_TIM12EN_Msk (0x1UL << RCC_APB1ENR1_TIM12EN_Pos) /*!< 0x00000040 */
#define RCC_APB1ENR1_TIM12EN RCC_APB1ENR1_TIM12EN_Msk /*!< TIM12 enable */
#define RCC_APB1ENR1_TIM13EN_Pos (7U)
#define RCC_APB1ENR1_TIM13EN_Msk (0x1UL << RCC_APB1ENR1_TIM13EN_Pos) /*!< 0x00000080 */
#define RCC_APB1ENR1_TIM13EN RCC_APB1ENR1_TIM13EN_Msk /*!< TIM13 enable */
#define RCC_APB1ENR1_TIM14EN_Pos (8U)
#define RCC_APB1ENR1_TIM14EN_Msk (0x1UL << RCC_APB1ENR1_TIM14EN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_TIM14EN RCC_APB1ENR1_TIM14EN_Msk /*!< TIM14 enable */
#define RCC_APB1ENR1_LPTIM1EN_Pos (9U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos) /*!< 0x00000200 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk /*!< LPTIM1 enable */
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk /*!< WWDG enable */
#define RCC_APB1ENR1_TIM10EN_Pos (12U)
#define RCC_APB1ENR1_TIM10EN_Msk (0x1UL << RCC_APB1ENR1_TIM10EN_Pos) /*!< 0x00001000 */
#define RCC_APB1ENR1_TIM10EN RCC_APB1ENR1_TIM10EN_Msk /*!< TIM10 enable */
#define RCC_APB1ENR1_TIM11EN_Pos (13U)
#define RCC_APB1ENR1_TIM11EN_Msk (0x1UL << RCC_APB1ENR1_TIM11EN_Pos) /*!< 0x00002000 */
#define RCC_APB1ENR1_TIM11EN RCC_APB1ENR1_TIM11EN_Msk /*!< TIM11 enable */
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk /*!< SPI2 enable */
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos) /*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk /*!< SPI3 enable */
#define RCC_APB1ENR1_SPDIFRX1EN_Pos (16U)
#define RCC_APB1ENR1_SPDIFRX1EN_Msk (0x1UL << RCC_APB1ENR1_SPDIFRX1EN_Pos)/*!< 0x00010000 */
#define RCC_APB1ENR1_SPDIFRX1EN RCC_APB1ENR1_SPDIFRX1EN_Msk /*!< SPDIFRX1 enable */
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk /*!< USART2 enable */
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) /*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk /*!< USART3 enable */
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) /*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk /*!< UART4 enable */
#define RCC_APB1ENR1_UART5EN_Pos (20U)
#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) /*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk /*!< UART5 enable */
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk /*!< I2C1 enable */
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk /*!< I2C2 enable */
#define RCC_APB1ENR1_I2C3EN_Pos (23U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk /*!< I2C3 enable */
#define RCC_APB1ENR1_I3C1EN_Pos (24U)
#define RCC_APB1ENR1_I3C1EN_Msk (0x1UL << RCC_APB1ENR1_I3C1EN_Pos) /*!< 0x01000000 */
#define RCC_APB1ENR1_I3C1EN RCC_APB1ENR1_I3C1EN_Msk /*!< I3C1 enable */
#define RCC_APB1ENR1_I3C2EN_Pos (25U)
#define RCC_APB1ENR1_I3C2EN_Msk (0x1UL << RCC_APB1ENR1_I3C2EN_Pos) /*!< 0x02000000 */
#define RCC_APB1ENR1_I3C2EN RCC_APB1ENR1_I3C2EN_Msk /*!< I3C2 enable */
#define RCC_APB1ENR1_UART7EN_Pos (30U)
#define RCC_APB1ENR1_UART7EN_Msk (0x1UL << RCC_APB1ENR1_UART7EN_Pos) /*!< 0x40000000 */
#define RCC_APB1ENR1_UART7EN RCC_APB1ENR1_UART7EN_Msk /*!< UART7 enable */
#define RCC_APB1ENR1_UART8EN_Pos (31U)
#define RCC_APB1ENR1_UART8EN_Msk (0x1UL << RCC_APB1ENR1_UART8EN_Pos) /*!< 0x80000000 */
#define RCC_APB1ENR1_UART8EN RCC_APB1ENR1_UART8EN_Msk /*!< UART8 enable */
/***************** Bit definition for RCC_APB1ENR2 register *****************/
#define RCC_APB1ENR2_MDIOSEN_Pos (5U)
#define RCC_APB1ENR2_MDIOSEN_Msk (0x1UL << RCC_APB1ENR2_MDIOSEN_Pos) /*!< 0x00000020 */
#define RCC_APB1ENR2_MDIOSEN RCC_APB1ENR2_MDIOSEN_Msk /*!< MDIOS enable */
#define RCC_APB1ENR2_FDCANEN_Pos (8U)
#define RCC_APB1ENR2_FDCANEN_Msk (0x1UL << RCC_APB1ENR2_FDCANEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR2_FDCANEN RCC_APB1ENR2_FDCANEN_Msk /*!< FDCAN enable */
#define RCC_APB1ENR2_UCPD1EN_Pos (18U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) /*!< 0x00040000 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk /*!< UCPD1 enable */
/***************** Bit definition for RCC_APB2ENR register ******************/
#define RCC_APB2ENR_TIM1EN_Pos (0U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 enable */
#define RCC_APB2ENR_TIM8EN_Pos (1U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk /*!< TIM8 enable */
#define RCC_APB2ENR_USART1EN_Pos (4U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 enable */
#define RCC_APB2ENR_USART6EN_Pos (5U)
#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk /*!< USART6 enable */
#define RCC_APB2ENR_UART9EN_Pos (6U)
#define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
#define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk /*!< UART9 enable */
#define RCC_APB2ENR_USART10EN_Pos (7U)
#define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */
#define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk /*!< USART10 enable */
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 enable */
#define RCC_APB2ENR_SPI4EN_Pos (13U)
#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk /*!< SPI4 enable */
#define RCC_APB2ENR_TIM18EN_Pos (15U)
#define RCC_APB2ENR_TIM18EN_Msk (0x1UL << RCC_APB2ENR_TIM18EN_Pos) /*!< 0x00008000 */
#define RCC_APB2ENR_TIM18EN RCC_APB2ENR_TIM18EN_Msk /*!< TIM18 enable */
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk /*!< TIM15 enable */
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 enable */
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 enable */
#define RCC_APB2ENR_TIM9EN_Pos (19U)
#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00080000 */
#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 enable */
#define RCC_APB2ENR_SPI5EN_Pos (20U)
#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk /*!< SPI5 enable */
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk /*!< SAI1 enable */
#define RCC_APB2ENR_SAI2EN_Pos (22U)
#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00400000 */
#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk /*!< SAI2 enable */
/***************** Bit definition for RCC_APB3ENR register ******************/
#define RCC_APB3ENR_DFTEN_Pos (2U)
#define RCC_APB3ENR_DFTEN_Msk (0x1UL << RCC_APB3ENR_DFTEN_Pos) /*!< 0x00000004 */
#define RCC_APB3ENR_DFTEN RCC_APB3ENR_DFTEN_Msk /*!< DFT enable */
/***************** Bit definition for RCC_APB4ENR1 register *****************/
#define RCC_APB4ENR1_HDPEN_Pos (2U)
#define RCC_APB4ENR1_HDPEN_Msk (0x1UL << RCC_APB4ENR1_HDPEN_Pos) /*!< 0x00000004 */
#define RCC_APB4ENR1_HDPEN RCC_APB4ENR1_HDPEN_Msk /*!< HDP enable */
#define RCC_APB4ENR1_LPUART1EN_Pos (3U)
#define RCC_APB4ENR1_LPUART1EN_Msk (0x1UL << RCC_APB4ENR1_LPUART1EN_Pos) /*!< 0x00000008 */
#define RCC_APB4ENR1_LPUART1EN RCC_APB4ENR1_LPUART1EN_Msk /*!< LPUART1 enable */
#define RCC_APB4ENR1_SPI6EN_Pos (5U)
#define RCC_APB4ENR1_SPI6EN_Msk (0x1UL << RCC_APB4ENR1_SPI6EN_Pos) /*!< 0x00000020 */
#define RCC_APB4ENR1_SPI6EN RCC_APB4ENR1_SPI6EN_Msk /*!< SPI6 enable */
#define RCC_APB4ENR1_I2C4EN_Pos (7U)
#define RCC_APB4ENR1_I2C4EN_Msk (0x1UL << RCC_APB4ENR1_I2C4EN_Pos) /*!< 0x00000080 */
#define RCC_APB4ENR1_I2C4EN RCC_APB4ENR1_I2C4EN_Msk /*!< I2C4 enable */
#define RCC_APB4ENR1_LPTIM2EN_Pos (9U)
#define RCC_APB4ENR1_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM2EN_Pos) /*!< 0x00000200 */
#define RCC_APB4ENR1_LPTIM2EN RCC_APB4ENR1_LPTIM2EN_Msk /*!< LPTIM2 enable */
#define RCC_APB4ENR1_LPTIM3EN_Pos (10U)
#define RCC_APB4ENR1_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM3EN_Pos) /*!< 0x00000400 */
#define RCC_APB4ENR1_LPTIM3EN RCC_APB4ENR1_LPTIM3EN_Msk /*!< LPTIM3 enable */
#define RCC_APB4ENR1_LPTIM4EN_Pos (11U)
#define RCC_APB4ENR1_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM4EN_Pos) /*!< 0x00000800 */
#define RCC_APB4ENR1_LPTIM4EN RCC_APB4ENR1_LPTIM4EN_Msk /*!< LPTIM4 enable */
#define RCC_APB4ENR1_LPTIM5EN_Pos (12U)
#define RCC_APB4ENR1_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR1_LPTIM5EN_Pos) /*!< 0x00001000 */
#define RCC_APB4ENR1_LPTIM5EN RCC_APB4ENR1_LPTIM5EN_Msk /*!< LPTIM5 enable */
#define RCC_APB4ENR1_VREFBUFEN_Pos (15U)
#define RCC_APB4ENR1_VREFBUFEN_Msk (0x1UL << RCC_APB4ENR1_VREFBUFEN_Pos) /*!< 0x00008000 */
#define RCC_APB4ENR1_VREFBUFEN RCC_APB4ENR1_VREFBUFEN_Msk /*!< VREFBUF enable */
#define RCC_APB4ENR1_RTCEN_Pos (16U)
#define RCC_APB4ENR1_RTCEN_Msk (0x1UL << RCC_APB4ENR1_RTCEN_Pos) /*!< 0x00010000 */
#define RCC_APB4ENR1_RTCEN RCC_APB4ENR1_RTCEN_Msk /*!< RTC enable */
#define RCC_APB4ENR1_RTCAPBEN_Pos (17U)
#define RCC_APB4ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR1_RTCAPBEN_Pos) /*!< 0x00020000 */
#define RCC_APB4ENR1_RTCAPBEN RCC_APB4ENR1_RTCAPBEN_Msk /*!< RTCAPB enable */
/***************** Bit definition for RCC_APB4ENR2 register *****************/
#define RCC_APB4ENR2_SYSCFGEN_Pos (0U)
#define RCC_APB4ENR2_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR2_SYSCFGEN_Pos) /*!< 0x00000001 */
#define RCC_APB4ENR2_SYSCFGEN RCC_APB4ENR2_SYSCFGEN_Msk /*!< SYSCFG enable */
#define RCC_APB4ENR2_BSECEN_Pos (1U)
#define RCC_APB4ENR2_BSECEN_Msk (0x1UL << RCC_APB4ENR2_BSECEN_Pos) /*!< 0x00000002 */
#define RCC_APB4ENR2_BSECEN RCC_APB4ENR2_BSECEN_Msk /*!< BSEC enable */
#define RCC_APB4ENR2_DTSEN_Pos (2U)
#define RCC_APB4ENR2_DTSEN_Msk (0x1UL << RCC_APB4ENR2_DTSEN_Pos) /*!< 0x00000004 */
#define RCC_APB4ENR2_DTSEN RCC_APB4ENR2_DTSEN_Msk /*!< DTS enable */
/***************** Bit definition for RCC_APB5ENR register ******************/
#define RCC_APB5ENR_LTDCEN_Pos (1U)
#define RCC_APB5ENR_LTDCEN_Msk (0x1UL << RCC_APB5ENR_LTDCEN_Pos) /*!< 0x00000002 */
#define RCC_APB5ENR_LTDCEN RCC_APB5ENR_LTDCEN_Msk /*!< LTDC enable */
#define RCC_APB5ENR_DCMIPPEN_Pos (2U)
#define RCC_APB5ENR_DCMIPPEN_Msk (0x1UL << RCC_APB5ENR_DCMIPPEN_Pos) /*!< 0x00000004 */
#define RCC_APB5ENR_DCMIPPEN RCC_APB5ENR_DCMIPPEN_Msk /*!< DCMIPP enable */
#define RCC_APB5ENR_GFXTIMEN_Pos (4U)
#define RCC_APB5ENR_GFXTIMEN_Msk (0x1UL << RCC_APB5ENR_GFXTIMEN_Pos) /*!< 0x00000010 */
#define RCC_APB5ENR_GFXTIMEN RCC_APB5ENR_GFXTIMEN_Msk /*!< GFXTIM enable */
#define RCC_APB5ENR_VENCEN_Pos (5U)
#define RCC_APB5ENR_VENCEN_Msk (0x1UL << RCC_APB5ENR_VENCEN_Pos) /*!< 0x00000020 */
#define RCC_APB5ENR_VENCEN RCC_APB5ENR_VENCEN_Msk /*!< VENC enable */
#define RCC_APB5ENR_CSIEN_Pos (6U)
#define RCC_APB5ENR_CSIEN_Msk (0x1UL << RCC_APB5ENR_CSIEN_Pos) /*!< 0x00000040 */
#define RCC_APB5ENR_CSIEN RCC_APB5ENR_CSIEN_Msk /*!< CSI enable */
/***************** Bit definition for RCC_BUSLPENR register *****************/
#define RCC_BUSLPENR_ACLKNLPEN_Pos (0U)
#define RCC_BUSLPENR_ACLKNLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNLPEN_Pos) /*!< 0x00000001 */
#define RCC_BUSLPENR_ACLKNLPEN RCC_BUSLPENR_ACLKNLPEN_Msk /*!< ACLKN enable */
#define RCC_BUSLPENR_ACLKNCLPEN_Pos (1U)
#define RCC_BUSLPENR_ACLKNCLPEN_Msk (0x1UL << RCC_BUSLPENR_ACLKNCLPEN_Pos)/*!< 0x00000002 */
#define RCC_BUSLPENR_ACLKNCLPEN RCC_BUSLPENR_ACLKNCLPEN_Msk /*!< ACLKNC enable */
/**************** Bit definition for RCC_MISCLPENR register *****************/
#define RCC_MISCLPENR_DBGLPEN_Pos (0U)
#define RCC_MISCLPENR_DBGLPEN_Msk (0x1UL << RCC_MISCLPENR_DBGLPEN_Pos) /*!< 0x00000001 */
#define RCC_MISCLPENR_DBGLPEN RCC_MISCLPENR_DBGLPEN_Msk /*!< DBG enable */
#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos (3U)
#define RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk (0x1UL << RCC_MISCLPENR_XSPIPHYCOMPLPEN_Pos) /*!< 0x00000008 */
#define RCC_MISCLPENR_XSPIPHYCOMPLPEN RCC_MISCLPENR_XSPIPHYCOMPLPEN_Msk /*!< XSPIPHYCOMP enable */
#define RCC_MISCLPENR_PERLPEN_Pos (6U)
#define RCC_MISCLPENR_PERLPEN_Msk (0x1UL << RCC_MISCLPENR_PERLPEN_Pos) /*!< 0x00000040 */
#define RCC_MISCLPENR_PERLPEN RCC_MISCLPENR_PERLPEN_Msk /*!< PER enable */
/***************** Bit definition for RCC_MEMLPENR register *****************/
#define RCC_MEMLPENR_AXISRAM3LPEN_Pos (0U)
#define RCC_MEMLPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM3LPEN_Pos) /*!< 0x00000001 */
#define RCC_MEMLPENR_AXISRAM3LPEN RCC_MEMLPENR_AXISRAM3LPEN_Msk /*!< AXISRAM3 enable */
#define RCC_MEMLPENR_AXISRAM4LPEN_Pos (1U)
#define RCC_MEMLPENR_AXISRAM4LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM4LPEN_Pos) /*!< 0x00000002 */
#define RCC_MEMLPENR_AXISRAM4LPEN RCC_MEMLPENR_AXISRAM4LPEN_Msk /*!< AXISRAM4 enable */
#define RCC_MEMLPENR_AXISRAM5LPEN_Pos (2U)
#define RCC_MEMLPENR_AXISRAM5LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM5LPEN_Pos) /*!< 0x00000004 */
#define RCC_MEMLPENR_AXISRAM5LPEN RCC_MEMLPENR_AXISRAM5LPEN_Msk /*!< AXISRAM5 enable */
#define RCC_MEMLPENR_AXISRAM6LPEN_Pos (3U)
#define RCC_MEMLPENR_AXISRAM6LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM6LPEN_Pos) /*!< 0x00000008 */
#define RCC_MEMLPENR_AXISRAM6LPEN RCC_MEMLPENR_AXISRAM6LPEN_Msk /*!< AXISRAM6 enable */
#define RCC_MEMLPENR_AHBSRAM1LPEN_Pos (4U)
#define RCC_MEMLPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM1LPEN_Pos) /*!< 0x00000010 */
#define RCC_MEMLPENR_AHBSRAM1LPEN RCC_MEMLPENR_AHBSRAM1LPEN_Msk /*!< AHBSRAM1 enable */
#define RCC_MEMLPENR_AHBSRAM2LPEN_Pos (5U)
#define RCC_MEMLPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AHBSRAM2LPEN_Pos) /*!< 0x00000020 */
#define RCC_MEMLPENR_AHBSRAM2LPEN RCC_MEMLPENR_AHBSRAM2LPEN_Msk /*!< AHBSRAM2 enable */
#define RCC_MEMLPENR_BKPSRAMLPEN_Pos (6U)
#define RCC_MEMLPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_BKPSRAMLPEN_Pos) /*!< 0x00000040 */
#define RCC_MEMLPENR_BKPSRAMLPEN RCC_MEMLPENR_BKPSRAMLPEN_Msk /*!< BKPSRAM enable */
#define RCC_MEMLPENR_AXISRAM1LPEN_Pos (7U)
#define RCC_MEMLPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM1LPEN_Pos) /*!< 0x00000080 */
#define RCC_MEMLPENR_AXISRAM1LPEN RCC_MEMLPENR_AXISRAM1LPEN_Msk /*!< AXISRAM1 enable */
#define RCC_MEMLPENR_AXISRAM2LPEN_Pos (8U)
#define RCC_MEMLPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_MEMLPENR_AXISRAM2LPEN_Pos) /*!< 0x00000100 */
#define RCC_MEMLPENR_AXISRAM2LPEN RCC_MEMLPENR_AXISRAM2LPEN_Msk /*!< AXISRAM2 enable */
#define RCC_MEMLPENR_FLEXRAMLPEN_Pos (9U)
#define RCC_MEMLPENR_FLEXRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_FLEXRAMLPEN_Pos) /*!< 0x00000200 */
#define RCC_MEMLPENR_FLEXRAMLPEN RCC_MEMLPENR_FLEXRAMLPEN_Msk /*!< FLEXRAM enable */
#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos (10U)
#define RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_CACHEAXIRAMLPEN_Pos) /*!< 0x00000400 */
#define RCC_MEMLPENR_CACHEAXIRAMLPEN RCC_MEMLPENR_CACHEAXIRAMLPEN_Msk /*!< CACHEAXIRAM enable */
#define RCC_MEMLPENR_VENCRAMLPEN_Pos (11U)
#define RCC_MEMLPENR_VENCRAMLPEN_Msk (0x1UL << RCC_MEMLPENR_VENCRAMLPEN_Pos) /*!< 0x00000800 */
#define RCC_MEMLPENR_VENCRAMLPEN RCC_MEMLPENR_VENCRAMLPEN_Msk /*!< VENCRAM enable */
#define RCC_MEMLPENR_BOOTROMLPEN_Pos (12U)
#define RCC_MEMLPENR_BOOTROMLPEN_Msk (0x1UL << RCC_MEMLPENR_BOOTROMLPEN_Pos) /*!< 0x00001000 */
#define RCC_MEMLPENR_BOOTROMLPEN RCC_MEMLPENR_BOOTROMLPEN_Msk /*!< Boot ROM enable */
/**************** Bit definition for RCC_AHB1LPENR register *****************/
#define RCC_AHB1LPENR_GPDMA1LPEN_Pos (4U)
#define RCC_AHB1LPENR_GPDMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_GPDMA1LPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1LPENR_GPDMA1LPEN RCC_AHB1LPENR_GPDMA1LPEN_Msk /*!< GPDMA1 enable */
#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)/*!< 0x00000020 */
#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk /*!< ADC12 enable */
/**************** Bit definition for RCC_AHB2LPENR register *****************/
#define RCC_AHB2LPENR_RAMCFGLPEN_Pos (12U)
#define RCC_AHB2LPENR_RAMCFGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RAMCFGLPEN_Pos) /*!< 0x00001000 */
#define RCC_AHB2LPENR_RAMCFGLPEN RCC_AHB2LPENR_RAMCFGLPEN_Msk /*!< RAMCFG enable */
#define RCC_AHB2LPENR_MDF1LPEN_Pos (16U)
#define RCC_AHB2LPENR_MDF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_MDF1LPEN_Pos) /*!< 0x00010000 */
#define RCC_AHB2LPENR_MDF1LPEN RCC_AHB2LPENR_MDF1LPEN_Msk /*!< MDF1 enable */
#define RCC_AHB2LPENR_ADF1LPEN_Pos (17U)
#define RCC_AHB2LPENR_ADF1LPEN_Msk (0x1UL << RCC_AHB2LPENR_ADF1LPEN_Pos) /*!< 0x00020000 */
#define RCC_AHB2LPENR_ADF1LPEN RCC_AHB2LPENR_ADF1LPEN_Msk /*!< ADF1 enable */
/**************** Bit definition for RCC_AHB3LPENR register *****************/
#define RCC_AHB3LPENR_RNGLPEN_Pos (0U)
#define RCC_AHB3LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB3LPENR_RNGLPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3LPENR_RNGLPEN RCC_AHB3LPENR_RNGLPEN_Msk /*!< RNG enable */
#define RCC_AHB3LPENR_HASHLPEN_Pos (1U)
#define RCC_AHB3LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_HASHLPEN_Pos) /*!< 0x00000002 */
#define RCC_AHB3LPENR_HASHLPEN RCC_AHB3LPENR_HASHLPEN_Msk /*!< HASH enable */
#define RCC_AHB3LPENR_CRYPLPEN_Pos (2U)
#define RCC_AHB3LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB3LPENR_CRYPLPEN_Pos) /*!< 0x00000004 */
#define RCC_AHB3LPENR_CRYPLPEN RCC_AHB3LPENR_CRYPLPEN_Msk /*!< CRYP enable */
#define RCC_AHB3LPENR_SAESLPEN_Pos (4U)
#define RCC_AHB3LPENR_SAESLPEN_Msk (0x1UL << RCC_AHB3LPENR_SAESLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB3LPENR_SAESLPEN RCC_AHB3LPENR_SAESLPEN_Msk /*!< SAES enable */
#define RCC_AHB3LPENR_PKALPEN_Pos (8U)
#define RCC_AHB3LPENR_PKALPEN_Msk (0x1UL << RCC_AHB3LPENR_PKALPEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3LPENR_PKALPEN RCC_AHB3LPENR_PKALPEN_Msk /*!< PKA enable */
#define RCC_AHB3LPENR_RIFSCLPEN_Pos (9U)
#define RCC_AHB3LPENR_RIFSCLPEN_Msk (0x1UL << RCC_AHB3LPENR_RIFSCLPEN_Pos)/*!< 0x00000200 */
#define RCC_AHB3LPENR_RIFSCLPEN RCC_AHB3LPENR_RIFSCLPEN_Msk /*!< RIFSC enable */
#define RCC_AHB3LPENR_IACLPEN_Pos (10U)
#define RCC_AHB3LPENR_IACLPEN_Msk (0x1UL << RCC_AHB3LPENR_IACLPEN_Pos) /*!< 0x00000400 */
#define RCC_AHB3LPENR_IACLPEN RCC_AHB3LPENR_IACLPEN_Msk /*!< IAC enable */
#define RCC_AHB3LPENR_RISAFLPEN_Pos (14U)
#define RCC_AHB3LPENR_RISAFLPEN_Msk (0x1UL << RCC_AHB3LPENR_RISAFLPEN_Pos)/*!< 0x00004000 */
#define RCC_AHB3LPENR_RISAFLPEN RCC_AHB3LPENR_RISAFLPEN_Msk /*!< RISAF enable */
/**************** Bit definition for RCC_AHB4LPENR register *****************/
#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)/*!< 0x00000001 */
#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk /*!< GPIO A enable */
#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)/*!< 0x00000002 */
#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk /*!< GPIO B enable */
#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)/*!< 0x00000004 */
#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk /*!< GPIO C enable */
#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)/*!< 0x00000008 */
#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk /*!< GPIO D enable */
#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)/*!< 0x00000010 */
#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk /*!< GPIO E enable */
#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)/*!< 0x00000020 */
#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk /*!< GPIO F enable */
#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)/*!< 0x00000040 */
#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk /*!< GPIO G enable */
#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)/*!< 0x00000080 */
#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk /*!< GPIO H enable */
#define RCC_AHB4LPENR_GPIONLPEN_Pos (13U)
#define RCC_AHB4LPENR_GPIONLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIONLPEN_Pos)/*!< 0x00002000 */
#define RCC_AHB4LPENR_GPIONLPEN RCC_AHB4LPENR_GPIONLPEN_Msk /*!< GPIO N enable */
#define RCC_AHB4LPENR_GPIOOLPEN_Pos (14U)
#define RCC_AHB4LPENR_GPIOOLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOOLPEN_Pos)/*!< 0x00004000 */
#define RCC_AHB4LPENR_GPIOOLPEN RCC_AHB4LPENR_GPIOOLPEN_Msk /*!< GPIO O enable */
#define RCC_AHB4LPENR_GPIOPLPEN_Pos (15U)
#define RCC_AHB4LPENR_GPIOPLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOPLPEN_Pos)/*!< 0x00008000 */
#define RCC_AHB4LPENR_GPIOPLPEN RCC_AHB4LPENR_GPIOPLPEN_Msk /*!< GPIO P enable */
#define RCC_AHB4LPENR_GPIOQLPEN_Pos (16U)
#define RCC_AHB4LPENR_GPIOQLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOQLPEN_Pos)/*!< 0x00010000 */
#define RCC_AHB4LPENR_GPIOQLPEN RCC_AHB4LPENR_GPIOQLPEN_Msk /*!< GPIO Q enable */
#define RCC_AHB4LPENR_PWRLPEN_Pos (18U)
#define RCC_AHB4LPENR_PWRLPEN_Msk (0x1UL << RCC_AHB4LPENR_PWRLPEN_Pos) /*!< 0x00040000 */
#define RCC_AHB4LPENR_PWRLPEN RCC_AHB4LPENR_PWRLPEN_Msk /*!< PWR enable */
#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk /*!< CRC enable */
/**************** Bit definition for RCC_AHB5LPENR register *****************/
#define RCC_AHB5LPENR_HPDMA1LPEN_Pos (0U)
#define RCC_AHB5LPENR_HPDMA1LPEN_Msk (0x1UL << RCC_AHB5LPENR_HPDMA1LPEN_Pos) /*!< 0x00000001 */
#define RCC_AHB5LPENR_HPDMA1LPEN RCC_AHB5LPENR_HPDMA1LPEN_Msk /*!< HPDMA1 enable */
#define RCC_AHB5LPENR_DMA2DLPEN_Pos (1U)
#define RCC_AHB5LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_DMA2DLPEN_Pos)/*!< 0x00000002 */
#define RCC_AHB5LPENR_DMA2DLPEN RCC_AHB5LPENR_DMA2DLPEN_Msk /*!< DMA2D enable */
#define RCC_AHB5LPENR_JPEGLPEN_Pos (3U)
#define RCC_AHB5LPENR_JPEGLPEN_Msk (0x1UL << RCC_AHB5LPENR_JPEGLPEN_Pos) /*!< 0x00000008 */
#define RCC_AHB5LPENR_JPEGLPEN RCC_AHB5LPENR_JPEGLPEN_Msk /*!< JPEG enable */
#define RCC_AHB5LPENR_FMCLPEN_Pos (4U)
#define RCC_AHB5LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB5LPENR_FMCLPEN_Pos) /*!< 0x00000010 */
#define RCC_AHB5LPENR_FMCLPEN RCC_AHB5LPENR_FMCLPEN_Msk /*!< FMC enable */
#define RCC_AHB5LPENR_XSPI1LPEN_Pos (5U)
#define RCC_AHB5LPENR_XSPI1LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI1LPEN_Pos)/*!< 0x00000020 */
#define RCC_AHB5LPENR_XSPI1LPEN RCC_AHB5LPENR_XSPI1LPEN_Msk /*!< XSPI1 enable */
#define RCC_AHB5LPENR_PSSILPEN_Pos (6U)
#define RCC_AHB5LPENR_PSSILPEN_Msk (0x1UL << RCC_AHB5LPENR_PSSILPEN_Pos) /*!< 0x00000040 */
#define RCC_AHB5LPENR_PSSILPEN RCC_AHB5LPENR_PSSILPEN_Msk /*!< PSSI enable */
#define RCC_AHB5LPENR_SDMMC2LPEN_Pos (7U)
#define RCC_AHB5LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */
#define RCC_AHB5LPENR_SDMMC2LPEN RCC_AHB5LPENR_SDMMC2LPEN_Msk /*!< SDMMC2 enable */
#define RCC_AHB5LPENR_SDMMC1LPEN_Pos (8U)
#define RCC_AHB5LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB5LPENR_SDMMC1LPEN_Pos) /*!< 0x00000100 */
#define RCC_AHB5LPENR_SDMMC1LPEN RCC_AHB5LPENR_SDMMC1LPEN_Msk /*!< SDMMC1 enable */
#define RCC_AHB5LPENR_XSPI2LPEN_Pos (12U)
#define RCC_AHB5LPENR_XSPI2LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI2LPEN_Pos)/*!< 0x00001000 */
#define RCC_AHB5LPENR_XSPI2LPEN RCC_AHB5LPENR_XSPI2LPEN_Msk /*!< XSPI2 enable */
#define RCC_AHB5LPENR_XSPIMLPEN_Pos (13U)
#define RCC_AHB5LPENR_XSPIMLPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPIMLPEN_Pos)/*!< 0x00002000 */
#define RCC_AHB5LPENR_XSPIMLPEN RCC_AHB5LPENR_XSPIMLPEN_Msk /*!< XSPIM enable */
#define RCC_AHB5LPENR_MCE1LPEN_Pos (14U)
#define RCC_AHB5LPENR_MCE1LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE1LPEN_Pos) /*!< 0x00004000 */
#define RCC_AHB5LPENR_MCE1LPEN RCC_AHB5LPENR_MCE1LPEN_Msk /*!< MCE1 enable */
#define RCC_AHB5LPENR_MCE2LPEN_Pos (15U)
#define RCC_AHB5LPENR_MCE2LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE2LPEN_Pos) /*!< 0x00008000 */
#define RCC_AHB5LPENR_MCE2LPEN RCC_AHB5LPENR_MCE2LPEN_Msk /*!< MCE2 enable */
#define RCC_AHB5LPENR_MCE3LPEN_Pos (16U)
#define RCC_AHB5LPENR_MCE3LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE3LPEN_Pos) /*!< 0x00010000 */
#define RCC_AHB5LPENR_MCE3LPEN RCC_AHB5LPENR_MCE3LPEN_Msk /*!< MCE3 enable */
#define RCC_AHB5LPENR_XSPI3LPEN_Pos (17U)
#define RCC_AHB5LPENR_XSPI3LPEN_Msk (0x1UL << RCC_AHB5LPENR_XSPI3LPEN_Pos)/*!< 0x00020000 */
#define RCC_AHB5LPENR_XSPI3LPEN RCC_AHB5LPENR_XSPI3LPEN_Msk /*!< XSPI3 enable */
#define RCC_AHB5LPENR_MCE4LPEN_Pos (18U)
#define RCC_AHB5LPENR_MCE4LPEN_Msk (0x1UL << RCC_AHB5LPENR_MCE4LPEN_Pos) /*!< 0x00040000 */
#define RCC_AHB5LPENR_MCE4LPEN RCC_AHB5LPENR_MCE4LPEN_Msk /*!< MCE4 enable */
#define RCC_AHB5LPENR_GFXMMULPEN_Pos (19U)
#define RCC_AHB5LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB5LPENR_GFXMMULPEN_Pos) /*!< 0x00080000 */
#define RCC_AHB5LPENR_GFXMMULPEN RCC_AHB5LPENR_GFXMMULPEN_Msk /*!< GFXMMU enable */
#define RCC_AHB5LPENR_GPU2DLPEN_Pos (20U)
#define RCC_AHB5LPENR_GPU2DLPEN_Msk (0x1UL << RCC_AHB5LPENR_GPU2DLPEN_Pos)/*!< 0x00100000 */
#define RCC_AHB5LPENR_GPU2DLPEN RCC_AHB5LPENR_GPU2DLPEN_Msk /*!< GPU2D enable */
#define RCC_AHB5LPENR_ETH1MACLPEN_Pos (22U)
#define RCC_AHB5LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1MACLPEN_Pos) /*!< 0x00400000 */
#define RCC_AHB5LPENR_ETH1MACLPEN RCC_AHB5LPENR_ETH1MACLPEN_Msk /*!< ETH1MAC enable */
#define RCC_AHB5LPENR_ETH1TXLPEN_Pos (23U)
#define RCC_AHB5LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1TXLPEN_Pos) /*!< 0x00800000 */
#define RCC_AHB5LPENR_ETH1TXLPEN RCC_AHB5LPENR_ETH1TXLPEN_Msk /*!< ETH1TX enable */
#define RCC_AHB5LPENR_ETH1RXLPEN_Pos (24U)
#define RCC_AHB5LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1RXLPEN_Pos) /*!< 0x01000000 */
#define RCC_AHB5LPENR_ETH1RXLPEN RCC_AHB5LPENR_ETH1RXLPEN_Msk /*!< ETH1RX enable */
#define RCC_AHB5LPENR_ETH1LPEN_Pos (25U)
#define RCC_AHB5LPENR_ETH1LPEN_Msk (0x1UL << RCC_AHB5LPENR_ETH1LPEN_Pos) /*!< 0x02000000 */
#define RCC_AHB5LPENR_ETH1LPEN RCC_AHB5LPENR_ETH1LPEN_Msk /*!< ETH1 enable */
#define RCC_AHB5LPENR_OTG1LPEN_Pos (26U)
#define RCC_AHB5LPENR_OTG1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG1LPEN_Pos) /*!< 0x04000000 */
#define RCC_AHB5LPENR_OTG1LPEN RCC_AHB5LPENR_OTG1LPEN_Msk /*!< OTG1 enable */
#define RCC_AHB5LPENR_OTGPHY1LPEN_Pos (27U)
#define RCC_AHB5LPENR_OTGPHY1LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY1LPEN_Pos) /*!< 0x08000000 */
#define RCC_AHB5LPENR_OTGPHY1LPEN RCC_AHB5LPENR_OTGPHY1LPEN_Msk /*!< OTGPHY1 enable */
#define RCC_AHB5LPENR_OTGPHY2LPEN_Pos (28U)
#define RCC_AHB5LPENR_OTGPHY2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTGPHY2LPEN_Pos) /*!< 0x10000000 */
#define RCC_AHB5LPENR_OTGPHY2LPEN RCC_AHB5LPENR_OTGPHY2LPEN_Msk /*!< OTGPHY2 enable */
#define RCC_AHB5LPENR_OTG2LPEN_Pos (29U)
#define RCC_AHB5LPENR_OTG2LPEN_Msk (0x1UL << RCC_AHB5LPENR_OTG2LPEN_Pos) /*!< 0x20000000 */
#define RCC_AHB5LPENR_OTG2LPEN RCC_AHB5LPENR_OTG2LPEN_Msk /*!< OTG2 enable */
#define RCC_AHB5LPENR_CACHEAXILPEN_Pos (30U)
#define RCC_AHB5LPENR_CACHEAXILPEN_Msk (0x1UL << RCC_AHB5LPENR_CACHEAXILPEN_Pos) /*!< 0x40000000 */
#define RCC_AHB5LPENR_CACHEAXILPEN RCC_AHB5LPENR_CACHEAXILPEN_Msk /*!< CACHEAXI enable */
#define RCC_AHB5LPENR_NPULPEN_Pos (31U)
#define RCC_AHB5LPENR_NPULPEN_Msk (0x1UL << RCC_AHB5LPENR_NPULPEN_Pos) /*!< 0x80000000 */
#define RCC_AHB5LPENR_NPULPEN RCC_AHB5LPENR_NPULPEN_Msk /*!< NPU enable */
/**************** Bit definition for RCC_APB1LPENR1 register ****************/
#define RCC_APB1LPENR1_TIM2LPEN_Pos (0U)
#define RCC_APB1LPENR1_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM2LPEN_Pos)/*!< 0x00000001 */
#define RCC_APB1LPENR1_TIM2LPEN RCC_APB1LPENR1_TIM2LPEN_Msk /*!< TIM2 enable */
#define RCC_APB1LPENR1_TIM3LPEN_Pos (1U)
#define RCC_APB1LPENR1_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM3LPEN_Pos)/*!< 0x00000002 */
#define RCC_APB1LPENR1_TIM3LPEN RCC_APB1LPENR1_TIM3LPEN_Msk /*!< TIM3 enable */
#define RCC_APB1LPENR1_TIM4LPEN_Pos (2U)
#define RCC_APB1LPENR1_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM4LPEN_Pos)/*!< 0x00000004 */
#define RCC_APB1LPENR1_TIM4LPEN RCC_APB1LPENR1_TIM4LPEN_Msk /*!< TIM4 enable */
#define RCC_APB1LPENR1_TIM5LPEN_Pos (3U)
#define RCC_APB1LPENR1_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM5LPEN_Pos)/*!< 0x00000008 */
#define RCC_APB1LPENR1_TIM5LPEN RCC_APB1LPENR1_TIM5LPEN_Msk /*!< TIM5 enable */
#define RCC_APB1LPENR1_TIM6LPEN_Pos (4U)
#define RCC_APB1LPENR1_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM6LPEN_Pos)/*!< 0x00000010 */
#define RCC_APB1LPENR1_TIM6LPEN RCC_APB1LPENR1_TIM6LPEN_Msk /*!< TIM6 enable */
#define RCC_APB1LPENR1_TIM7LPEN_Pos (5U)
#define RCC_APB1LPENR1_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM7LPEN_Pos)/*!< 0x00000020 */
#define RCC_APB1LPENR1_TIM7LPEN RCC_APB1LPENR1_TIM7LPEN_Msk /*!< TIM7 enable */
#define RCC_APB1LPENR1_TIM12LPEN_Pos (6U)
#define RCC_APB1LPENR1_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM12LPEN_Pos) /*!< 0x00000040 */
#define RCC_APB1LPENR1_TIM12LPEN RCC_APB1LPENR1_TIM12LPEN_Msk /*!< TIM12 enable */
#define RCC_APB1LPENR1_TIM13LPEN_Pos (7U)
#define RCC_APB1LPENR1_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM13LPEN_Pos) /*!< 0x00000080 */
#define RCC_APB1LPENR1_TIM13LPEN RCC_APB1LPENR1_TIM13LPEN_Msk /*!< TIM13 enable */
#define RCC_APB1LPENR1_TIM14LPEN_Pos (8U)
#define RCC_APB1LPENR1_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM14LPEN_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENR1_TIM14LPEN RCC_APB1LPENR1_TIM14LPEN_Msk /*!< TIM14 enable */
#define RCC_APB1LPENR1_LPTIM1LPEN_Pos (9U)
#define RCC_APB1LPENR1_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR1_LPTIM1LPEN_Pos) /*!< 0x00000200 */
#define RCC_APB1LPENR1_LPTIM1LPEN RCC_APB1LPENR1_LPTIM1LPEN_Msk /*!< LPTIM1 enable */
#define RCC_APB1LPENR1_WWDGLPEN_Pos (11U)
#define RCC_APB1LPENR1_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR1_WWDGLPEN_Pos)/*!< 0x00000800 */
#define RCC_APB1LPENR1_WWDGLPEN RCC_APB1LPENR1_WWDGLPEN_Msk /*!< WWDG enable */
#define RCC_APB1LPENR1_TIM10LPEN_Pos (12U)
#define RCC_APB1LPENR1_TIM10LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM10LPEN_Pos) /*!< 0x00001000 */
#define RCC_APB1LPENR1_TIM10LPEN RCC_APB1LPENR1_TIM10LPEN_Msk /*!< TIM10 enable */
#define RCC_APB1LPENR1_TIM11LPEN_Pos (13U)
#define RCC_APB1LPENR1_TIM11LPEN_Msk (0x1UL << RCC_APB1LPENR1_TIM11LPEN_Pos) /*!< 0x00002000 */
#define RCC_APB1LPENR1_TIM11LPEN RCC_APB1LPENR1_TIM11LPEN_Msk /*!< TIM11 enable */
#define RCC_APB1LPENR1_SPI2LPEN_Pos (14U)
#define RCC_APB1LPENR1_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI2LPEN_Pos)/*!< 0x00004000 */
#define RCC_APB1LPENR1_SPI2LPEN RCC_APB1LPENR1_SPI2LPEN_Msk /*!< SPI2 enable */
#define RCC_APB1LPENR1_SPI3LPEN_Pos (15U)
#define RCC_APB1LPENR1_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPI3LPEN_Pos)/*!< 0x00008000 */
#define RCC_APB1LPENR1_SPI3LPEN RCC_APB1LPENR1_SPI3LPEN_Msk /*!< SPI3 enable */
#define RCC_APB1LPENR1_SPDIFRX1LPEN_Pos (16U)
#define RCC_APB1LPENR1_SPDIFRX1LPEN_Msk (0x1UL << RCC_APB1LPENR1_SPDIFRX1LPEN_Pos) /*!< 0x00010000 */
#define RCC_APB1LPENR1_SPDIFRX1LPEN RCC_APB1LPENR1_SPDIFRX1LPEN_Msk /*!< SPDIFRX1 enable */
#define RCC_APB1LPENR1_USART2LPEN_Pos (17U)
#define RCC_APB1LPENR1_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART2LPEN_Pos) /*!< 0x00020000 */
#define RCC_APB1LPENR1_USART2LPEN RCC_APB1LPENR1_USART2LPEN_Msk /*!< USART2 enable */
#define RCC_APB1LPENR1_USART3LPEN_Pos (18U)
#define RCC_APB1LPENR1_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR1_USART3LPEN_Pos) /*!< 0x00040000 */
#define RCC_APB1LPENR1_USART3LPEN RCC_APB1LPENR1_USART3LPEN_Msk /*!< USART3 enable */
#define RCC_APB1LPENR1_UART4LPEN_Pos (19U)
#define RCC_APB1LPENR1_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART4LPEN_Pos) /*!< 0x00080000 */
#define RCC_APB1LPENR1_UART4LPEN RCC_APB1LPENR1_UART4LPEN_Msk /*!< UART4 enable */
#define RCC_APB1LPENR1_UART5LPEN_Pos (20U)
#define RCC_APB1LPENR1_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART5LPEN_Pos) /*!< 0x00100000 */
#define RCC_APB1LPENR1_UART5LPEN RCC_APB1LPENR1_UART5LPEN_Msk /*!< UART5 enable */
#define RCC_APB1LPENR1_I2C1LPEN_Pos (21U)
#define RCC_APB1LPENR1_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C1LPEN_Pos)/*!< 0x00200000 */
#define RCC_APB1LPENR1_I2C1LPEN RCC_APB1LPENR1_I2C1LPEN_Msk /*!< I2C1 enable */
#define RCC_APB1LPENR1_I2C2LPEN_Pos (22U)
#define RCC_APB1LPENR1_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C2LPEN_Pos)/*!< 0x00400000 */
#define RCC_APB1LPENR1_I2C2LPEN RCC_APB1LPENR1_I2C2LPEN_Msk /*!< I2C2 enable */
#define RCC_APB1LPENR1_I2C3LPEN_Pos (23U)
#define RCC_APB1LPENR1_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR1_I2C3LPEN_Pos)/*!< 0x00800000 */
#define RCC_APB1LPENR1_I2C3LPEN RCC_APB1LPENR1_I2C3LPEN_Msk /*!< I2C3 enable */
#define RCC_APB1LPENR1_I3C1LPEN_Pos (24U)
#define RCC_APB1LPENR1_I3C1LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C1LPEN_Pos)/*!< 0x01000000 */
#define RCC_APB1LPENR1_I3C1LPEN RCC_APB1LPENR1_I3C1LPEN_Msk /*!< I3C1 enable */
#define RCC_APB1LPENR1_I3C2LPEN_Pos (25U)
#define RCC_APB1LPENR1_I3C2LPEN_Msk (0x1UL << RCC_APB1LPENR1_I3C2LPEN_Pos)/*!< 0x02000000 */
#define RCC_APB1LPENR1_I3C2LPEN RCC_APB1LPENR1_I3C2LPEN_Msk /*!< I3C2 enable */
#define RCC_APB1LPENR1_UART7LPEN_Pos (30U)
#define RCC_APB1LPENR1_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART7LPEN_Pos) /*!< 0x40000000 */
#define RCC_APB1LPENR1_UART7LPEN RCC_APB1LPENR1_UART7LPEN_Msk /*!< UART7 enable */
#define RCC_APB1LPENR1_UART8LPEN_Pos (31U)
#define RCC_APB1LPENR1_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR1_UART8LPEN_Pos) /*!< 0x80000000 */
#define RCC_APB1LPENR1_UART8LPEN RCC_APB1LPENR1_UART8LPEN_Msk /*!< UART8 enable */
/**************** Bit definition for RCC_APB1LPENR2 register ****************/
#define RCC_APB1LPENR2_MDIOSLPEN_Pos (5U)
#define RCC_APB1LPENR2_MDIOSLPEN_Msk (0x1UL << RCC_APB1LPENR2_MDIOSLPEN_Pos) /*!< 0x00000020 */
#define RCC_APB1LPENR2_MDIOSLPEN RCC_APB1LPENR2_MDIOSLPEN_Msk /*!< MDIOS enable in Sleep mode */
#define RCC_APB1LPENR2_FDCANLPEN_Pos (8U)
#define RCC_APB1LPENR2_FDCANLPEN_Msk (0x1UL << RCC_APB1LPENR2_FDCANLPEN_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENR2_FDCANLPEN RCC_APB1LPENR2_FDCANLPEN_Msk /*!< FDCAN enablein Sleep mode */
#define RCC_APB1LPENR2_UCPD1LPEN_Pos (18U)
#define RCC_APB1LPENR2_UCPD1LPEN_Msk (0x1UL << RCC_APB1LPENR2_UCPD1LPEN_Pos) /*!< 0x00040000 */
#define RCC_APB1LPENR2_UCPD1LPEN RCC_APB1LPENR2_UCPD1LPEN_Msk /*!< UCPD1 enable in Sleep mode */
/**************** Bit definition for RCC_APB2LPENR register *****************/
#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk /*!< TIM1 enable */
#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk /*!< TIM8 enable */
#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 enable */
#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk /*!< USART6 enable */
#define RCC_APB2LPENR_UART9LPEN_Pos (6U)
#define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos)/*!< 0x00000040 */
#define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk /*!< UART9 enable */
#define RCC_APB2LPENR_USART10LPEN_Pos (7U)
#define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */
#define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk /*!< USART10 enable */
#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 enable */
#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk /*!< SPI4 enable */
#define RCC_APB2LPENR_TIM18LPEN_Pos (15U)
#define RCC_APB2LPENR_TIM18LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM18LPEN_Pos)/*!< 0x00008000 */
#define RCC_APB2LPENR_TIM18LPEN RCC_APB2LPENR_TIM18LPEN_Msk /*!< TIM18 enable */
#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)/*!< 0x00010000 */
#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk /*!< TIM15 enable */
#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)/*!< 0x00020000 */
#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk /*!< TIM16 enable */
#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)/*!< 0x00040000 */
#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk /*!< TIM17 enable */
#define RCC_APB2LPENR_TIM9LPEN_Pos (19U)
#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00080000 */
#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 enable */
#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk /*!< SPI5 enable */
#define RCC_APB2LPENR_SAI1LPEN_Pos (21U)
#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00200000 */
#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk /*!< SAI1 enable */
#define RCC_APB2LPENR_SAI2LPEN_Pos (22U)
#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00400000 */
#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk /*!< SAI2 enable */
/**************** Bit definition for RCC_APB3LPENR register *****************/
#define RCC_APB3LPENR_DFTLPEN_Pos (2U)
#define RCC_APB3LPENR_DFTLPEN_Msk (0x1UL << RCC_APB3LPENR_DFTLPEN_Pos) /*!< 0x00000004 */
#define RCC_APB3LPENR_DFTLPEN RCC_APB3LPENR_DFTLPEN_Msk /*!< DFT enable */
/**************** Bit definition for RCC_APB4LPENR1 register ****************/
#define RCC_APB4LPENR1_HDPLPEN_Pos (2U)
#define RCC_APB4LPENR1_HDPLPEN_Msk (0x1UL << RCC_APB4LPENR1_HDPLPEN_Pos) /*!< 0x00000004 */
#define RCC_APB4LPENR1_HDPLPEN RCC_APB4LPENR1_HDPLPEN_Msk /*!< HDP enable */
#define RCC_APB4LPENR1_LPUART1LPEN_Pos (3U)
#define RCC_APB4LPENR1_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPUART1LPEN_Pos) /*!< 0x00000008 */
#define RCC_APB4LPENR1_LPUART1LPEN RCC_APB4LPENR1_LPUART1LPEN_Msk /*!< LPUART1 enable */
#define RCC_APB4LPENR1_SPI6LPEN_Pos (5U)
#define RCC_APB4LPENR1_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR1_SPI6LPEN_Pos)/*!< 0x00000020 */
#define RCC_APB4LPENR1_SPI6LPEN RCC_APB4LPENR1_SPI6LPEN_Msk /*!< SPI6 enable */
#define RCC_APB4LPENR1_I2C4LPEN_Pos (7U)
#define RCC_APB4LPENR1_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR1_I2C4LPEN_Pos)/*!< 0x00000080 */
#define RCC_APB4LPENR1_I2C4LPEN RCC_APB4LPENR1_I2C4LPEN_Msk /*!< I2C4 enable */
#define RCC_APB4LPENR1_LPTIM2LPEN_Pos (9U)
#define RCC_APB4LPENR1_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM2LPEN_Pos) /*!< 0x00000200 */
#define RCC_APB4LPENR1_LPTIM2LPEN RCC_APB4LPENR1_LPTIM2LPEN_Msk /*!< LPTIM2 enable */
#define RCC_APB4LPENR1_LPTIM3LPEN_Pos (10U)
#define RCC_APB4LPENR1_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM3LPEN_Pos) /*!< 0x00000400 */
#define RCC_APB4LPENR1_LPTIM3LPEN RCC_APB4LPENR1_LPTIM3LPEN_Msk /*!< LPTIM3 enable */
#define RCC_APB4LPENR1_LPTIM4LPEN_Pos (11U)
#define RCC_APB4LPENR1_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM4LPEN_Pos) /*!< 0x00000800 */
#define RCC_APB4LPENR1_LPTIM4LPEN RCC_APB4LPENR1_LPTIM4LPEN_Msk /*!< LPTIM4 enable */
#define RCC_APB4LPENR1_LPTIM5LPEN_Pos (12U)
#define RCC_APB4LPENR1_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR1_LPTIM5LPEN_Pos) /*!< 0x00001000 */
#define RCC_APB4LPENR1_LPTIM5LPEN RCC_APB4LPENR1_LPTIM5LPEN_Msk /*!< LPTIM5 enable */
#define RCC_APB4LPENR1_VREFBUFLPEN_Pos (15U)
#define RCC_APB4LPENR1_VREFBUFLPEN_Msk (0x1UL << RCC_APB4LPENR1_VREFBUFLPEN_Pos) /*!< 0x00008000 */
#define RCC_APB4LPENR1_VREFBUFLPEN RCC_APB4LPENR1_VREFBUFLPEN_Msk /*!< VREFBUF enable */
#define RCC_APB4LPENR1_RTCLPEN_Pos (16U)
#define RCC_APB4LPENR1_RTCLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCLPEN_Pos) /*!< 0x00010000 */
#define RCC_APB4LPENR1_RTCLPEN RCC_APB4LPENR1_RTCLPEN_Msk /*!< RTC enable */
#define RCC_APB4LPENR1_RTCAPBLPEN_Pos (17U)
#define RCC_APB4LPENR1_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR1_RTCAPBLPEN_Pos) /*!< 0x00020000 */
#define RCC_APB4LPENR1_RTCAPBLPEN RCC_APB4LPENR1_RTCAPBLPEN_Msk /*!< RTCAPB enable */
/**************** Bit definition for RCC_APB4LPENR2 register ****************/
#define RCC_APB4LPENR2_SYSCFGLPEN_Pos (0U)
#define RCC_APB4LPENR2_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR2_SYSCFGLPEN_Pos) /*!< 0x00000001 */
#define RCC_APB4LPENR2_SYSCFGLPEN RCC_APB4LPENR2_SYSCFGLPEN_Msk /*!< SYSCFG enable */
#define RCC_APB4LPENR2_BSECLPEN_Pos (1U)
#define RCC_APB4LPENR2_BSECLPEN_Msk (0x1UL << RCC_APB4LPENR2_BSECLPEN_Pos)/*!< 0x00000002 */
#define RCC_APB4LPENR2_BSECLPEN RCC_APB4LPENR2_BSECLPEN_Msk /*!< BSEC enable */
#define RCC_APB4LPENR2_DTSLPEN_Pos (2U)
#define RCC_APB4LPENR2_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR2_DTSLPEN_Pos) /*!< 0x00000004 */
#define RCC_APB4LPENR2_DTSLPEN RCC_APB4LPENR2_DTSLPEN_Msk /*!< DTS enable */
/**************** Bit definition for RCC_APB5LPENR register *****************/
#define RCC_APB5LPENR_LTDCLPEN_Pos (1U)
#define RCC_APB5LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB5LPENR_LTDCLPEN_Pos) /*!< 0x00000002 */
#define RCC_APB5LPENR_LTDCLPEN RCC_APB5LPENR_LTDCLPEN_Msk /*!< LTDC enable */
#define RCC_APB5LPENR_DCMIPPLPEN_Pos (2U)
#define RCC_APB5LPENR_DCMIPPLPEN_Msk (0x1UL << RCC_APB5LPENR_DCMIPPLPEN_Pos) /*!< 0x00000004 */
#define RCC_APB5LPENR_DCMIPPLPEN RCC_APB5LPENR_DCMIPPLPEN_Msk /*!< DCMIPP enable */
#define RCC_APB5LPENR_GFXTIMLPEN_Pos (4U)
#define RCC_APB5LPENR_GFXTIMLPEN_Msk (0x1UL << RCC_APB5LPENR_GFXTIMLPEN_Pos) /*!< 0x00000010 */
#define RCC_APB5LPENR_GFXTIMLPEN RCC_APB5LPENR_GFXTIMLPEN_Msk /*!< GFXTIM enable */
#define RCC_APB5LPENR_VENCLPEN_Pos (5U)
#define RCC_APB5LPENR_VENCLPEN_Msk (0x1UL << RCC_APB5LPENR_VENCLPEN_Pos) /*!< 0x00000020 */
#define RCC_APB5LPENR_VENCLPEN RCC_APB5LPENR_VENCLPEN_Msk /*!< VENC enable */
#define RCC_APB5LPENR_CSILPEN_Pos (6U)
#define RCC_APB5LPENR_CSILPEN_Msk (0x1UL << RCC_APB5LPENR_CSILPEN_Pos) /*!< 0x00000040 */
#define RCC_APB5LPENR_CSILPEN RCC_APB5LPENR_CSILPEN_Msk /*!< CSI enable */
/******************* Bit definition for RCC_RDCR register *******************/
#define RCC_RDCR_MRD_Pos (16U)
#define RCC_RDCR_MRD_Msk (0x1FUL << RCC_RDCR_MRD_Pos) /*!< 0x001F0000 */
#define RCC_RDCR_MRD RCC_RDCR_MRD_Msk /*!< Minimum reset duration */
/***************** Bit definition for RCC_SECCFGR0 register *****************/
#define RCC_SECCFGR0_LSISEC_Pos (0U)
#define RCC_SECCFGR0_LSISEC_Msk (0x1UL << RCC_SECCFGR0_LSISEC_Pos) /*!< 0x00000001 */
#define RCC_SECCFGR0_LSISEC RCC_SECCFGR0_LSISEC_Msk /*!< Secure protection of LSI oscillator configuration bits */
#define RCC_SECCFGR0_LSESEC_Pos (1U)
#define RCC_SECCFGR0_LSESEC_Msk (0x1UL << RCC_SECCFGR0_LSESEC_Pos) /*!< 0x00000002 */
#define RCC_SECCFGR0_LSESEC RCC_SECCFGR0_LSESEC_Msk /*!< Secure protection of LSE oscillator configuration bits */
#define RCC_SECCFGR0_MSISEC_Pos (2U)
#define RCC_SECCFGR0_MSISEC_Msk (0x1UL << RCC_SECCFGR0_MSISEC_Pos) /*!< 0x00000004 */
#define RCC_SECCFGR0_MSISEC RCC_SECCFGR0_MSISEC_Msk /*!< Secure protection of MSI oscillator configuration bits */
#define RCC_SECCFGR0_HSISEC_Pos (3U)
#define RCC_SECCFGR0_HSISEC_Msk (0x1UL << RCC_SECCFGR0_HSISEC_Pos) /*!< 0x00000008 */
#define RCC_SECCFGR0_HSISEC RCC_SECCFGR0_HSISEC_Msk /*!< Secure protection of HSI oscillator configuration bits */
#define RCC_SECCFGR0_HSESEC_Pos (4U)
#define RCC_SECCFGR0_HSESEC_Msk (0x1UL << RCC_SECCFGR0_HSESEC_Pos) /*!< 0x00000010 */
#define RCC_SECCFGR0_HSESEC RCC_SECCFGR0_HSESEC_Msk /*!< Secure protection of HSE oscillator configuration bits */
/**************** Bit definition for RCC_PRIVCFGR0 register *****************/
#define RCC_PRIVCFGR0_LSIPRIV_Pos (0U)
#define RCC_PRIVCFGR0_LSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSIPRIV_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGR0_LSIPRIV RCC_PRIVCFGR0_LSIPRIV_Msk /*!< Privileged protection of LSI oscillator configuration bits */
#define RCC_PRIVCFGR0_LSEPRIV_Pos (1U)
#define RCC_PRIVCFGR0_LSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_LSEPRIV_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGR0_LSEPRIV RCC_PRIVCFGR0_LSEPRIV_Msk /*!< Privileged protection of LSE oscillator configuration bits */
#define RCC_PRIVCFGR0_MSIPRIV_Pos (2U)
#define RCC_PRIVCFGR0_MSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_MSIPRIV_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGR0_MSIPRIV RCC_PRIVCFGR0_MSIPRIV_Msk /*!< Privileged protection of MSI oscillator configuration bits */
#define RCC_PRIVCFGR0_HSIPRIV_Pos (3U)
#define RCC_PRIVCFGR0_HSIPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSIPRIV_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGR0_HSIPRIV RCC_PRIVCFGR0_HSIPRIV_Msk /*!< Privileged protection of HSI oscillator configuration bits */
#define RCC_PRIVCFGR0_HSEPRIV_Pos (4U)
#define RCC_PRIVCFGR0_HSEPRIV_Msk (0x1UL << RCC_PRIVCFGR0_HSEPRIV_Pos) /*!< 0x00000010 */
#define RCC_PRIVCFGR0_HSEPRIV RCC_PRIVCFGR0_HSEPRIV_Msk /*!< Privileged protection of HSE oscillator configuration bits */
/**************** Bit definition for RCC_LOCKCFGR0 register *****************/
#define RCC_LOCKCFGR0_LSILOCK_Pos (0U)
#define RCC_LOCKCFGR0_LSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSILOCK_Pos) /*!< 0x00000001 */
#define RCC_LOCKCFGR0_LSILOCK RCC_LOCKCFGR0_LSILOCK_Msk /*!< Locked protection of LSI oscillator configuration bits */
#define RCC_LOCKCFGR0_LSELOCK_Pos (1U)
#define RCC_LOCKCFGR0_LSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_LSELOCK_Pos) /*!< 0x00000002 */
#define RCC_LOCKCFGR0_LSELOCK RCC_LOCKCFGR0_LSELOCK_Msk /*!< Locked protection of LSE oscillator configuration bits */
#define RCC_LOCKCFGR0_MSILOCK_Pos (2U)
#define RCC_LOCKCFGR0_MSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_MSILOCK_Pos) /*!< 0x00000004 */
#define RCC_LOCKCFGR0_MSILOCK RCC_LOCKCFGR0_MSILOCK_Msk /*!< Locked protection of MSI oscillator configuration bits */
#define RCC_LOCKCFGR0_HSILOCK_Pos (3U)
#define RCC_LOCKCFGR0_HSILOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSILOCK_Pos) /*!< 0x00000008 */
#define RCC_LOCKCFGR0_HSILOCK RCC_LOCKCFGR0_HSILOCK_Msk /*!< Locked protection of HSI oscillator configuration bits */
#define RCC_LOCKCFGR0_HSELOCK_Pos (4U)
#define RCC_LOCKCFGR0_HSELOCK_Msk (0x1UL << RCC_LOCKCFGR0_HSELOCK_Pos) /*!< 0x00000010 */
#define RCC_LOCKCFGR0_HSELOCK RCC_LOCKCFGR0_HSELOCK_Msk /*!< Locked protection of HSE oscillator configuration bits */
/***************** Bit definition for RCC_PUBCFGR0 register *****************/
#define RCC_PUBCFGR0_LSIPUB_Pos (0U)
#define RCC_PUBCFGR0_LSIPUB_Msk (0x1UL << RCC_PUBCFGR0_LSIPUB_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGR0_LSIPUB RCC_PUBCFGR0_LSIPUB_Msk /*!< Public protection of LSI oscillator configuration bits */
#define RCC_PUBCFGR0_LSEPUB_Pos (1U)
#define RCC_PUBCFGR0_LSEPUB_Msk (0x1UL << RCC_PUBCFGR0_LSEPUB_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGR0_LSEPUB RCC_PUBCFGR0_LSEPUB_Msk /*!< Public protection of LSE oscillator configuration bits */
#define RCC_PUBCFGR0_MSIPUB_Pos (2U)
#define RCC_PUBCFGR0_MSIPUB_Msk (0x1UL << RCC_PUBCFGR0_MSIPUB_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGR0_MSIPUB RCC_PUBCFGR0_MSIPUB_Msk /*!< Public protection of MSI oscillator configuration bits */
#define RCC_PUBCFGR0_HSIPUB_Pos (3U)
#define RCC_PUBCFGR0_HSIPUB_Msk (0x1UL << RCC_PUBCFGR0_HSIPUB_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGR0_HSIPUB RCC_PUBCFGR0_HSIPUB_Msk /*!< Public protection of HSI oscillator configuration bits */
#define RCC_PUBCFGR0_HSEPUB_Pos (4U)
#define RCC_PUBCFGR0_HSEPUB_Msk (0x1UL << RCC_PUBCFGR0_HSEPUB_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGR0_HSEPUB RCC_PUBCFGR0_HSEPUB_Msk /*!< Public protection of HSE oscillator configuration bits */
/***************** Bit definition for RCC_SECCFGR1 register *****************/
#define RCC_SECCFGR1_PLL1SEC_Pos (0U)
#define RCC_SECCFGR1_PLL1SEC_Msk (0x1UL << RCC_SECCFGR1_PLL1SEC_Pos) /*!< 0x00000001 */
#define RCC_SECCFGR1_PLL1SEC RCC_SECCFGR1_PLL1SEC_Msk /*!< Secure protection of PLL1 configuration bits */
#define RCC_SECCFGR1_PLL2SEC_Pos (1U)
#define RCC_SECCFGR1_PLL2SEC_Msk (0x1UL << RCC_SECCFGR1_PLL2SEC_Pos) /*!< 0x00000002 */
#define RCC_SECCFGR1_PLL2SEC RCC_SECCFGR1_PLL2SEC_Msk /*!< Secure protection of PLL2 configuration bits */
#define RCC_SECCFGR1_PLL3SEC_Pos (2U)
#define RCC_SECCFGR1_PLL3SEC_Msk (0x1UL << RCC_SECCFGR1_PLL3SEC_Pos) /*!< 0x00000004 */
#define RCC_SECCFGR1_PLL3SEC RCC_SECCFGR1_PLL3SEC_Msk /*!< Secure protection of PLL3 configuration bits */
#define RCC_SECCFGR1_PLL4SEC_Pos (3U)
#define RCC_SECCFGR1_PLL4SEC_Msk (0x1UL << RCC_SECCFGR1_PLL4SEC_Pos) /*!< 0x00000008 */
#define RCC_SECCFGR1_PLL4SEC RCC_SECCFGR1_PLL4SEC_Msk /*!< Secure protection of PLL4 configuration bits */
/**************** Bit definition for RCC_PRIVCFGR1 register *****************/
#define RCC_PRIVCFGR1_PLL1PRIV_Pos (0U)
#define RCC_PRIVCFGR1_PLL1PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL1PRIV_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGR1_PLL1PRIV RCC_PRIVCFGR1_PLL1PRIV_Msk /*!< Privileged protection of PLL1 configuration bits */
#define RCC_PRIVCFGR1_PLL2PRIV_Pos (1U)
#define RCC_PRIVCFGR1_PLL2PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL2PRIV_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGR1_PLL2PRIV RCC_PRIVCFGR1_PLL2PRIV_Msk /*!< Privileged protection of PLL2 configuration bits */
#define RCC_PRIVCFGR1_PLL3PRIV_Pos (2U)
#define RCC_PRIVCFGR1_PLL3PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL3PRIV_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGR1_PLL3PRIV RCC_PRIVCFGR1_PLL3PRIV_Msk /*!< Privileged protection of PLL3 configuration bits */
#define RCC_PRIVCFGR1_PLL4PRIV_Pos (3U)
#define RCC_PRIVCFGR1_PLL4PRIV_Msk (0x1UL << RCC_PRIVCFGR1_PLL4PRIV_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGR1_PLL4PRIV RCC_PRIVCFGR1_PLL4PRIV_Msk /*!< Privileged protection of PLL4 configuration bits */
/**************** Bit definition for RCC_LOCKCFGR1 register *****************/
#define RCC_LOCKCFGR1_PLL1LOCK_Pos (0U)
#define RCC_LOCKCFGR1_PLL1LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL1LOCK_Pos) /*!< 0x00000001 */
#define RCC_LOCKCFGR1_PLL1LOCK RCC_LOCKCFGR1_PLL1LOCK_Msk /*!< Locked protection of PLL1 configuration bits */
#define RCC_LOCKCFGR1_PLL2LOCK_Pos (1U)
#define RCC_LOCKCFGR1_PLL2LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL2LOCK_Pos) /*!< 0x00000002 */
#define RCC_LOCKCFGR1_PLL2LOCK RCC_LOCKCFGR1_PLL2LOCK_Msk /*!< Locked protection of PLL2 configuration bits */
#define RCC_LOCKCFGR1_PLL3LOCK_Pos (2U)
#define RCC_LOCKCFGR1_PLL3LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL3LOCK_Pos) /*!< 0x00000004 */
#define RCC_LOCKCFGR1_PLL3LOCK RCC_LOCKCFGR1_PLL3LOCK_Msk /*!< Locked protection of PLL3 configuration bits */
#define RCC_LOCKCFGR1_PLL4LOCK_Pos (3U)
#define RCC_LOCKCFGR1_PLL4LOCK_Msk (0x1UL << RCC_LOCKCFGR1_PLL4LOCK_Pos) /*!< 0x00000008 */
#define RCC_LOCKCFGR1_PLL4LOCK RCC_LOCKCFGR1_PLL4LOCK_Msk /*!< Locked protection of PLL4 configuration bits */
/***************** Bit definition for RCC_PUBCFGR1 register *****************/
#define RCC_PUBCFGR1_PLL1PUB_Pos (0U)
#define RCC_PUBCFGR1_PLL1PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL1PUB_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGR1_PLL1PUB RCC_PUBCFGR1_PLL1PUB_Msk /*!< Public protection of PLL1 configuration bits */
#define RCC_PUBCFGR1_PLL2PUB_Pos (1U)
#define RCC_PUBCFGR1_PLL2PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL2PUB_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGR1_PLL2PUB RCC_PUBCFGR1_PLL2PUB_Msk /*!< Public protection of PLL2 configuration bits */
#define RCC_PUBCFGR1_PLL3PUB_Pos (2U)
#define RCC_PUBCFGR1_PLL3PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL3PUB_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGR1_PLL3PUB RCC_PUBCFGR1_PLL3PUB_Msk /*!< Public protection of PLL3 configuration bits */
#define RCC_PUBCFGR1_PLL4PUB_Pos (3U)
#define RCC_PUBCFGR1_PLL4PUB_Msk (0x1UL << RCC_PUBCFGR1_PLL4PUB_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGR1_PLL4PUB RCC_PUBCFGR1_PLL4PUB_Msk /*!< Public protection of PLL4 configuration bits */
/***************** Bit definition for RCC_SECCFGR2 register *****************/
#define RCC_SECCFGR2_IC1SEC_Pos (0U)
#define RCC_SECCFGR2_IC1SEC_Msk (0x1UL << RCC_SECCFGR2_IC1SEC_Pos) /*!< 0x00000001 */
#define RCC_SECCFGR2_IC1SEC RCC_SECCFGR2_IC1SEC_Msk /*!< Secure protection of IC1 divider configuration bits */
#define RCC_SECCFGR2_IC2SEC_Pos (1U)
#define RCC_SECCFGR2_IC2SEC_Msk (0x1UL << RCC_SECCFGR2_IC2SEC_Pos) /*!< 0x00000002 */
#define RCC_SECCFGR2_IC2SEC RCC_SECCFGR2_IC2SEC_Msk /*!< Secure protection of IC2 divider configuration bits */
#define RCC_SECCFGR2_IC3SEC_Pos (2U)
#define RCC_SECCFGR2_IC3SEC_Msk (0x1UL << RCC_SECCFGR2_IC3SEC_Pos) /*!< 0x00000004 */
#define RCC_SECCFGR2_IC3SEC RCC_SECCFGR2_IC3SEC_Msk /*!< Secure protection of IC3 divider configuration bits */
#define RCC_SECCFGR2_IC4SEC_Pos (3U)
#define RCC_SECCFGR2_IC4SEC_Msk (0x1UL << RCC_SECCFGR2_IC4SEC_Pos) /*!< 0x00000008 */
#define RCC_SECCFGR2_IC4SEC RCC_SECCFGR2_IC4SEC_Msk /*!< Secure protection of IC4 divider configuration bits */
#define RCC_SECCFGR2_IC5SEC_Pos (4U)
#define RCC_SECCFGR2_IC5SEC_Msk (0x1UL << RCC_SECCFGR2_IC5SEC_Pos) /*!< 0x00000010 */
#define RCC_SECCFGR2_IC5SEC RCC_SECCFGR2_IC5SEC_Msk /*!< Secure protection of IC5 divider configuration bits */
#define RCC_SECCFGR2_IC6SEC_Pos (5U)
#define RCC_SECCFGR2_IC6SEC_Msk (0x1UL << RCC_SECCFGR2_IC6SEC_Pos) /*!< 0x00000020 */
#define RCC_SECCFGR2_IC6SEC RCC_SECCFGR2_IC6SEC_Msk /*!< Secure protection of IC6 divider configuration bits */
#define RCC_SECCFGR2_IC7SEC_Pos (6U)
#define RCC_SECCFGR2_IC7SEC_Msk (0x1UL << RCC_SECCFGR2_IC7SEC_Pos) /*!< 0x00000040 */
#define RCC_SECCFGR2_IC7SEC RCC_SECCFGR2_IC7SEC_Msk /*!< Secure protection of IC7 divider configuration bits */
#define RCC_SECCFGR2_IC8SEC_Pos (7U)
#define RCC_SECCFGR2_IC8SEC_Msk (0x1UL << RCC_SECCFGR2_IC8SEC_Pos) /*!< 0x00000080 */
#define RCC_SECCFGR2_IC8SEC RCC_SECCFGR2_IC8SEC_Msk /*!< Secure protection of IC8 divider configuration bits */
#define RCC_SECCFGR2_IC9SEC_Pos (8U)
#define RCC_SECCFGR2_IC9SEC_Msk (0x1UL << RCC_SECCFGR2_IC9SEC_Pos) /*!< 0x00000100 */
#define RCC_SECCFGR2_IC9SEC RCC_SECCFGR2_IC9SEC_Msk /*!< Secure protection of IC9 divider configuration bits */
#define RCC_SECCFGR2_IC10SEC_Pos (9U)
#define RCC_SECCFGR2_IC10SEC_Msk (0x1UL << RCC_SECCFGR2_IC10SEC_Pos) /*!< 0x00000200 */
#define RCC_SECCFGR2_IC10SEC RCC_SECCFGR2_IC10SEC_Msk /*!< Secure protection of IC10 divider configuration bits */
#define RCC_SECCFGR2_IC11SEC_Pos (10U)
#define RCC_SECCFGR2_IC11SEC_Msk (0x1UL << RCC_SECCFGR2_IC11SEC_Pos) /*!< 0x00000400 */
#define RCC_SECCFGR2_IC11SEC RCC_SECCFGR2_IC11SEC_Msk /*!< Secure protection of IC11 divider configuration bits */
#define RCC_SECCFGR2_IC12SEC_Pos (11U)
#define RCC_SECCFGR2_IC12SEC_Msk (0x1UL << RCC_SECCFGR2_IC12SEC_Pos) /*!< 0x00000800 */
#define RCC_SECCFGR2_IC12SEC RCC_SECCFGR2_IC12SEC_Msk /*!< Secure protection of IC12 divider configuration bits */
#define RCC_SECCFGR2_IC13SEC_Pos (12U)
#define RCC_SECCFGR2_IC13SEC_Msk (0x1UL << RCC_SECCFGR2_IC13SEC_Pos) /*!< 0x00001000 */
#define RCC_SECCFGR2_IC13SEC RCC_SECCFGR2_IC13SEC_Msk /*!< Secure protection of IC13 divider configuration bits */
#define RCC_SECCFGR2_IC14SEC_Pos (13U)
#define RCC_SECCFGR2_IC14SEC_Msk (0x1UL << RCC_SECCFGR2_IC14SEC_Pos) /*!< 0x00002000 */
#define RCC_SECCFGR2_IC14SEC RCC_SECCFGR2_IC14SEC_Msk /*!< Secure protection of IC14 divider configuration bits */
#define RCC_SECCFGR2_IC15SEC_Pos (14U)
#define RCC_SECCFGR2_IC15SEC_Msk (0x1UL << RCC_SECCFGR2_IC15SEC_Pos) /*!< 0x00004000 */
#define RCC_SECCFGR2_IC15SEC RCC_SECCFGR2_IC15SEC_Msk /*!< Secure protection of IC15 divider configuration bits */
#define RCC_SECCFGR2_IC16SEC_Pos (15U)
#define RCC_SECCFGR2_IC16SEC_Msk (0x1UL << RCC_SECCFGR2_IC16SEC_Pos) /*!< 0x00008000 */
#define RCC_SECCFGR2_IC16SEC RCC_SECCFGR2_IC16SEC_Msk /*!< Secure protection of IC16 divider configuration bits */
#define RCC_SECCFGR2_IC17SEC_Pos (16U)
#define RCC_SECCFGR2_IC17SEC_Msk (0x1UL << RCC_SECCFGR2_IC17SEC_Pos) /*!< 0x00010000 */
#define RCC_SECCFGR2_IC17SEC RCC_SECCFGR2_IC17SEC_Msk /*!< Secure protection of IC17 divider configuration bits */
#define RCC_SECCFGR2_IC18SEC_Pos (17U)
#define RCC_SECCFGR2_IC18SEC_Msk (0x1UL << RCC_SECCFGR2_IC18SEC_Pos) /*!< 0x00020000 */
#define RCC_SECCFGR2_IC18SEC RCC_SECCFGR2_IC18SEC_Msk /*!< Secure protection of IC18 divider configuration bits */
#define RCC_SECCFGR2_IC19SEC_Pos (18U)
#define RCC_SECCFGR2_IC19SEC_Msk (0x1UL << RCC_SECCFGR2_IC19SEC_Pos) /*!< 0x00040000 */
#define RCC_SECCFGR2_IC19SEC RCC_SECCFGR2_IC19SEC_Msk /*!< Secure protection of IC19 divider configuration bits */
#define RCC_SECCFGR2_IC20SEC_Pos (19U)
#define RCC_SECCFGR2_IC20SEC_Msk (0x1UL << RCC_SECCFGR2_IC20SEC_Pos) /*!< 0x00080000 */
#define RCC_SECCFGR2_IC20SEC RCC_SECCFGR2_IC20SEC_Msk /*!< Secure protection of IC20 divider configuration bits */
/**************** Bit definition for RCC_PRIVCFGR2 register *****************/
#define RCC_PRIVCFGR2_IC1PRIV_Pos (0U)
#define RCC_PRIVCFGR2_IC1PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC1PRIV_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGR2_IC1PRIV RCC_PRIVCFGR2_IC1PRIV_Msk /*!< Privileged protection of IC1 divider configuration bits */
#define RCC_PRIVCFGR2_IC2PRIV_Pos (1U)
#define RCC_PRIVCFGR2_IC2PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC2PRIV_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGR2_IC2PRIV RCC_PRIVCFGR2_IC2PRIV_Msk /*!< Privileged protection of IC2 divider configuration bits */
#define RCC_PRIVCFGR2_IC3PRIV_Pos (2U)
#define RCC_PRIVCFGR2_IC3PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC3PRIV_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGR2_IC3PRIV RCC_PRIVCFGR2_IC3PRIV_Msk /*!< Privileged protection of IC3 divider configuration bits */
#define RCC_PRIVCFGR2_IC4PRIV_Pos (3U)
#define RCC_PRIVCFGR2_IC4PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC4PRIV_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGR2_IC4PRIV RCC_PRIVCFGR2_IC4PRIV_Msk /*!< Privileged protection of IC4 divider configuration bits */
#define RCC_PRIVCFGR2_IC5PRIV_Pos (4U)
#define RCC_PRIVCFGR2_IC5PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC5PRIV_Pos) /*!< 0x00000010 */
#define RCC_PRIVCFGR2_IC5PRIV RCC_PRIVCFGR2_IC5PRIV_Msk /*!< Privileged protection of IC5 divider configuration bits */
#define RCC_PRIVCFGR2_IC6PRIV_Pos (5U)
#define RCC_PRIVCFGR2_IC6PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC6PRIV_Pos) /*!< 0x00000020 */
#define RCC_PRIVCFGR2_IC6PRIV RCC_PRIVCFGR2_IC6PRIV_Msk /*!< Privileged protection of IC6 divider configuration bits */
#define RCC_PRIVCFGR2_IC7PRIV_Pos (6U)
#define RCC_PRIVCFGR2_IC7PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC7PRIV_Pos) /*!< 0x00000040 */
#define RCC_PRIVCFGR2_IC7PRIV RCC_PRIVCFGR2_IC7PRIV_Msk /*!< Privileged protection of IC7 divider configuration bits */
#define RCC_PRIVCFGR2_IC8PRIV_Pos (7U)
#define RCC_PRIVCFGR2_IC8PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC8PRIV_Pos) /*!< 0x00000080 */
#define RCC_PRIVCFGR2_IC8PRIV RCC_PRIVCFGR2_IC8PRIV_Msk /*!< Privileged protection of IC8 divider configuration bits */
#define RCC_PRIVCFGR2_IC9PRIV_Pos (8U)
#define RCC_PRIVCFGR2_IC9PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC9PRIV_Pos) /*!< 0x00000100 */
#define RCC_PRIVCFGR2_IC9PRIV RCC_PRIVCFGR2_IC9PRIV_Msk /*!< Privileged protection of IC9 divider configuration bits */
#define RCC_PRIVCFGR2_IC10PRIV_Pos (9U)
#define RCC_PRIVCFGR2_IC10PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC10PRIV_Pos) /*!< 0x00000200 */
#define RCC_PRIVCFGR2_IC10PRIV RCC_PRIVCFGR2_IC10PRIV_Msk /*!< Privileged protection of IC10 divider configuration bits */
#define RCC_PRIVCFGR2_IC11PRIV_Pos (10U)
#define RCC_PRIVCFGR2_IC11PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC11PRIV_Pos) /*!< 0x00000400 */
#define RCC_PRIVCFGR2_IC11PRIV RCC_PRIVCFGR2_IC11PRIV_Msk /*!< Privileged protection of IC11 divider configuration bits */
#define RCC_PRIVCFGR2_IC12PRIV_Pos (11U)
#define RCC_PRIVCFGR2_IC12PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC12PRIV_Pos) /*!< 0x00000800 */
#define RCC_PRIVCFGR2_IC12PRIV RCC_PRIVCFGR2_IC12PRIV_Msk /*!< Privileged protection of IC12 divider configuration bits */
#define RCC_PRIVCFGR2_IC13PRIV_Pos (12U)
#define RCC_PRIVCFGR2_IC13PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC13PRIV_Pos) /*!< 0x00001000 */
#define RCC_PRIVCFGR2_IC13PRIV RCC_PRIVCFGR2_IC13PRIV_Msk /*!< Privileged protection of IC13 divider configuration bits */
#define RCC_PRIVCFGR2_IC14PRIV_Pos (13U)
#define RCC_PRIVCFGR2_IC14PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC14PRIV_Pos) /*!< 0x00002000 */
#define RCC_PRIVCFGR2_IC14PRIV RCC_PRIVCFGR2_IC14PRIV_Msk /*!< Privileged protection of IC14 divider configuration bits */
#define RCC_PRIVCFGR2_IC15PRIV_Pos (14U)
#define RCC_PRIVCFGR2_IC15PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC15PRIV_Pos) /*!< 0x00004000 */
#define RCC_PRIVCFGR2_IC15PRIV RCC_PRIVCFGR2_IC15PRIV_Msk /*!< Privileged protection of IC15 divider configuration bits */
#define RCC_PRIVCFGR2_IC16PRIV_Pos (15U)
#define RCC_PRIVCFGR2_IC16PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC16PRIV_Pos) /*!< 0x00008000 */
#define RCC_PRIVCFGR2_IC16PRIV RCC_PRIVCFGR2_IC16PRIV_Msk /*!< Privileged protection of IC16 divider configuration bits */
#define RCC_PRIVCFGR2_IC17PRIV_Pos (16U)
#define RCC_PRIVCFGR2_IC17PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC17PRIV_Pos) /*!< 0x00010000 */
#define RCC_PRIVCFGR2_IC17PRIV RCC_PRIVCFGR2_IC17PRIV_Msk /*!< Privileges protection of IC17 divider configuration bits */
#define RCC_PRIVCFGR2_IC18PRIV_Pos (17U)
#define RCC_PRIVCFGR2_IC18PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC18PRIV_Pos) /*!< 0x00020000 */
#define RCC_PRIVCFGR2_IC18PRIV RCC_PRIVCFGR2_IC18PRIV_Msk /*!< Privilege protection of IC18 divider configuration bits */
#define RCC_PRIVCFGR2_IC19PRIV_Pos (18U)
#define RCC_PRIVCFGR2_IC19PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC19PRIV_Pos) /*!< 0x00040000 */
#define RCC_PRIVCFGR2_IC19PRIV RCC_PRIVCFGR2_IC19PRIV_Msk /*!< Privileged protection of IC19 divider configuration bits */
#define RCC_PRIVCFGR2_IC20PRIV_Pos (19U)
#define RCC_PRIVCFGR2_IC20PRIV_Msk (0x1UL << RCC_PRIVCFGR2_IC20PRIV_Pos) /*!< 0x00080000 */
#define RCC_PRIVCFGR2_IC20PRIV RCC_PRIVCFGR2_IC20PRIV_Msk /*!< Privileged protection of IC20 divider configuration bits */
/**************** Bit definition for RCC_LOCKCFGR2 register *****************/
#define RCC_LOCKCFGR2_IC1LOCK_Pos (0U)
#define RCC_LOCKCFGR2_IC1LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC1LOCK_Pos) /*!< 0x00000001 */
#define RCC_LOCKCFGR2_IC1LOCK RCC_LOCKCFGR2_IC1LOCK_Msk /*!< Locked protection of IC1 divider configuration bits */
#define RCC_LOCKCFGR2_IC2LOCK_Pos (1U)
#define RCC_LOCKCFGR2_IC2LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC2LOCK_Pos) /*!< 0x00000002 */
#define RCC_LOCKCFGR2_IC2LOCK RCC_LOCKCFGR2_IC2LOCK_Msk /*!< Locked protection of IC2 divider configuration bits */
#define RCC_LOCKCFGR2_IC3LOCK_Pos (2U)
#define RCC_LOCKCFGR2_IC3LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC3LOCK_Pos) /*!< 0x00000004 */
#define RCC_LOCKCFGR2_IC3LOCK RCC_LOCKCFGR2_IC3LOCK_Msk /*!< Locked protection of IC3 divider configuration bits */
#define RCC_LOCKCFGR2_IC4LOCK_Pos (3U)
#define RCC_LOCKCFGR2_IC4LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC4LOCK_Pos) /*!< 0x00000008 */
#define RCC_LOCKCFGR2_IC4LOCK RCC_LOCKCFGR2_IC4LOCK_Msk /*!< Locked protection of IC4 divider configuration bits */
#define RCC_LOCKCFGR2_IC5LOCK_Pos (4U)
#define RCC_LOCKCFGR2_IC5LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC5LOCK_Pos) /*!< 0x00000010 */
#define RCC_LOCKCFGR2_IC5LOCK RCC_LOCKCFGR2_IC5LOCK_Msk /*!< Locked protection of IC5 divider configuration bits */
#define RCC_LOCKCFGR2_IC6LOCK_Pos (5U)
#define RCC_LOCKCFGR2_IC6LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC6LOCK_Pos) /*!< 0x00000020 */
#define RCC_LOCKCFGR2_IC6LOCK RCC_LOCKCFGR2_IC6LOCK_Msk /*!< Locked protection of IC6 divider configuration bits */
#define RCC_LOCKCFGR2_IC7LOCK_Pos (6U)
#define RCC_LOCKCFGR2_IC7LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC7LOCK_Pos) /*!< 0x00000040 */
#define RCC_LOCKCFGR2_IC7LOCK RCC_LOCKCFGR2_IC7LOCK_Msk /*!< Locked protection of IC7 divider configuration bits */
#define RCC_LOCKCFGR2_IC8LOCK_Pos (7U)
#define RCC_LOCKCFGR2_IC8LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC8LOCK_Pos) /*!< 0x00000080 */
#define RCC_LOCKCFGR2_IC8LOCK RCC_LOCKCFGR2_IC8LOCK_Msk /*!< Locked protection of IC8 divider configuration bits */
#define RCC_LOCKCFGR2_IC9LOCK_Pos (8U)
#define RCC_LOCKCFGR2_IC9LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC9LOCK_Pos) /*!< 0x00000100 */
#define RCC_LOCKCFGR2_IC9LOCK RCC_LOCKCFGR2_IC9LOCK_Msk /*!< Locked protection of IC9 divider configuration bits */
#define RCC_LOCKCFGR2_IC10LOCK_Pos (9U)
#define RCC_LOCKCFGR2_IC10LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC10LOCK_Pos) /*!< 0x00000200 */
#define RCC_LOCKCFGR2_IC10LOCK RCC_LOCKCFGR2_IC10LOCK_Msk /*!< Locked protection of IC10 divider configuration bits */
#define RCC_LOCKCFGR2_IC11LOCK_Pos (10U)
#define RCC_LOCKCFGR2_IC11LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC11LOCK_Pos) /*!< 0x00000400 */
#define RCC_LOCKCFGR2_IC11LOCK RCC_LOCKCFGR2_IC11LOCK_Msk /*!< Locked protection of IC11 divider configuration bits */
#define RCC_LOCKCFGR2_IC12LOCK_Pos (11U)
#define RCC_LOCKCFGR2_IC12LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC12LOCK_Pos) /*!< 0x00000800 */
#define RCC_LOCKCFGR2_IC12LOCK RCC_LOCKCFGR2_IC12LOCK_Msk /*!< Locked protection of IC12 divider configuration bits */
#define RCC_LOCKCFGR2_IC13LOCK_Pos (12U)
#define RCC_LOCKCFGR2_IC13LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC13LOCK_Pos) /*!< 0x00001000 */
#define RCC_LOCKCFGR2_IC13LOCK RCC_LOCKCFGR2_IC13LOCK_Msk /*!< Locked protection of IC13 divider configuration bits */
#define RCC_LOCKCFGR2_IC14LOCK_Pos (13U)
#define RCC_LOCKCFGR2_IC14LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC14LOCK_Pos) /*!< 0x00002000 */
#define RCC_LOCKCFGR2_IC14LOCK RCC_LOCKCFGR2_IC14LOCK_Msk /*!< Locked protection of IC14 divider configuration bits */
#define RCC_LOCKCFGR2_IC15LOCK_Pos (14U)
#define RCC_LOCKCFGR2_IC15LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC15LOCK_Pos) /*!< 0x00004000 */
#define RCC_LOCKCFGR2_IC15LOCK RCC_LOCKCFGR2_IC15LOCK_Msk /*!< Locked protection of IC15 divider configuration bits */
#define RCC_LOCKCFGR2_IC16LOCK_Pos (15U)
#define RCC_LOCKCFGR2_IC16LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC16LOCK_Pos) /*!< 0x00008000 */
#define RCC_LOCKCFGR2_IC16LOCK RCC_LOCKCFGR2_IC16LOCK_Msk /*!< Locked protection of IC16 divider configuration bits */
#define RCC_LOCKCFGR2_IC17LOCK_Pos (16U)
#define RCC_LOCKCFGR2_IC17LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC17LOCK_Pos) /*!< 0x00010000 */
#define RCC_LOCKCFGR2_IC17LOCK RCC_LOCKCFGR2_IC17LOCK_Msk /*!< Locked protection of IC17 divider configuration bits */
#define RCC_LOCKCFGR2_IC18LOCK_Pos (17U)
#define RCC_LOCKCFGR2_IC18LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC18LOCK_Pos) /*!< 0x00020000 */
#define RCC_LOCKCFGR2_IC18LOCK RCC_LOCKCFGR2_IC18LOCK_Msk /*!< Locked protection of IC18 divider configuration bits */
#define RCC_LOCKCFGR2_IC19LOCK_Pos (18U)
#define RCC_LOCKCFGR2_IC19LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC19LOCK_Pos) /*!< 0x00040000 */
#define RCC_LOCKCFGR2_IC19LOCK RCC_LOCKCFGR2_IC19LOCK_Msk /*!< Locked protection of IC19 divider configuration bits */
#define RCC_LOCKCFGR2_IC20LOCK_Pos (19U)
#define RCC_LOCKCFGR2_IC20LOCK_Msk (0x1UL << RCC_LOCKCFGR2_IC20LOCK_Pos) /*!< 0x00080000 */
#define RCC_LOCKCFGR2_IC20LOCK RCC_LOCKCFGR2_IC20LOCK_Msk /*!< Locked protection of IC20 divider configuration bits */
/***************** Bit definition for RCC_PUBCFGR2 register *****************/
#define RCC_PUBCFGR2_IC1PUB_Pos (0U)
#define RCC_PUBCFGR2_IC1PUB_Msk (0x1UL << RCC_PUBCFGR2_IC1PUB_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGR2_IC1PUB RCC_PUBCFGR2_IC1PUB_Msk /*!< Public protection of IC1 divider configuration bits */
#define RCC_PUBCFGR2_IC2PUB_Pos (1U)
#define RCC_PUBCFGR2_IC2PUB_Msk (0x1UL << RCC_PUBCFGR2_IC2PUB_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGR2_IC2PUB RCC_PUBCFGR2_IC2PUB_Msk /*!< Public protection of IC2 divider configuration bits */
#define RCC_PUBCFGR2_IC3PUB_Pos (2U)
#define RCC_PUBCFGR2_IC3PUB_Msk (0x1UL << RCC_PUBCFGR2_IC3PUB_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGR2_IC3PUB RCC_PUBCFGR2_IC3PUB_Msk /*!< Public protection of IC3 divider configuration bits */
#define RCC_PUBCFGR2_IC4PUB_Pos (3U)
#define RCC_PUBCFGR2_IC4PUB_Msk (0x1UL << RCC_PUBCFGR2_IC4PUB_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGR2_IC4PUB RCC_PUBCFGR2_IC4PUB_Msk /*!< Public protection of IC4 divider configuration bits */
#define RCC_PUBCFGR2_IC5PUB_Pos (4U)
#define RCC_PUBCFGR2_IC5PUB_Msk (0x1UL << RCC_PUBCFGR2_IC5PUB_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGR2_IC5PUB RCC_PUBCFGR2_IC5PUB_Msk /*!< Public protection of IC5 divider configuration bits */
#define RCC_PUBCFGR2_IC6PUB_Pos (5U)
#define RCC_PUBCFGR2_IC6PUB_Msk (0x1UL << RCC_PUBCFGR2_IC6PUB_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGR2_IC6PUB RCC_PUBCFGR2_IC6PUB_Msk /*!< Public protection of IC6 divider configuration bits */
#define RCC_PUBCFGR2_IC7PUB_Pos (6U)
#define RCC_PUBCFGR2_IC7PUB_Msk (0x1UL << RCC_PUBCFGR2_IC7PUB_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGR2_IC7PUB RCC_PUBCFGR2_IC7PUB_Msk /*!< Public protection of IC7 divider configuration bits */
#define RCC_PUBCFGR2_IC8PUB_Pos (7U)
#define RCC_PUBCFGR2_IC8PUB_Msk (0x1UL << RCC_PUBCFGR2_IC8PUB_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGR2_IC8PUB RCC_PUBCFGR2_IC8PUB_Msk /*!< Public protection of IC8 divider configuration bits */
#define RCC_PUBCFGR2_IC9PUB_Pos (8U)
#define RCC_PUBCFGR2_IC9PUB_Msk (0x1UL << RCC_PUBCFGR2_IC9PUB_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGR2_IC9PUB RCC_PUBCFGR2_IC9PUB_Msk /*!< Public protection of IC9 divider configuration bits */
#define RCC_PUBCFGR2_IC10PUB_Pos (9U)
#define RCC_PUBCFGR2_IC10PUB_Msk (0x1UL << RCC_PUBCFGR2_IC10PUB_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGR2_IC10PUB RCC_PUBCFGR2_IC10PUB_Msk /*!< Public protection of IC10 divider configuration bits */
#define RCC_PUBCFGR2_IC11PUB_Pos (10U)
#define RCC_PUBCFGR2_IC11PUB_Msk (0x1UL << RCC_PUBCFGR2_IC11PUB_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGR2_IC11PUB RCC_PUBCFGR2_IC11PUB_Msk /*!< Public protection of IC11 divider configuration bits */
#define RCC_PUBCFGR2_IC12PUB_Pos (11U)
#define RCC_PUBCFGR2_IC12PUB_Msk (0x1UL << RCC_PUBCFGR2_IC12PUB_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGR2_IC12PUB RCC_PUBCFGR2_IC12PUB_Msk /*!< Public protection of IC12 divider configuration bits */
#define RCC_PUBCFGR2_IC13PUB_Pos (12U)
#define RCC_PUBCFGR2_IC13PUB_Msk (0x1UL << RCC_PUBCFGR2_IC13PUB_Pos) /*!< 0x00001000 */
#define RCC_PUBCFGR2_IC13PUB RCC_PUBCFGR2_IC13PUB_Msk /*!< Public protection of IC13 divider configuration bits */
#define RCC_PUBCFGR2_IC14PUB_Pos (13U)
#define RCC_PUBCFGR2_IC14PUB_Msk (0x1UL << RCC_PUBCFGR2_IC14PUB_Pos) /*!< 0x00002000 */
#define RCC_PUBCFGR2_IC14PUB RCC_PUBCFGR2_IC14PUB_Msk /*!< Public protection of IC14 divider configuration bits */
#define RCC_PUBCFGR2_IC15PUB_Pos (14U)
#define RCC_PUBCFGR2_IC15PUB_Msk (0x1UL << RCC_PUBCFGR2_IC15PUB_Pos) /*!< 0x00004000 */
#define RCC_PUBCFGR2_IC15PUB RCC_PUBCFGR2_IC15PUB_Msk /*!< Public protection of IC15 divider configuration bits */
#define RCC_PUBCFGR2_IC16PUB_Pos (15U)
#define RCC_PUBCFGR2_IC16PUB_Msk (0x1UL << RCC_PUBCFGR2_IC16PUB_Pos) /*!< 0x00008000 */
#define RCC_PUBCFGR2_IC16PUB RCC_PUBCFGR2_IC16PUB_Msk /*!< Public protection of IC16 divider configuration bits */
#define RCC_PUBCFGR2_IC17PUB_Pos (16U)
#define RCC_PUBCFGR2_IC17PUB_Msk (0x1UL << RCC_PUBCFGR2_IC17PUB_Pos) /*!< 0x00010000 */
#define RCC_PUBCFGR2_IC17PUB RCC_PUBCFGR2_IC17PUB_Msk /*!< Public protection of IC17 divider configuration bits */
#define RCC_PUBCFGR2_IC18PUB_Pos (17U)
#define RCC_PUBCFGR2_IC18PUB_Msk (0x1UL << RCC_PUBCFGR2_IC18PUB_Pos) /*!< 0x00020000 */
#define RCC_PUBCFGR2_IC18PUB RCC_PUBCFGR2_IC18PUB_Msk /*!< Public protection of IC18 divider configuration bits */
#define RCC_PUBCFGR2_IC19PUB_Pos (18U)
#define RCC_PUBCFGR2_IC19PUB_Msk (0x1UL << RCC_PUBCFGR2_IC19PUB_Pos) /*!< 0x00040000 */
#define RCC_PUBCFGR2_IC19PUB RCC_PUBCFGR2_IC19PUB_Msk /*!< Public protection of IC19 divider configuration bits */
#define RCC_PUBCFGR2_IC20PUB_Pos (19U)
#define RCC_PUBCFGR2_IC20PUB_Msk (0x1UL << RCC_PUBCFGR2_IC20PUB_Pos) /*!< 0x00080000 */
#define RCC_PUBCFGR2_IC20PUB RCC_PUBCFGR2_IC20PUB_Msk /*!< Public protection of IC20 divider configuration bits */
/***************** Bit definition for RCC_SECCFGR3 register *****************/
#define RCC_SECCFGR3_MODSEC_Pos (0U)
#define RCC_SECCFGR3_MODSEC_Msk (0x1UL << RCC_SECCFGR3_MODSEC_Pos) /*!< 0x00000001 */
#define RCC_SECCFGR3_MODSEC RCC_SECCFGR3_MODSEC_Msk /*!< Secure protection of MOD system configuration bits */
#define RCC_SECCFGR3_SYSSEC_Pos (1U)
#define RCC_SECCFGR3_SYSSEC_Msk (0x1UL << RCC_SECCFGR3_SYSSEC_Pos) /*!< 0x00000002 */
#define RCC_SECCFGR3_SYSSEC RCC_SECCFGR3_SYSSEC_Msk /*!< Secure protection of SYS system configuration bit */
#define RCC_SECCFGR3_BUSSEC_Pos (2U)
#define RCC_SECCFGR3_BUSSEC_Msk (0x1UL << RCC_SECCFGR3_BUSSEC_Pos) /*!< 0x00000004 */
#define RCC_SECCFGR3_BUSSEC RCC_SECCFGR3_BUSSEC_Msk /*!< Secure protection of BUS system configuration bits */
#define RCC_SECCFGR3_PERSEC_Pos (3U)
#define RCC_SECCFGR3_PERSEC_Msk (0x1UL << RCC_SECCFGR3_PERSEC_Pos) /*!< 0x00000008 */
#define RCC_SECCFGR3_PERSEC RCC_SECCFGR3_PERSEC_Msk /*!< Secure protection of PER system configuration bits */
#define RCC_SECCFGR3_INTSEC_Pos (4U)
#define RCC_SECCFGR3_INTSEC_Msk (0x1UL << RCC_SECCFGR3_INTSEC_Pos) /*!< 0x00000010 */
#define RCC_SECCFGR3_INTSEC RCC_SECCFGR3_INTSEC_Msk /*!< Secure protection of INT system configuration bits */
#define RCC_SECCFGR3_RSTSEC_Pos (5U)
#define RCC_SECCFGR3_RSTSEC_Msk (0x1UL << RCC_SECCFGR3_RSTSEC_Pos) /*!< 0x00000020 */
#define RCC_SECCFGR3_RSTSEC RCC_SECCFGR3_RSTSEC_Msk /*!< Secure protection of RST system configuration bits */
/**************** Bit definition for RCC_PRIVCFGR3 register *****************/
#define RCC_PRIVCFGR3_MODPRIV_Pos (0U)
#define RCC_PRIVCFGR3_MODPRIV_Msk (0x1UL << RCC_PRIVCFGR3_MODPRIV_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGR3_MODPRIV RCC_PRIVCFGR3_MODPRIV_Msk /*!< Privileged protection of MOD system configuration bits */
#define RCC_PRIVCFGR3_SYSPRIV_Pos (1U)
#define RCC_PRIVCFGR3_SYSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_SYSPRIV_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGR3_SYSPRIV RCC_PRIVCFGR3_SYSPRIV_Msk /*!< Privileged protection of SYS system configuration bits */
#define RCC_PRIVCFGR3_BUSPRIV_Pos (2U)
#define RCC_PRIVCFGR3_BUSPRIV_Msk (0x1UL << RCC_PRIVCFGR3_BUSPRIV_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGR3_BUSPRIV RCC_PRIVCFGR3_BUSPRIV_Msk /*!< Privileged protection of BUS system configuration bits */
#define RCC_PRIVCFGR3_PERPRIV_Pos (3U)
#define RCC_PRIVCFGR3_PERPRIV_Msk (0x1UL << RCC_PRIVCFGR3_PERPRIV_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGR3_PERPRIV RCC_PRIVCFGR3_PERPRIV_Msk /*!< Privileged protection of PER system configuration bits */
#define RCC_PRIVCFGR3_INTPRIV_Pos (4U)
#define RCC_PRIVCFGR3_INTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_INTPRIV_Pos) /*!< 0x00000010 */
#define RCC_PRIVCFGR3_INTPRIV RCC_PRIVCFGR3_INTPRIV_Msk /*!< Privileged protection of INT system configuration bits */
#define RCC_PRIVCFGR3_RSTPRIV_Pos (5U)
#define RCC_PRIVCFGR3_RSTPRIV_Msk (0x1UL << RCC_PRIVCFGR3_RSTPRIV_Pos) /*!< 0x00000020 */
#define RCC_PRIVCFGR3_RSTPRIV RCC_PRIVCFGR3_RSTPRIV_Msk /*!< Privileged protection of RST system configuration bits */
/**************** Bit definition for RCC_LOCKCFGR3 register *****************/
#define RCC_LOCKCFGR3_MODLOCK_Pos (0U)
#define RCC_LOCKCFGR3_MODLOCK_Msk (0x1UL << RCC_LOCKCFGR3_MODLOCK_Pos) /*!< 0x00000001 */
#define RCC_LOCKCFGR3_MODLOCK RCC_LOCKCFGR3_MODLOCK_Msk /*!< Locked protection of MOD system configuration bits */
#define RCC_LOCKCFGR3_SYSLOCK_Pos (1U)
#define RCC_LOCKCFGR3_SYSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_SYSLOCK_Pos) /*!< 0x00000002 */
#define RCC_LOCKCFGR3_SYSLOCK RCC_LOCKCFGR3_SYSLOCK_Msk /*!< Locked protection of SYS system configuration bits */
#define RCC_LOCKCFGR3_BUSLOCK_Pos (2U)
#define RCC_LOCKCFGR3_BUSLOCK_Msk (0x1UL << RCC_LOCKCFGR3_BUSLOCK_Pos) /*!< 0x00000004 */
#define RCC_LOCKCFGR3_BUSLOCK RCC_LOCKCFGR3_BUSLOCK_Msk /*!< Locked protection of BUS system configuration bits */
#define RCC_LOCKCFGR3_PERLOCK_Pos (3U)
#define RCC_LOCKCFGR3_PERLOCK_Msk (0x1UL << RCC_LOCKCFGR3_PERLOCK_Pos) /*!< 0x00000008 */
#define RCC_LOCKCFGR3_PERLOCK RCC_LOCKCFGR3_PERLOCK_Msk /*!< Locked protection of PER system configuration bits */
#define RCC_LOCKCFGR3_INTLOCK_Pos (4U)
#define RCC_LOCKCFGR3_INTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_INTLOCK_Pos) /*!< 0x00000010 */
#define RCC_LOCKCFGR3_INTLOCK RCC_LOCKCFGR3_INTLOCK_Msk /*!< Locked protection of INT system configuration bits */
#define RCC_LOCKCFGR3_RSTLOCK_Pos (5U)
#define RCC_LOCKCFGR3_RSTLOCK_Msk (0x1UL << RCC_LOCKCFGR3_RSTLOCK_Pos) /*!< 0x00000020 */
#define RCC_LOCKCFGR3_RSTLOCK RCC_LOCKCFGR3_RSTLOCK_Msk /*!< Locked protection of RST system configuration bits */
/***************** Bit definition for RCC_PUBCFGR3 register *****************/
#define RCC_PUBCFGR3_MODPUB_Pos (0U)
#define RCC_PUBCFGR3_MODPUB_Msk (0x1UL << RCC_PUBCFGR3_MODPUB_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGR3_MODPUB RCC_PUBCFGR3_MODPUB_Msk /*!< Public protection of MOD system configuration bits */
#define RCC_PUBCFGR3_SYSPUB_Pos (1U)
#define RCC_PUBCFGR3_SYSPUB_Msk (0x1UL << RCC_PUBCFGR3_SYSPUB_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGR3_SYSPUB RCC_PUBCFGR3_SYSPUB_Msk /*!< Public protection of SYS system configuration bits */
#define RCC_PUBCFGR3_BUSPUB_Pos (2U)
#define RCC_PUBCFGR3_BUSPUB_Msk (0x1UL << RCC_PUBCFGR3_BUSPUB_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGR3_BUSPUB RCC_PUBCFGR3_BUSPUB_Msk /*!< Public protection of BUS system configuration bits */
#define RCC_PUBCFGR3_PERPUB_Pos (3U)
#define RCC_PUBCFGR3_PERPUB_Msk (0x1UL << RCC_PUBCFGR3_PERPUB_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGR3_PERPUB RCC_PUBCFGR3_PERPUB_Msk /*!< Public protection of PER system configuration bits */
#define RCC_PUBCFGR3_INTPUB_Pos (4U)
#define RCC_PUBCFGR3_INTPUB_Msk (0x1UL << RCC_PUBCFGR3_INTPUB_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGR3_INTPUB RCC_PUBCFGR3_INTPUB_Msk /*!< Public protection of INT system configuration bits */
#define RCC_PUBCFGR3_RSTPUB_Pos (5U)
#define RCC_PUBCFGR3_RSTPUB_Msk (0x1UL << RCC_PUBCFGR3_RSTPUB_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGR3_RSTPUB RCC_PUBCFGR3_RSTPUB_Msk /*!< Public protection of RST system configuration bits */
/***************** Bit definition for RCC_SECCFGR4 register *****************/
#define RCC_SECCFGR4_ACLKNSEC_Pos (0U)
#define RCC_SECCFGR4_ACLKNSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNSEC_Pos) /*!< 0x00000001 */
#define RCC_SECCFGR4_ACLKNSEC RCC_SECCFGR4_ACLKNSEC_Msk /*!< Secure protection of ACLKN bus configuration bits */
#define RCC_SECCFGR4_ACLKNCSEC_Pos (1U)
#define RCC_SECCFGR4_ACLKNCSEC_Msk (0x1UL << RCC_SECCFGR4_ACLKNCSEC_Pos) /*!< 0x00000002 */
#define RCC_SECCFGR4_ACLKNCSEC RCC_SECCFGR4_ACLKNCSEC_Msk /*!< Secure protection of ACLKNC bus configuration bits */
#define RCC_SECCFGR4_AHBMSEC_Pos (2U)
#define RCC_SECCFGR4_AHBMSEC_Msk (0x1UL << RCC_SECCFGR4_AHBMSEC_Pos) /*!< 0x00000004 */
#define RCC_SECCFGR4_AHBMSEC RCC_SECCFGR4_AHBMSEC_Msk /*!< Secure protection of AHBM bus configuration bits */
#define RCC_SECCFGR4_AHB1SEC_Pos (3U)
#define RCC_SECCFGR4_AHB1SEC_Msk (0x1UL << RCC_SECCFGR4_AHB1SEC_Pos) /*!< 0x00000008 */
#define RCC_SECCFGR4_AHB1SEC RCC_SECCFGR4_AHB1SEC_Msk /*!< Secure protection of AHB1 bus configuration bits */
#define RCC_SECCFGR4_AHB2SEC_Pos (4U)
#define RCC_SECCFGR4_AHB2SEC_Msk (0x1UL << RCC_SECCFGR4_AHB2SEC_Pos) /*!< 0x00000010 */
#define RCC_SECCFGR4_AHB2SEC RCC_SECCFGR4_AHB2SEC_Msk /*!< Secure protection of AHB2 bus configuration bits */
#define RCC_SECCFGR4_AHB3SEC_Pos (5U)
#define RCC_SECCFGR4_AHB3SEC_Msk (0x1UL << RCC_SECCFGR4_AHB3SEC_Pos) /*!< 0x00000020 */
#define RCC_SECCFGR4_AHB3SEC RCC_SECCFGR4_AHB3SEC_Msk /*!< Secure protection of AHB3 bus configuration bits */
#define RCC_SECCFGR4_AHB4SEC_Pos (6U)
#define RCC_SECCFGR4_AHB4SEC_Msk (0x1UL << RCC_SECCFGR4_AHB4SEC_Pos) /*!< 0x00000040 */
#define RCC_SECCFGR4_AHB4SEC RCC_SECCFGR4_AHB4SEC_Msk /*!< Secure protection of AHB4 bus configuration bits */
#define RCC_SECCFGR4_AHB5SEC_Pos (7U)
#define RCC_SECCFGR4_AHB5SEC_Msk (0x1UL << RCC_SECCFGR4_AHB5SEC_Pos) /*!< 0x00000080 */
#define RCC_SECCFGR4_AHB5SEC RCC_SECCFGR4_AHB5SEC_Msk /*!< Secure protection of AHB5 bus configuration bits */
#define RCC_SECCFGR4_APB1SEC_Pos (8U)
#define RCC_SECCFGR4_APB1SEC_Msk (0x1UL << RCC_SECCFGR4_APB1SEC_Pos) /*!< 0x00000100 */
#define RCC_SECCFGR4_APB1SEC RCC_SECCFGR4_APB1SEC_Msk /*!< Secure protection of APB1 bus configuration bits */
#define RCC_SECCFGR4_APB2SEC_Pos (9U)
#define RCC_SECCFGR4_APB2SEC_Msk (0x1UL << RCC_SECCFGR4_APB2SEC_Pos) /*!< 0x00000200 */
#define RCC_SECCFGR4_APB2SEC RCC_SECCFGR4_APB2SEC_Msk /*!< Secure protection of APB2 bus configuration bits */
#define RCC_SECCFGR4_APB3SEC_Pos (10U)
#define RCC_SECCFGR4_APB3SEC_Msk (0x1UL << RCC_SECCFGR4_APB3SEC_Pos) /*!< 0x00000400 */
#define RCC_SECCFGR4_APB3SEC RCC_SECCFGR4_APB3SEC_Msk /*!< Secure protection of APB3 bus configuration bits */
#define RCC_SECCFGR4_APB4SEC_Pos (11U)
#define RCC_SECCFGR4_APB4SEC_Msk (0x1UL << RCC_SECCFGR4_APB4SEC_Pos) /*!< 0x00000800 */
#define RCC_SECCFGR4_APB4SEC RCC_SECCFGR4_APB4SEC_Msk /*!< Secure protection of APB4 bus configuration bits */
#define RCC_SECCFGR4_APB5SEC_Pos (12U)
#define RCC_SECCFGR4_APB5SEC_Msk (0x1UL << RCC_SECCFGR4_APB5SEC_Pos) /*!< 0x00001000 */
#define RCC_SECCFGR4_APB5SEC RCC_SECCFGR4_APB5SEC_Msk /*!< Secure protection of APB5 bus configuration bits */
#define RCC_SECCFGR4_NOCSEC_Pos (13U)
#define RCC_SECCFGR4_NOCSEC_Msk (0x1UL << RCC_SECCFGR4_NOCSEC_Pos) /*!< 0x00002000 */
#define RCC_SECCFGR4_NOCSEC RCC_SECCFGR4_NOCSEC_Msk /*!< Secure protection of NOC bus configuration bits */
/**************** Bit definition for RCC_PRIVCFGR4 register *****************/
#define RCC_PRIVCFGR4_ACLKNPRIV_Pos (0U)
#define RCC_PRIVCFGR4_ACLKNPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNPRIV_Pos)/*!< 0x00000001 */
#define RCC_PRIVCFGR4_ACLKNPRIV RCC_PRIVCFGR4_ACLKNPRIV_Msk /*!< Privileged protection of ACLKN bus configuration bits */
#define RCC_PRIVCFGR4_ACLKNCPRIV_Pos (1U)
#define RCC_PRIVCFGR4_ACLKNCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_ACLKNCPRIV_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGR4_ACLKNCPRIV RCC_PRIVCFGR4_ACLKNCPRIV_Msk /*!< Privileged protection of ACLKNC bus configuration bits */
#define RCC_PRIVCFGR4_AHBMPRIV_Pos (2U)
#define RCC_PRIVCFGR4_AHBMPRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHBMPRIV_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGR4_AHBMPRIV RCC_PRIVCFGR4_AHBMPRIV_Msk /*!< Privileged protection of AHBM bus configuration bits */
#define RCC_PRIVCFGR4_AHB1PRIV_Pos (3U)
#define RCC_PRIVCFGR4_AHB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB1PRIV_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGR4_AHB1PRIV RCC_PRIVCFGR4_AHB1PRIV_Msk /*!< Privileged protection of AHB1 bus configuration bits */
#define RCC_PRIVCFGR4_AHB2PRIV_Pos (4U)
#define RCC_PRIVCFGR4_AHB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB2PRIV_Pos) /*!< 0x00000010 */
#define RCC_PRIVCFGR4_AHB2PRIV RCC_PRIVCFGR4_AHB2PRIV_Msk /*!< Privileged protection of AHB2 bus configuration bits */
#define RCC_PRIVCFGR4_AHB3PRIV_Pos (5U)
#define RCC_PRIVCFGR4_AHB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB3PRIV_Pos) /*!< 0x00000020 */
#define RCC_PRIVCFGR4_AHB3PRIV RCC_PRIVCFGR4_AHB3PRIV_Msk /*!< Privileged protection of AHB3 bus configuration bits */
#define RCC_PRIVCFGR4_AHB4PRIV_Pos (6U)
#define RCC_PRIVCFGR4_AHB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB4PRIV_Pos) /*!< 0x00000040 */
#define RCC_PRIVCFGR4_AHB4PRIV RCC_PRIVCFGR4_AHB4PRIV_Msk /*!< Privileged protection of AHB4 bus configuration bits */
#define RCC_PRIVCFGR4_AHB5PRIV_Pos (7U)
#define RCC_PRIVCFGR4_AHB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_AHB5PRIV_Pos) /*!< 0x00000080 */
#define RCC_PRIVCFGR4_AHB5PRIV RCC_PRIVCFGR4_AHB5PRIV_Msk /*!< Privileged protection of AHB5 bus configuration bits */
#define RCC_PRIVCFGR4_APB1PRIV_Pos (8U)
#define RCC_PRIVCFGR4_APB1PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB1PRIV_Pos) /*!< 0x00000100 */
#define RCC_PRIVCFGR4_APB1PRIV RCC_PRIVCFGR4_APB1PRIV_Msk /*!< Privileged protection of APB1 bus configuration bits */
#define RCC_PRIVCFGR4_APB2PRIV_Pos (9U)
#define RCC_PRIVCFGR4_APB2PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB2PRIV_Pos) /*!< 0x00000200 */
#define RCC_PRIVCFGR4_APB2PRIV RCC_PRIVCFGR4_APB2PRIV_Msk /*!< Privileged protection of APB2 bus configuration bits */
#define RCC_PRIVCFGR4_APB3PRIV_Pos (10U)
#define RCC_PRIVCFGR4_APB3PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB3PRIV_Pos) /*!< 0x00000400 */
#define RCC_PRIVCFGR4_APB3PRIV RCC_PRIVCFGR4_APB3PRIV_Msk /*!< Privileged protection of APB3 bus configuration bits */
#define RCC_PRIVCFGR4_APB4PRIV_Pos (11U)
#define RCC_PRIVCFGR4_APB4PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB4PRIV_Pos) /*!< 0x00000800 */
#define RCC_PRIVCFGR4_APB4PRIV RCC_PRIVCFGR4_APB4PRIV_Msk /*!< Privileged protection of APB4 bus configuration bits */
#define RCC_PRIVCFGR4_APB5PRIV_Pos (12U)
#define RCC_PRIVCFGR4_APB5PRIV_Msk (0x1UL << RCC_PRIVCFGR4_APB5PRIV_Pos) /*!< 0x00001000 */
#define RCC_PRIVCFGR4_APB5PRIV RCC_PRIVCFGR4_APB5PRIV_Msk /*!< Privileged protection of APB5 bus configuration bits */
#define RCC_PRIVCFGR4_NOCPRIV_Pos (13U)
#define RCC_PRIVCFGR4_NOCPRIV_Msk (0x1UL << RCC_PRIVCFGR4_NOCPRIV_Pos) /*!< 0x00002000 */
#define RCC_PRIVCFGR4_NOCPRIV RCC_PRIVCFGR4_NOCPRIV_Msk /*!< Privileged protection of NOC bus configuration bits */
/**************** Bit definition for RCC_LOCKCFGR4 register *****************/
#define RCC_LOCKCFGR4_ACLKNLOCK_Pos (0U)
#define RCC_LOCKCFGR4_ACLKNLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNLOCK_Pos)/*!< 0x00000001 */
#define RCC_LOCKCFGR4_ACLKNLOCK RCC_LOCKCFGR4_ACLKNLOCK_Msk /*!< Locked protection of ACLKN bus configuration bits */
#define RCC_LOCKCFGR4_ACLKNCLOCK_Pos (1U)
#define RCC_LOCKCFGR4_ACLKNCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_ACLKNCLOCK_Pos) /*!< 0x00000002 */
#define RCC_LOCKCFGR4_ACLKNCLOCK RCC_LOCKCFGR4_ACLKNCLOCK_Msk /*!< Locked protection of ACLKNC bus configuration bits */
#define RCC_LOCKCFGR4_AHBMLOCK_Pos (2U)
#define RCC_LOCKCFGR4_AHBMLOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHBMLOCK_Pos) /*!< 0x00000004 */
#define RCC_LOCKCFGR4_AHBMLOCK RCC_LOCKCFGR4_AHBMLOCK_Msk /*!< Locked protection of AHBM bus configuration bits */
#define RCC_LOCKCFGR4_AHB1LOCK_Pos (3U)
#define RCC_LOCKCFGR4_AHB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB1LOCK_Pos) /*!< 0x00000008 */
#define RCC_LOCKCFGR4_AHB1LOCK RCC_LOCKCFGR4_AHB1LOCK_Msk /*!< Locked protection of AHB1 bus configuration bits */
#define RCC_LOCKCFGR4_AHB2LOCK_Pos (4U)
#define RCC_LOCKCFGR4_AHB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB2LOCK_Pos) /*!< 0x00000010 */
#define RCC_LOCKCFGR4_AHB2LOCK RCC_LOCKCFGR4_AHB2LOCK_Msk /*!< Locked protection of AHB2 bus configuration bits */
#define RCC_LOCKCFGR4_AHB3LOCK_Pos (5U)
#define RCC_LOCKCFGR4_AHB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB3LOCK_Pos) /*!< 0x00000020 */
#define RCC_LOCKCFGR4_AHB3LOCK RCC_LOCKCFGR4_AHB3LOCK_Msk /*!< Locked protection of AHB3 bus configuration bits */
#define RCC_LOCKCFGR4_AHB4LOCK_Pos (6U)
#define RCC_LOCKCFGR4_AHB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB4LOCK_Pos) /*!< 0x00000040 */
#define RCC_LOCKCFGR4_AHB4LOCK RCC_LOCKCFGR4_AHB4LOCK_Msk /*!< Locked protection of AHB4 bus configuration bits */
#define RCC_LOCKCFGR4_AHB5LOCK_Pos (7U)
#define RCC_LOCKCFGR4_AHB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_AHB5LOCK_Pos) /*!< 0x00000080 */
#define RCC_LOCKCFGR4_AHB5LOCK RCC_LOCKCFGR4_AHB5LOCK_Msk /*!< Locked protection of AHB5 bus configuration bits */
#define RCC_LOCKCFGR4_APB1LOCK_Pos (8U)
#define RCC_LOCKCFGR4_APB1LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB1LOCK_Pos) /*!< 0x00000100 */
#define RCC_LOCKCFGR4_APB1LOCK RCC_LOCKCFGR4_APB1LOCK_Msk /*!< Locked protection of APB1 bus configuration bits */
#define RCC_LOCKCFGR4_APB2LOCK_Pos (9U)
#define RCC_LOCKCFGR4_APB2LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB2LOCK_Pos) /*!< 0x00000200 */
#define RCC_LOCKCFGR4_APB2LOCK RCC_LOCKCFGR4_APB2LOCK_Msk /*!< Locked protection of APB2 bus configuration bits */
#define RCC_LOCKCFGR4_APB3LOCK_Pos (10U)
#define RCC_LOCKCFGR4_APB3LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB3LOCK_Pos) /*!< 0x00000400 */
#define RCC_LOCKCFGR4_APB3LOCK RCC_LOCKCFGR4_APB3LOCK_Msk /*!< Locked protection of APB3 bus configuration bits */
#define RCC_LOCKCFGR4_APB4LOCK_Pos (11U)
#define RCC_LOCKCFGR4_APB4LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB4LOCK_Pos) /*!< 0x00000800 */
#define RCC_LOCKCFGR4_APB4LOCK RCC_LOCKCFGR4_APB4LOCK_Msk /*!< Locked protection of APB4 bus configuration bits */
#define RCC_LOCKCFGR4_APB5LOCK_Pos (12U)
#define RCC_LOCKCFGR4_APB5LOCK_Msk (0x1UL << RCC_LOCKCFGR4_APB5LOCK_Pos) /*!< 0x00001000 */
#define RCC_LOCKCFGR4_APB5LOCK RCC_LOCKCFGR4_APB5LOCK_Msk /*!< Locked protection of APB5 bus configuration bits */
#define RCC_LOCKCFGR4_NOCLOCK_Pos (13U)
#define RCC_LOCKCFGR4_NOCLOCK_Msk (0x1UL << RCC_LOCKCFGR4_NOCLOCK_Pos) /*!< 0x00002000 */
#define RCC_LOCKCFGR4_NOCLOCK RCC_LOCKCFGR4_NOCLOCK_Msk /*!< Locked protection of NOC bus configuration bits */
/***************** Bit definition for RCC_PUBCFGR4 register *****************/
#define RCC_PUBCFGR4_ACLKNPUB_Pos (0U)
#define RCC_PUBCFGR4_ACLKNPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNPUB_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGR4_ACLKNPUB RCC_PUBCFGR4_ACLKNPUB_Msk /*!< Public protection of the ACLKN bus configuration bits */
#define RCC_PUBCFGR4_ACLKNCPUB_Pos (1U)
#define RCC_PUBCFGR4_ACLKNCPUB_Msk (0x1UL << RCC_PUBCFGR4_ACLKNCPUB_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGR4_ACLKNCPUB RCC_PUBCFGR4_ACLKNCPUB_Msk /*!< Public protection of ACLKNC bus configuration bits */
#define RCC_PUBCFGR4_AHBMPUB_Pos (2U)
#define RCC_PUBCFGR4_AHBMPUB_Msk (0x1UL << RCC_PUBCFGR4_AHBMPUB_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGR4_AHBMPUB RCC_PUBCFGR4_AHBMPUB_Msk /*!< Public protection of AHBM bus configuration bits */
#define RCC_PUBCFGR4_AHB1PUB_Pos (3U)
#define RCC_PUBCFGR4_AHB1PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB1PUB_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGR4_AHB1PUB RCC_PUBCFGR4_AHB1PUB_Msk /*!< Public protection of AHB1 bus configuration bits */
#define RCC_PUBCFGR4_AHB2PUB_Pos (4U)
#define RCC_PUBCFGR4_AHB2PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB2PUB_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGR4_AHB2PUB RCC_PUBCFGR4_AHB2PUB_Msk /*!< Public protection of AHB2 bus configuration bits */
#define RCC_PUBCFGR4_AHB3PUB_Pos (5U)
#define RCC_PUBCFGR4_AHB3PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB3PUB_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGR4_AHB3PUB RCC_PUBCFGR4_AHB3PUB_Msk /*!< Public protection of AHB3 bus configuration bits */
#define RCC_PUBCFGR4_AHB4PUB_Pos (6U)
#define RCC_PUBCFGR4_AHB4PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB4PUB_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGR4_AHB4PUB RCC_PUBCFGR4_AHB4PUB_Msk /*!< Public protection of AHB4 bus configuration bits */
#define RCC_PUBCFGR4_AHB5PUB_Pos (7U)
#define RCC_PUBCFGR4_AHB5PUB_Msk (0x1UL << RCC_PUBCFGR4_AHB5PUB_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGR4_AHB5PUB RCC_PUBCFGR4_AHB5PUB_Msk /*!< Public protection of AHB5 bus configuration bits */
#define RCC_PUBCFGR4_APB1PUB_Pos (8U)
#define RCC_PUBCFGR4_APB1PUB_Msk (0x1UL << RCC_PUBCFGR4_APB1PUB_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGR4_APB1PUB RCC_PUBCFGR4_APB1PUB_Msk /*!< Public protection of APB1 bus configuration bits */
#define RCC_PUBCFGR4_APB2PUB_Pos (9U)
#define RCC_PUBCFGR4_APB2PUB_Msk (0x1UL << RCC_PUBCFGR4_APB2PUB_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGR4_APB2PUB RCC_PUBCFGR4_APB2PUB_Msk /*!< Public protection of APB2 bus configuration bits */
#define RCC_PUBCFGR4_APB3PUB_Pos (10U)
#define RCC_PUBCFGR4_APB3PUB_Msk (0x1UL << RCC_PUBCFGR4_APB3PUB_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGR4_APB3PUB RCC_PUBCFGR4_APB3PUB_Msk /*!< Public protection of APB3 bus configuration bits */
#define RCC_PUBCFGR4_APB4PUB_Pos (11U)
#define RCC_PUBCFGR4_APB4PUB_Msk (0x1UL << RCC_PUBCFGR4_APB4PUB_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGR4_APB4PUB RCC_PUBCFGR4_APB4PUB_Msk /*!< Public protection of APB4 bus configuration bits */
#define RCC_PUBCFGR4_APB5PUB_Pos (12U)
#define RCC_PUBCFGR4_APB5PUB_Msk (0x1UL << RCC_PUBCFGR4_APB5PUB_Pos) /*!< 0x00001000 */
#define RCC_PUBCFGR4_APB5PUB RCC_PUBCFGR4_APB5PUB_Msk /*!< Public protection of APB5 bus configuration bits */
#define RCC_PUBCFGR4_NOCPUB_Pos (13U)
#define RCC_PUBCFGR4_NOCPUB_Msk (0x1UL << RCC_PUBCFGR4_NOCPUB_Pos) /*!< 0x00002000 */
#define RCC_PUBCFGR4_NOCPUB RCC_PUBCFGR4_NOCPUB_Msk /*!< Public protection of NOC bus configuration bits */
/***************** Bit definition for RCC_PUBCFGR5 register *****************/
#define RCC_PUBCFGR5_AXISRAM3PUB_Pos (0U)
#define RCC_PUBCFGR5_AXISRAM3PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM3PUB_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGR5_AXISRAM3PUB RCC_PUBCFGR5_AXISRAM3PUB_Msk /*!< Public protection of AXISRAM3 bus configuration bits */
#define RCC_PUBCFGR5_AXISRAM4PUB_Pos (1U)
#define RCC_PUBCFGR5_AXISRAM4PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM4PUB_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGR5_AXISRAM4PUB RCC_PUBCFGR5_AXISRAM4PUB_Msk /*!< Public protection of AXISRAM4 bus configuration bits */
#define RCC_PUBCFGR5_AXISRAM5PUB_Pos (2U)
#define RCC_PUBCFGR5_AXISRAM5PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM5PUB_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGR5_AXISRAM5PUB RCC_PUBCFGR5_AXISRAM5PUB_Msk /*!< Public protection of AXISRAM5 bus configuration bits */
#define RCC_PUBCFGR5_AXISRAM6PUB_Pos (3U)
#define RCC_PUBCFGR5_AXISRAM6PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM6PUB_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGR5_AXISRAM6PUB RCC_PUBCFGR5_AXISRAM6PUB_Msk /*!< Public protection of AXISRAM6 bus configuration bits */
#define RCC_PUBCFGR5_AHBSRAM1PUB_Pos (4U)
#define RCC_PUBCFGR5_AHBSRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM1PUB_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGR5_AHBSRAM1PUB RCC_PUBCFGR5_AHBSRAM1PUB_Msk /*!< Public protection of AHBSRAM1 bus configuration bits */
#define RCC_PUBCFGR5_AHBSRAM2PUB_Pos (5U)
#define RCC_PUBCFGR5_AHBSRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AHBSRAM2PUB_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGR5_AHBSRAM2PUB RCC_PUBCFGR5_AHBSRAM2PUB_Msk /*!< Public protection of AHBSRAM2 bus configuration bits */
#define RCC_PUBCFGR5_BKPSRAMPUB_Pos (6U)
#define RCC_PUBCFGR5_BKPSRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_BKPSRAMPUB_Pos)/*!< 0x00000040 */
#define RCC_PUBCFGR5_BKPSRAMPUB RCC_PUBCFGR5_BKPSRAMPUB_Msk /*!< Public protection of BKPSRAM bus configuration bits */
#define RCC_PUBCFGR5_AXISRAM1PUB_Pos (7U)
#define RCC_PUBCFGR5_AXISRAM1PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM1PUB_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGR5_AXISRAM1PUB RCC_PUBCFGR5_AXISRAM1PUB_Msk /*!< Public protection of AXISRAM1 bus configuration bits */
#define RCC_PUBCFGR5_AXISRAM2PUB_Pos (8U)
#define RCC_PUBCFGR5_AXISRAM2PUB_Msk (0x1UL << RCC_PUBCFGR5_AXISRAM2PUB_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGR5_AXISRAM2PUB RCC_PUBCFGR5_AXISRAM2PUB_Msk /*!< Public protection of AXISRAM2 bus configuration bits */
#define RCC_PUBCFGR5_FLEXRAMPUB_Pos (9U)
#define RCC_PUBCFGR5_FLEXRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_FLEXRAMPUB_Pos)/*!< 0x00000200 */
#define RCC_PUBCFGR5_FLEXRAMPUB RCC_PUBCFGR5_FLEXRAMPUB_Msk /*!< Public protection of FLEXRAM bus configuration bits */
#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos (10U)
#define RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_CACHEAXIRAMPUB_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGR5_CACHEAXIRAMPUB RCC_PUBCFGR5_CACHEAXIRAMPUB_Msk /*!< Public protection of CACHEAXIRAM bus configuration bits */
#define RCC_PUBCFGR5_VENCRAMPUB_Pos (11U)
#define RCC_PUBCFGR5_VENCRAMPUB_Msk (0x1UL << RCC_PUBCFGR5_VENCRAMPUB_Pos)/*!< 0x00000800 */
#define RCC_PUBCFGR5_VENCRAMPUB RCC_PUBCFGR5_VENCRAMPUB_Msk /*!< Public protection of VENCRAM bus configuration bits */
/******************* Bit definition for RCC_CSR register ********************/
#define RCC_CSR_LSIONS_Pos (0U)
#define RCC_CSR_LSIONS_Msk (0x1UL << RCC_CSR_LSIONS_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSIONS RCC_CSR_LSIONS_Msk /*!< LSI oscillator enable */
#define RCC_CSR_LSEONS_Pos (1U)
#define RCC_CSR_LSEONS_Msk (0x1UL << RCC_CSR_LSEONS_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSEONS RCC_CSR_LSEONS_Msk /*!< LSE oscillator enable */
#define RCC_CSR_MSIONS_Pos (2U)
#define RCC_CSR_MSIONS_Msk (0x1UL << RCC_CSR_MSIONS_Pos) /*!< 0x00000004 */
#define RCC_CSR_MSIONS RCC_CSR_MSIONS_Msk /*!< MSI oscillator enable */
#define RCC_CSR_HSIONS_Pos (3U)
#define RCC_CSR_HSIONS_Msk (0x1UL << RCC_CSR_HSIONS_Pos) /*!< 0x00000008 */
#define RCC_CSR_HSIONS RCC_CSR_HSIONS_Msk /*!< HSI oscillator enable */
#define RCC_CSR_HSEONS_Pos (4U)
#define RCC_CSR_HSEONS_Msk (0x1UL << RCC_CSR_HSEONS_Pos) /*!< 0x00000010 */
#define RCC_CSR_HSEONS RCC_CSR_HSEONS_Msk /*!< HSE oscillator enable */
#define RCC_CSR_PLL1ONS_Pos (8U)
#define RCC_CSR_PLL1ONS_Msk (0x1UL << RCC_CSR_PLL1ONS_Pos) /*!< 0x00000100 */
#define RCC_CSR_PLL1ONS RCC_CSR_PLL1ONS_Msk /*!< PLL1 oscillator enable */
#define RCC_CSR_PLL2ONS_Pos (9U)
#define RCC_CSR_PLL2ONS_Msk (0x1UL << RCC_CSR_PLL2ONS_Pos) /*!< 0x00000200 */
#define RCC_CSR_PLL2ONS RCC_CSR_PLL2ONS_Msk /*!< PLL2 oscillator enable */
#define RCC_CSR_PLL3ONS_Pos (10U)
#define RCC_CSR_PLL3ONS_Msk (0x1UL << RCC_CSR_PLL3ONS_Pos) /*!< 0x00000400 */
#define RCC_CSR_PLL3ONS RCC_CSR_PLL3ONS_Msk /*!< PLL3 oscillator enable */
#define RCC_CSR_PLL4ONS_Pos (11U)
#define RCC_CSR_PLL4ONS_Msk (0x1UL << RCC_CSR_PLL4ONS_Pos) /*!< 0x00000800 */
#define RCC_CSR_PLL4ONS RCC_CSR_PLL4ONS_Msk /*!< PLL4 oscillator enable */
/***************** Bit definition for RCC_STOPCSR register ******************/
#define RCC_STOPCSR_MSISTOPENS_Pos (0U)
#define RCC_STOPCSR_MSISTOPENS_Msk (0x1UL << RCC_STOPCSR_MSISTOPENS_Pos) /*!< 0x00000001 */
#define RCC_STOPCSR_MSISTOPENS RCC_STOPCSR_MSISTOPENS_Msk /*!< MSI oscillator enable */
#define RCC_STOPCSR_HSISTOPENS_Pos (1U)
#define RCC_STOPCSR_HSISTOPENS_Msk (0x1UL << RCC_STOPCSR_HSISTOPENS_Pos) /*!< 0x00000002 */
#define RCC_STOPCSR_HSISTOPENS RCC_STOPCSR_HSISTOPENS_Msk /*!< HSI oscillator enable */
/**************** Bit definition for RCC_MISCRSTSR register *****************/
#define RCC_MISCRSTSR_DBGRSTS_Pos (0U)
#define RCC_MISCRSTSR_DBGRSTS_Msk (0x1UL << RCC_MISCRSTSR_DBGRSTS_Pos) /*!< 0x00000001 */
#define RCC_MISCRSTSR_DBGRSTS RCC_MISCRSTSR_DBGRSTS_Msk /*!< DBG reset */
#define RCC_MISCRSTSR_XSPIPHY1RSTS_Pos (4U)
#define RCC_MISCRSTSR_XSPIPHY1RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY1RSTS_Pos) /*!< 0x00000010 */
#define RCC_MISCRSTSR_XSPIPHY1RSTS RCC_MISCRSTSR_XSPIPHY1RSTS_Msk /*!< XSPIPHY1 reset */
#define RCC_MISCRSTSR_XSPIPHY2RSTS_Pos (5U)
#define RCC_MISCRSTSR_XSPIPHY2RSTS_Msk (0x1UL << RCC_MISCRSTSR_XSPIPHY2RSTS_Pos) /*!< 0x00000020 */
#define RCC_MISCRSTSR_XSPIPHY2RSTS RCC_MISCRSTSR_XSPIPHY2RSTS_Msk /*!< XSPIPHY2 reset */
#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos (7U)
#define RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC1DLLRSTS_Pos) /*!< 0x00000080 */
#define RCC_MISCRSTSR_SDMMC1DLLRSTS RCC_MISCRSTSR_SDMMC1DLLRSTS_Msk /*!< SDMMC1DLL reset */
#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos (8U)
#define RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk (0x1UL << RCC_MISCRSTSR_SDMMC2DLLRSTS_Pos) /*!< 0x00000100 */
#define RCC_MISCRSTSR_SDMMC2DLLRSTS RCC_MISCRSTSR_SDMMC2DLLRSTS_Msk /*!< SDMMC2DLL reset */
/***************** Bit definition for RCC_MEMRSTSR register *****************/
#define RCC_MEMRSTSR_AXISRAM3RSTS_Pos (0U)
#define RCC_MEMRSTSR_AXISRAM3RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM3RSTS_Pos) /*!< 0x00000001 */
#define RCC_MEMRSTSR_AXISRAM3RSTS RCC_MEMRSTSR_AXISRAM3RSTS_Msk /*!< AXISRAM3 reset */
#define RCC_MEMRSTSR_AXISRAM4RSTS_Pos (1U)
#define RCC_MEMRSTSR_AXISRAM4RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM4RSTS_Pos) /*!< 0x00000002 */
#define RCC_MEMRSTSR_AXISRAM4RSTS RCC_MEMRSTSR_AXISRAM4RSTS_Msk /*!< AXISRAM4 reset */
#define RCC_MEMRSTSR_AXISRAM5RSTS_Pos (2U)
#define RCC_MEMRSTSR_AXISRAM5RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM5RSTS_Pos) /*!< 0x00000004 */
#define RCC_MEMRSTSR_AXISRAM5RSTS RCC_MEMRSTSR_AXISRAM5RSTS_Msk /*!< AXISRAM5 reset */
#define RCC_MEMRSTSR_AXISRAM6RSTS_Pos (3U)
#define RCC_MEMRSTSR_AXISRAM6RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM6RSTS_Pos) /*!< 0x00000008 */
#define RCC_MEMRSTSR_AXISRAM6RSTS RCC_MEMRSTSR_AXISRAM6RSTS_Msk /*!< AXISRAM6 reset */
#define RCC_MEMRSTSR_AHBSRAM1RSTS_Pos (4U)
#define RCC_MEMRSTSR_AHBSRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM1RSTS_Pos) /*!< 0x00000010 */
#define RCC_MEMRSTSR_AHBSRAM1RSTS RCC_MEMRSTSR_AHBSRAM1RSTS_Msk /*!< AHBSRAM1 reset */
#define RCC_MEMRSTSR_AHBSRAM2RSTS_Pos (5U)
#define RCC_MEMRSTSR_AHBSRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AHBSRAM2RSTS_Pos) /*!< 0x00000020 */
#define RCC_MEMRSTSR_AHBSRAM2RSTS RCC_MEMRSTSR_AHBSRAM2RSTS_Msk /*!< AHBSRAM2 reset */
#define RCC_MEMRSTSR_AXISRAM1RSTS_Pos (7U)
#define RCC_MEMRSTSR_AXISRAM1RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM1RSTS_Pos) /*!< 0x00000080 */
#define RCC_MEMRSTSR_AXISRAM1RSTS RCC_MEMRSTSR_AXISRAM1RSTS_Msk /*!< AXISRAM1 reset */
#define RCC_MEMRSTSR_AXISRAM2RSTS_Pos (8U)
#define RCC_MEMRSTSR_AXISRAM2RSTS_Msk (0x1UL << RCC_MEMRSTSR_AXISRAM2RSTS_Pos) /*!< 0x00000100 */
#define RCC_MEMRSTSR_AXISRAM2RSTS RCC_MEMRSTSR_AXISRAM2RSTS_Msk /*!< AXISRAM2 reset */
#define RCC_MEMRSTSR_FLEXRAMRSTS_Pos (9U)
#define RCC_MEMRSTSR_FLEXRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_FLEXRAMRSTS_Pos) /*!< 0x00000200 */
#define RCC_MEMRSTSR_FLEXRAMRSTS RCC_MEMRSTSR_FLEXRAMRSTS_Msk /*!< FLEXRAM reset */
#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos (10U)
#define RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_CACHEAXIRAMRSTS_Pos) /*!< 0x00000400 */
#define RCC_MEMRSTSR_CACHEAXIRAMRSTS RCC_MEMRSTSR_CACHEAXIRAMRSTS_Msk /*!< CACHEAXIRAM reset */
#define RCC_MEMRSTSR_VENCRAMRSTS_Pos (11U)
#define RCC_MEMRSTSR_VENCRAMRSTS_Msk (0x1UL << RCC_MEMRSTSR_VENCRAMRSTS_Pos) /*!< 0x00000800 */
#define RCC_MEMRSTSR_VENCRAMRSTS RCC_MEMRSTSR_VENCRAMRSTS_Msk /*!< VENCRAM reset */
#define RCC_MEMRSTSR_BOOTROMRSTS_Pos (12U)
#define RCC_MEMRSTSR_BOOTROMRSTS_Msk (0x1UL << RCC_MEMRSTSR_BOOTROMRSTS_Pos) /*!< 0x00001000 */
#define RCC_MEMRSTSR_BOOTROMRSTS RCC_MEMRSTSR_BOOTROMRSTS_Msk /*!< Boot ROM reset */
/**************** Bit definition for RCC_AHB1RSTSR register *****************/
#define RCC_AHB1RSTSR_GPDMA1RSTS_Pos (4U)
#define RCC_AHB1RSTSR_GPDMA1RSTS_Msk (0x1UL << RCC_AHB1RSTSR_GPDMA1RSTS_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTSR_GPDMA1RSTS RCC_AHB1RSTSR_GPDMA1RSTS_Msk /*!< GPDMA1 reset */
#define RCC_AHB1RSTSR_ADC12RSTS_Pos (5U)
#define RCC_AHB1RSTSR_ADC12RSTS_Msk (0x1UL << RCC_AHB1RSTSR_ADC12RSTS_Pos)/*!< 0x00000020 */
#define RCC_AHB1RSTSR_ADC12RSTS RCC_AHB1RSTSR_ADC12RSTS_Msk /*!< ADC12 reset */
/**************** Bit definition for RCC_AHB2RSTSR register *****************/
#define RCC_AHB2RSTSR_RAMCFGRSTS_Pos (12U)
#define RCC_AHB2RSTSR_RAMCFGRSTS_Msk (0x1UL << RCC_AHB2RSTSR_RAMCFGRSTS_Pos) /*!< 0x00001000 */
#define RCC_AHB2RSTSR_RAMCFGRSTS RCC_AHB2RSTSR_RAMCFGRSTS_Msk /*!< RAMCFG reset */
#define RCC_AHB2RSTSR_MDF1RSTS_Pos (16U)
#define RCC_AHB2RSTSR_MDF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_MDF1RSTS_Pos) /*!< 0x00010000 */
#define RCC_AHB2RSTSR_MDF1RSTS RCC_AHB2RSTSR_MDF1RSTS_Msk /*!< MDF1 reset */
#define RCC_AHB2RSTSR_ADF1RSTS_Pos (17U)
#define RCC_AHB2RSTSR_ADF1RSTS_Msk (0x1UL << RCC_AHB2RSTSR_ADF1RSTS_Pos) /*!< 0x00020000 */
#define RCC_AHB2RSTSR_ADF1RSTS RCC_AHB2RSTSR_ADF1RSTS_Msk /*!< ADF1 reset */
/**************** Bit definition for RCC_AHB3RSTSR register *****************/
#define RCC_AHB3RSTSR_RNGRSTS_Pos (0U)
#define RCC_AHB3RSTSR_RNGRSTS_Msk (0x1UL << RCC_AHB3RSTSR_RNGRSTS_Pos) /*!< 0x00000001 */
#define RCC_AHB3RSTSR_RNGRSTS RCC_AHB3RSTSR_RNGRSTS_Msk /*!< RNG reset */
#define RCC_AHB3RSTSR_HASHRSTS_Pos (1U)
#define RCC_AHB3RSTSR_HASHRSTS_Msk (0x1UL << RCC_AHB3RSTSR_HASHRSTS_Pos) /*!< 0x00000002 */
#define RCC_AHB3RSTSR_HASHRSTS RCC_AHB3RSTSR_HASHRSTS_Msk /*!< HASH reset */
#define RCC_AHB3RSTSR_CRYPRSTS_Pos (2U)
#define RCC_AHB3RSTSR_CRYPRSTS_Msk (0x1UL << RCC_AHB3RSTSR_CRYPRSTS_Pos) /*!< 0x00000004 */
#define RCC_AHB3RSTSR_CRYPRSTS RCC_AHB3RSTSR_CRYPRSTS_Msk /*!< CRYP reset */
#define RCC_AHB3RSTSR_SAESRSTS_Pos (4U)
#define RCC_AHB3RSTSR_SAESRSTS_Msk (0x1UL << RCC_AHB3RSTSR_SAESRSTS_Pos) /*!< 0x00000010 */
#define RCC_AHB3RSTSR_SAESRSTS RCC_AHB3RSTSR_SAESRSTS_Msk /*!< SAES reset */
#define RCC_AHB3RSTSR_PKARSTS_Pos (8U)
#define RCC_AHB3RSTSR_PKARSTS_Msk (0x1UL << RCC_AHB3RSTSR_PKARSTS_Pos) /*!< 0x00000100 */
#define RCC_AHB3RSTSR_PKARSTS RCC_AHB3RSTSR_PKARSTS_Msk /*!< PKA reset */
#define RCC_AHB3RSTSR_IACRSTS_Pos (10U)
#define RCC_AHB3RSTSR_IACRSTS_Msk (0x1UL << RCC_AHB3RSTSR_IACRSTS_Pos) /*!< 0x00000400 */
#define RCC_AHB3RSTSR_IACRSTS RCC_AHB3RSTSR_IACRSTS_Msk /*!< IAC reset */
/**************** Bit definition for RCC_AHB4RSTSR register *****************/
#define RCC_AHB4RSTSR_GPIOARSTS_Pos (0U)
#define RCC_AHB4RSTSR_GPIOARSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOARSTS_Pos)/*!< 0x00000001 */
#define RCC_AHB4RSTSR_GPIOARSTS RCC_AHB4RSTSR_GPIOARSTS_Msk /*!< GPIO A reset */
#define RCC_AHB4RSTSR_GPIOBRSTS_Pos (1U)
#define RCC_AHB4RSTSR_GPIOBRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOBRSTS_Pos)/*!< 0x00000002 */
#define RCC_AHB4RSTSR_GPIOBRSTS RCC_AHB4RSTSR_GPIOBRSTS_Msk /*!< GPIO B reset */
#define RCC_AHB4RSTSR_GPIOCRSTS_Pos (2U)
#define RCC_AHB4RSTSR_GPIOCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOCRSTS_Pos)/*!< 0x00000004 */
#define RCC_AHB4RSTSR_GPIOCRSTS RCC_AHB4RSTSR_GPIOCRSTS_Msk /*!< GPIO C reset */
#define RCC_AHB4RSTSR_GPIODRSTS_Pos (3U)
#define RCC_AHB4RSTSR_GPIODRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIODRSTS_Pos)/*!< 0x00000008 */
#define RCC_AHB4RSTSR_GPIODRSTS RCC_AHB4RSTSR_GPIODRSTS_Msk /*!< GPIO D reset */
#define RCC_AHB4RSTSR_GPIOERSTS_Pos (4U)
#define RCC_AHB4RSTSR_GPIOERSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOERSTS_Pos)/*!< 0x00000010 */
#define RCC_AHB4RSTSR_GPIOERSTS RCC_AHB4RSTSR_GPIOERSTS_Msk /*!< GPIO E reset */
#define RCC_AHB4RSTSR_GPIOFRSTS_Pos (5U)
#define RCC_AHB4RSTSR_GPIOFRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOFRSTS_Pos)/*!< 0x00000020 */
#define RCC_AHB4RSTSR_GPIOFRSTS RCC_AHB4RSTSR_GPIOFRSTS_Msk /*!< GPIO F reset */
#define RCC_AHB4RSTSR_GPIOGRSTS_Pos (6U)
#define RCC_AHB4RSTSR_GPIOGRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOGRSTS_Pos)/*!< 0x00000040 */
#define RCC_AHB4RSTSR_GPIOGRSTS RCC_AHB4RSTSR_GPIOGRSTS_Msk /*!< GPIO G reset */
#define RCC_AHB4RSTSR_GPIOHRSTS_Pos (7U)
#define RCC_AHB4RSTSR_GPIOHRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOHRSTS_Pos)/*!< 0x00000080 */
#define RCC_AHB4RSTSR_GPIOHRSTS RCC_AHB4RSTSR_GPIOHRSTS_Msk /*!< GPIO H reset */
#define RCC_AHB4RSTSR_GPIONRSTS_Pos (13U)
#define RCC_AHB4RSTSR_GPIONRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIONRSTS_Pos)/*!< 0x00002000 */
#define RCC_AHB4RSTSR_GPIONRSTS RCC_AHB4RSTSR_GPIONRSTS_Msk /*!< GPIO N reset */
#define RCC_AHB4RSTSR_GPIOORSTS_Pos (14U)
#define RCC_AHB4RSTSR_GPIOORSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOORSTS_Pos)/*!< 0x00004000 */
#define RCC_AHB4RSTSR_GPIOORSTS RCC_AHB4RSTSR_GPIOORSTS_Msk /*!< GPIO O reset */
#define RCC_AHB4RSTSR_GPIOPRSTS_Pos (15U)
#define RCC_AHB4RSTSR_GPIOPRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOPRSTS_Pos)/*!< 0x00008000 */
#define RCC_AHB4RSTSR_GPIOPRSTS RCC_AHB4RSTSR_GPIOPRSTS_Msk /*!< GPIO P reset */
#define RCC_AHB4RSTSR_GPIOQRSTS_Pos (16U)
#define RCC_AHB4RSTSR_GPIOQRSTS_Msk (0x1UL << RCC_AHB4RSTSR_GPIOQRSTS_Pos)/*!< 0x00010000 */
#define RCC_AHB4RSTSR_GPIOQRSTS RCC_AHB4RSTSR_GPIOQRSTS_Msk /*!< GPIO Q reset */
#define RCC_AHB4RSTSR_PWRRSTS_Pos (18U)
#define RCC_AHB4RSTSR_PWRRSTS_Msk (0x1UL << RCC_AHB4RSTSR_PWRRSTS_Pos) /*!< 0x00040000 */
#define RCC_AHB4RSTSR_PWRRSTS RCC_AHB4RSTSR_PWRRSTS_Msk /*!< PWR reset */
#define RCC_AHB4RSTSR_CRCRSTS_Pos (19U)
#define RCC_AHB4RSTSR_CRCRSTS_Msk (0x1UL << RCC_AHB4RSTSR_CRCRSTS_Pos) /*!< 0x00080000 */
#define RCC_AHB4RSTSR_CRCRSTS RCC_AHB4RSTSR_CRCRSTS_Msk /*!< CRC reset */
/**************** Bit definition for RCC_AHB5RSTSR register *****************/
#define RCC_AHB5RSTSR_HPDMA1RSTS_Pos (0U)
#define RCC_AHB5RSTSR_HPDMA1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_HPDMA1RSTS_Pos) /*!< 0x00000001 */
#define RCC_AHB5RSTSR_HPDMA1RSTS RCC_AHB5RSTSR_HPDMA1RSTS_Msk /*!< HPDMA1 reset */
#define RCC_AHB5RSTSR_DMA2DRSTS_Pos (1U)
#define RCC_AHB5RSTSR_DMA2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_DMA2DRSTS_Pos)/*!< 0x00000002 */
#define RCC_AHB5RSTSR_DMA2DRSTS RCC_AHB5RSTSR_DMA2DRSTS_Msk /*!< DMA2D reset */
#define RCC_AHB5RSTSR_JPEGRSTS_Pos (3U)
#define RCC_AHB5RSTSR_JPEGRSTS_Msk (0x1UL << RCC_AHB5RSTSR_JPEGRSTS_Pos) /*!< 0x00000008 */
#define RCC_AHB5RSTSR_JPEGRSTS RCC_AHB5RSTSR_JPEGRSTS_Msk /*!< JPEG reset */
#define RCC_AHB5RSTSR_FMCRSTS_Pos (4U)
#define RCC_AHB5RSTSR_FMCRSTS_Msk (0x1UL << RCC_AHB5RSTSR_FMCRSTS_Pos) /*!< 0x00000010 */
#define RCC_AHB5RSTSR_FMCRSTS RCC_AHB5RSTSR_FMCRSTS_Msk /*!< FMC reset */
#define RCC_AHB5RSTSR_XSPI1RSTS_Pos (5U)
#define RCC_AHB5RSTSR_XSPI1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI1RSTS_Pos)/*!< 0x00000020 */
#define RCC_AHB5RSTSR_XSPI1RSTS RCC_AHB5RSTSR_XSPI1RSTS_Msk /*!< XSPI1 reset */
#define RCC_AHB5RSTSR_PSSIRSTS_Pos (6U)
#define RCC_AHB5RSTSR_PSSIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_PSSIRSTS_Pos) /*!< 0x00000040 */
#define RCC_AHB5RSTSR_PSSIRSTS RCC_AHB5RSTSR_PSSIRSTS_Msk /*!< PSSI reset */
#define RCC_AHB5RSTSR_SDMMC2RSTS_Pos (7U)
#define RCC_AHB5RSTSR_SDMMC2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC2RSTS_Pos) /*!< 0x00000080 */
#define RCC_AHB5RSTSR_SDMMC2RSTS RCC_AHB5RSTSR_SDMMC2RSTS_Msk /*!< SDMMC2 reset */
#define RCC_AHB5RSTSR_SDMMC1RSTS_Pos (8U)
#define RCC_AHB5RSTSR_SDMMC1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_SDMMC1RSTS_Pos) /*!< 0x00000100 */
#define RCC_AHB5RSTSR_SDMMC1RSTS RCC_AHB5RSTSR_SDMMC1RSTS_Msk /*!< SDMMC1 reset */
#define RCC_AHB5RSTSR_XSPI2RSTS_Pos (12U)
#define RCC_AHB5RSTSR_XSPI2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI2RSTS_Pos)/*!< 0x00001000 */
#define RCC_AHB5RSTSR_XSPI2RSTS RCC_AHB5RSTSR_XSPI2RSTS_Msk /*!< XSPI2 reset */
#define RCC_AHB5RSTSR_XSPIMRSTS_Pos (13U)
#define RCC_AHB5RSTSR_XSPIMRSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPIMRSTS_Pos)/*!< 0x00002000 */
#define RCC_AHB5RSTSR_XSPIMRSTS RCC_AHB5RSTSR_XSPIMRSTS_Msk /*!< XSPIM reset */
#define RCC_AHB5RSTSR_XSPI3RSTS_Pos (17U)
#define RCC_AHB5RSTSR_XSPI3RSTS_Msk (0x1UL << RCC_AHB5RSTSR_XSPI3RSTS_Pos)/*!< 0x00020000 */
#define RCC_AHB5RSTSR_XSPI3RSTS RCC_AHB5RSTSR_XSPI3RSTS_Msk /*!< XSPI3 reset */
#define RCC_AHB5RSTSR_GFXMMURSTS_Pos (19U)
#define RCC_AHB5RSTSR_GFXMMURSTS_Msk (0x1UL << RCC_AHB5RSTSR_GFXMMURSTS_Pos) /*!< 0x00080000 */
#define RCC_AHB5RSTSR_GFXMMURSTS RCC_AHB5RSTSR_GFXMMURSTS_Msk /*!< GFXMMU reset */
#define RCC_AHB5RSTSR_GPU2DRSTS_Pos (20U)
#define RCC_AHB5RSTSR_GPU2DRSTS_Msk (0x1UL << RCC_AHB5RSTSR_GPU2DRSTS_Pos)/*!< 0x00100000 */
#define RCC_AHB5RSTSR_GPU2DRSTS RCC_AHB5RSTSR_GPU2DRSTS_Msk /*!< GPU2D reset */
#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos (23U)
#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Pos) /*!< 0x00800000 */
#define RCC_AHB5RSTSR_OTG1PHYCTLRSTS RCC_AHB5RSTSR_OTG1PHYCTLRSTS_Msk /*!< OTG1PHYCTL reset */
#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos (24U)
#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Pos) /*!< 0x01000000 */
#define RCC_AHB5RSTSR_OTG2PHYCTLRSTS RCC_AHB5RSTSR_OTG2PHYCTLRSTS_Msk /*!< OTG2PHYCTL reset */
#define RCC_AHB5RSTSR_ETH1RSTS_Pos (25U)
#define RCC_AHB5RSTSR_ETH1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_ETH1RSTS_Pos) /*!< 0x02000000 */
#define RCC_AHB5RSTSR_ETH1RSTS RCC_AHB5RSTSR_ETH1RSTS_Msk /*!< ETH1 reset */
#define RCC_AHB5RSTSR_OTG1RSTS_Pos (26U)
#define RCC_AHB5RSTSR_OTG1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG1RSTS_Pos) /*!< 0x04000000 */
#define RCC_AHB5RSTSR_OTG1RSTS RCC_AHB5RSTSR_OTG1RSTS_Msk /*!< OTG1 reset */
#define RCC_AHB5RSTSR_OTGPHY1RSTS_Pos (27U)
#define RCC_AHB5RSTSR_OTGPHY1RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY1RSTS_Pos) /*!< 0x08000000 */
#define RCC_AHB5RSTSR_OTGPHY1RSTS RCC_AHB5RSTSR_OTGPHY1RSTS_Msk /*!< OTGPHY1 reset */
#define RCC_AHB5RSTSR_OTGPHY2RSTS_Pos (28U)
#define RCC_AHB5RSTSR_OTGPHY2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTGPHY2RSTS_Pos) /*!< 0x10000000 */
#define RCC_AHB5RSTSR_OTGPHY2RSTS RCC_AHB5RSTSR_OTGPHY2RSTS_Msk /*!< OTGPHY2 reset */
#define RCC_AHB5RSTSR_OTG2RSTS_Pos (29U)
#define RCC_AHB5RSTSR_OTG2RSTS_Msk (0x1UL << RCC_AHB5RSTSR_OTG2RSTS_Pos) /*!< 0x20000000 */
#define RCC_AHB5RSTSR_OTG2RSTS RCC_AHB5RSTSR_OTG2RSTS_Msk /*!< OTG2 reset */
#define RCC_AHB5RSTSR_CACHEAXIRSTS_Pos (30U)
#define RCC_AHB5RSTSR_CACHEAXIRSTS_Msk (0x1UL << RCC_AHB5RSTSR_CACHEAXIRSTS_Pos) /*!< 0x40000000 */
#define RCC_AHB5RSTSR_CACHEAXIRSTS RCC_AHB5RSTSR_CACHEAXIRSTS_Msk /*!< CACHEAXI reset */
#define RCC_AHB5RSTSR_NPURSTS_Pos (31U)
#define RCC_AHB5RSTSR_NPURSTS_Msk (0x1UL << RCC_AHB5RSTSR_NPURSTS_Pos) /*!< 0x80000000 */
#define RCC_AHB5RSTSR_NPURSTS RCC_AHB5RSTSR_NPURSTS_Msk /*!< NPU reset */
/**************** Bit definition for RCC_APB1RSTSR1 register ****************/
#define RCC_APB1RSTSR1_TIM2RSTS_Pos (0U)
#define RCC_APB1RSTSR1_TIM2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM2RSTS_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTSR1_TIM2RSTS RCC_APB1RSTSR1_TIM2RSTS_Msk /*!< TIM2 reset */
#define RCC_APB1RSTSR1_TIM3RSTS_Pos (1U)
#define RCC_APB1RSTSR1_TIM3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM3RSTS_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTSR1_TIM3RSTS RCC_APB1RSTSR1_TIM3RSTS_Msk /*!< TIM3 reset */
#define RCC_APB1RSTSR1_TIM4RSTS_Pos (2U)
#define RCC_APB1RSTSR1_TIM4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM4RSTS_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTSR1_TIM4RSTS RCC_APB1RSTSR1_TIM4RSTS_Msk /*!< TIM4 reset */
#define RCC_APB1RSTSR1_TIM5RSTS_Pos (3U)
#define RCC_APB1RSTSR1_TIM5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM5RSTS_Pos)/*!< 0x00000008 */
#define RCC_APB1RSTSR1_TIM5RSTS RCC_APB1RSTSR1_TIM5RSTS_Msk /*!< TIM5 reset */
#define RCC_APB1RSTSR1_TIM6RSTS_Pos (4U)
#define RCC_APB1RSTSR1_TIM6RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM6RSTS_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTSR1_TIM6RSTS RCC_APB1RSTSR1_TIM6RSTS_Msk /*!< TIM6 reset */
#define RCC_APB1RSTSR1_TIM7RSTS_Pos (5U)
#define RCC_APB1RSTSR1_TIM7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM7RSTS_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTSR1_TIM7RSTS RCC_APB1RSTSR1_TIM7RSTS_Msk /*!< TIM7 reset */
#define RCC_APB1RSTSR1_TIM12RSTS_Pos (6U)
#define RCC_APB1RSTSR1_TIM12RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM12RSTS_Pos) /*!< 0x00000040 */
#define RCC_APB1RSTSR1_TIM12RSTS RCC_APB1RSTSR1_TIM12RSTS_Msk /*!< TIM12 reset */
#define RCC_APB1RSTSR1_TIM13RSTS_Pos (7U)
#define RCC_APB1RSTSR1_TIM13RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM13RSTS_Pos) /*!< 0x00000080 */
#define RCC_APB1RSTSR1_TIM13RSTS RCC_APB1RSTSR1_TIM13RSTS_Msk /*!< TIM13 reset */
#define RCC_APB1RSTSR1_TIM14RSTS_Pos (8U)
#define RCC_APB1RSTSR1_TIM14RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM14RSTS_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTSR1_TIM14RSTS RCC_APB1RSTSR1_TIM14RSTS_Msk /*!< TIM14 reset */
#define RCC_APB1RSTSR1_LPTIM1RSTS_Pos (9U)
#define RCC_APB1RSTSR1_LPTIM1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_LPTIM1RSTS_Pos) /*!< 0x00000200 */
#define RCC_APB1RSTSR1_LPTIM1RSTS RCC_APB1RSTSR1_LPTIM1RSTS_Msk /*!< LPTIM1 reset */
#define RCC_APB1RSTSR1_WWDGRSTS_Pos (11U)
#define RCC_APB1RSTSR1_WWDGRSTS_Msk (0x1UL << RCC_APB1RSTSR1_WWDGRSTS_Pos)/*!< 0x00000800 */
#define RCC_APB1RSTSR1_WWDGRSTS RCC_APB1RSTSR1_WWDGRSTS_Msk /*!< WWDG reset */
#define RCC_APB1RSTSR1_TIM10RSTS_Pos (12U)
#define RCC_APB1RSTSR1_TIM10RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM10RSTS_Pos) /*!< 0x00001000 */
#define RCC_APB1RSTSR1_TIM10RSTS RCC_APB1RSTSR1_TIM10RSTS_Msk /*!< TIM10 reset */
#define RCC_APB1RSTSR1_TIM11RSTS_Pos (13U)
#define RCC_APB1RSTSR1_TIM11RSTS_Msk (0x1UL << RCC_APB1RSTSR1_TIM11RSTS_Pos) /*!< 0x00002000 */
#define RCC_APB1RSTSR1_TIM11RSTS RCC_APB1RSTSR1_TIM11RSTS_Msk /*!< TIM11 reset */
#define RCC_APB1RSTSR1_SPI2RSTS_Pos (14U)
#define RCC_APB1RSTSR1_SPI2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI2RSTS_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTSR1_SPI2RSTS RCC_APB1RSTSR1_SPI2RSTS_Msk /*!< SPI2 reset */
#define RCC_APB1RSTSR1_SPI3RSTS_Pos (15U)
#define RCC_APB1RSTSR1_SPI3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPI3RSTS_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTSR1_SPI3RSTS RCC_APB1RSTSR1_SPI3RSTS_Msk /*!< SPI3 reset */
#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos (16U)
#define RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_SPDIFRX1RSTS_Pos) /*!< 0x00010000 */
#define RCC_APB1RSTSR1_SPDIFRX1RSTS RCC_APB1RSTSR1_SPDIFRX1RSTS_Msk /*!< SPDIFRX1 reset */
#define RCC_APB1RSTSR1_USART2RSTS_Pos (17U)
#define RCC_APB1RSTSR1_USART2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART2RSTS_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTSR1_USART2RSTS RCC_APB1RSTSR1_USART2RSTS_Msk /*!< USART2 reset */
#define RCC_APB1RSTSR1_USART3RSTS_Pos (18U)
#define RCC_APB1RSTSR1_USART3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_USART3RSTS_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTSR1_USART3RSTS RCC_APB1RSTSR1_USART3RSTS_Msk /*!< USART3 reset */
#define RCC_APB1RSTSR1_UART4RSTS_Pos (19U)
#define RCC_APB1RSTSR1_UART4RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART4RSTS_Pos) /*!< 0x00080000 */
#define RCC_APB1RSTSR1_UART4RSTS RCC_APB1RSTSR1_UART4RSTS_Msk /*!< UART4 reset */
#define RCC_APB1RSTSR1_UART5RSTS_Pos (20U)
#define RCC_APB1RSTSR1_UART5RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART5RSTS_Pos) /*!< 0x00100000 */
#define RCC_APB1RSTSR1_UART5RSTS RCC_APB1RSTSR1_UART5RSTS_Msk /*!< UART5 reset */
#define RCC_APB1RSTSR1_I2C1RSTS_Pos (21U)
#define RCC_APB1RSTSR1_I2C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C1RSTS_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTSR1_I2C1RSTS RCC_APB1RSTSR1_I2C1RSTS_Msk /*!< I2C1 reset */
#define RCC_APB1RSTSR1_I2C2RSTS_Pos (22U)
#define RCC_APB1RSTSR1_I2C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C2RSTS_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTSR1_I2C2RSTS RCC_APB1RSTSR1_I2C2RSTS_Msk /*!< I2C2 reset */
#define RCC_APB1RSTSR1_I2C3RSTS_Pos (23U)
#define RCC_APB1RSTSR1_I2C3RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I2C3RSTS_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTSR1_I2C3RSTS RCC_APB1RSTSR1_I2C3RSTS_Msk /*!< I2C3 reset */
#define RCC_APB1RSTSR1_I3C1RSTS_Pos (24U)
#define RCC_APB1RSTSR1_I3C1RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C1RSTS_Pos)/*!< 0x01000000 */
#define RCC_APB1RSTSR1_I3C1RSTS RCC_APB1RSTSR1_I3C1RSTS_Msk /*!< I3C1 reset */
#define RCC_APB1RSTSR1_I3C2RSTS_Pos (25U)
#define RCC_APB1RSTSR1_I3C2RSTS_Msk (0x1UL << RCC_APB1RSTSR1_I3C2RSTS_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTSR1_I3C2RSTS RCC_APB1RSTSR1_I3C2RSTS_Msk /*!< I3C2 reset */
#define RCC_APB1RSTSR1_UART7RSTS_Pos (30U)
#define RCC_APB1RSTSR1_UART7RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART7RSTS_Pos) /*!< 0x40000000 */
#define RCC_APB1RSTSR1_UART7RSTS RCC_APB1RSTSR1_UART7RSTS_Msk /*!< UART7 reset */
#define RCC_APB1RSTSR1_UART8RSTS_Pos (31U)
#define RCC_APB1RSTSR1_UART8RSTS_Msk (0x1UL << RCC_APB1RSTSR1_UART8RSTS_Pos) /*!< 0x80000000 */
#define RCC_APB1RSTSR1_UART8RSTS RCC_APB1RSTSR1_UART8RSTS_Msk /*!< UART8 reset */
/**************** Bit definition for RCC_APB1RSTSR2 register ****************/
#define RCC_APB1RSTSR2_MDIOSRSTS_Pos (5U)
#define RCC_APB1RSTSR2_MDIOSRSTS_Msk (0x1UL << RCC_APB1RSTSR2_MDIOSRSTS_Pos) /*!< 0x00000020 */
#define RCC_APB1RSTSR2_MDIOSRSTS RCC_APB1RSTSR2_MDIOSRSTS_Msk /*!< MDIOS reset */
#define RCC_APB1RSTSR2_FDCANRSTS_Pos (8U)
#define RCC_APB1RSTSR2_FDCANRSTS_Msk (0x1UL << RCC_APB1RSTSR2_FDCANRSTS_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTSR2_FDCANRSTS RCC_APB1RSTSR2_FDCANRSTS_Msk /*!< FDCAN reset */
#define RCC_APB1RSTSR2_UCPD1RSTS_Pos (18U)
#define RCC_APB1RSTSR2_UCPD1RSTS_Msk (0x1UL << RCC_APB1RSTSR2_UCPD1RSTS_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTSR2_UCPD1RSTS RCC_APB1RSTSR2_UCPD1RSTS_Msk /*!< UCPD1 reset */
/**************** Bit definition for RCC_APB2RSTSR register *****************/
#define RCC_APB2RSTSR_TIM1RSTS_Pos (0U)
#define RCC_APB2RSTSR_TIM1RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM1RSTS_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTSR_TIM1RSTS RCC_APB2RSTSR_TIM1RSTS_Msk /*!< TIM1 reset */
#define RCC_APB2RSTSR_TIM8RSTS_Pos (1U)
#define RCC_APB2RSTSR_TIM8RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM8RSTS_Pos) /*!< 0x00000002 */
#define RCC_APB2RSTSR_TIM8RSTS RCC_APB2RSTSR_TIM8RSTS_Msk /*!< TIM8 reset */
#define RCC_APB2RSTSR_USART1RSTS_Pos (4U)
#define RCC_APB2RSTSR_USART1RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART1RSTS_Pos) /*!< 0x00000010 */
#define RCC_APB2RSTSR_USART1RSTS RCC_APB2RSTSR_USART1RSTS_Msk /*!< USART1 reset */
#define RCC_APB2RSTSR_USART6RSTS_Pos (5U)
#define RCC_APB2RSTSR_USART6RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART6RSTS_Pos) /*!< 0x00000020 */
#define RCC_APB2RSTSR_USART6RSTS RCC_APB2RSTSR_USART6RSTS_Msk /*!< USART6 reset */
#define RCC_APB2RSTSR_UART9RSTS_Pos (6U)
#define RCC_APB2RSTSR_UART9RSTS_Msk (0x1UL << RCC_APB2RSTSR_UART9RSTS_Pos)/*!< 0x00000040 */
#define RCC_APB2RSTSR_UART9RSTS RCC_APB2RSTSR_UART9RSTS_Msk /*!< UART9 reset */
#define RCC_APB2RSTSR_USART10RSTS_Pos (7U)
#define RCC_APB2RSTSR_USART10RSTS_Msk (0x1UL << RCC_APB2RSTSR_USART10RSTS_Pos) /*!< 0x00000080 */
#define RCC_APB2RSTSR_USART10RSTS RCC_APB2RSTSR_USART10RSTS_Msk /*!< USART10 reset */
#define RCC_APB2RSTSR_SPI1RSTS_Pos (12U)
#define RCC_APB2RSTSR_SPI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI1RSTS_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTSR_SPI1RSTS RCC_APB2RSTSR_SPI1RSTS_Msk /*!< SPI1 reset */
#define RCC_APB2RSTSR_SPI4RSTS_Pos (13U)
#define RCC_APB2RSTSR_SPI4RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI4RSTS_Pos) /*!< 0x00002000 */
#define RCC_APB2RSTSR_SPI4RSTS RCC_APB2RSTSR_SPI4RSTS_Msk /*!< SPI4 reset */
#define RCC_APB2RSTSR_TIM18RSTS_Pos (15U)
#define RCC_APB2RSTSR_TIM18RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM18RSTS_Pos)/*!< 0x00008000 */
#define RCC_APB2RSTSR_TIM18RSTS RCC_APB2RSTSR_TIM18RSTS_Msk /*!< TIM18 reset */
#define RCC_APB2RSTSR_TIM15RSTS_Pos (16U)
#define RCC_APB2RSTSR_TIM15RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM15RSTS_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTSR_TIM15RSTS RCC_APB2RSTSR_TIM15RSTS_Msk /*!< TIM15 reset */
#define RCC_APB2RSTSR_TIM16RSTS_Pos (17U)
#define RCC_APB2RSTSR_TIM16RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM16RSTS_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTSR_TIM16RSTS RCC_APB2RSTSR_TIM16RSTS_Msk /*!< TIM16 reset */
#define RCC_APB2RSTSR_TIM17RSTS_Pos (18U)
#define RCC_APB2RSTSR_TIM17RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM17RSTS_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTSR_TIM17RSTS RCC_APB2RSTSR_TIM17RSTS_Msk /*!< TIM17 reset */
#define RCC_APB2RSTSR_TIM9RSTS_Pos (19U)
#define RCC_APB2RSTSR_TIM9RSTS_Msk (0x1UL << RCC_APB2RSTSR_TIM9RSTS_Pos) /*!< 0x00080000 */
#define RCC_APB2RSTSR_TIM9RSTS RCC_APB2RSTSR_TIM9RSTS_Msk /*!< TIM9 reset */
#define RCC_APB2RSTSR_SPI5RSTS_Pos (20U)
#define RCC_APB2RSTSR_SPI5RSTS_Msk (0x1UL << RCC_APB2RSTSR_SPI5RSTS_Pos) /*!< 0x00100000 */
#define RCC_APB2RSTSR_SPI5RSTS RCC_APB2RSTSR_SPI5RSTS_Msk /*!< SPI5 reset */
#define RCC_APB2RSTSR_SAI1RSTS_Pos (21U)
#define RCC_APB2RSTSR_SAI1RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI1RSTS_Pos) /*!< 0x00200000 */
#define RCC_APB2RSTSR_SAI1RSTS RCC_APB2RSTSR_SAI1RSTS_Msk /*!< SAI1 reset */
#define RCC_APB2RSTSR_SAI2RSTS_Pos (22U)
#define RCC_APB2RSTSR_SAI2RSTS_Msk (0x1UL << RCC_APB2RSTSR_SAI2RSTS_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTSR_SAI2RSTS RCC_APB2RSTSR_SAI2RSTS_Msk /*!< SAI2 reset */
/**************** Bit definition for RCC_APB4RSTSR1 register ****************/
#define RCC_APB4RSTSR1_HDPRSTS_Pos (2U)
#define RCC_APB4RSTSR1_HDPRSTS_Msk (0x1UL << RCC_APB4RSTSR1_HDPRSTS_Pos) /*!< 0x00000004 */
#define RCC_APB4RSTSR1_HDPRSTS RCC_APB4RSTSR1_HDPRSTS_Msk /*!< HDP reset */
#define RCC_APB4RSTSR1_LPUART1RSTS_Pos (3U)
#define RCC_APB4RSTSR1_LPUART1RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPUART1RSTS_Pos) /*!< 0x00000008 */
#define RCC_APB4RSTSR1_LPUART1RSTS RCC_APB4RSTSR1_LPUART1RSTS_Msk /*!< LPUART1 reset */
#define RCC_APB4RSTSR1_SPI6RSTS_Pos (5U)
#define RCC_APB4RSTSR1_SPI6RSTS_Msk (0x1UL << RCC_APB4RSTSR1_SPI6RSTS_Pos)/*!< 0x00000020 */
#define RCC_APB4RSTSR1_SPI6RSTS RCC_APB4RSTSR1_SPI6RSTS_Msk /*!< SPI6 reset */
#define RCC_APB4RSTSR1_I2C4RSTS_Pos (7U)
#define RCC_APB4RSTSR1_I2C4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_I2C4RSTS_Pos)/*!< 0x00000080 */
#define RCC_APB4RSTSR1_I2C4RSTS RCC_APB4RSTSR1_I2C4RSTS_Msk /*!< I2C4 reset */
#define RCC_APB4RSTSR1_LPTIM2RSTS_Pos (9U)
#define RCC_APB4RSTSR1_LPTIM2RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM2RSTS_Pos) /*!< 0x00000200 */
#define RCC_APB4RSTSR1_LPTIM2RSTS RCC_APB4RSTSR1_LPTIM2RSTS_Msk /*!< LPTIM2 reset */
#define RCC_APB4RSTSR1_LPTIM3RSTS_Pos (10U)
#define RCC_APB4RSTSR1_LPTIM3RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM3RSTS_Pos) /*!< 0x00000400 */
#define RCC_APB4RSTSR1_LPTIM3RSTS RCC_APB4RSTSR1_LPTIM3RSTS_Msk /*!< LPTIM3 reset */
#define RCC_APB4RSTSR1_LPTIM4RSTS_Pos (11U)
#define RCC_APB4RSTSR1_LPTIM4RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM4RSTS_Pos) /*!< 0x00000800 */
#define RCC_APB4RSTSR1_LPTIM4RSTS RCC_APB4RSTSR1_LPTIM4RSTS_Msk /*!< LPTIM4 reset */
#define RCC_APB4RSTSR1_LPTIM5RSTS_Pos (12U)
#define RCC_APB4RSTSR1_LPTIM5RSTS_Msk (0x1UL << RCC_APB4RSTSR1_LPTIM5RSTS_Pos) /*!< 0x00001000 */
#define RCC_APB4RSTSR1_LPTIM5RSTS RCC_APB4RSTSR1_LPTIM5RSTS_Msk /*!< LPTIM5 reset */
#define RCC_APB4RSTSR1_VREFBUFRSTS_Pos (15U)
#define RCC_APB4RSTSR1_VREFBUFRSTS_Msk (0x1UL << RCC_APB4RSTSR1_VREFBUFRSTS_Pos) /*!< 0x00008000 */
#define RCC_APB4RSTSR1_VREFBUFRSTS RCC_APB4RSTSR1_VREFBUFRSTS_Msk /*!< VREFBUF reset */
#define RCC_APB4RSTSR1_RTCRSTS_Pos (16U)
#define RCC_APB4RSTSR1_RTCRSTS_Msk (0x1UL << RCC_APB4RSTSR1_RTCRSTS_Pos) /*!< 0x00010000 */
#define RCC_APB4RSTSR1_RTCRSTS RCC_APB4RSTSR1_RTCRSTS_Msk /*!< RTC reset */
/**************** Bit definition for RCC_APB4RSTSR2 register ****************/
#define RCC_APB4RSTSR2_SYSCFGRSTS_Pos (0U)
#define RCC_APB4RSTSR2_SYSCFGRSTS_Msk (0x1UL << RCC_APB4RSTSR2_SYSCFGRSTS_Pos) /*!< 0x00000001 */
#define RCC_APB4RSTSR2_SYSCFGRSTS RCC_APB4RSTSR2_SYSCFGRSTS_Msk /*!< SYSCFG reset */
#define RCC_APB4RSTSR2_DTSRSTS_Pos (2U)
#define RCC_APB4RSTSR2_DTSRSTS_Msk (0x1UL << RCC_APB4RSTSR2_DTSRSTS_Pos) /*!< 0x00000004 */
#define RCC_APB4RSTSR2_DTSRSTS RCC_APB4RSTSR2_DTSRSTS_Msk /*!< DTS reset */
/**************** Bit definition for RCC_APB5RSTSR register *****************/
#define RCC_APB5RSTSR_LTDCRSTS_Pos (1U)
#define RCC_APB5RSTSR_LTDCRSTS_Msk (0x1UL << RCC_APB5RSTSR_LTDCRSTS_Pos) /*!< 0x00000002 */
#define RCC_APB5RSTSR_LTDCRSTS RCC_APB5RSTSR_LTDCRSTS_Msk /*!< LTDC reset */
#define RCC_APB5RSTSR_DCMIPPRSTS_Pos (2U)
#define RCC_APB5RSTSR_DCMIPPRSTS_Msk (0x1UL << RCC_APB5RSTSR_DCMIPPRSTS_Pos) /*!< 0x00000004 */
#define RCC_APB5RSTSR_DCMIPPRSTS RCC_APB5RSTSR_DCMIPPRSTS_Msk /*!< DCMIPP reset */
#define RCC_APB5RSTSR_GFXTIMRSTS_Pos (4U)
#define RCC_APB5RSTSR_GFXTIMRSTS_Msk (0x1UL << RCC_APB5RSTSR_GFXTIMRSTS_Pos) /*!< 0x00000010 */
#define RCC_APB5RSTSR_GFXTIMRSTS RCC_APB5RSTSR_GFXTIMRSTS_Msk /*!< GFXTIM reset */
#define RCC_APB5RSTSR_VENCRSTS_Pos (5U)
#define RCC_APB5RSTSR_VENCRSTS_Msk (0x1UL << RCC_APB5RSTSR_VENCRSTS_Pos) /*!< 0x00000020 */
#define RCC_APB5RSTSR_VENCRSTS RCC_APB5RSTSR_VENCRSTS_Msk /*!< VENC reset */
#define RCC_APB5RSTSR_CSIRSTS_Pos (6U)
#define RCC_APB5RSTSR_CSIRSTS_Msk (0x1UL << RCC_APB5RSTSR_CSIRSTS_Pos) /*!< 0x00000040 */
#define RCC_APB5RSTSR_CSIRSTS RCC_APB5RSTSR_CSIRSTS_Msk /*!< CSI reset */
/***************** Bit definition for RCC_DIVENSR register ******************/
#define RCC_DIVENSR_IC1ENS_Pos (0U)
#define RCC_DIVENSR_IC1ENS_Msk (0x1UL << RCC_DIVENSR_IC1ENS_Pos) /*!< 0x00000001 */
#define RCC_DIVENSR_IC1ENS RCC_DIVENSR_IC1ENS_Msk /*!< IC1 enable */
#define RCC_DIVENSR_IC2ENS_Pos (1U)
#define RCC_DIVENSR_IC2ENS_Msk (0x1UL << RCC_DIVENSR_IC2ENS_Pos) /*!< 0x00000002 */
#define RCC_DIVENSR_IC2ENS RCC_DIVENSR_IC2ENS_Msk /*!< IC2 enable */
#define RCC_DIVENSR_IC3ENS_Pos (2U)
#define RCC_DIVENSR_IC3ENS_Msk (0x1UL << RCC_DIVENSR_IC3ENS_Pos) /*!< 0x00000004 */
#define RCC_DIVENSR_IC3ENS RCC_DIVENSR_IC3ENS_Msk /*!< IC3 enable */
#define RCC_DIVENSR_IC4ENS_Pos (3U)
#define RCC_DIVENSR_IC4ENS_Msk (0x1UL << RCC_DIVENSR_IC4ENS_Pos) /*!< 0x00000008 */
#define RCC_DIVENSR_IC4ENS RCC_DIVENSR_IC4ENS_Msk /*!< IC4 enable */
#define RCC_DIVENSR_IC5ENS_Pos (4U)
#define RCC_DIVENSR_IC5ENS_Msk (0x1UL << RCC_DIVENSR_IC5ENS_Pos) /*!< 0x00000010 */
#define RCC_DIVENSR_IC5ENS RCC_DIVENSR_IC5ENS_Msk /*!< IC5 enable */
#define RCC_DIVENSR_IC6ENS_Pos (5U)
#define RCC_DIVENSR_IC6ENS_Msk (0x1UL << RCC_DIVENSR_IC6ENS_Pos) /*!< 0x00000020 */
#define RCC_DIVENSR_IC6ENS RCC_DIVENSR_IC6ENS_Msk /*!< IC6 enable */
#define RCC_DIVENSR_IC7ENS_Pos (6U)
#define RCC_DIVENSR_IC7ENS_Msk (0x1UL << RCC_DIVENSR_IC7ENS_Pos) /*!< 0x00000040 */
#define RCC_DIVENSR_IC7ENS RCC_DIVENSR_IC7ENS_Msk /*!< IC7 enable */
#define RCC_DIVENSR_IC8ENS_Pos (7U)
#define RCC_DIVENSR_IC8ENS_Msk (0x1UL << RCC_DIVENSR_IC8ENS_Pos) /*!< 0x00000080 */
#define RCC_DIVENSR_IC8ENS RCC_DIVENSR_IC8ENS_Msk /*!< IC8 enable */
#define RCC_DIVENSR_IC9ENS_Pos (8U)
#define RCC_DIVENSR_IC9ENS_Msk (0x1UL << RCC_DIVENSR_IC9ENS_Pos) /*!< 0x00000100 */
#define RCC_DIVENSR_IC9ENS RCC_DIVENSR_IC9ENS_Msk /*!< IC9 enable */
#define RCC_DIVENSR_IC10ENS_Pos (9U)
#define RCC_DIVENSR_IC10ENS_Msk (0x1UL << RCC_DIVENSR_IC10ENS_Pos) /*!< 0x00000200 */
#define RCC_DIVENSR_IC10ENS RCC_DIVENSR_IC10ENS_Msk /*!< IC10 enable */
#define RCC_DIVENSR_IC11ENS_Pos (10U)
#define RCC_DIVENSR_IC11ENS_Msk (0x1UL << RCC_DIVENSR_IC11ENS_Pos) /*!< 0x00000400 */
#define RCC_DIVENSR_IC11ENS RCC_DIVENSR_IC11ENS_Msk /*!< IC11 enable */
#define RCC_DIVENSR_IC12ENS_Pos (11U)
#define RCC_DIVENSR_IC12ENS_Msk (0x1UL << RCC_DIVENSR_IC12ENS_Pos) /*!< 0x00000800 */
#define RCC_DIVENSR_IC12ENS RCC_DIVENSR_IC12ENS_Msk /*!< IC12 enable */
#define RCC_DIVENSR_IC13ENS_Pos (12U)
#define RCC_DIVENSR_IC13ENS_Msk (0x1UL << RCC_DIVENSR_IC13ENS_Pos) /*!< 0x00001000 */
#define RCC_DIVENSR_IC13ENS RCC_DIVENSR_IC13ENS_Msk /*!< IC13 enable */
#define RCC_DIVENSR_IC14ENS_Pos (13U)
#define RCC_DIVENSR_IC14ENS_Msk (0x1UL << RCC_DIVENSR_IC14ENS_Pos) /*!< 0x00002000 */
#define RCC_DIVENSR_IC14ENS RCC_DIVENSR_IC14ENS_Msk /*!< IC14 enable */
#define RCC_DIVENSR_IC15ENS_Pos (14U)
#define RCC_DIVENSR_IC15ENS_Msk (0x1UL << RCC_DIVENSR_IC15ENS_Pos) /*!< 0x00004000 */
#define RCC_DIVENSR_IC15ENS RCC_DIVENSR_IC15ENS_Msk /*!< IC15 enable */
#define RCC_DIVENSR_IC16ENS_Pos (15U)
#define RCC_DIVENSR_IC16ENS_Msk (0x1UL << RCC_DIVENSR_IC16ENS_Pos) /*!< 0x00008000 */
#define RCC_DIVENSR_IC16ENS RCC_DIVENSR_IC16ENS_Msk /*!< IC16 enable */
#define RCC_DIVENSR_IC17ENS_Pos (16U)
#define RCC_DIVENSR_IC17ENS_Msk (0x1UL << RCC_DIVENSR_IC17ENS_Pos) /*!< 0x00010000 */
#define RCC_DIVENSR_IC17ENS RCC_DIVENSR_IC17ENS_Msk /*!< IC17 enable */
#define RCC_DIVENSR_IC18ENS_Pos (17U)
#define RCC_DIVENSR_IC18ENS_Msk (0x1UL << RCC_DIVENSR_IC18ENS_Pos) /*!< 0x00020000 */
#define RCC_DIVENSR_IC18ENS RCC_DIVENSR_IC18ENS_Msk /*!< IC18 enable */
#define RCC_DIVENSR_IC19ENS_Pos (18U)
#define RCC_DIVENSR_IC19ENS_Msk (0x1UL << RCC_DIVENSR_IC19ENS_Pos) /*!< 0x00040000 */
#define RCC_DIVENSR_IC19ENS RCC_DIVENSR_IC19ENS_Msk /*!< IC19 enable */
#define RCC_DIVENSR_IC20ENS_Pos (19U)
#define RCC_DIVENSR_IC20ENS_Msk (0x1UL << RCC_DIVENSR_IC20ENS_Pos) /*!< 0x00080000 */
#define RCC_DIVENSR_IC20ENS RCC_DIVENSR_IC20ENS_Msk /*!< IC20 enable */
/***************** Bit definition for RCC_BUSENSR register ******************/
#define RCC_BUSENSR_ACLKNENS_Pos (0U)
#define RCC_BUSENSR_ACLKNENS_Msk (0x1UL << RCC_BUSENSR_ACLKNENS_Pos) /*!< 0x00000001 */
#define RCC_BUSENSR_ACLKNENS RCC_BUSENSR_ACLKNENS_Msk /*!< ACLKN enable */
#define RCC_BUSENSR_ACLKNCENS_Pos (1U)
#define RCC_BUSENSR_ACLKNCENS_Msk (0x1UL << RCC_BUSENSR_ACLKNCENS_Pos) /*!< 0x00000002 */
#define RCC_BUSENSR_ACLKNCENS RCC_BUSENSR_ACLKNCENS_Msk /*!< ACLKNC enable */
#define RCC_BUSENSR_AHBMENS_Pos (2U)
#define RCC_BUSENSR_AHBMENS_Msk (0x1UL << RCC_BUSENSR_AHBMENS_Pos) /*!< 0x00000004 */
#define RCC_BUSENSR_AHBMENS RCC_BUSENSR_AHBMENS_Msk /*!< AHBM enable */
#define RCC_BUSENSR_AHB1ENS_Pos (3U)
#define RCC_BUSENSR_AHB1ENS_Msk (0x1UL << RCC_BUSENSR_AHB1ENS_Pos) /*!< 0x00000008 */
#define RCC_BUSENSR_AHB1ENS RCC_BUSENSR_AHB1ENS_Msk /*!< AHB1 enable */
#define RCC_BUSENSR_AHB2ENS_Pos (4U)
#define RCC_BUSENSR_AHB2ENS_Msk (0x1UL << RCC_BUSENSR_AHB2ENS_Pos) /*!< 0x00000010 */
#define RCC_BUSENSR_AHB2ENS RCC_BUSENSR_AHB2ENS_Msk /*!< AHB2 enable */
#define RCC_BUSENSR_AHB3ENS_Pos (5U)
#define RCC_BUSENSR_AHB3ENS_Msk (0x1UL << RCC_BUSENSR_AHB3ENS_Pos) /*!< 0x00000020 */
#define RCC_BUSENSR_AHB3ENS RCC_BUSENSR_AHB3ENS_Msk /*!< AHB3 enable */
#define RCC_BUSENSR_AHB4ENS_Pos (6U)
#define RCC_BUSENSR_AHB4ENS_Msk (0x1UL << RCC_BUSENSR_AHB4ENS_Pos) /*!< 0x00000040 */
#define RCC_BUSENSR_AHB4ENS RCC_BUSENSR_AHB4ENS_Msk /*!< AHB4 enable */
#define RCC_BUSENSR_AHB5ENS_Pos (7U)
#define RCC_BUSENSR_AHB5ENS_Msk (0x1UL << RCC_BUSENSR_AHB5ENS_Pos) /*!< 0x00000080 */
#define RCC_BUSENSR_AHB5ENS RCC_BUSENSR_AHB5ENS_Msk /*!< AHB5 enable */
#define RCC_BUSENSR_APB1ENS_Pos (8U)
#define RCC_BUSENSR_APB1ENS_Msk (0x1UL << RCC_BUSENSR_APB1ENS_Pos) /*!< 0x00000100 */
#define RCC_BUSENSR_APB1ENS RCC_BUSENSR_APB1ENS_Msk /*!< APB1 enable */
#define RCC_BUSENSR_APB2ENS_Pos (9U)
#define RCC_BUSENSR_APB2ENS_Msk (0x1UL << RCC_BUSENSR_APB2ENS_Pos) /*!< 0x00000200 */
#define RCC_BUSENSR_APB2ENS RCC_BUSENSR_APB2ENS_Msk /*!< APB2 enable */
#define RCC_BUSENSR_APB3ENS_Pos (10U)
#define RCC_BUSENSR_APB3ENS_Msk (0x1UL << RCC_BUSENSR_APB3ENS_Pos) /*!< 0x00000400 */
#define RCC_BUSENSR_APB3ENS RCC_BUSENSR_APB3ENS_Msk /*!< APB3 enable */
#define RCC_BUSENSR_APB4ENS_Pos (11U)
#define RCC_BUSENSR_APB4ENS_Msk (0x1UL << RCC_BUSENSR_APB4ENS_Pos) /*!< 0x00000800 */
#define RCC_BUSENSR_APB4ENS RCC_BUSENSR_APB4ENS_Msk /*!< APB4 enable */
#define RCC_BUSENSR_APB5ENS_Pos (12U)
#define RCC_BUSENSR_APB5ENS_Msk (0x1UL << RCC_BUSENSR_APB5ENS_Pos) /*!< 0x00001000 */
#define RCC_BUSENSR_APB5ENS RCC_BUSENSR_APB5ENS_Msk /*!< APB5 enable */
/***************** Bit definition for RCC_MISCENSR register *****************/
#define RCC_MISCENSR_DBGENS_Pos (0U)
#define RCC_MISCENSR_DBGENS_Msk (0x1UL << RCC_MISCENSR_DBGENS_Pos) /*!< 0x00000001 */
#define RCC_MISCENSR_DBGENS RCC_MISCENSR_DBGENS_Msk /*!< DBG enable */
#define RCC_MISCENSR_MCO1ENS_Pos (1U)
#define RCC_MISCENSR_MCO1ENS_Msk (0x1UL << RCC_MISCENSR_MCO1ENS_Pos) /*!< 0x00000002 */
#define RCC_MISCENSR_MCO1ENS RCC_MISCENSR_MCO1ENS_Msk /*!< MCO1 enable */
#define RCC_MISCENSR_MCO2ENS_Pos (2U)
#define RCC_MISCENSR_MCO2ENS_Msk (0x1UL << RCC_MISCENSR_MCO2ENS_Pos) /*!< 0x00000004 */
#define RCC_MISCENSR_MCO2ENS RCC_MISCENSR_MCO2ENS_Msk /*!< MCO2 enable */
#define RCC_MISCENSR_XSPIPHYCOMPENS_Pos (3U)
#define RCC_MISCENSR_XSPIPHYCOMPENS_Msk (0x1UL << RCC_MISCENSR_XSPIPHYCOMPENS_Pos) /*!< 0x00000008 */
#define RCC_MISCENSR_XSPIPHYCOMPENS RCC_MISCENSR_XSPIPHYCOMPENS_Msk /*!< XSPIPHYCOMP enable */
#define RCC_MISCENSR_PERENS_Pos (6U)
#define RCC_MISCENSR_PERENS_Msk (0x1UL << RCC_MISCENSR_PERENS_Pos) /*!< 0x00000040 */
#define RCC_MISCENSR_PERENS RCC_MISCENSR_PERENS_Msk /*!< PER enable */
/***************** Bit definition for RCC_MEMENSR register ******************/
#define RCC_MEMENSR_AXISRAM3ENS_Pos (0U)
#define RCC_MEMENSR_AXISRAM3ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM3ENS_Pos)/*!< 0x00000001 */
#define RCC_MEMENSR_AXISRAM3ENS RCC_MEMENSR_AXISRAM3ENS_Msk /*!< AXISRAM3 enable */
#define RCC_MEMENSR_AXISRAM4ENS_Pos (1U)
#define RCC_MEMENSR_AXISRAM4ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM4ENS_Pos)/*!< 0x00000002 */
#define RCC_MEMENSR_AXISRAM4ENS RCC_MEMENSR_AXISRAM4ENS_Msk /*!< AXISRAM4 enable */
#define RCC_MEMENSR_AXISRAM5ENS_Pos (2U)
#define RCC_MEMENSR_AXISRAM5ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM5ENS_Pos)/*!< 0x00000004 */
#define RCC_MEMENSR_AXISRAM5ENS RCC_MEMENSR_AXISRAM5ENS_Msk /*!< AXISRAM5 enable */
#define RCC_MEMENSR_AXISRAM6ENS_Pos (3U)
#define RCC_MEMENSR_AXISRAM6ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM6ENS_Pos)/*!< 0x00000008 */
#define RCC_MEMENSR_AXISRAM6ENS RCC_MEMENSR_AXISRAM6ENS_Msk /*!< AXISRAM6 enable */
#define RCC_MEMENSR_AHBSRAM1ENS_Pos (4U)
#define RCC_MEMENSR_AHBSRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM1ENS_Pos)/*!< 0x00000010 */
#define RCC_MEMENSR_AHBSRAM1ENS RCC_MEMENSR_AHBSRAM1ENS_Msk /*!< AHBSRAM1 enable */
#define RCC_MEMENSR_AHBSRAM2ENS_Pos (5U)
#define RCC_MEMENSR_AHBSRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AHBSRAM2ENS_Pos)/*!< 0x00000020 */
#define RCC_MEMENSR_AHBSRAM2ENS RCC_MEMENSR_AHBSRAM2ENS_Msk /*!< AHBSRAM2 enable */
#define RCC_MEMENSR_BKPSRAMENS_Pos (6U)
#define RCC_MEMENSR_BKPSRAMENS_Msk (0x1UL << RCC_MEMENSR_BKPSRAMENS_Pos) /*!< 0x00000040 */
#define RCC_MEMENSR_BKPSRAMENS RCC_MEMENSR_BKPSRAMENS_Msk /*!< BKPSRAM enable */
#define RCC_MEMENSR_AXISRAM1ENS_Pos (7U)
#define RCC_MEMENSR_AXISRAM1ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM1ENS_Pos)/*!< 0x00000080 */
#define RCC_MEMENSR_AXISRAM1ENS RCC_MEMENSR_AXISRAM1ENS_Msk /*!< AXISRAM1 enable */
#define RCC_MEMENSR_AXISRAM2ENS_Pos (8U)
#define RCC_MEMENSR_AXISRAM2ENS_Msk (0x1UL << RCC_MEMENSR_AXISRAM2ENS_Pos)/*!< 0x00000100 */
#define RCC_MEMENSR_AXISRAM2ENS RCC_MEMENSR_AXISRAM2ENS_Msk /*!< AXISRAM2 enable */
#define RCC_MEMENSR_FLEXRAMENS_Pos (9U)
#define RCC_MEMENSR_FLEXRAMENS_Msk (0x1UL << RCC_MEMENSR_FLEXRAMENS_Pos) /*!< 0x00000200 */
#define RCC_MEMENSR_FLEXRAMENS RCC_MEMENSR_FLEXRAMENS_Msk /*!< FLEXRAM enable */
#define RCC_MEMENSR_CACHEAXIRAMENS_Pos (10U)
#define RCC_MEMENSR_CACHEAXIRAMENS_Msk (0x1UL << RCC_MEMENSR_CACHEAXIRAMENS_Pos) /*!< 0x00000400 */
#define RCC_MEMENSR_CACHEAXIRAMENS RCC_MEMENSR_CACHEAXIRAMENS_Msk /*!< CACHEAXIRAM enable */
#define RCC_MEMENSR_VENCRAMENS_Pos (11U)
#define RCC_MEMENSR_VENCRAMENS_Msk (0x1UL << RCC_MEMENSR_VENCRAMENS_Pos) /*!< 0x00000800 */
#define RCC_MEMENSR_VENCRAMENS RCC_MEMENSR_VENCRAMENS_Msk /*!< VENCRAM enable */
#define RCC_MEMENSR_BOOTROMENS_Pos (12U)
#define RCC_MEMENSR_BOOTROMENS_Msk (0x1UL << RCC_MEMENSR_BOOTROMENS_Pos) /*!< 0x00001000 */
#define RCC_MEMENSR_BOOTROMENS RCC_MEMENSR_BOOTROMENS_Msk /*!< Boot ROM enable */
/***************** Bit definition for RCC_AHB1ENSR register *****************/
#define RCC_AHB1ENSR_GPDMA1ENS_Pos (4U)
#define RCC_AHB1ENSR_GPDMA1ENS_Msk (0x1UL << RCC_AHB1ENSR_GPDMA1ENS_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENSR_GPDMA1ENS RCC_AHB1ENSR_GPDMA1ENS_Msk /*!< GPDMA1 enable */
#define RCC_AHB1ENSR_ADC12ENS_Pos (5U)
#define RCC_AHB1ENSR_ADC12ENS_Msk (0x1UL << RCC_AHB1ENSR_ADC12ENS_Pos) /*!< 0x00000020 */
#define RCC_AHB1ENSR_ADC12ENS RCC_AHB1ENSR_ADC12ENS_Msk /*!< ADC12 enable */
/***************** Bit definition for RCC_AHB2ENSR register *****************/
#define RCC_AHB2ENSR_RAMCFGENS_Pos (12U)
#define RCC_AHB2ENSR_RAMCFGENS_Msk (0x1UL << RCC_AHB2ENSR_RAMCFGENS_Pos) /*!< 0x00001000 */
#define RCC_AHB2ENSR_RAMCFGENS RCC_AHB2ENSR_RAMCFGENS_Msk /*!< RAMCFG enable */
#define RCC_AHB2ENSR_MDF1ENS_Pos (16U)
#define RCC_AHB2ENSR_MDF1ENS_Msk (0x1UL << RCC_AHB2ENSR_MDF1ENS_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENSR_MDF1ENS RCC_AHB2ENSR_MDF1ENS_Msk /*!< MDF1 enable */
#define RCC_AHB2ENSR_ADF1ENS_Pos (17U)
#define RCC_AHB2ENSR_ADF1ENS_Msk (0x1UL << RCC_AHB2ENSR_ADF1ENS_Pos) /*!< 0x00020000 */
#define RCC_AHB2ENSR_ADF1ENS RCC_AHB2ENSR_ADF1ENS_Msk /*!< ADF1 enable */
/***************** Bit definition for RCC_AHB3ENSR register *****************/
#define RCC_AHB3ENSR_RNGENS_Pos (0U)
#define RCC_AHB3ENSR_RNGENS_Msk (0x1UL << RCC_AHB3ENSR_RNGENS_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENSR_RNGENS RCC_AHB3ENSR_RNGENS_Msk /*!< RNG enable */
#define RCC_AHB3ENSR_HASHENS_Pos (1U)
#define RCC_AHB3ENSR_HASHENS_Msk (0x1UL << RCC_AHB3ENSR_HASHENS_Pos) /*!< 0x00000002 */
#define RCC_AHB3ENSR_HASHENS RCC_AHB3ENSR_HASHENS_Msk /*!< HASH enable */
#define RCC_AHB3ENSR_CRYPENS_Pos (2U)
#define RCC_AHB3ENSR_CRYPENS_Msk (0x1UL << RCC_AHB3ENSR_CRYPENS_Pos) /*!< 0x00000004 */
#define RCC_AHB3ENSR_CRYPENS RCC_AHB3ENSR_CRYPENS_Msk /*!< CRYP enable */
#define RCC_AHB3ENSR_SAESENS_Pos (4U)
#define RCC_AHB3ENSR_SAESENS_Msk (0x1UL << RCC_AHB3ENSR_SAESENS_Pos) /*!< 0x00000010 */
#define RCC_AHB3ENSR_SAESENS RCC_AHB3ENSR_SAESENS_Msk /*!< SAES enable */
#define RCC_AHB3ENSR_PKAENS_Pos (8U)
#define RCC_AHB3ENSR_PKAENS_Msk (0x1UL << RCC_AHB3ENSR_PKAENS_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENSR_PKAENS RCC_AHB3ENSR_PKAENS_Msk /*!< PKA enable */
#define RCC_AHB3ENSR_RIFSCENS_Pos (9U)
#define RCC_AHB3ENSR_RIFSCENS_Msk (0x1UL << RCC_AHB3ENSR_RIFSCENS_Pos) /*!< 0x00000200 */
#define RCC_AHB3ENSR_RIFSCENS RCC_AHB3ENSR_RIFSCENS_Msk /*!< RIFSC enable */
#define RCC_AHB3ENSR_IACENS_Pos (10U)
#define RCC_AHB3ENSR_IACENS_Msk (0x1UL << RCC_AHB3ENSR_IACENS_Pos) /*!< 0x00000400 */
#define RCC_AHB3ENSR_IACENS RCC_AHB3ENSR_IACENS_Msk /*!< IAC enable */
#define RCC_AHB3ENSR_RISAFENS_Pos (14U)
#define RCC_AHB3ENSR_RISAFENS_Msk (0x1UL << RCC_AHB3ENSR_RISAFENS_Pos) /*!< 0x00004000 */
#define RCC_AHB3ENSR_RISAFENS RCC_AHB3ENSR_RISAFENS_Msk /*!< RISAF enable */
/***************** Bit definition for RCC_AHB4ENSR register *****************/
#define RCC_AHB4ENSR_GPIOAENS_Pos (0U)
#define RCC_AHB4ENSR_GPIOAENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOAENS_Pos) /*!< 0x00000001 */
#define RCC_AHB4ENSR_GPIOAENS RCC_AHB4ENSR_GPIOAENS_Msk /*!< GPIO A enable */
#define RCC_AHB4ENSR_GPIOBENS_Pos (1U)
#define RCC_AHB4ENSR_GPIOBENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOBENS_Pos) /*!< 0x00000002 */
#define RCC_AHB4ENSR_GPIOBENS RCC_AHB4ENSR_GPIOBENS_Msk /*!< GPIO B enable */
#define RCC_AHB4ENSR_GPIOCENS_Pos (2U)
#define RCC_AHB4ENSR_GPIOCENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOCENS_Pos) /*!< 0x00000004 */
#define RCC_AHB4ENSR_GPIOCENS RCC_AHB4ENSR_GPIOCENS_Msk /*!< GPIO C enable */
#define RCC_AHB4ENSR_GPIODENS_Pos (3U)
#define RCC_AHB4ENSR_GPIODENS_Msk (0x1UL << RCC_AHB4ENSR_GPIODENS_Pos) /*!< 0x00000008 */
#define RCC_AHB4ENSR_GPIODENS RCC_AHB4ENSR_GPIODENS_Msk /*!< GPIO D enable */
#define RCC_AHB4ENSR_GPIOEENS_Pos (4U)
#define RCC_AHB4ENSR_GPIOEENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOEENS_Pos) /*!< 0x00000010 */
#define RCC_AHB4ENSR_GPIOEENS RCC_AHB4ENSR_GPIOEENS_Msk /*!< GPIO E enable */
#define RCC_AHB4ENSR_GPIOFENS_Pos (5U)
#define RCC_AHB4ENSR_GPIOFENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOFENS_Pos) /*!< 0x00000020 */
#define RCC_AHB4ENSR_GPIOFENS RCC_AHB4ENSR_GPIOFENS_Msk /*!< GPIO F enable */
#define RCC_AHB4ENSR_GPIOGENS_Pos (6U)
#define RCC_AHB4ENSR_GPIOGENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOGENS_Pos) /*!< 0x00000040 */
#define RCC_AHB4ENSR_GPIOGENS RCC_AHB4ENSR_GPIOGENS_Msk /*!< GPIO G enable */
#define RCC_AHB4ENSR_GPIOHENS_Pos (7U)
#define RCC_AHB4ENSR_GPIOHENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOHENS_Pos) /*!< 0x00000080 */
#define RCC_AHB4ENSR_GPIOHENS RCC_AHB4ENSR_GPIOHENS_Msk /*!< GPIO H enable */
#define RCC_AHB4ENSR_GPIONENS_Pos (13U)
#define RCC_AHB4ENSR_GPIONENS_Msk (0x1UL << RCC_AHB4ENSR_GPIONENS_Pos) /*!< 0x00002000 */
#define RCC_AHB4ENSR_GPIONENS RCC_AHB4ENSR_GPIONENS_Msk /*!< GPIO N enable */
#define RCC_AHB4ENSR_GPIOOENS_Pos (14U)
#define RCC_AHB4ENSR_GPIOOENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOOENS_Pos) /*!< 0x00004000 */
#define RCC_AHB4ENSR_GPIOOENS RCC_AHB4ENSR_GPIOOENS_Msk /*!< GPIO O enable */
#define RCC_AHB4ENSR_GPIOPENS_Pos (15U)
#define RCC_AHB4ENSR_GPIOPENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOPENS_Pos) /*!< 0x00008000 */
#define RCC_AHB4ENSR_GPIOPENS RCC_AHB4ENSR_GPIOPENS_Msk /*!< GPIO P enable */
#define RCC_AHB4ENSR_GPIOQENS_Pos (16U)
#define RCC_AHB4ENSR_GPIOQENS_Msk (0x1UL << RCC_AHB4ENSR_GPIOQENS_Pos) /*!< 0x00010000 */
#define RCC_AHB4ENSR_GPIOQENS RCC_AHB4ENSR_GPIOQENS_Msk /*!< GPIO Q enable */
#define RCC_AHB4ENSR_PWRENS_Pos (18U)
#define RCC_AHB4ENSR_PWRENS_Msk (0x1UL << RCC_AHB4ENSR_PWRENS_Pos) /*!< 0x00040000 */
#define RCC_AHB4ENSR_PWRENS RCC_AHB4ENSR_PWRENS_Msk /*!< PWR enable */
#define RCC_AHB4ENSR_CRCENS_Pos (19U)
#define RCC_AHB4ENSR_CRCENS_Msk (0x1UL << RCC_AHB4ENSR_CRCENS_Pos) /*!< 0x00080000 */
#define RCC_AHB4ENSR_CRCENS RCC_AHB4ENSR_CRCENS_Msk /*!< CRC enable */
/***************** Bit definition for RCC_AHB5ENSR register *****************/
#define RCC_AHB5ENSR_HPDMA1ENS_Pos (0U)
#define RCC_AHB5ENSR_HPDMA1ENS_Msk (0x1UL << RCC_AHB5ENSR_HPDMA1ENS_Pos) /*!< 0x00000001 */
#define RCC_AHB5ENSR_HPDMA1ENS RCC_AHB5ENSR_HPDMA1ENS_Msk /*!< HPDMA1 enable */
#define RCC_AHB5ENSR_DMA2DENS_Pos (1U)
#define RCC_AHB5ENSR_DMA2DENS_Msk (0x1UL << RCC_AHB5ENSR_DMA2DENS_Pos) /*!< 0x00000002 */
#define RCC_AHB5ENSR_DMA2DENS RCC_AHB5ENSR_DMA2DENS_Msk /*!< DMA2D enable */
#define RCC_AHB5ENSR_JPEGENS_Pos (3U)
#define RCC_AHB5ENSR_JPEGENS_Msk (0x1UL << RCC_AHB5ENSR_JPEGENS_Pos) /*!< 0x00000008 */
#define RCC_AHB5ENSR_JPEGENS RCC_AHB5ENSR_JPEGENS_Msk /*!< JPEG enable */
#define RCC_AHB5ENSR_FMCENS_Pos (4U)
#define RCC_AHB5ENSR_FMCENS_Msk (0x1UL << RCC_AHB5ENSR_FMCENS_Pos) /*!< 0x00000010 */
#define RCC_AHB5ENSR_FMCENS RCC_AHB5ENSR_FMCENS_Msk /*!< FMC enable */
#define RCC_AHB5ENSR_XSPI1ENS_Pos (5U)
#define RCC_AHB5ENSR_XSPI1ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI1ENS_Pos) /*!< 0x00000020 */
#define RCC_AHB5ENSR_XSPI1ENS RCC_AHB5ENSR_XSPI1ENS_Msk /*!< XSPI1 enable */
#define RCC_AHB5ENSR_PSSIENS_Pos (6U)
#define RCC_AHB5ENSR_PSSIENS_Msk (0x1UL << RCC_AHB5ENSR_PSSIENS_Pos) /*!< 0x00000040 */
#define RCC_AHB5ENSR_PSSIENS RCC_AHB5ENSR_PSSIENS_Msk /*!< PSSI enable */
#define RCC_AHB5ENSR_SDMMC2ENS_Pos (7U)
#define RCC_AHB5ENSR_SDMMC2ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC2ENS_Pos) /*!< 0x00000080 */
#define RCC_AHB5ENSR_SDMMC2ENS RCC_AHB5ENSR_SDMMC2ENS_Msk /*!< SDMMC2 enable */
#define RCC_AHB5ENSR_SDMMC1ENS_Pos (8U)
#define RCC_AHB5ENSR_SDMMC1ENS_Msk (0x1UL << RCC_AHB5ENSR_SDMMC1ENS_Pos) /*!< 0x00000100 */
#define RCC_AHB5ENSR_SDMMC1ENS RCC_AHB5ENSR_SDMMC1ENS_Msk /*!< SDMMC1 enable */
#define RCC_AHB5ENSR_XSPI2ENS_Pos (12U)
#define RCC_AHB5ENSR_XSPI2ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI2ENS_Pos) /*!< 0x00001000 */
#define RCC_AHB5ENSR_XSPI2ENS RCC_AHB5ENSR_XSPI2ENS_Msk /*!< XSPI2 enable */
#define RCC_AHB5ENSR_XSPIMENS_Pos (13U)
#define RCC_AHB5ENSR_XSPIMENS_Msk (0x1UL << RCC_AHB5ENSR_XSPIMENS_Pos) /*!< 0x00002000 */
#define RCC_AHB5ENSR_XSPIMENS RCC_AHB5ENSR_XSPIMENS_Msk /*!< XSPIM enable */
#define RCC_AHB5ENSR_MCE1ENS_Pos (14U)
#define RCC_AHB5ENSR_MCE1ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE1ENS_Pos) /*!< 0x00004000 */
#define RCC_AHB5ENSR_MCE1ENS RCC_AHB5ENSR_MCE1ENS_Msk /*!< MCE1 enable */
#define RCC_AHB5ENSR_MCE2ENS_Pos (15U)
#define RCC_AHB5ENSR_MCE2ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE2ENS_Pos) /*!< 0x00008000 */
#define RCC_AHB5ENSR_MCE2ENS RCC_AHB5ENSR_MCE2ENS_Msk /*!< MCE2 enable */
#define RCC_AHB5ENSR_MCE3ENS_Pos (16U)
#define RCC_AHB5ENSR_MCE3ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE3ENS_Pos) /*!< 0x00010000 */
#define RCC_AHB5ENSR_MCE3ENS RCC_AHB5ENSR_MCE3ENS_Msk /*!< MCE3 enable */
#define RCC_AHB5ENSR_XSPI3ENS_Pos (17U)
#define RCC_AHB5ENSR_XSPI3ENS_Msk (0x1UL << RCC_AHB5ENSR_XSPI3ENS_Pos) /*!< 0x00020000 */
#define RCC_AHB5ENSR_XSPI3ENS RCC_AHB5ENSR_XSPI3ENS_Msk /*!< XSPI3 enable */
#define RCC_AHB5ENSR_MCE4ENS_Pos (18U)
#define RCC_AHB5ENSR_MCE4ENS_Msk (0x1UL << RCC_AHB5ENSR_MCE4ENS_Pos) /*!< 0x00040000 */
#define RCC_AHB5ENSR_MCE4ENS RCC_AHB5ENSR_MCE4ENS_Msk /*!< MCE4 enable */
#define RCC_AHB5ENSR_GFXMMUENS_Pos (19U)
#define RCC_AHB5ENSR_GFXMMUENS_Msk (0x1UL << RCC_AHB5ENSR_GFXMMUENS_Pos) /*!< 0x00080000 */
#define RCC_AHB5ENSR_GFXMMUENS RCC_AHB5ENSR_GFXMMUENS_Msk /*!< GFXMMU enable */
#define RCC_AHB5ENSR_GPU2DENS_Pos (20U)
#define RCC_AHB5ENSR_GPU2DENS_Msk (0x1UL << RCC_AHB5ENSR_GPU2DENS_Pos) /*!< 0x00100000 */
#define RCC_AHB5ENSR_GPU2DENS RCC_AHB5ENSR_GPU2DENS_Msk /*!< GPU2D enable */
#define RCC_AHB5ENSR_ETH1MACENS_Pos (22U)
#define RCC_AHB5ENSR_ETH1MACENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1MACENS_Pos)/*!< 0x00400000 */
#define RCC_AHB5ENSR_ETH1MACENS RCC_AHB5ENSR_ETH1MACENS_Msk /*!< ETH1MAC enable */
#define RCC_AHB5ENSR_ETH1TXENS_Pos (23U)
#define RCC_AHB5ENSR_ETH1TXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1TXENS_Pos) /*!< 0x00800000 */
#define RCC_AHB5ENSR_ETH1TXENS RCC_AHB5ENSR_ETH1TXENS_Msk /*!< ETH1TX enable */
#define RCC_AHB5ENSR_ETH1RXENS_Pos (24U)
#define RCC_AHB5ENSR_ETH1RXENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1RXENS_Pos) /*!< 0x01000000 */
#define RCC_AHB5ENSR_ETH1RXENS RCC_AHB5ENSR_ETH1RXENS_Msk /*!< ETH1RX enable */
#define RCC_AHB5ENSR_ETH1ENS_Pos (25U)
#define RCC_AHB5ENSR_ETH1ENS_Msk (0x1UL << RCC_AHB5ENSR_ETH1ENS_Pos) /*!< 0x02000000 */
#define RCC_AHB5ENSR_ETH1ENS RCC_AHB5ENSR_ETH1ENS_Msk /*!< ETH1 enable */
#define RCC_AHB5ENSR_OTG1ENS_Pos (26U)
#define RCC_AHB5ENSR_OTG1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG1ENS_Pos) /*!< 0x04000000 */
#define RCC_AHB5ENSR_OTG1ENS RCC_AHB5ENSR_OTG1ENS_Msk /*!< OTG1 enable */
#define RCC_AHB5ENSR_OTGPHY1ENS_Pos (27U)
#define RCC_AHB5ENSR_OTGPHY1ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY1ENS_Pos)/*!< 0x08000000 */
#define RCC_AHB5ENSR_OTGPHY1ENS RCC_AHB5ENSR_OTGPHY1ENS_Msk /*!< OTGPHY1 enable */
#define RCC_AHB5ENSR_OTGPHY2ENS_Pos (28U)
#define RCC_AHB5ENSR_OTGPHY2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTGPHY2ENS_Pos)/*!< 0x10000000 */
#define RCC_AHB5ENSR_OTGPHY2ENS RCC_AHB5ENSR_OTGPHY2ENS_Msk /*!< OTGPHY2 enable */
#define RCC_AHB5ENSR_OTG2ENS_Pos (29U)
#define RCC_AHB5ENSR_OTG2ENS_Msk (0x1UL << RCC_AHB5ENSR_OTG2ENS_Pos) /*!< 0x20000000 */
#define RCC_AHB5ENSR_OTG2ENS RCC_AHB5ENSR_OTG2ENS_Msk /*!< OTG2 enable */
#define RCC_AHB5ENSR_CACHEAXIENS_Pos (30U)
#define RCC_AHB5ENSR_CACHEAXIENS_Msk (0x1UL << RCC_AHB5ENSR_CACHEAXIENS_Pos) /*!< 0x40000000 */
#define RCC_AHB5ENSR_CACHEAXIENS RCC_AHB5ENSR_CACHEAXIENS_Msk /*!< CACHEAXI enable */
#define RCC_AHB5ENSR_NPUENS_Pos (31U)
#define RCC_AHB5ENSR_NPUENS_Msk (0x1UL << RCC_AHB5ENSR_NPUENS_Pos) /*!< 0x80000000 */
#define RCC_AHB5ENSR_NPUENS RCC_AHB5ENSR_NPUENS_Msk /*!< NPU enable */
/**************** Bit definition for RCC_APB1ENSR1 register *****************/
#define RCC_APB1ENSR1_TIM2ENS_Pos (0U)
#define RCC_APB1ENSR1_TIM2ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM2ENS_Pos) /*!< 0x00000001 */
#define RCC_APB1ENSR1_TIM2ENS RCC_APB1ENSR1_TIM2ENS_Msk /*!< TIM2 enable */
#define RCC_APB1ENSR1_TIM3ENS_Pos (1U)
#define RCC_APB1ENSR1_TIM3ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM3ENS_Pos) /*!< 0x00000002 */
#define RCC_APB1ENSR1_TIM3ENS RCC_APB1ENSR1_TIM3ENS_Msk /*!< TIM3 enable */
#define RCC_APB1ENSR1_TIM4ENS_Pos (2U)
#define RCC_APB1ENSR1_TIM4ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM4ENS_Pos) /*!< 0x00000004 */
#define RCC_APB1ENSR1_TIM4ENS RCC_APB1ENSR1_TIM4ENS_Msk /*!< TIM4 enable */
#define RCC_APB1ENSR1_TIM5ENS_Pos (3U)
#define RCC_APB1ENSR1_TIM5ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM5ENS_Pos) /*!< 0x00000008 */
#define RCC_APB1ENSR1_TIM5ENS RCC_APB1ENSR1_TIM5ENS_Msk /*!< TIM5 enable */
#define RCC_APB1ENSR1_TIM6ENS_Pos (4U)
#define RCC_APB1ENSR1_TIM6ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM6ENS_Pos) /*!< 0x00000010 */
#define RCC_APB1ENSR1_TIM6ENS RCC_APB1ENSR1_TIM6ENS_Msk /*!< TIM6 enable */
#define RCC_APB1ENSR1_TIM7ENS_Pos (5U)
#define RCC_APB1ENSR1_TIM7ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM7ENS_Pos) /*!< 0x00000020 */
#define RCC_APB1ENSR1_TIM7ENS RCC_APB1ENSR1_TIM7ENS_Msk /*!< TIM7 enable */
#define RCC_APB1ENSR1_TIM12ENS_Pos (6U)
#define RCC_APB1ENSR1_TIM12ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM12ENS_Pos) /*!< 0x00000040 */
#define RCC_APB1ENSR1_TIM12ENS RCC_APB1ENSR1_TIM12ENS_Msk /*!< TIM12 enable */
#define RCC_APB1ENSR1_TIM13ENS_Pos (7U)
#define RCC_APB1ENSR1_TIM13ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM13ENS_Pos) /*!< 0x00000080 */
#define RCC_APB1ENSR1_TIM13ENS RCC_APB1ENSR1_TIM13ENS_Msk /*!< TIM13 enable */
#define RCC_APB1ENSR1_TIM14ENS_Pos (8U)
#define RCC_APB1ENSR1_TIM14ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM14ENS_Pos) /*!< 0x00000100 */
#define RCC_APB1ENSR1_TIM14ENS RCC_APB1ENSR1_TIM14ENS_Msk /*!< TIM14 enable */
#define RCC_APB1ENSR1_LPTIM1ENS_Pos (9U)
#define RCC_APB1ENSR1_LPTIM1ENS_Msk (0x1UL << RCC_APB1ENSR1_LPTIM1ENS_Pos)/*!< 0x00000200 */
#define RCC_APB1ENSR1_LPTIM1ENS RCC_APB1ENSR1_LPTIM1ENS_Msk /*!< LPTIM1 enable */
#define RCC_APB1ENSR1_WWDGENS_Pos (11U)
#define RCC_APB1ENSR1_WWDGENS_Msk (0x1UL << RCC_APB1ENSR1_WWDGENS_Pos) /*!< 0x00000800 */
#define RCC_APB1ENSR1_WWDGENS RCC_APB1ENSR1_WWDGENS_Msk /*!< WWDG enable */
#define RCC_APB1ENSR1_TIM10ENS_Pos (12U)
#define RCC_APB1ENSR1_TIM10ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM10ENS_Pos) /*!< 0x00001000 */
#define RCC_APB1ENSR1_TIM10ENS RCC_APB1ENSR1_TIM10ENS_Msk /*!< TIM10 enable */
#define RCC_APB1ENSR1_TIM11ENS_Pos (13U)
#define RCC_APB1ENSR1_TIM11ENS_Msk (0x1UL << RCC_APB1ENSR1_TIM11ENS_Pos) /*!< 0x00002000 */
#define RCC_APB1ENSR1_TIM11ENS RCC_APB1ENSR1_TIM11ENS_Msk /*!< TIM11 enable */
#define RCC_APB1ENSR1_SPI2ENS_Pos (14U)
#define RCC_APB1ENSR1_SPI2ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI2ENS_Pos) /*!< 0x00004000 */
#define RCC_APB1ENSR1_SPI2ENS RCC_APB1ENSR1_SPI2ENS_Msk /*!< SPI2 enable */
#define RCC_APB1ENSR1_SPI3ENS_Pos (15U)
#define RCC_APB1ENSR1_SPI3ENS_Msk (0x1UL << RCC_APB1ENSR1_SPI3ENS_Pos) /*!< 0x00008000 */
#define RCC_APB1ENSR1_SPI3ENS RCC_APB1ENSR1_SPI3ENS_Msk /*!< SPI3 enable */
#define RCC_APB1ENSR1_SPDIFRX1ENS_Pos (16U)
#define RCC_APB1ENSR1_SPDIFRX1ENS_Msk (0x1UL << RCC_APB1ENSR1_SPDIFRX1ENS_Pos) /*!< 0x00010000 */
#define RCC_APB1ENSR1_SPDIFRX1ENS RCC_APB1ENSR1_SPDIFRX1ENS_Msk /*!< SPDIFRX1 enable */
#define RCC_APB1ENSR1_USART2ENS_Pos (17U)
#define RCC_APB1ENSR1_USART2ENS_Msk (0x1UL << RCC_APB1ENSR1_USART2ENS_Pos)/*!< 0x00020000 */
#define RCC_APB1ENSR1_USART2ENS RCC_APB1ENSR1_USART2ENS_Msk /*!< USART2 enable */
#define RCC_APB1ENSR1_USART3ENS_Pos (18U)
#define RCC_APB1ENSR1_USART3ENS_Msk (0x1UL << RCC_APB1ENSR1_USART3ENS_Pos)/*!< 0x00040000 */
#define RCC_APB1ENSR1_USART3ENS RCC_APB1ENSR1_USART3ENS_Msk /*!< USART3 enable */
#define RCC_APB1ENSR1_UART4ENS_Pos (19U)
#define RCC_APB1ENSR1_UART4ENS_Msk (0x1UL << RCC_APB1ENSR1_UART4ENS_Pos) /*!< 0x00080000 */
#define RCC_APB1ENSR1_UART4ENS RCC_APB1ENSR1_UART4ENS_Msk /*!< UART4 enable */
#define RCC_APB1ENSR1_UART5ENS_Pos (20U)
#define RCC_APB1ENSR1_UART5ENS_Msk (0x1UL << RCC_APB1ENSR1_UART5ENS_Pos) /*!< 0x00100000 */
#define RCC_APB1ENSR1_UART5ENS RCC_APB1ENSR1_UART5ENS_Msk /*!< UART5 enable */
#define RCC_APB1ENSR1_I2C1ENS_Pos (21U)
#define RCC_APB1ENSR1_I2C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C1ENS_Pos) /*!< 0x00200000 */
#define RCC_APB1ENSR1_I2C1ENS RCC_APB1ENSR1_I2C1ENS_Msk /*!< I2C1 enable */
#define RCC_APB1ENSR1_I2C2ENS_Pos (22U)
#define RCC_APB1ENSR1_I2C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C2ENS_Pos) /*!< 0x00400000 */
#define RCC_APB1ENSR1_I2C2ENS RCC_APB1ENSR1_I2C2ENS_Msk /*!< I2C2 enable */
#define RCC_APB1ENSR1_I2C3ENS_Pos (23U)
#define RCC_APB1ENSR1_I2C3ENS_Msk (0x1UL << RCC_APB1ENSR1_I2C3ENS_Pos) /*!< 0x00800000 */
#define RCC_APB1ENSR1_I2C3ENS RCC_APB1ENSR1_I2C3ENS_Msk /*!< I2C3 enable */
#define RCC_APB1ENSR1_I3C1ENS_Pos (24U)
#define RCC_APB1ENSR1_I3C1ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C1ENS_Pos) /*!< 0x01000000 */
#define RCC_APB1ENSR1_I3C1ENS RCC_APB1ENSR1_I3C1ENS_Msk /*!< I3C1 enable */
#define RCC_APB1ENSR1_I3C2ENS_Pos (25U)
#define RCC_APB1ENSR1_I3C2ENS_Msk (0x1UL << RCC_APB1ENSR1_I3C2ENS_Pos) /*!< 0x02000000 */
#define RCC_APB1ENSR1_I3C2ENS RCC_APB1ENSR1_I3C2ENS_Msk /*!< I3C2 enable */
#define RCC_APB1ENSR1_UART7ENS_Pos (30U)
#define RCC_APB1ENSR1_UART7ENS_Msk (0x1UL << RCC_APB1ENSR1_UART7ENS_Pos) /*!< 0x40000000 */
#define RCC_APB1ENSR1_UART7ENS RCC_APB1ENSR1_UART7ENS_Msk /*!< UART7 enable */
#define RCC_APB1ENSR1_UART8ENS_Pos (31U)
#define RCC_APB1ENSR1_UART8ENS_Msk (0x1UL << RCC_APB1ENSR1_UART8ENS_Pos) /*!< 0x80000000 */
#define RCC_APB1ENSR1_UART8ENS RCC_APB1ENSR1_UART8ENS_Msk /*!< UART8 enable */
/**************** Bit definition for RCC_APB1ENSR2 register *****************/
#define RCC_APB1ENSR2_MDIOSENS_Pos (5U)
#define RCC_APB1ENSR2_MDIOSENS_Msk (0x1UL << RCC_APB1ENSR2_MDIOSENS_Pos) /*!< 0x00000020 */
#define RCC_APB1ENSR2_MDIOSENS RCC_APB1ENSR2_MDIOSENS_Msk /*!< MDIOS enable */
#define RCC_APB1ENSR2_FDCANENS_Pos (8U)
#define RCC_APB1ENSR2_FDCANENS_Msk (0x1UL << RCC_APB1ENSR2_FDCANENS_Pos) /*!< 0x00000100 */
#define RCC_APB1ENSR2_FDCANENS RCC_APB1ENSR2_FDCANENS_Msk /*!< FDCAN enable */
#define RCC_APB1ENSR2_UCPD1ENS_Pos (18U)
#define RCC_APB1ENSR2_UCPD1ENS_Msk (0x1UL << RCC_APB1ENSR2_UCPD1ENS_Pos) /*!< 0x00040000 */
#define RCC_APB1ENSR2_UCPD1ENS RCC_APB1ENSR2_UCPD1ENS_Msk /*!< UCPD1 enable */
/***************** Bit definition for RCC_APB2ENSR register *****************/
#define RCC_APB2ENSR_TIM1ENS_Pos (0U)
#define RCC_APB2ENSR_TIM1ENS_Msk (0x1UL << RCC_APB2ENSR_TIM1ENS_Pos) /*!< 0x00000001 */
#define RCC_APB2ENSR_TIM1ENS RCC_APB2ENSR_TIM1ENS_Msk /*!< TIM1 enable */
#define RCC_APB2ENSR_TIM8ENS_Pos (1U)
#define RCC_APB2ENSR_TIM8ENS_Msk (0x1UL << RCC_APB2ENSR_TIM8ENS_Pos) /*!< 0x00000002 */
#define RCC_APB2ENSR_TIM8ENS RCC_APB2ENSR_TIM8ENS_Msk /*!< TIM8 enable */
#define RCC_APB2ENSR_USART1ENS_Pos (4U)
#define RCC_APB2ENSR_USART1ENS_Msk (0x1UL << RCC_APB2ENSR_USART1ENS_Pos) /*!< 0x00000010 */
#define RCC_APB2ENSR_USART1ENS RCC_APB2ENSR_USART1ENS_Msk /*!< USART1 enable */
#define RCC_APB2ENSR_USART6ENS_Pos (5U)
#define RCC_APB2ENSR_USART6ENS_Msk (0x1UL << RCC_APB2ENSR_USART6ENS_Pos) /*!< 0x00000020 */
#define RCC_APB2ENSR_USART6ENS RCC_APB2ENSR_USART6ENS_Msk /*!< USART6 enable */
#define RCC_APB2ENSR_UART9ENS_Pos (6U)
#define RCC_APB2ENSR_UART9ENS_Msk (0x1UL << RCC_APB2ENSR_UART9ENS_Pos) /*!< 0x00000040 */
#define RCC_APB2ENSR_UART9ENS RCC_APB2ENSR_UART9ENS_Msk /*!< UART9 enable */
#define RCC_APB2ENSR_USART10ENS_Pos (7U)
#define RCC_APB2ENSR_USART10ENS_Msk (0x1UL << RCC_APB2ENSR_USART10ENS_Pos)/*!< 0x00000080 */
#define RCC_APB2ENSR_USART10ENS RCC_APB2ENSR_USART10ENS_Msk /*!< USART10 enable */
#define RCC_APB2ENSR_SPI1ENS_Pos (12U)
#define RCC_APB2ENSR_SPI1ENS_Msk (0x1UL << RCC_APB2ENSR_SPI1ENS_Pos) /*!< 0x00001000 */
#define RCC_APB2ENSR_SPI1ENS RCC_APB2ENSR_SPI1ENS_Msk /*!< SPI1 enable */
#define RCC_APB2ENSR_SPI4ENS_Pos (13U)
#define RCC_APB2ENSR_SPI4ENS_Msk (0x1UL << RCC_APB2ENSR_SPI4ENS_Pos) /*!< 0x00002000 */
#define RCC_APB2ENSR_SPI4ENS RCC_APB2ENSR_SPI4ENS_Msk /*!< SPI4 enable */
#define RCC_APB2ENSR_TIM18ENS_Pos (15U)
#define RCC_APB2ENSR_TIM18ENS_Msk (0x1UL << RCC_APB2ENSR_TIM18ENS_Pos) /*!< 0x00008000 */
#define RCC_APB2ENSR_TIM18ENS RCC_APB2ENSR_TIM18ENS_Msk /*!< TIM18 enable */
#define RCC_APB2ENSR_TIM15ENS_Pos (16U)
#define RCC_APB2ENSR_TIM15ENS_Msk (0x1UL << RCC_APB2ENSR_TIM15ENS_Pos) /*!< 0x00010000 */
#define RCC_APB2ENSR_TIM15ENS RCC_APB2ENSR_TIM15ENS_Msk /*!< TIM15 enable */
#define RCC_APB2ENSR_TIM16ENS_Pos (17U)
#define RCC_APB2ENSR_TIM16ENS_Msk (0x1UL << RCC_APB2ENSR_TIM16ENS_Pos) /*!< 0x00020000 */
#define RCC_APB2ENSR_TIM16ENS RCC_APB2ENSR_TIM16ENS_Msk /*!< TIM16 enable */
#define RCC_APB2ENSR_TIM17ENS_Pos (18U)
#define RCC_APB2ENSR_TIM17ENS_Msk (0x1UL << RCC_APB2ENSR_TIM17ENS_Pos) /*!< 0x00040000 */
#define RCC_APB2ENSR_TIM17ENS RCC_APB2ENSR_TIM17ENS_Msk /*!< TIM17 enable */
#define RCC_APB2ENSR_TIM9ENS_Pos (19U)
#define RCC_APB2ENSR_TIM9ENS_Msk (0x1UL << RCC_APB2ENSR_TIM9ENS_Pos) /*!< 0x00080000 */
#define RCC_APB2ENSR_TIM9ENS RCC_APB2ENSR_TIM9ENS_Msk /*!< TIM9 enable */
#define RCC_APB2ENSR_SPI5ENS_Pos (20U)
#define RCC_APB2ENSR_SPI5ENS_Msk (0x1UL << RCC_APB2ENSR_SPI5ENS_Pos) /*!< 0x00100000 */
#define RCC_APB2ENSR_SPI5ENS RCC_APB2ENSR_SPI5ENS_Msk /*!< SPI5 enable */
#define RCC_APB2ENSR_SAI1ENS_Pos (21U)
#define RCC_APB2ENSR_SAI1ENS_Msk (0x1UL << RCC_APB2ENSR_SAI1ENS_Pos) /*!< 0x00200000 */
#define RCC_APB2ENSR_SAI1ENS RCC_APB2ENSR_SAI1ENS_Msk /*!< SAI1 enable */
#define RCC_APB2ENSR_SAI2ENS_Pos (22U)
#define RCC_APB2ENSR_SAI2ENS_Msk (0x1UL << RCC_APB2ENSR_SAI2ENS_Pos) /*!< 0x00400000 */
#define RCC_APB2ENSR_SAI2ENS RCC_APB2ENSR_SAI2ENS_Msk /*!< SAI2 enable */
/***************** Bit definition for RCC_APB3ENSR register *****************/
#define RCC_APB3ENSR_DFTENS_Pos (2U)
#define RCC_APB3ENSR_DFTENS_Msk (0x1UL << RCC_APB3ENSR_DFTENS_Pos) /*!< 0x00000004 */
#define RCC_APB3ENSR_DFTENS RCC_APB3ENSR_DFTENS_Msk /*!< DFT enable */
/**************** Bit definition for RCC_APB4ENSR1 register *****************/
#define RCC_APB4ENSR1_HDPENS_Pos (2U)
#define RCC_APB4ENSR1_HDPENS_Msk (0x1UL << RCC_APB4ENSR1_HDPENS_Pos) /*!< 0x00000004 */
#define RCC_APB4ENSR1_HDPENS RCC_APB4ENSR1_HDPENS_Msk /*!< HDP enable */
#define RCC_APB4ENSR1_LPUART1ENS_Pos (3U)
#define RCC_APB4ENSR1_LPUART1ENS_Msk (0x1UL << RCC_APB4ENSR1_LPUART1ENS_Pos) /*!< 0x00000008 */
#define RCC_APB4ENSR1_LPUART1ENS RCC_APB4ENSR1_LPUART1ENS_Msk /*!< LPUART1 enable */
#define RCC_APB4ENSR1_SPI6ENS_Pos (5U)
#define RCC_APB4ENSR1_SPI6ENS_Msk (0x1UL << RCC_APB4ENSR1_SPI6ENS_Pos) /*!< 0x00000020 */
#define RCC_APB4ENSR1_SPI6ENS RCC_APB4ENSR1_SPI6ENS_Msk /*!< SPI6 enable */
#define RCC_APB4ENSR1_I2C4ENS_Pos (7U)
#define RCC_APB4ENSR1_I2C4ENS_Msk (0x1UL << RCC_APB4ENSR1_I2C4ENS_Pos) /*!< 0x00000080 */
#define RCC_APB4ENSR1_I2C4ENS RCC_APB4ENSR1_I2C4ENS_Msk /*!< I2C4 enable */
#define RCC_APB4ENSR1_LPTIM2ENS_Pos (9U)
#define RCC_APB4ENSR1_LPTIM2ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM2ENS_Pos)/*!< 0x00000200 */
#define RCC_APB4ENSR1_LPTIM2ENS RCC_APB4ENSR1_LPTIM2ENS_Msk /*!< LPTIM2 enable */
#define RCC_APB4ENSR1_LPTIM3ENS_Pos (10U)
#define RCC_APB4ENSR1_LPTIM3ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM3ENS_Pos)/*!< 0x00000400 */
#define RCC_APB4ENSR1_LPTIM3ENS RCC_APB4ENSR1_LPTIM3ENS_Msk /*!< LPTIM3 enable */
#define RCC_APB4ENSR1_LPTIM4ENS_Pos (11U)
#define RCC_APB4ENSR1_LPTIM4ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM4ENS_Pos)/*!< 0x00000800 */
#define RCC_APB4ENSR1_LPTIM4ENS RCC_APB4ENSR1_LPTIM4ENS_Msk /*!< LPTIM4 enable */
#define RCC_APB4ENSR1_LPTIM5ENS_Pos (12U)
#define RCC_APB4ENSR1_LPTIM5ENS_Msk (0x1UL << RCC_APB4ENSR1_LPTIM5ENS_Pos)/*!< 0x00001000 */
#define RCC_APB4ENSR1_LPTIM5ENS RCC_APB4ENSR1_LPTIM5ENS_Msk /*!< LPTIM5 enable */
#define RCC_APB4ENSR1_VREFBUFENS_Pos (15U)
#define RCC_APB4ENSR1_VREFBUFENS_Msk (0x1UL << RCC_APB4ENSR1_VREFBUFENS_Pos) /*!< 0x00008000 */
#define RCC_APB4ENSR1_VREFBUFENS RCC_APB4ENSR1_VREFBUFENS_Msk /*!< VREFBUF enable */
#define RCC_APB4ENSR1_RTCENS_Pos (16U)
#define RCC_APB4ENSR1_RTCENS_Msk (0x1UL << RCC_APB4ENSR1_RTCENS_Pos) /*!< 0x00010000 */
#define RCC_APB4ENSR1_RTCENS RCC_APB4ENSR1_RTCENS_Msk /*!< RTC enable */
#define RCC_APB4ENSR1_RTCAPBENS_Pos (17U)
#define RCC_APB4ENSR1_RTCAPBENS_Msk (0x1UL << RCC_APB4ENSR1_RTCAPBENS_Pos)/*!< 0x00020000 */
#define RCC_APB4ENSR1_RTCAPBENS RCC_APB4ENSR1_RTCAPBENS_Msk /*!< RTCAPB enable */
/**************** Bit definition for RCC_APB4ENSR2 register *****************/
#define RCC_APB4ENSR2_SYSCFGENS_Pos (0U)
#define RCC_APB4ENSR2_SYSCFGENS_Msk (0x1UL << RCC_APB4ENSR2_SYSCFGENS_Pos)/*!< 0x00000001 */
#define RCC_APB4ENSR2_SYSCFGENS RCC_APB4ENSR2_SYSCFGENS_Msk /*!< SYSCFG enable */
#define RCC_APB4ENSR2_BSECENS_Pos (1U)
#define RCC_APB4ENSR2_BSECENS_Msk (0x1UL << RCC_APB4ENSR2_BSECENS_Pos) /*!< 0x00000002 */
#define RCC_APB4ENSR2_BSECENS RCC_APB4ENSR2_BSECENS_Msk /*!< BSEC enable */
#define RCC_APB4ENSR2_DTSENS_Pos (2U)
#define RCC_APB4ENSR2_DTSENS_Msk (0x1UL << RCC_APB4ENSR2_DTSENS_Pos) /*!< 0x00000004 */
#define RCC_APB4ENSR2_DTSENS RCC_APB4ENSR2_DTSENS_Msk /*!< DTS enable */
/***************** Bit definition for RCC_APB5ENSR register *****************/
#define RCC_APB5ENSR_LTDCENS_Pos (1U)
#define RCC_APB5ENSR_LTDCENS_Msk (0x1UL << RCC_APB5ENSR_LTDCENS_Pos) /*!< 0x00000002 */
#define RCC_APB5ENSR_LTDCENS RCC_APB5ENSR_LTDCENS_Msk /*!< LTDC enable */
#define RCC_APB5ENSR_DCMIPPENS_Pos (2U)
#define RCC_APB5ENSR_DCMIPPENS_Msk (0x1UL << RCC_APB5ENSR_DCMIPPENS_Pos) /*!< 0x00000004 */
#define RCC_APB5ENSR_DCMIPPENS RCC_APB5ENSR_DCMIPPENS_Msk /*!< DCMIPP enable */
#define RCC_APB5ENSR_GFXTIMENS_Pos (4U)
#define RCC_APB5ENSR_GFXTIMENS_Msk (0x1UL << RCC_APB5ENSR_GFXTIMENS_Pos) /*!< 0x00000010 */
#define RCC_APB5ENSR_GFXTIMENS RCC_APB5ENSR_GFXTIMENS_Msk /*!< GFXTIM enable */
#define RCC_APB5ENSR_VENCENS_Pos (5U)
#define RCC_APB5ENSR_VENCENS_Msk (0x1UL << RCC_APB5ENSR_VENCENS_Pos) /*!< 0x00000020 */
#define RCC_APB5ENSR_VENCENS RCC_APB5ENSR_VENCENS_Msk /*!< VENC enable */
#define RCC_APB5ENSR_CSIENS_Pos (6U)
#define RCC_APB5ENSR_CSIENS_Msk (0x1UL << RCC_APB5ENSR_CSIENS_Pos) /*!< 0x00000040 */
#define RCC_APB5ENSR_CSIENS RCC_APB5ENSR_CSIENS_Msk /*!< CSI enable */
/**************** Bit definition for RCC_BUSLPENSR register *****************/
#define RCC_BUSLPENSR_ACLKNLPENS_Pos (0U)
#define RCC_BUSLPENSR_ACLKNLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNLPENS_Pos) /*!< 0x00000001 */
#define RCC_BUSLPENSR_ACLKNLPENS RCC_BUSLPENSR_ACLKNLPENS_Msk /*!< ACLKN enable */
#define RCC_BUSLPENSR_ACLKNCLPENS_Pos (1U)
#define RCC_BUSLPENSR_ACLKNCLPENS_Msk (0x1UL << RCC_BUSLPENSR_ACLKNCLPENS_Pos) /*!< 0x00000002 */
#define RCC_BUSLPENSR_ACLKNCLPENS RCC_BUSLPENSR_ACLKNCLPENS_Msk /*!< ACLKNC enable */
/**************** Bit definition for RCC_MISCLPENSR register ****************/
#define RCC_MISCLPENSR_DBGLPENS_Pos (0U)
#define RCC_MISCLPENSR_DBGLPENS_Msk (0x1UL << RCC_MISCLPENSR_DBGLPENS_Pos)/*!< 0x00000001 */
#define RCC_MISCLPENSR_DBGLPENS RCC_MISCLPENSR_DBGLPENS_Msk /*!< DBG enable */
#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos (3U)
#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk (0x1UL << RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Pos) /*!< 0x00000008 */
#define RCC_MISCLPENSR_XSPIPHYCOMPLPENS RCC_MISCLPENSR_XSPIPHYCOMPLPENS_Msk /*!< XSPIPHYCOMP enable */
#define RCC_MISCLPENSR_PERLPENS_Pos (6U)
#define RCC_MISCLPENSR_PERLPENS_Msk (0x1UL << RCC_MISCLPENSR_PERLPENS_Pos)/*!< 0x00000040 */
#define RCC_MISCLPENSR_PERLPENS RCC_MISCLPENSR_PERLPENS_Msk /*!< PER enable */
/**************** Bit definition for RCC_MEMLPENSR register *****************/
#define RCC_MEMLPENSR_AXISRAM3LPENS_Pos (0U)
#define RCC_MEMLPENSR_AXISRAM3LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM3LPENS_Pos) /*!< 0x00000001 */
#define RCC_MEMLPENSR_AXISRAM3LPENS RCC_MEMLPENSR_AXISRAM3LPENS_Msk /*!< AXISRAM3 enable */
#define RCC_MEMLPENSR_AXISRAM4LPENS_Pos (1U)
#define RCC_MEMLPENSR_AXISRAM4LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM4LPENS_Pos) /*!< 0x00000002 */
#define RCC_MEMLPENSR_AXISRAM4LPENS RCC_MEMLPENSR_AXISRAM4LPENS_Msk /*!< AXISRAM4 enable */
#define RCC_MEMLPENSR_AXISRAM5LPENS_Pos (2U)
#define RCC_MEMLPENSR_AXISRAM5LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM5LPENS_Pos) /*!< 0x00000004 */
#define RCC_MEMLPENSR_AXISRAM5LPENS RCC_MEMLPENSR_AXISRAM5LPENS_Msk /*!< AXISRAM5 enable */
#define RCC_MEMLPENSR_AXISRAM6LPENS_Pos (3U)
#define RCC_MEMLPENSR_AXISRAM6LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM6LPENS_Pos) /*!< 0x00000008 */
#define RCC_MEMLPENSR_AXISRAM6LPENS RCC_MEMLPENSR_AXISRAM6LPENS_Msk /*!< AXISRAM6 enable */
#define RCC_MEMLPENSR_AHBSRAM1LPENS_Pos (4U)
#define RCC_MEMLPENSR_AHBSRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM1LPENS_Pos) /*!< 0x00000010 */
#define RCC_MEMLPENSR_AHBSRAM1LPENS RCC_MEMLPENSR_AHBSRAM1LPENS_Msk /*!< AHBSRAM1 enable */
#define RCC_MEMLPENSR_AHBSRAM2LPENS_Pos (5U)
#define RCC_MEMLPENSR_AHBSRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AHBSRAM2LPENS_Pos) /*!< 0x00000020 */
#define RCC_MEMLPENSR_AHBSRAM2LPENS RCC_MEMLPENSR_AHBSRAM2LPENS_Msk /*!< AHBSRAM2 enable */
#define RCC_MEMLPENSR_BKPSRAMLPENS_Pos (6U)
#define RCC_MEMLPENSR_BKPSRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BKPSRAMLPENS_Pos) /*!< 0x00000040 */
#define RCC_MEMLPENSR_BKPSRAMLPENS RCC_MEMLPENSR_BKPSRAMLPENS_Msk /*!< BKPSRAM enable */
#define RCC_MEMLPENSR_AXISRAM1LPENS_Pos (7U)
#define RCC_MEMLPENSR_AXISRAM1LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM1LPENS_Pos) /*!< 0x00000080 */
#define RCC_MEMLPENSR_AXISRAM1LPENS RCC_MEMLPENSR_AXISRAM1LPENS_Msk /*!< AXISRAM1 enable */
#define RCC_MEMLPENSR_AXISRAM2LPENS_Pos (8U)
#define RCC_MEMLPENSR_AXISRAM2LPENS_Msk (0x1UL << RCC_MEMLPENSR_AXISRAM2LPENS_Pos) /*!< 0x00000100 */
#define RCC_MEMLPENSR_AXISRAM2LPENS RCC_MEMLPENSR_AXISRAM2LPENS_Msk /*!< AXISRAM2 enable */
#define RCC_MEMLPENSR_FLEXRAMLPENS_Pos (9U)
#define RCC_MEMLPENSR_FLEXRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_FLEXRAMLPENS_Pos) /*!< 0x00000200 */
#define RCC_MEMLPENSR_FLEXRAMLPENS RCC_MEMLPENSR_FLEXRAMLPENS_Msk /*!< FLEXRAM enable */
#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos (10U)
#define RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_CACHEAXIRAMLPENS_Pos) /*!< 0x00000400 */
#define RCC_MEMLPENSR_CACHEAXIRAMLPENS RCC_MEMLPENSR_CACHEAXIRAMLPENS_Msk /*!< CACHEAXIRAM enable */
#define RCC_MEMLPENSR_VENCRAMLPENS_Pos (11U)
#define RCC_MEMLPENSR_VENCRAMLPENS_Msk (0x1UL << RCC_MEMLPENSR_VENCRAMLPENS_Pos) /*!< 0x00000800 */
#define RCC_MEMLPENSR_VENCRAMLPENS RCC_MEMLPENSR_VENCRAMLPENS_Msk /*!< VENCRAM enable */
#define RCC_MEMLPENSR_BOOTROMLPENS_Pos (12U)
#define RCC_MEMLPENSR_BOOTROMLPENS_Msk (0x1UL << RCC_MEMLPENSR_BOOTROMLPENS_Pos) /*!< 0x00001000 */
#define RCC_MEMLPENSR_BOOTROMLPENS RCC_MEMLPENSR_BOOTROMLPENS_Msk /*!< Boot ROM enable */
/**************** Bit definition for RCC_AHB1LPENSR register ****************/
#define RCC_AHB1LPENSR_GPDMA1LPENS_Pos (4U)
#define RCC_AHB1LPENSR_GPDMA1LPENS_Msk (0x1UL << RCC_AHB1LPENSR_GPDMA1LPENS_Pos) /*!< 0x00000010 */
#define RCC_AHB1LPENSR_GPDMA1LPENS RCC_AHB1LPENSR_GPDMA1LPENS_Msk /*!< GPDMA1 enable */
#define RCC_AHB1LPENSR_ADC12LPENS_Pos (5U)
#define RCC_AHB1LPENSR_ADC12LPENS_Msk (0x1UL << RCC_AHB1LPENSR_ADC12LPENS_Pos) /*!< 0x00000020 */
#define RCC_AHB1LPENSR_ADC12LPENS RCC_AHB1LPENSR_ADC12LPENS_Msk /*!< ADC12 enable */
/**************** Bit definition for RCC_AHB2LPENSR register ****************/
#define RCC_AHB2LPENSR_RAMCFGLPENS_Pos (12U)
#define RCC_AHB2LPENSR_RAMCFGLPENS_Msk (0x1UL << RCC_AHB2LPENSR_RAMCFGLPENS_Pos) /*!< 0x00001000 */
#define RCC_AHB2LPENSR_RAMCFGLPENS RCC_AHB2LPENSR_RAMCFGLPENS_Msk /*!< RAMCFG enable */
#define RCC_AHB2LPENSR_MDF1LPENS_Pos (16U)
#define RCC_AHB2LPENSR_MDF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_MDF1LPENS_Pos) /*!< 0x00010000 */
#define RCC_AHB2LPENSR_MDF1LPENS RCC_AHB2LPENSR_MDF1LPENS_Msk /*!< MDF1 enable */
#define RCC_AHB2LPENSR_ADF1LPENS_Pos (17U)
#define RCC_AHB2LPENSR_ADF1LPENS_Msk (0x1UL << RCC_AHB2LPENSR_ADF1LPENS_Pos) /*!< 0x00020000 */
#define RCC_AHB2LPENSR_ADF1LPENS RCC_AHB2LPENSR_ADF1LPENS_Msk /*!< ADF1 enable */
/**************** Bit definition for RCC_AHB3LPENSR register ****************/
#define RCC_AHB3LPENSR_RNGLPENS_Pos (0U)
#define RCC_AHB3LPENSR_RNGLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RNGLPENS_Pos)/*!< 0x00000001 */
#define RCC_AHB3LPENSR_RNGLPENS RCC_AHB3LPENSR_RNGLPENS_Msk /*!< RNG enable */
#define RCC_AHB3LPENSR_HASHLPENS_Pos (1U)
#define RCC_AHB3LPENSR_HASHLPENS_Msk (0x1UL << RCC_AHB3LPENSR_HASHLPENS_Pos) /*!< 0x00000002 */
#define RCC_AHB3LPENSR_HASHLPENS RCC_AHB3LPENSR_HASHLPENS_Msk /*!< HASH enable */
#define RCC_AHB3LPENSR_CRYPLPENS_Pos (2U)
#define RCC_AHB3LPENSR_CRYPLPENS_Msk (0x1UL << RCC_AHB3LPENSR_CRYPLPENS_Pos) /*!< 0x00000004 */
#define RCC_AHB3LPENSR_CRYPLPENS RCC_AHB3LPENSR_CRYPLPENS_Msk /*!< CRYP enable */
#define RCC_AHB3LPENSR_SAESLPENS_Pos (4U)
#define RCC_AHB3LPENSR_SAESLPENS_Msk (0x1UL << RCC_AHB3LPENSR_SAESLPENS_Pos) /*!< 0x00000010 */
#define RCC_AHB3LPENSR_SAESLPENS RCC_AHB3LPENSR_SAESLPENS_Msk /*!< SAES enable */
#define RCC_AHB3LPENSR_PKALPENS_Pos (8U)
#define RCC_AHB3LPENSR_PKALPENS_Msk (0x1UL << RCC_AHB3LPENSR_PKALPENS_Pos)/*!< 0x00000100 */
#define RCC_AHB3LPENSR_PKALPENS RCC_AHB3LPENSR_PKALPENS_Msk /*!< PKA enable */
#define RCC_AHB3LPENSR_RIFSCLPENS_Pos (9U)
#define RCC_AHB3LPENSR_RIFSCLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RIFSCLPENS_Pos) /*!< 0x00000200 */
#define RCC_AHB3LPENSR_RIFSCLPENS RCC_AHB3LPENSR_RIFSCLPENS_Msk /*!< RIFSC enable */
#define RCC_AHB3LPENSR_IACLPENS_Pos (10U)
#define RCC_AHB3LPENSR_IACLPENS_Msk (0x1UL << RCC_AHB3LPENSR_IACLPENS_Pos)/*!< 0x00000400 */
#define RCC_AHB3LPENSR_IACLPENS RCC_AHB3LPENSR_IACLPENS_Msk /*!< IAC enable in Sleep mode */
#define RCC_AHB3LPENSR_RISAFLPENS_Pos (14U)
#define RCC_AHB3LPENSR_RISAFLPENS_Msk (0x1UL << RCC_AHB3LPENSR_RISAFLPENS_Pos) /*!< 0x00004000 */
#define RCC_AHB3LPENSR_RISAFLPENS RCC_AHB3LPENSR_RISAFLPENS_Msk /*!< RISAF enable */
/**************** Bit definition for RCC_AHB4LPENSR register ****************/
#define RCC_AHB4LPENSR_GPIOALPENS_Pos (0U)
#define RCC_AHB4LPENSR_GPIOALPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOALPENS_Pos) /*!< 0x00000001 */
#define RCC_AHB4LPENSR_GPIOALPENS RCC_AHB4LPENSR_GPIOALPENS_Msk /*!< GPIO A enable */
#define RCC_AHB4LPENSR_GPIOBLPENS_Pos (1U)
#define RCC_AHB4LPENSR_GPIOBLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOBLPENS_Pos) /*!< 0x00000002 */
#define RCC_AHB4LPENSR_GPIOBLPENS RCC_AHB4LPENSR_GPIOBLPENS_Msk /*!< GPIO B enable */
#define RCC_AHB4LPENSR_GPIOCLPENS_Pos (2U)
#define RCC_AHB4LPENSR_GPIOCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOCLPENS_Pos) /*!< 0x00000004 */
#define RCC_AHB4LPENSR_GPIOCLPENS RCC_AHB4LPENSR_GPIOCLPENS_Msk /*!< GPIO C enable */
#define RCC_AHB4LPENSR_GPIODLPENS_Pos (3U)
#define RCC_AHB4LPENSR_GPIODLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIODLPENS_Pos) /*!< 0x00000008 */
#define RCC_AHB4LPENSR_GPIODLPENS RCC_AHB4LPENSR_GPIODLPENS_Msk /*!< GPIO D enable */
#define RCC_AHB4LPENSR_GPIOELPENS_Pos (4U)
#define RCC_AHB4LPENSR_GPIOELPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOELPENS_Pos) /*!< 0x00000010 */
#define RCC_AHB4LPENSR_GPIOELPENS RCC_AHB4LPENSR_GPIOELPENS_Msk /*!< GPIO E enable */
#define RCC_AHB4LPENSR_GPIOFLPENS_Pos (5U)
#define RCC_AHB4LPENSR_GPIOFLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOFLPENS_Pos) /*!< 0x00000020 */
#define RCC_AHB4LPENSR_GPIOFLPENS RCC_AHB4LPENSR_GPIOFLPENS_Msk /*!< GPIO F enable */
#define RCC_AHB4LPENSR_GPIOGLPENS_Pos (6U)
#define RCC_AHB4LPENSR_GPIOGLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOGLPENS_Pos) /*!< 0x00000040 */
#define RCC_AHB4LPENSR_GPIOGLPENS RCC_AHB4LPENSR_GPIOGLPENS_Msk /*!< GPIO G enable */
#define RCC_AHB4LPENSR_GPIOHLPENS_Pos (7U)
#define RCC_AHB4LPENSR_GPIOHLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOHLPENS_Pos) /*!< 0x00000080 */
#define RCC_AHB4LPENSR_GPIOHLPENS RCC_AHB4LPENSR_GPIOHLPENS_Msk /*!< GPIO H enable */
#define RCC_AHB4LPENSR_GPIONLPENS_Pos (13U)
#define RCC_AHB4LPENSR_GPIONLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIONLPENS_Pos) /*!< 0x00002000 */
#define RCC_AHB4LPENSR_GPIONLPENS RCC_AHB4LPENSR_GPIONLPENS_Msk /*!< GPIO N enable */
#define RCC_AHB4LPENSR_GPIOOLPENS_Pos (14U)
#define RCC_AHB4LPENSR_GPIOOLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOOLPENS_Pos) /*!< 0x00004000 */
#define RCC_AHB4LPENSR_GPIOOLPENS RCC_AHB4LPENSR_GPIOOLPENS_Msk /*!< GPIO O enable */
#define RCC_AHB4LPENSR_GPIOPLPENS_Pos (15U)
#define RCC_AHB4LPENSR_GPIOPLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOPLPENS_Pos) /*!< 0x00008000 */
#define RCC_AHB4LPENSR_GPIOPLPENS RCC_AHB4LPENSR_GPIOPLPENS_Msk /*!< GPIO P enable */
#define RCC_AHB4LPENSR_GPIOQLPENS_Pos (16U)
#define RCC_AHB4LPENSR_GPIOQLPENS_Msk (0x1UL << RCC_AHB4LPENSR_GPIOQLPENS_Pos) /*!< 0x00010000 */
#define RCC_AHB4LPENSR_GPIOQLPENS RCC_AHB4LPENSR_GPIOQLPENS_Msk /*!< GPIO Q enable */
#define RCC_AHB4LPENSR_PWRLPENS_Pos (18U)
#define RCC_AHB4LPENSR_PWRLPENS_Msk (0x1UL << RCC_AHB4LPENSR_PWRLPENS_Pos)/*!< 0x00040000 */
#define RCC_AHB4LPENSR_PWRLPENS RCC_AHB4LPENSR_PWRLPENS_Msk /*!< PWR enable */
#define RCC_AHB4LPENSR_CRCLPENS_Pos (19U)
#define RCC_AHB4LPENSR_CRCLPENS_Msk (0x1UL << RCC_AHB4LPENSR_CRCLPENS_Pos)/*!< 0x00080000 */
#define RCC_AHB4LPENSR_CRCLPENS RCC_AHB4LPENSR_CRCLPENS_Msk /*!< CRC enable */
/**************** Bit definition for RCC_AHB5LPENSR register ****************/
#define RCC_AHB5LPENSR_HPDMA1LPENS_Pos (0U)
#define RCC_AHB5LPENSR_HPDMA1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_HPDMA1LPENS_Pos) /*!< 0x00000001 */
#define RCC_AHB5LPENSR_HPDMA1LPENS RCC_AHB5LPENSR_HPDMA1LPENS_Msk /*!< HPDMA1 enable */
#define RCC_AHB5LPENSR_DMA2DLPENS_Pos (1U)
#define RCC_AHB5LPENSR_DMA2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_DMA2DLPENS_Pos) /*!< 0x00000002 */
#define RCC_AHB5LPENSR_DMA2DLPENS RCC_AHB5LPENSR_DMA2DLPENS_Msk /*!< DMA2D enable */
#define RCC_AHB5LPENSR_JPEGLPENS_Pos (3U)
#define RCC_AHB5LPENSR_JPEGLPENS_Msk (0x1UL << RCC_AHB5LPENSR_JPEGLPENS_Pos) /*!< 0x00000008 */
#define RCC_AHB5LPENSR_JPEGLPENS RCC_AHB5LPENSR_JPEGLPENS_Msk /*!< JPEG enable */
#define RCC_AHB5LPENSR_FMCLPENS_Pos (4U)
#define RCC_AHB5LPENSR_FMCLPENS_Msk (0x1UL << RCC_AHB5LPENSR_FMCLPENS_Pos)/*!< 0x00000010 */
#define RCC_AHB5LPENSR_FMCLPENS RCC_AHB5LPENSR_FMCLPENS_Msk /*!< FMC enable */
#define RCC_AHB5LPENSR_XSPI1LPENS_Pos (5U)
#define RCC_AHB5LPENSR_XSPI1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI1LPENS_Pos) /*!< 0x00000020 */
#define RCC_AHB5LPENSR_XSPI1LPENS RCC_AHB5LPENSR_XSPI1LPENS_Msk /*!< XSPI1 enable */
#define RCC_AHB5LPENSR_PSSILPENS_Pos (6U)
#define RCC_AHB5LPENSR_PSSILPENS_Msk (0x1UL << RCC_AHB5LPENSR_PSSILPENS_Pos) /*!< 0x00000040 */
#define RCC_AHB5LPENSR_PSSILPENS RCC_AHB5LPENSR_PSSILPENS_Msk /*!< PSSI enable */
#define RCC_AHB5LPENSR_SDMMC2LPENS_Pos (7U)
#define RCC_AHB5LPENSR_SDMMC2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC2LPENS_Pos) /*!< 0x00000080 */
#define RCC_AHB5LPENSR_SDMMC2LPENS RCC_AHB5LPENSR_SDMMC2LPENS_Msk /*!< SDMMC2 enable */
#define RCC_AHB5LPENSR_SDMMC1LPENS_Pos (8U)
#define RCC_AHB5LPENSR_SDMMC1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_SDMMC1LPENS_Pos) /*!< 0x00000100 */
#define RCC_AHB5LPENSR_SDMMC1LPENS RCC_AHB5LPENSR_SDMMC1LPENS_Msk /*!< SDMMC1 enable */
#define RCC_AHB5LPENSR_XSPI2LPENS_Pos (12U)
#define RCC_AHB5LPENSR_XSPI2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI2LPENS_Pos) /*!< 0x00001000 */
#define RCC_AHB5LPENSR_XSPI2LPENS RCC_AHB5LPENSR_XSPI2LPENS_Msk /*!< XSPI2 enable */
#define RCC_AHB5LPENSR_XSPIMLPENS_Pos (13U)
#define RCC_AHB5LPENSR_XSPIMLPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPIMLPENS_Pos) /*!< 0x00002000 */
#define RCC_AHB5LPENSR_XSPIMLPENS RCC_AHB5LPENSR_XSPIMLPENS_Msk /*!< XSPIM enable */
#define RCC_AHB5LPENSR_MCE1LPENS_Pos (14U)
#define RCC_AHB5LPENSR_MCE1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE1LPENS_Pos) /*!< 0x00004000 */
#define RCC_AHB5LPENSR_MCE1LPENS RCC_AHB5LPENSR_MCE1LPENS_Msk /*!< MCE1 enable */
#define RCC_AHB5LPENSR_MCE2LPENS_Pos (15U)
#define RCC_AHB5LPENSR_MCE2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE2LPENS_Pos) /*!< 0x00008000 */
#define RCC_AHB5LPENSR_MCE2LPENS RCC_AHB5LPENSR_MCE2LPENS_Msk /*!< MCE2 enable */
#define RCC_AHB5LPENSR_MCE3LPENS_Pos (16U)
#define RCC_AHB5LPENSR_MCE3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE3LPENS_Pos) /*!< 0x00010000 */
#define RCC_AHB5LPENSR_MCE3LPENS RCC_AHB5LPENSR_MCE3LPENS_Msk /*!< MCE3 enable */
#define RCC_AHB5LPENSR_XSPI3LPENS_Pos (17U)
#define RCC_AHB5LPENSR_XSPI3LPENS_Msk (0x1UL << RCC_AHB5LPENSR_XSPI3LPENS_Pos) /*!< 0x00020000 */
#define RCC_AHB5LPENSR_XSPI3LPENS RCC_AHB5LPENSR_XSPI3LPENS_Msk /*!< XSPI3 enable */
#define RCC_AHB5LPENSR_MCE4LPENS_Pos (18U)
#define RCC_AHB5LPENSR_MCE4LPENS_Msk (0x1UL << RCC_AHB5LPENSR_MCE4LPENS_Pos) /*!< 0x00040000 */
#define RCC_AHB5LPENSR_MCE4LPENS RCC_AHB5LPENSR_MCE4LPENS_Msk /*!< MCE4 enable */
#define RCC_AHB5LPENSR_GFXMMULPENS_Pos (19U)
#define RCC_AHB5LPENSR_GFXMMULPENS_Msk (0x1UL << RCC_AHB5LPENSR_GFXMMULPENS_Pos) /*!< 0x00080000 */
#define RCC_AHB5LPENSR_GFXMMULPENS RCC_AHB5LPENSR_GFXMMULPENS_Msk /*!< GFXMMU enable */
#define RCC_AHB5LPENSR_GPU2DLPENS_Pos (20U)
#define RCC_AHB5LPENSR_GPU2DLPENS_Msk (0x1UL << RCC_AHB5LPENSR_GPU2DLPENS_Pos) /*!< 0x00100000 */
#define RCC_AHB5LPENSR_GPU2DLPENS RCC_AHB5LPENSR_GPU2DLPENS_Msk /*!< GPU2D enable */
#define RCC_AHB5LPENSR_ETH1MACLPENS_Pos (22U)
#define RCC_AHB5LPENSR_ETH1MACLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1MACLPENS_Pos) /*!< 0x00400000 */
#define RCC_AHB5LPENSR_ETH1MACLPENS RCC_AHB5LPENSR_ETH1MACLPENS_Msk /*!< ETH1MAC enable */
#define RCC_AHB5LPENSR_ETH1TXLPENS_Pos (23U)
#define RCC_AHB5LPENSR_ETH1TXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1TXLPENS_Pos) /*!< 0x00800000 */
#define RCC_AHB5LPENSR_ETH1TXLPENS RCC_AHB5LPENSR_ETH1TXLPENS_Msk /*!< ETH1TX enable */
#define RCC_AHB5LPENSR_ETH1RXLPENS_Pos (24U)
#define RCC_AHB5LPENSR_ETH1RXLPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1RXLPENS_Pos) /*!< 0x01000000 */
#define RCC_AHB5LPENSR_ETH1RXLPENS RCC_AHB5LPENSR_ETH1RXLPENS_Msk /*!< ETH1RX enable */
#define RCC_AHB5LPENSR_ETH1LPENS_Pos (25U)
#define RCC_AHB5LPENSR_ETH1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_ETH1LPENS_Pos) /*!< 0x02000000 */
#define RCC_AHB5LPENSR_ETH1LPENS RCC_AHB5LPENSR_ETH1LPENS_Msk /*!< ETH1 enable */
#define RCC_AHB5LPENSR_OTG1LPENS_Pos (26U)
#define RCC_AHB5LPENSR_OTG1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG1LPENS_Pos) /*!< 0x04000000 */
#define RCC_AHB5LPENSR_OTG1LPENS RCC_AHB5LPENSR_OTG1LPENS_Msk /*!< OTG1 enable */
#define RCC_AHB5LPENSR_OTGPHY1LPENS_Pos (27U)
#define RCC_AHB5LPENSR_OTGPHY1LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY1LPENS_Pos) /*!< 0x08000000 */
#define RCC_AHB5LPENSR_OTGPHY1LPENS RCC_AHB5LPENSR_OTGPHY1LPENS_Msk /*!< OTGPHY1 enable */
#define RCC_AHB5LPENSR_OTGPHY2LPENS_Pos (28U)
#define RCC_AHB5LPENSR_OTGPHY2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTGPHY2LPENS_Pos) /*!< 0x10000000 */
#define RCC_AHB5LPENSR_OTGPHY2LPENS RCC_AHB5LPENSR_OTGPHY2LPENS_Msk /*!< OTGPHY2 enable */
#define RCC_AHB5LPENSR_OTG2LPENS_Pos (29U)
#define RCC_AHB5LPENSR_OTG2LPENS_Msk (0x1UL << RCC_AHB5LPENSR_OTG2LPENS_Pos) /*!< 0x20000000 */
#define RCC_AHB5LPENSR_OTG2LPENS RCC_AHB5LPENSR_OTG2LPENS_Msk /*!< OTG2 enable */
#define RCC_AHB5LPENSR_CACHEAXILPENS_Pos (30U)
#define RCC_AHB5LPENSR_CACHEAXILPENS_Msk (0x1UL << RCC_AHB5LPENSR_CACHEAXILPENS_Pos) /*!< 0x40000000 */
#define RCC_AHB5LPENSR_CACHEAXILPENS RCC_AHB5LPENSR_CACHEAXILPENS_Msk /*!< CACHEAXI enable */
#define RCC_AHB5LPENSR_NPULPENS_Pos (31U)
#define RCC_AHB5LPENSR_NPULPENS_Msk (0x1UL << RCC_AHB5LPENSR_NPULPENS_Pos)/*!< 0x80000000 */
#define RCC_AHB5LPENSR_NPULPENS RCC_AHB5LPENSR_NPULPENS_Msk /*!< NPU enable */
/*************** Bit definition for RCC_APB1LPENSR1 register ****************/
#define RCC_APB1LPENSR1_TIM2LPENS_Pos (0U)
#define RCC_APB1LPENSR1_TIM2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM2LPENS_Pos) /*!< 0x00000001 */
#define RCC_APB1LPENSR1_TIM2LPENS RCC_APB1LPENSR1_TIM2LPENS_Msk /*!< TIM2 enable */
#define RCC_APB1LPENSR1_TIM3LPENS_Pos (1U)
#define RCC_APB1LPENSR1_TIM3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM3LPENS_Pos) /*!< 0x00000002 */
#define RCC_APB1LPENSR1_TIM3LPENS RCC_APB1LPENSR1_TIM3LPENS_Msk /*!< TIM3 enable */
#define RCC_APB1LPENSR1_TIM4LPENS_Pos (2U)
#define RCC_APB1LPENSR1_TIM4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM4LPENS_Pos) /*!< 0x00000004 */
#define RCC_APB1LPENSR1_TIM4LPENS RCC_APB1LPENSR1_TIM4LPENS_Msk /*!< TIM4 enable */
#define RCC_APB1LPENSR1_TIM5LPENS_Pos (3U)
#define RCC_APB1LPENSR1_TIM5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM5LPENS_Pos) /*!< 0x00000008 */
#define RCC_APB1LPENSR1_TIM5LPENS RCC_APB1LPENSR1_TIM5LPENS_Msk /*!< TIM5 enable */
#define RCC_APB1LPENSR1_TIM6LPENS_Pos (4U)
#define RCC_APB1LPENSR1_TIM6LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM6LPENS_Pos) /*!< 0x00000010 */
#define RCC_APB1LPENSR1_TIM6LPENS RCC_APB1LPENSR1_TIM6LPENS_Msk /*!< TIM6 enable */
#define RCC_APB1LPENSR1_TIM7LPENS_Pos (5U)
#define RCC_APB1LPENSR1_TIM7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM7LPENS_Pos) /*!< 0x00000020 */
#define RCC_APB1LPENSR1_TIM7LPENS RCC_APB1LPENSR1_TIM7LPENS_Msk /*!< TIM7 enable */
#define RCC_APB1LPENSR1_TIM12LPENS_Pos (6U)
#define RCC_APB1LPENSR1_TIM12LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM12LPENS_Pos) /*!< 0x00000040 */
#define RCC_APB1LPENSR1_TIM12LPENS RCC_APB1LPENSR1_TIM12LPENS_Msk /*!< TIM12 enable */
#define RCC_APB1LPENSR1_TIM13LPENS_Pos (7U)
#define RCC_APB1LPENSR1_TIM13LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM13LPENS_Pos) /*!< 0x00000080 */
#define RCC_APB1LPENSR1_TIM13LPENS RCC_APB1LPENSR1_TIM13LPENS_Msk /*!< TIM13 enable */
#define RCC_APB1LPENSR1_TIM14LPENS_Pos (8U)
#define RCC_APB1LPENSR1_TIM14LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM14LPENS_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENSR1_TIM14LPENS RCC_APB1LPENSR1_TIM14LPENS_Msk /*!< TIM14 enable */
#define RCC_APB1LPENSR1_LPTIM1LPENS_Pos (9U)
#define RCC_APB1LPENSR1_LPTIM1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_LPTIM1LPENS_Pos) /*!< 0x00000200 */
#define RCC_APB1LPENSR1_LPTIM1LPENS RCC_APB1LPENSR1_LPTIM1LPENS_Msk /*!< LPTIM1 enable */
#define RCC_APB1LPENSR1_WWDGLPENS_Pos (11U)
#define RCC_APB1LPENSR1_WWDGLPENS_Msk (0x1UL << RCC_APB1LPENSR1_WWDGLPENS_Pos) /*!< 0x00000800 */
#define RCC_APB1LPENSR1_WWDGLPENS RCC_APB1LPENSR1_WWDGLPENS_Msk /*!< WWDG enable */
#define RCC_APB1LPENSR1_TIM10LPENS_Pos (12U)
#define RCC_APB1LPENSR1_TIM10LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM10LPENS_Pos) /*!< 0x00001000 */
#define RCC_APB1LPENSR1_TIM10LPENS RCC_APB1LPENSR1_TIM10LPENS_Msk /*!< TIM10 enable */
#define RCC_APB1LPENSR1_TIM11LPENS_Pos (13U)
#define RCC_APB1LPENSR1_TIM11LPENS_Msk (0x1UL << RCC_APB1LPENSR1_TIM11LPENS_Pos) /*!< 0x00002000 */
#define RCC_APB1LPENSR1_TIM11LPENS RCC_APB1LPENSR1_TIM11LPENS_Msk /*!< TIM11 enable */
#define RCC_APB1LPENSR1_SPI2LPENS_Pos (14U)
#define RCC_APB1LPENSR1_SPI2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI2LPENS_Pos) /*!< 0x00004000 */
#define RCC_APB1LPENSR1_SPI2LPENS RCC_APB1LPENSR1_SPI2LPENS_Msk /*!< SPI2 enable */
#define RCC_APB1LPENSR1_SPI3LPENS_Pos (15U)
#define RCC_APB1LPENSR1_SPI3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPI3LPENS_Pos) /*!< 0x00008000 */
#define RCC_APB1LPENSR1_SPI3LPENS RCC_APB1LPENSR1_SPI3LPENS_Msk /*!< SPI3 enable */
#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos (16U)
#define RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_SPDIFRX1LPENS_Pos) /*!< 0x00010000 */
#define RCC_APB1LPENSR1_SPDIFRX1LPENS RCC_APB1LPENSR1_SPDIFRX1LPENS_Msk /*!< SPDIFRX1 enable */
#define RCC_APB1LPENSR1_USART2LPENS_Pos (17U)
#define RCC_APB1LPENSR1_USART2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART2LPENS_Pos) /*!< 0x00020000 */
#define RCC_APB1LPENSR1_USART2LPENS RCC_APB1LPENSR1_USART2LPENS_Msk /*!< USART2 enable */
#define RCC_APB1LPENSR1_USART3LPENS_Pos (18U)
#define RCC_APB1LPENSR1_USART3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_USART3LPENS_Pos) /*!< 0x00040000 */
#define RCC_APB1LPENSR1_USART3LPENS RCC_APB1LPENSR1_USART3LPENS_Msk /*!< USART3 enable */
#define RCC_APB1LPENSR1_UART4LPENS_Pos (19U)
#define RCC_APB1LPENSR1_UART4LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART4LPENS_Pos) /*!< 0x00080000 */
#define RCC_APB1LPENSR1_UART4LPENS RCC_APB1LPENSR1_UART4LPENS_Msk /*!< UART4 enable */
#define RCC_APB1LPENSR1_UART5LPENS_Pos (20U)
#define RCC_APB1LPENSR1_UART5LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART5LPENS_Pos) /*!< 0x00100000 */
#define RCC_APB1LPENSR1_UART5LPENS RCC_APB1LPENSR1_UART5LPENS_Msk /*!< UART5 enable */
#define RCC_APB1LPENSR1_I2C1LPENS_Pos (21U)
#define RCC_APB1LPENSR1_I2C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C1LPENS_Pos) /*!< 0x00200000 */
#define RCC_APB1LPENSR1_I2C1LPENS RCC_APB1LPENSR1_I2C1LPENS_Msk /*!< I2C1 enable */
#define RCC_APB1LPENSR1_I2C2LPENS_Pos (22U)
#define RCC_APB1LPENSR1_I2C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C2LPENS_Pos) /*!< 0x00400000 */
#define RCC_APB1LPENSR1_I2C2LPENS RCC_APB1LPENSR1_I2C2LPENS_Msk /*!< I2C2 enable */
#define RCC_APB1LPENSR1_I2C3LPENS_Pos (23U)
#define RCC_APB1LPENSR1_I2C3LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I2C3LPENS_Pos) /*!< 0x00800000 */
#define RCC_APB1LPENSR1_I2C3LPENS RCC_APB1LPENSR1_I2C3LPENS_Msk /*!< I2C3 enable */
#define RCC_APB1LPENSR1_I3C1LPENS_Pos (24U)
#define RCC_APB1LPENSR1_I3C1LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C1LPENS_Pos) /*!< 0x01000000 */
#define RCC_APB1LPENSR1_I3C1LPENS RCC_APB1LPENSR1_I3C1LPENS_Msk /*!< I3C1 enable */
#define RCC_APB1LPENSR1_I3C2LPENS_Pos (25U)
#define RCC_APB1LPENSR1_I3C2LPENS_Msk (0x1UL << RCC_APB1LPENSR1_I3C2LPENS_Pos) /*!< 0x02000000 */
#define RCC_APB1LPENSR1_I3C2LPENS RCC_APB1LPENSR1_I3C2LPENS_Msk /*!< I3C2 enable */
#define RCC_APB1LPENSR1_UART7LPENS_Pos (30U)
#define RCC_APB1LPENSR1_UART7LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART7LPENS_Pos) /*!< 0x40000000 */
#define RCC_APB1LPENSR1_UART7LPENS RCC_APB1LPENSR1_UART7LPENS_Msk /*!< UART7 enable */
#define RCC_APB1LPENSR1_UART8LPENS_Pos (31U)
#define RCC_APB1LPENSR1_UART8LPENS_Msk (0x1UL << RCC_APB1LPENSR1_UART8LPENS_Pos) /*!< 0x80000000 */
#define RCC_APB1LPENSR1_UART8LPENS RCC_APB1LPENSR1_UART8LPENS_Msk /*!< UART8 enable */
/*************** Bit definition for RCC_APB1LPENSR2 register ****************/
#define RCC_APB1LPENSR2_MDIOSLPENS_Pos (5U)
#define RCC_APB1LPENSR2_MDIOSLPENS_Msk (0x1UL << RCC_APB1LPENSR2_MDIOSLPENS_Pos) /*!< 0x00000020 */
#define RCC_APB1LPENSR2_MDIOSLPENS RCC_APB1LPENSR2_MDIOSLPENS_Msk /*!< MDIOS enable */
#define RCC_APB1LPENSR2_FDCANLPENS_Pos (8U)
#define RCC_APB1LPENSR2_FDCANLPENS_Msk (0x1UL << RCC_APB1LPENSR2_FDCANLPENS_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENSR2_FDCANLPENS RCC_APB1LPENSR2_FDCANLPENS_Msk /*!< FDCAN enable */
#define RCC_APB1LPENSR2_UCPD1LPENS_Pos (18U)
#define RCC_APB1LPENSR2_UCPD1LPENS_Msk (0x1UL << RCC_APB1LPENSR2_UCPD1LPENS_Pos) /*!< 0x00040000 */
#define RCC_APB1LPENSR2_UCPD1LPENS RCC_APB1LPENSR2_UCPD1LPENS_Msk /*!< UCPD1 enable */
/**************** Bit definition for RCC_APB2LPENSR register ****************/
#define RCC_APB2LPENSR_TIM1LPENS_Pos (0U)
#define RCC_APB2LPENSR_TIM1LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM1LPENS_Pos) /*!< 0x00000001 */
#define RCC_APB2LPENSR_TIM1LPENS RCC_APB2LPENSR_TIM1LPENS_Msk /*!< TIM1 enable */
#define RCC_APB2LPENSR_TIM8LPENS_Pos (1U)
#define RCC_APB2LPENSR_TIM8LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM8LPENS_Pos) /*!< 0x00000002 */
#define RCC_APB2LPENSR_TIM8LPENS RCC_APB2LPENSR_TIM8LPENS_Msk /*!< TIM8 enable */
#define RCC_APB2LPENSR_USART1LPENS_Pos (4U)
#define RCC_APB2LPENSR_USART1LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART1LPENS_Pos) /*!< 0x00000010 */
#define RCC_APB2LPENSR_USART1LPENS RCC_APB2LPENSR_USART1LPENS_Msk /*!< USART1 enable */
#define RCC_APB2LPENSR_USART6LPENS_Pos (5U)
#define RCC_APB2LPENSR_USART6LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART6LPENS_Pos) /*!< 0x00000020 */
#define RCC_APB2LPENSR_USART6LPENS RCC_APB2LPENSR_USART6LPENS_Msk /*!< USART6 enable */
#define RCC_APB2LPENSR_UART9LPENS_Pos (6U)
#define RCC_APB2LPENSR_UART9LPENS_Msk (0x1UL << RCC_APB2LPENSR_UART9LPENS_Pos) /*!< 0x00000040 */
#define RCC_APB2LPENSR_UART9LPENS RCC_APB2LPENSR_UART9LPENS_Msk /*!< UART9 enable */
#define RCC_APB2LPENSR_USART10LPENS_Pos (7U)
#define RCC_APB2LPENSR_USART10LPENS_Msk (0x1UL << RCC_APB2LPENSR_USART10LPENS_Pos) /*!< 0x00000080 */
#define RCC_APB2LPENSR_USART10LPENS RCC_APB2LPENSR_USART10LPENS_Msk /*!< USART10 enable */
#define RCC_APB2LPENSR_SPI1LPENS_Pos (12U)
#define RCC_APB2LPENSR_SPI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI1LPENS_Pos) /*!< 0x00001000 */
#define RCC_APB2LPENSR_SPI1LPENS RCC_APB2LPENSR_SPI1LPENS_Msk /*!< SPI1 enable */
#define RCC_APB2LPENSR_SPI4LPENS_Pos (13U)
#define RCC_APB2LPENSR_SPI4LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI4LPENS_Pos) /*!< 0x00002000 */
#define RCC_APB2LPENSR_SPI4LPENS RCC_APB2LPENSR_SPI4LPENS_Msk /*!< SPI4 enable */
#define RCC_APB2LPENSR_TIM18LPENS_Pos (15U)
#define RCC_APB2LPENSR_TIM18LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM18LPENS_Pos) /*!< 0x00008000 */
#define RCC_APB2LPENSR_TIM18LPENS RCC_APB2LPENSR_TIM18LPENS_Msk /*!< TIM18 enable */
#define RCC_APB2LPENSR_TIM15LPENS_Pos (16U)
#define RCC_APB2LPENSR_TIM15LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM15LPENS_Pos) /*!< 0x00010000 */
#define RCC_APB2LPENSR_TIM15LPENS RCC_APB2LPENSR_TIM15LPENS_Msk /*!< TIM15 enable */
#define RCC_APB2LPENSR_TIM16LPENS_Pos (17U)
#define RCC_APB2LPENSR_TIM16LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM16LPENS_Pos) /*!< 0x00020000 */
#define RCC_APB2LPENSR_TIM16LPENS RCC_APB2LPENSR_TIM16LPENS_Msk /*!< TIM16 enable */
#define RCC_APB2LPENSR_TIM17LPENS_Pos (18U)
#define RCC_APB2LPENSR_TIM17LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM17LPENS_Pos) /*!< 0x00040000 */
#define RCC_APB2LPENSR_TIM17LPENS RCC_APB2LPENSR_TIM17LPENS_Msk /*!< TIM17 enable */
#define RCC_APB2LPENSR_TIM9LPENS_Pos (19U)
#define RCC_APB2LPENSR_TIM9LPENS_Msk (0x1UL << RCC_APB2LPENSR_TIM9LPENS_Pos) /*!< 0x00080000 */
#define RCC_APB2LPENSR_TIM9LPENS RCC_APB2LPENSR_TIM9LPENS_Msk /*!< TIM9 enable */
#define RCC_APB2LPENSR_SPI5LPENS_Pos (20U)
#define RCC_APB2LPENSR_SPI5LPENS_Msk (0x1UL << RCC_APB2LPENSR_SPI5LPENS_Pos) /*!< 0x00100000 */
#define RCC_APB2LPENSR_SPI5LPENS RCC_APB2LPENSR_SPI5LPENS_Msk /*!< SPI5 enable */
#define RCC_APB2LPENSR_SAI1LPENS_Pos (21U)
#define RCC_APB2LPENSR_SAI1LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI1LPENS_Pos) /*!< 0x00200000 */
#define RCC_APB2LPENSR_SAI1LPENS RCC_APB2LPENSR_SAI1LPENS_Msk /*!< SAI1 enable */
#define RCC_APB2LPENSR_SAI2LPENS_Pos (22U)
#define RCC_APB2LPENSR_SAI2LPENS_Msk (0x1UL << RCC_APB2LPENSR_SAI2LPENS_Pos) /*!< 0x00400000 */
#define RCC_APB2LPENSR_SAI2LPENS RCC_APB2LPENSR_SAI2LPENS_Msk /*!< SAI2 enable */
/**************** Bit definition for RCC_APB3LPENSR register ****************/
#define RCC_APB3LPENSR_DFTLPENS_Pos (2U)
#define RCC_APB3LPENSR_DFTLPENS_Msk (0x1UL << RCC_APB3LPENSR_DFTLPENS_Pos)/*!< 0x00000004 */
#define RCC_APB3LPENSR_DFTLPENS RCC_APB3LPENSR_DFTLPENS_Msk /*!< DFT enable */
/*************** Bit definition for RCC_APB4LPENSR1 register ****************/
#define RCC_APB4LPENSR1_HDPLPENS_Pos (2U)
#define RCC_APB4LPENSR1_HDPLPENS_Msk (0x1UL << RCC_APB4LPENSR1_HDPLPENS_Pos) /*!< 0x00000004 */
#define RCC_APB4LPENSR1_HDPLPENS RCC_APB4LPENSR1_HDPLPENS_Msk /*!< HDP enable */
#define RCC_APB4LPENSR1_LPUART1LPENS_Pos (3U)
#define RCC_APB4LPENSR1_LPUART1LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPUART1LPENS_Pos) /*!< 0x00000008 */
#define RCC_APB4LPENSR1_LPUART1LPENS RCC_APB4LPENSR1_LPUART1LPENS_Msk /*!< LPUART1 enable */
#define RCC_APB4LPENSR1_SPI6LPENS_Pos (5U)
#define RCC_APB4LPENSR1_SPI6LPENS_Msk (0x1UL << RCC_APB4LPENSR1_SPI6LPENS_Pos) /*!< 0x00000020 */
#define RCC_APB4LPENSR1_SPI6LPENS RCC_APB4LPENSR1_SPI6LPENS_Msk /*!< SPI6 enable */
#define RCC_APB4LPENSR1_I2C4LPENS_Pos (7U)
#define RCC_APB4LPENSR1_I2C4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_I2C4LPENS_Pos) /*!< 0x00000080 */
#define RCC_APB4LPENSR1_I2C4LPENS RCC_APB4LPENSR1_I2C4LPENS_Msk /*!< I2C4 enable */
#define RCC_APB4LPENSR1_LPTIM2LPENS_Pos (9U)
#define RCC_APB4LPENSR1_LPTIM2LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM2LPENS_Pos) /*!< 0x00000200 */
#define RCC_APB4LPENSR1_LPTIM2LPENS RCC_APB4LPENSR1_LPTIM2LPENS_Msk /*!< LPTIM2 enable */
#define RCC_APB4LPENSR1_LPTIM3LPENS_Pos (10U)
#define RCC_APB4LPENSR1_LPTIM3LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM3LPENS_Pos) /*!< 0x00000400 */
#define RCC_APB4LPENSR1_LPTIM3LPENS RCC_APB4LPENSR1_LPTIM3LPENS_Msk /*!< LPTIM3 enable */
#define RCC_APB4LPENSR1_LPTIM4LPENS_Pos (11U)
#define RCC_APB4LPENSR1_LPTIM4LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM4LPENS_Pos) /*!< 0x00000800 */
#define RCC_APB4LPENSR1_LPTIM4LPENS RCC_APB4LPENSR1_LPTIM4LPENS_Msk /*!< LPTIM4 enable */
#define RCC_APB4LPENSR1_LPTIM5LPENS_Pos (12U)
#define RCC_APB4LPENSR1_LPTIM5LPENS_Msk (0x1UL << RCC_APB4LPENSR1_LPTIM5LPENS_Pos) /*!< 0x00001000 */
#define RCC_APB4LPENSR1_LPTIM5LPENS RCC_APB4LPENSR1_LPTIM5LPENS_Msk /*!< LPTIM5 enable */
#define RCC_APB4LPENSR1_VREFBUFLPENS_Pos (15U)
#define RCC_APB4LPENSR1_VREFBUFLPENS_Msk (0x1UL << RCC_APB4LPENSR1_VREFBUFLPENS_Pos) /*!< 0x00008000 */
#define RCC_APB4LPENSR1_VREFBUFLPENS RCC_APB4LPENSR1_VREFBUFLPENS_Msk /*!< VREFBUF enable */
#define RCC_APB4LPENSR1_RTCLPENS_Pos (16U)
#define RCC_APB4LPENSR1_RTCLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCLPENS_Pos) /*!< 0x00010000 */
#define RCC_APB4LPENSR1_RTCLPENS RCC_APB4LPENSR1_RTCLPENS_Msk /*!< RTC enable */
#define RCC_APB4LPENSR1_RTCAPBLPENS_Pos (17U)
#define RCC_APB4LPENSR1_RTCAPBLPENS_Msk (0x1UL << RCC_APB4LPENSR1_RTCAPBLPENS_Pos) /*!< 0x00020000 */
#define RCC_APB4LPENSR1_RTCAPBLPENS RCC_APB4LPENSR1_RTCAPBLPENS_Msk /*!< RTCAPB enable */
/*************** Bit definition for RCC_APB4LPENSR2 register ****************/
#define RCC_APB4LPENSR2_SYSCFGLPENS_Pos (0U)
#define RCC_APB4LPENSR2_SYSCFGLPENS_Msk (0x1UL << RCC_APB4LPENSR2_SYSCFGLPENS_Pos) /*!< 0x00000001 */
#define RCC_APB4LPENSR2_SYSCFGLPENS RCC_APB4LPENSR2_SYSCFGLPENS_Msk /*!< SYSCFG enable */
#define RCC_APB4LPENSR2_BSECLPENS_Pos (1U)
#define RCC_APB4LPENSR2_BSECLPENS_Msk (0x1UL << RCC_APB4LPENSR2_BSECLPENS_Pos) /*!< 0x00000002 */
#define RCC_APB4LPENSR2_BSECLPENS RCC_APB4LPENSR2_BSECLPENS_Msk /*!< BSEC enable */
#define RCC_APB4LPENSR2_DTSLPENS_Pos (2U)
#define RCC_APB4LPENSR2_DTSLPENS_Msk (0x1UL << RCC_APB4LPENSR2_DTSLPENS_Pos) /*!< 0x00000004 */
#define RCC_APB4LPENSR2_DTSLPENS RCC_APB4LPENSR2_DTSLPENS_Msk /*!< DTS enable */
/**************** Bit definition for RCC_APB5LPENSR register ****************/
#define RCC_APB5LPENSR_LTDCLPENS_Pos (1U)
#define RCC_APB5LPENSR_LTDCLPENS_Msk (0x1UL << RCC_APB5LPENSR_LTDCLPENS_Pos) /*!< 0x00000002 */
#define RCC_APB5LPENSR_LTDCLPENS RCC_APB5LPENSR_LTDCLPENS_Msk /*!< LTDC enable */
#define RCC_APB5LPENSR_DCMIPPLPENS_Pos (2U)
#define RCC_APB5LPENSR_DCMIPPLPENS_Msk (0x1UL << RCC_APB5LPENSR_DCMIPPLPENS_Pos) /*!< 0x00000004 */
#define RCC_APB5LPENSR_DCMIPPLPENS RCC_APB5LPENSR_DCMIPPLPENS_Msk /*!< DCMIPP enable */
#define RCC_APB5LPENSR_GFXTIMLPENS_Pos (4U)
#define RCC_APB5LPENSR_GFXTIMLPENS_Msk (0x1UL << RCC_APB5LPENSR_GFXTIMLPENS_Pos) /*!< 0x00000010 */
#define RCC_APB5LPENSR_GFXTIMLPENS RCC_APB5LPENSR_GFXTIMLPENS_Msk /*!< GFXTIM enable */
#define RCC_APB5LPENSR_VENCLPENS_Pos (5U)
#define RCC_APB5LPENSR_VENCLPENS_Msk (0x1UL << RCC_APB5LPENSR_VENCLPENS_Pos) /*!< 0x00000020 */
#define RCC_APB5LPENSR_VENCLPENS RCC_APB5LPENSR_VENCLPENS_Msk /*!< VENC enable */
#define RCC_APB5LPENSR_CSILPENS_Pos (6U)
#define RCC_APB5LPENSR_CSILPENS_Msk (0x1UL << RCC_APB5LPENSR_CSILPENS_Pos)/*!< 0x00000040 */
#define RCC_APB5LPENSR_CSILPENS RCC_APB5LPENSR_CSILPENS_Msk /*!< CSI enable */
/**************** Bit definition for RCC_PRIVCFGSR0 register ****************/
#define RCC_PRIVCFGSR0_LSIPRIVS_Pos (0U)
#define RCC_PRIVCFGSR0_LSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSIPRIVS_Pos)/*!< 0x00000001 */
#define RCC_PRIVCFGSR0_LSIPRIVS RCC_PRIVCFGSR0_LSIPRIVS_Msk /*!< Privileged protection of the LSI configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR0_LSEPRIVS_Pos (1U)
#define RCC_PRIVCFGSR0_LSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_LSEPRIVS_Pos)/*!< 0x00000002 */
#define RCC_PRIVCFGSR0_LSEPRIVS RCC_PRIVCFGSR0_LSEPRIVS_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR0_MSIPRIVS_Pos (2U)
#define RCC_PRIVCFGSR0_MSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_MSIPRIVS_Pos)/*!< 0x00000004 */
#define RCC_PRIVCFGSR0_MSIPRIVS RCC_PRIVCFGSR0_MSIPRIVS_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR0_HSIPRIVS_Pos (3U)
#define RCC_PRIVCFGSR0_HSIPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSIPRIVS_Pos)/*!< 0x00000008 */
#define RCC_PRIVCFGSR0_HSIPRIVS RCC_PRIVCFGSR0_HSIPRIVS_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR0_HSEPRIVS_Pos (4U)
#define RCC_PRIVCFGSR0_HSEPRIVS_Msk (0x1UL << RCC_PRIVCFGSR0_HSEPRIVS_Pos)/*!< 0x00000010 */
#define RCC_PRIVCFGSR0_HSEPRIVS RCC_PRIVCFGSR0_HSEPRIVS_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGSR0 register *****************/
#define RCC_PUBCFGSR0_LSIPUBS_Pos (0U)
#define RCC_PUBCFGSR0_LSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSIPUBS_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGSR0_LSIPUBS RCC_PUBCFGSR0_LSIPUBS_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR0_LSEPUBS_Pos (1U)
#define RCC_PUBCFGSR0_LSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_LSEPUBS_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGSR0_LSEPUBS RCC_PUBCFGSR0_LSEPUBS_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR0_MSIPUBS_Pos (2U)
#define RCC_PUBCFGSR0_MSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_MSIPUBS_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGSR0_MSIPUBS RCC_PUBCFGSR0_MSIPUBS_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR0_HSIPUBS_Pos (3U)
#define RCC_PUBCFGSR0_HSIPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSIPUBS_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGSR0_HSIPUBS RCC_PUBCFGSR0_HSIPUBS_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR0_HSEPUBS_Pos (4U)
#define RCC_PUBCFGSR0_HSEPUBS_Msk (0x1UL << RCC_PUBCFGSR0_HSEPUBS_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGSR0_HSEPUBS RCC_PUBCFGSR0_HSEPUBS_Msk /*!< Public protection of he HSE configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGSR1 register ****************/
#define RCC_PRIVCFGSR1_PLL1PRIVS_Pos (0U)
#define RCC_PRIVCFGSR1_PLL1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL1PRIVS_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGSR1_PLL1PRIVS RCC_PRIVCFGSR1_PLL1PRIVS_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR1_PLL2PRIVS_Pos (1U)
#define RCC_PRIVCFGSR1_PLL2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL2PRIVS_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGSR1_PLL2PRIVS RCC_PRIVCFGSR1_PLL2PRIVS_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR1_PLL3PRIVS_Pos (2U)
#define RCC_PRIVCFGSR1_PLL3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL3PRIVS_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGSR1_PLL3PRIVS RCC_PRIVCFGSR1_PLL3PRIVS_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR1_PLL4PRIVS_Pos (3U)
#define RCC_PRIVCFGSR1_PLL4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR1_PLL4PRIVS_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGSR1_PLL4PRIVS RCC_PRIVCFGSR1_PLL4PRIVS_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGSR1 register *****************/
#define RCC_PUBCFGSR1_PLL1PUBS_Pos (0U)
#define RCC_PUBCFGSR1_PLL1PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL1PUBS_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGSR1_PLL1PUBS RCC_PUBCFGSR1_PLL1PUBS_Msk /*!< Public protection of PLL1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR1_PLL2PUBS_Pos (1U)
#define RCC_PUBCFGSR1_PLL2PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL2PUBS_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGSR1_PLL2PUBS RCC_PUBCFGSR1_PLL2PUBS_Msk /*!< Public protection of PLL2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR1_PLL3PUBS_Pos (2U)
#define RCC_PUBCFGSR1_PLL3PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL3PUBS_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGSR1_PLL3PUBS RCC_PUBCFGSR1_PLL3PUBS_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR1_PLL4PUBS_Pos (3U)
#define RCC_PUBCFGSR1_PLL4PUBS_Msk (0x1UL << RCC_PUBCFGSR1_PLL4PUBS_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGSR1_PLL4PUBS RCC_PUBCFGSR1_PLL4PUBS_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGSR2 register ****************/
#define RCC_PRIVCFGSR2_IC1PRIVS_Pos (0U)
#define RCC_PRIVCFGSR2_IC1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC1PRIVS_Pos)/*!< 0x00000001 */
#define RCC_PRIVCFGSR2_IC1PRIVS RCC_PRIVCFGSR2_IC1PRIVS_Msk /*!< Privileged protection of IC1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC2PRIVS_Pos (1U)
#define RCC_PRIVCFGSR2_IC2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC2PRIVS_Pos)/*!< 0x00000002 */
#define RCC_PRIVCFGSR2_IC2PRIVS RCC_PRIVCFGSR2_IC2PRIVS_Msk /*!< Privileged protection of IC2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC3PRIVS_Pos (2U)
#define RCC_PRIVCFGSR2_IC3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC3PRIVS_Pos)/*!< 0x00000004 */
#define RCC_PRIVCFGSR2_IC3PRIVS RCC_PRIVCFGSR2_IC3PRIVS_Msk /*!< Privileged protection of IC3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC4PRIVS_Pos (3U)
#define RCC_PRIVCFGSR2_IC4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC4PRIVS_Pos)/*!< 0x00000008 */
#define RCC_PRIVCFGSR2_IC4PRIVS RCC_PRIVCFGSR2_IC4PRIVS_Msk /*!< Privileged protection of IC4 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC5PRIVS_Pos (4U)
#define RCC_PRIVCFGSR2_IC5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC5PRIVS_Pos)/*!< 0x00000010 */
#define RCC_PRIVCFGSR2_IC5PRIVS RCC_PRIVCFGSR2_IC5PRIVS_Msk /*!< Privileged protection of IC5 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC6PRIVS_Pos (5U)
#define RCC_PRIVCFGSR2_IC6PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC6PRIVS_Pos)/*!< 0x00000020 */
#define RCC_PRIVCFGSR2_IC6PRIVS RCC_PRIVCFGSR2_IC6PRIVS_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC7PRIVS_Pos (6U)
#define RCC_PRIVCFGSR2_IC7PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC7PRIVS_Pos)/*!< 0x00000040 */
#define RCC_PRIVCFGSR2_IC7PRIVS RCC_PRIVCFGSR2_IC7PRIVS_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC8PRIVS_Pos (7U)
#define RCC_PRIVCFGSR2_IC8PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC8PRIVS_Pos)/*!< 0x00000080 */
#define RCC_PRIVCFGSR2_IC8PRIVS RCC_PRIVCFGSR2_IC8PRIVS_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC9PRIVS_Pos (8U)
#define RCC_PRIVCFGSR2_IC9PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC9PRIVS_Pos)/*!< 0x00000100 */
#define RCC_PRIVCFGSR2_IC9PRIVS RCC_PRIVCFGSR2_IC9PRIVS_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC10PRIVS_Pos (9U)
#define RCC_PRIVCFGSR2_IC10PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC10PRIVS_Pos) /*!< 0x00000200 */
#define RCC_PRIVCFGSR2_IC10PRIVS RCC_PRIVCFGSR2_IC10PRIVS_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC11PRIVS_Pos (10U)
#define RCC_PRIVCFGSR2_IC11PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC11PRIVS_Pos) /*!< 0x00000400 */
#define RCC_PRIVCFGSR2_IC11PRIVS RCC_PRIVCFGSR2_IC11PRIVS_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC12PRIVS_Pos (11U)
#define RCC_PRIVCFGSR2_IC12PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC12PRIVS_Pos) /*!< 0x00000800 */
#define RCC_PRIVCFGSR2_IC12PRIVS RCC_PRIVCFGSR2_IC12PRIVS_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC13PRIVS_Pos (12U)
#define RCC_PRIVCFGSR2_IC13PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC13PRIVS_Pos) /*!< 0x00001000 */
#define RCC_PRIVCFGSR2_IC13PRIVS RCC_PRIVCFGSR2_IC13PRIVS_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC14PRIVS_Pos (13U)
#define RCC_PRIVCFGSR2_IC14PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC14PRIVS_Pos) /*!< 0x00002000 */
#define RCC_PRIVCFGSR2_IC14PRIVS RCC_PRIVCFGSR2_IC14PRIVS_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC15PRIVS_Pos (14U)
#define RCC_PRIVCFGSR2_IC15PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC15PRIVS_Pos) /*!< 0x00004000 */
#define RCC_PRIVCFGSR2_IC15PRIVS RCC_PRIVCFGSR2_IC15PRIVS_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC16PRIVS_Pos (15U)
#define RCC_PRIVCFGSR2_IC16PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC16PRIVS_Pos) /*!< 0x00008000 */
#define RCC_PRIVCFGSR2_IC16PRIVS RCC_PRIVCFGSR2_IC16PRIVS_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC17PRIVS_Pos (16U)
#define RCC_PRIVCFGSR2_IC17PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC17PRIVS_Pos) /*!< 0x00010000 */
#define RCC_PRIVCFGSR2_IC17PRIVS RCC_PRIVCFGSR2_IC17PRIVS_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC18PRIVS_Pos (17U)
#define RCC_PRIVCFGSR2_IC18PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC18PRIVS_Pos) /*!< 0x00020000 */
#define RCC_PRIVCFGSR2_IC18PRIVS RCC_PRIVCFGSR2_IC18PRIVS_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC19PRIVS_Pos (18U)
#define RCC_PRIVCFGSR2_IC19PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC19PRIVS_Pos) /*!< 0x00040000 */
#define RCC_PRIVCFGSR2_IC19PRIVS RCC_PRIVCFGSR2_IC19PRIVS_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR2_IC20PRIVS_Pos (19U)
#define RCC_PRIVCFGSR2_IC20PRIVS_Msk (0x1UL << RCC_PRIVCFGSR2_IC20PRIVS_Pos) /*!< 0x00080000 */
#define RCC_PRIVCFGSR2_IC20PRIVS RCC_PRIVCFGSR2_IC20PRIVS_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGSR2 register *****************/
#define RCC_PUBCFGSR2_IC1PUBS_Pos (0U)
#define RCC_PUBCFGSR2_IC1PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC1PUBS_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGSR2_IC1PUBS RCC_PUBCFGSR2_IC1PUBS_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC2PUBS_Pos (1U)
#define RCC_PUBCFGSR2_IC2PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC2PUBS_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGSR2_IC2PUBS RCC_PUBCFGSR2_IC2PUBS_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC3PUBS_Pos (2U)
#define RCC_PUBCFGSR2_IC3PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC3PUBS_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGSR2_IC3PUBS RCC_PUBCFGSR2_IC3PUBS_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC4PUBS_Pos (3U)
#define RCC_PUBCFGSR2_IC4PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC4PUBS_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGSR2_IC4PUBS RCC_PUBCFGSR2_IC4PUBS_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC5PUBS_Pos (4U)
#define RCC_PUBCFGSR2_IC5PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC5PUBS_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGSR2_IC5PUBS RCC_PUBCFGSR2_IC5PUBS_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC6PUBS_Pos (5U)
#define RCC_PUBCFGSR2_IC6PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC6PUBS_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGSR2_IC6PUBS RCC_PUBCFGSR2_IC6PUBS_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC7PUBS_Pos (6U)
#define RCC_PUBCFGSR2_IC7PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC7PUBS_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGSR2_IC7PUBS RCC_PUBCFGSR2_IC7PUBS_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC8PUBS_Pos (7U)
#define RCC_PUBCFGSR2_IC8PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC8PUBS_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGSR2_IC8PUBS RCC_PUBCFGSR2_IC8PUBS_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC9PUBS_Pos (8U)
#define RCC_PUBCFGSR2_IC9PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC9PUBS_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGSR2_IC9PUBS RCC_PUBCFGSR2_IC9PUBS_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC10PUBS_Pos (9U)
#define RCC_PUBCFGSR2_IC10PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC10PUBS_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGSR2_IC10PUBS RCC_PUBCFGSR2_IC10PUBS_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC11PUBS_Pos (10U)
#define RCC_PUBCFGSR2_IC11PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC11PUBS_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGSR2_IC11PUBS RCC_PUBCFGSR2_IC11PUBS_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC12PUBS_Pos (11U)
#define RCC_PUBCFGSR2_IC12PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC12PUBS_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGSR2_IC12PUBS RCC_PUBCFGSR2_IC12PUBS_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC13PUBS_Pos (12U)
#define RCC_PUBCFGSR2_IC13PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC13PUBS_Pos) /*!< 0x00001000 */
#define RCC_PUBCFGSR2_IC13PUBS RCC_PUBCFGSR2_IC13PUBS_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC14PUBS_Pos (13U)
#define RCC_PUBCFGSR2_IC14PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC14PUBS_Pos) /*!< 0x00002000 */
#define RCC_PUBCFGSR2_IC14PUBS RCC_PUBCFGSR2_IC14PUBS_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC15PUBS_Pos (14U)
#define RCC_PUBCFGSR2_IC15PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC15PUBS_Pos) /*!< 0x00004000 */
#define RCC_PUBCFGSR2_IC15PUBS RCC_PUBCFGSR2_IC15PUBS_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC16PUBS_Pos (15U)
#define RCC_PUBCFGSR2_IC16PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC16PUBS_Pos) /*!< 0x00008000 */
#define RCC_PUBCFGSR2_IC16PUBS RCC_PUBCFGSR2_IC16PUBS_Msk /*!< Public protection of th IC16 configuration bits (enable, ready, divider */
#define RCC_PUBCFGSR2_IC17PUBS_Pos (16U)
#define RCC_PUBCFGSR2_IC17PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC17PUBS_Pos) /*!< 0x00010000 */
#define RCC_PUBCFGSR2_IC17PUBS RCC_PUBCFGSR2_IC17PUBS_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC18PUBS_Pos (17U)
#define RCC_PUBCFGSR2_IC18PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC18PUBS_Pos) /*!< 0x00020000 */
#define RCC_PUBCFGSR2_IC18PUBS RCC_PUBCFGSR2_IC18PUBS_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC19PUBS_Pos (18U)
#define RCC_PUBCFGSR2_IC19PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC19PUBS_Pos) /*!< 0x00040000 */
#define RCC_PUBCFGSR2_IC19PUBS RCC_PUBCFGSR2_IC19PUBS_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR2_IC20PUBS_Pos (19U)
#define RCC_PUBCFGSR2_IC20PUBS_Msk (0x1UL << RCC_PUBCFGSR2_IC20PUBS_Pos) /*!< 0x00080000 */
#define RCC_PUBCFGSR2_IC20PUBS RCC_PUBCFGSR2_IC20PUBS_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGSR3 register ****************/
#define RCC_PRIVCFGSR3_MODPRIVS_Pos (0U)
#define RCC_PRIVCFGSR3_MODPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_MODPRIVS_Pos)/*!< 0x00000001 */
#define RCC_PRIVCFGSR3_MODPRIVS RCC_PRIVCFGSR3_MODPRIVS_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR3_SYSPRIVS_Pos (1U)
#define RCC_PRIVCFGSR3_SYSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_SYSPRIVS_Pos)/*!< 0x00000002 */
#define RCC_PRIVCFGSR3_SYSPRIVS RCC_PRIVCFGSR3_SYSPRIVS_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR3_BUSPRIVS_Pos (2U)
#define RCC_PRIVCFGSR3_BUSPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_BUSPRIVS_Pos)/*!< 0x00000004 */
#define RCC_PRIVCFGSR3_BUSPRIVS RCC_PRIVCFGSR3_BUSPRIVS_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR3_PERPRIVS_Pos (3U)
#define RCC_PRIVCFGSR3_PERPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_PERPRIVS_Pos)/*!< 0x00000008 */
#define RCC_PRIVCFGSR3_PERPRIVS RCC_PRIVCFGSR3_PERPRIVS_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR3_INTPRIVS_Pos (4U)
#define RCC_PRIVCFGSR3_INTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_INTPRIVS_Pos)/*!< 0x00000010 */
#define RCC_PRIVCFGSR3_INTPRIVS RCC_PRIVCFGSR3_INTPRIVS_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR3_RSTPRIVS_Pos (5U)
#define RCC_PRIVCFGSR3_RSTPRIVS_Msk (0x1UL << RCC_PRIVCFGSR3_RSTPRIVS_Pos)/*!< 0x00000020 */
#define RCC_PRIVCFGSR3_RSTPRIVS RCC_PRIVCFGSR3_RSTPRIVS_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGSR3 register *****************/
#define RCC_PUBCFGSR3_MODPUBS_Pos (0U)
#define RCC_PUBCFGSR3_MODPUBS_Msk (0x1UL << RCC_PUBCFGSR3_MODPUBS_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGSR3_MODPUBS RCC_PUBCFGSR3_MODPUBS_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR3_SYSPUBS_Pos (1U)
#define RCC_PUBCFGSR3_SYSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_SYSPUBS_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGSR3_SYSPUBS RCC_PUBCFGSR3_SYSPUBS_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR3_BUSPUBS_Pos (2U)
#define RCC_PUBCFGSR3_BUSPUBS_Msk (0x1UL << RCC_PUBCFGSR3_BUSPUBS_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGSR3_BUSPUBS RCC_PUBCFGSR3_BUSPUBS_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR3_PERPUBS_Pos (3U)
#define RCC_PUBCFGSR3_PERPUBS_Msk (0x1UL << RCC_PUBCFGSR3_PERPUBS_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGSR3_PERPUBS RCC_PUBCFGSR3_PERPUBS_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR3_INTPUBS_Pos (4U)
#define RCC_PUBCFGSR3_INTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_INTPUBS_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGSR3_INTPUBS RCC_PUBCFGSR3_INTPUBS_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR3_RSTPUBS_Pos (5U)
#define RCC_PUBCFGSR3_RSTPUBS_Msk (0x1UL << RCC_PUBCFGSR3_RSTPUBS_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGSR3_RSTPUBS RCC_PUBCFGSR3_RSTPUBS_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGSR4 register ****************/
#define RCC_PRIVCFGSR4_ACLKNPRIVS_Pos (0U)
#define RCC_PRIVCFGSR4_ACLKNPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNPRIVS_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGSR4_ACLKNPRIVS RCC_PRIVCFGSR4_ACLKNPRIVS_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos (1U)
#define RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_ACLKNCPRIVS_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGSR4_ACLKNCPRIVS RCC_PRIVCFGSR4_ACLKNCPRIVS_Msk /*!< Privileged protection of th ACLKNC configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_AHBMPRIVS_Pos (2U)
#define RCC_PRIVCFGSR4_AHBMPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHBMPRIVS_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGSR4_AHBMPRIVS RCC_PRIVCFGSR4_AHBMPRIVS_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_AHB1PRIVS_Pos (3U)
#define RCC_PRIVCFGSR4_AHB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB1PRIVS_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGSR4_AHB1PRIVS RCC_PRIVCFGSR4_AHB1PRIVS_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_AHB2PRIVS_Pos (4U)
#define RCC_PRIVCFGSR4_AHB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB2PRIVS_Pos) /*!< 0x00000010 */
#define RCC_PRIVCFGSR4_AHB2PRIVS RCC_PRIVCFGSR4_AHB2PRIVS_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_AHB3PRIVS_Pos (5U)
#define RCC_PRIVCFGSR4_AHB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB3PRIVS_Pos) /*!< 0x00000020 */
#define RCC_PRIVCFGSR4_AHB3PRIVS RCC_PRIVCFGSR4_AHB3PRIVS_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_AHB4PRIVS_Pos (6U)
#define RCC_PRIVCFGSR4_AHB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB4PRIVS_Pos) /*!< 0x00000040 */
#define RCC_PRIVCFGSR4_AHB4PRIVS RCC_PRIVCFGSR4_AHB4PRIVS_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_AHB5PRIVS_Pos (7U)
#define RCC_PRIVCFGSR4_AHB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_AHB5PRIVS_Pos) /*!< 0x00000080 */
#define RCC_PRIVCFGSR4_AHB5PRIVS RCC_PRIVCFGSR4_AHB5PRIVS_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_APB1PRIVS_Pos (8U)
#define RCC_PRIVCFGSR4_APB1PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB1PRIVS_Pos) /*!< 0x00000100 */
#define RCC_PRIVCFGSR4_APB1PRIVS RCC_PRIVCFGSR4_APB1PRIVS_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_APB2PRIVS_Pos (9U)
#define RCC_PRIVCFGSR4_APB2PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB2PRIVS_Pos) /*!< 0x00000200 */
#define RCC_PRIVCFGSR4_APB2PRIVS RCC_PRIVCFGSR4_APB2PRIVS_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_APB3PRIVS_Pos (10U)
#define RCC_PRIVCFGSR4_APB3PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB3PRIVS_Pos) /*!< 0x00000400 */
#define RCC_PRIVCFGSR4_APB3PRIVS RCC_PRIVCFGSR4_APB3PRIVS_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_APB4PRIVS_Pos (11U)
#define RCC_PRIVCFGSR4_APB4PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB4PRIVS_Pos) /*!< 0x00000800 */
#define RCC_PRIVCFGSR4_APB4PRIVS RCC_PRIVCFGSR4_APB4PRIVS_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_APB5PRIVS_Pos (12U)
#define RCC_PRIVCFGSR4_APB5PRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_APB5PRIVS_Pos) /*!< 0x00001000 */
#define RCC_PRIVCFGSR4_APB5PRIVS RCC_PRIVCFGSR4_APB5PRIVS_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGSR4_NOCPRIVS_Pos (13U)
#define RCC_PRIVCFGSR4_NOCPRIVS_Msk (0x1UL << RCC_PRIVCFGSR4_NOCPRIVS_Pos)/*!< 0x00002000 */
#define RCC_PRIVCFGSR4_NOCPRIVS RCC_PRIVCFGSR4_NOCPRIVS_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGSR4 register *****************/
#define RCC_PUBCFGSR4_ACLKNPUBS_Pos (0U)
#define RCC_PUBCFGSR4_ACLKNPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNPUBS_Pos)/*!< 0x00000001 */
#define RCC_PUBCFGSR4_ACLKNPUBS RCC_PUBCFGSR4_ACLKNPUBS_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_ACLKNCPUBS_Pos (1U)
#define RCC_PUBCFGSR4_ACLKNCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_ACLKNCPUBS_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGSR4_ACLKNCPUBS RCC_PUBCFGSR4_ACLKNCPUBS_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_AHBMPUBS_Pos (2U)
#define RCC_PUBCFGSR4_AHBMPUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHBMPUBS_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGSR4_AHBMPUBS RCC_PUBCFGSR4_AHBMPUBS_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_AHB1PUBS_Pos (3U)
#define RCC_PUBCFGSR4_AHB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB1PUBS_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGSR4_AHB1PUBS RCC_PUBCFGSR4_AHB1PUBS_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_AHB2PUBS_Pos (4U)
#define RCC_PUBCFGSR4_AHB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB2PUBS_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGSR4_AHB2PUBS RCC_PUBCFGSR4_AHB2PUBS_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_AHB3PUBS_Pos (5U)
#define RCC_PUBCFGSR4_AHB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB3PUBS_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGSR4_AHB3PUBS RCC_PUBCFGSR4_AHB3PUBS_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_AHB4PUBS_Pos (6U)
#define RCC_PUBCFGSR4_AHB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB4PUBS_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGSR4_AHB4PUBS RCC_PUBCFGSR4_AHB4PUBS_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_AHB5PUBS_Pos (7U)
#define RCC_PUBCFGSR4_AHB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_AHB5PUBS_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGSR4_AHB5PUBS RCC_PUBCFGSR4_AHB5PUBS_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_APB1PUBS_Pos (8U)
#define RCC_PUBCFGSR4_APB1PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB1PUBS_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGSR4_APB1PUBS RCC_PUBCFGSR4_APB1PUBS_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_APB2PUBS_Pos (9U)
#define RCC_PUBCFGSR4_APB2PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB2PUBS_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGSR4_APB2PUBS RCC_PUBCFGSR4_APB2PUBS_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_APB3PUBS_Pos (10U)
#define RCC_PUBCFGSR4_APB3PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB3PUBS_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGSR4_APB3PUBS RCC_PUBCFGSR4_APB3PUBS_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_APB4PUBS_Pos (11U)
#define RCC_PUBCFGSR4_APB4PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB4PUBS_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGSR4_APB4PUBS RCC_PUBCFGSR4_APB4PUBS_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_APB5PUBS_Pos (12U)
#define RCC_PUBCFGSR4_APB5PUBS_Msk (0x1UL << RCC_PUBCFGSR4_APB5PUBS_Pos) /*!< 0x00001000 */
#define RCC_PUBCFGSR4_APB5PUBS RCC_PUBCFGSR4_APB5PUBS_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR4_NOCPUBS_Pos (13U)
#define RCC_PUBCFGSR4_NOCPUBS_Msk (0x1UL << RCC_PUBCFGSR4_NOCPUBS_Pos) /*!< 0x00002000 */
#define RCC_PUBCFGSR4_NOCPUBS RCC_PUBCFGSR4_NOCPUBS_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGSR5 register *****************/
#define RCC_PUBCFGSR5_AXISRAM3PUBS_Pos (0U)
#define RCC_PUBCFGSR5_AXISRAM3PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM3PUBS_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGSR5_AXISRAM3PUBS RCC_PUBCFGSR5_AXISRAM3PUBS_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_AXISRAM4PUBS_Pos (1U)
#define RCC_PUBCFGSR5_AXISRAM4PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM4PUBS_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGSR5_AXISRAM4PUBS RCC_PUBCFGSR5_AXISRAM4PUBS_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_AXISRAM5PUBS_Pos (2U)
#define RCC_PUBCFGSR5_AXISRAM5PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM5PUBS_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGSR5_AXISRAM5PUBS RCC_PUBCFGSR5_AXISRAM5PUBS_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_AXISRAM6PUBS_Pos (3U)
#define RCC_PUBCFGSR5_AXISRAM6PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM6PUBS_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGSR5_AXISRAM6PUBS RCC_PUBCFGSR5_AXISRAM6PUBS_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos (4U)
#define RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM1PUBS_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGSR5_AHBSRAM1PUBS RCC_PUBCFGSR5_AHBSRAM1PUBS_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos (5U)
#define RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AHBSRAM2PUBS_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGSR5_AHBSRAM2PUBS RCC_PUBCFGSR5_AHBSRAM2PUBS_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_BKPSRAMPUBS_Pos (6U)
#define RCC_PUBCFGSR5_BKPSRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_BKPSRAMPUBS_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGSR5_BKPSRAMPUBS RCC_PUBCFGSR5_BKPSRAMPUBS_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_AXISRAM1PUBS_Pos (7U)
#define RCC_PUBCFGSR5_AXISRAM1PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM1PUBS_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGSR5_AXISRAM1PUBS RCC_PUBCFGSR5_AXISRAM1PUBS_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_AXISRAM2PUBS_Pos (8U)
#define RCC_PUBCFGSR5_AXISRAM2PUBS_Msk (0x1UL << RCC_PUBCFGSR5_AXISRAM2PUBS_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGSR5_AXISRAM2PUBS RCC_PUBCFGSR5_AXISRAM2PUBS_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_FLEXRAMPUBS_Pos (9U)
#define RCC_PUBCFGSR5_FLEXRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_FLEXRAMPUBS_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGSR5_FLEXRAMPUBS RCC_PUBCFGSR5_FLEXRAMPUBS_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos (10U)
#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGSR5_CACHEAXIRAMPUBS RCC_PUBCFGSR5_CACHEAXIRAMPUBS_Msk /*!< Public protection of CACHEAXIRAM configuration bits (enable, ready, divider) */
#define RCC_PUBCFGSR5_VENCRAMPUBS_Pos (11U)
#define RCC_PUBCFGSR5_VENCRAMPUBS_Msk (0x1UL << RCC_PUBCFGSR5_VENCRAMPUBS_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGSR5_VENCRAMPUBS RCC_PUBCFGSR5_VENCRAMPUBS_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
/******************* Bit definition for RCC_CCR register ********************/
#define RCC_CCR_LSIONC_Pos (0U)
#define RCC_CCR_LSIONC_Msk (0x1UL << RCC_CCR_LSIONC_Pos) /*!< 0x00000001 */
#define RCC_CCR_LSIONC RCC_CCR_LSIONC_Msk /*!< LSI oscillator enable */
#define RCC_CCR_LSEONC_Pos (1U)
#define RCC_CCR_LSEONC_Msk (0x1UL << RCC_CCR_LSEONC_Pos) /*!< 0x00000002 */
#define RCC_CCR_LSEONC RCC_CCR_LSEONC_Msk /*!< LSE oscillator enable */
#define RCC_CCR_MSIONC_Pos (2U)
#define RCC_CCR_MSIONC_Msk (0x1UL << RCC_CCR_MSIONC_Pos) /*!< 0x00000004 */
#define RCC_CCR_MSIONC RCC_CCR_MSIONC_Msk /*!< MSI oscillator enable */
#define RCC_CCR_HSIONC_Pos (3U)
#define RCC_CCR_HSIONC_Msk (0x1UL << RCC_CCR_HSIONC_Pos) /*!< 0x00000008 */
#define RCC_CCR_HSIONC RCC_CCR_HSIONC_Msk /*!< HSI oscillator enable */
#define RCC_CCR_HSEONC_Pos (4U)
#define RCC_CCR_HSEONC_Msk (0x1UL << RCC_CCR_HSEONC_Pos) /*!< 0x00000010 */
#define RCC_CCR_HSEONC RCC_CCR_HSEONC_Msk /*!< HSE oscillator enable */
#define RCC_CCR_PLL1ONC_Pos (8U)
#define RCC_CCR_PLL1ONC_Msk (0x1UL << RCC_CCR_PLL1ONC_Pos) /*!< 0x00000100 */
#define RCC_CCR_PLL1ONC RCC_CCR_PLL1ONC_Msk /*!< PLL1 oscillator enable */
#define RCC_CCR_PLL2ONC_Pos (9U)
#define RCC_CCR_PLL2ONC_Msk (0x1UL << RCC_CCR_PLL2ONC_Pos) /*!< 0x00000200 */
#define RCC_CCR_PLL2ONC RCC_CCR_PLL2ONC_Msk /*!< PLL2 oscillator enable */
#define RCC_CCR_PLL3ONC_Pos (10U)
#define RCC_CCR_PLL3ONC_Msk (0x1UL << RCC_CCR_PLL3ONC_Pos) /*!< 0x00000400 */
#define RCC_CCR_PLL3ONC RCC_CCR_PLL3ONC_Msk /*!< PLL3 oscillator enable */
#define RCC_CCR_PLL4ONC_Pos (11U)
#define RCC_CCR_PLL4ONC_Msk (0x1UL << RCC_CCR_PLL4ONC_Pos) /*!< 0x00000800 */
#define RCC_CCR_PLL4ONC RCC_CCR_PLL4ONC_Msk /*!< PLL4 oscillator enable */
/***************** Bit definition for RCC_STOPCCR register ******************/
#define RCC_STOPCCR_MSISTOPENC_Pos (0U)
#define RCC_STOPCCR_MSISTOPENC_Msk (0x1UL << RCC_STOPCCR_MSISTOPENC_Pos) /*!< 0x00000001 */
#define RCC_STOPCCR_MSISTOPENC RCC_STOPCCR_MSISTOPENC_Msk /*!< MSI oscillator enable */
#define RCC_STOPCCR_HSISTOPENC_Pos (1U)
#define RCC_STOPCCR_HSISTOPENC_Msk (0x1UL << RCC_STOPCCR_HSISTOPENC_Pos) /*!< 0x00000002 */
#define RCC_STOPCCR_HSISTOPENC RCC_STOPCCR_HSISTOPENC_Msk /*!< HSI oscillator enable */
/**************** Bit definition for RCC_MISCRSTCR register *****************/
#define RCC_MISCRSTCR_DBGRSTC_Pos (0U)
#define RCC_MISCRSTCR_DBGRSTC_Msk (0x1UL << RCC_MISCRSTCR_DBGRSTC_Pos) /*!< 0x00000001 */
#define RCC_MISCRSTCR_DBGRSTC RCC_MISCRSTCR_DBGRSTC_Msk /*!< DBG reset */
#define RCC_MISCRSTCR_XSPIPHY1RSTC_Pos (4U)
#define RCC_MISCRSTCR_XSPIPHY1RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY1RSTC_Pos) /*!< 0x00000010 */
#define RCC_MISCRSTCR_XSPIPHY1RSTC RCC_MISCRSTCR_XSPIPHY1RSTC_Msk /*!< XSPIPHY1 reset */
#define RCC_MISCRSTCR_XSPIPHY2RSTC_Pos (5U)
#define RCC_MISCRSTCR_XSPIPHY2RSTC_Msk (0x1UL << RCC_MISCRSTCR_XSPIPHY2RSTC_Pos) /*!< 0x00000020 */
#define RCC_MISCRSTCR_XSPIPHY2RSTC RCC_MISCRSTCR_XSPIPHY2RSTC_Msk /*!< XSPIPHY2 reset */
#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos (7U)
#define RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC1DLLRSTC_Pos) /*!< 0x00000080 */
#define RCC_MISCRSTCR_SDMMC1DLLRSTC RCC_MISCRSTCR_SDMMC1DLLRSTC_Msk /*!< SDMMC1DLL reset */
#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos (8U)
#define RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk (0x1UL << RCC_MISCRSTCR_SDMMC2DLLRSTC_Pos) /*!< 0x00000100 */
#define RCC_MISCRSTCR_SDMMC2DLLRSTC RCC_MISCRSTCR_SDMMC2DLLRSTC_Msk /*!< SDMMC2DLL reset */
/***************** Bit definition for RCC_MEMRSTCR register *****************/
#define RCC_MEMRSTCR_AXISRAM3RSTC_Pos (0U)
#define RCC_MEMRSTCR_AXISRAM3RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM3RSTC_Pos) /*!< 0x00000001 */
#define RCC_MEMRSTCR_AXISRAM3RSTC RCC_MEMRSTCR_AXISRAM3RSTC_Msk /*!< AXISRAM3 reset */
#define RCC_MEMRSTCR_AXISRAM4RSTC_Pos (1U)
#define RCC_MEMRSTCR_AXISRAM4RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM4RSTC_Pos) /*!< 0x00000002 */
#define RCC_MEMRSTCR_AXISRAM4RSTC RCC_MEMRSTCR_AXISRAM4RSTC_Msk /*!< AXISRAM4 reset */
#define RCC_MEMRSTCR_AXISRAM5RSTC_Pos (2U)
#define RCC_MEMRSTCR_AXISRAM5RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM5RSTC_Pos) /*!< 0x00000004 */
#define RCC_MEMRSTCR_AXISRAM5RSTC RCC_MEMRSTCR_AXISRAM5RSTC_Msk /*!< AXISRAM5 reset */
#define RCC_MEMRSTCR_AXISRAM6RSTC_Pos (3U)
#define RCC_MEMRSTCR_AXISRAM6RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM6RSTC_Pos) /*!< 0x00000008 */
#define RCC_MEMRSTCR_AXISRAM6RSTC RCC_MEMRSTCR_AXISRAM6RSTC_Msk /*!< AXISRAM6 reset */
#define RCC_MEMRSTCR_AHBSRAM1RSTC_Pos (4U)
#define RCC_MEMRSTCR_AHBSRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM1RSTC_Pos) /*!< 0x00000010 */
#define RCC_MEMRSTCR_AHBSRAM1RSTC RCC_MEMRSTCR_AHBSRAM1RSTC_Msk /*!< AHBSRAM1 reset */
#define RCC_MEMRSTCR_AHBSRAM2RSTC_Pos (5U)
#define RCC_MEMRSTCR_AHBSRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AHBSRAM2RSTC_Pos) /*!< 0x00000020 */
#define RCC_MEMRSTCR_AHBSRAM2RSTC RCC_MEMRSTCR_AHBSRAM2RSTC_Msk /*!< AHBSRAM2 reset */
#define RCC_MEMRSTCR_AXISRAM1RSTC_Pos (7U)
#define RCC_MEMRSTCR_AXISRAM1RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM1RSTC_Pos) /*!< 0x00000080 */
#define RCC_MEMRSTCR_AXISRAM1RSTC RCC_MEMRSTCR_AXISRAM1RSTC_Msk /*!< AXISRAM1 reset */
#define RCC_MEMRSTCR_AXISRAM2RSTC_Pos (8U)
#define RCC_MEMRSTCR_AXISRAM2RSTC_Msk (0x1UL << RCC_MEMRSTCR_AXISRAM2RSTC_Pos) /*!< 0x00000100 */
#define RCC_MEMRSTCR_AXISRAM2RSTC RCC_MEMRSTCR_AXISRAM2RSTC_Msk /*!< AXISRAM2 reset */
#define RCC_MEMRSTCR_FLEXRAMRSTC_Pos (9U)
#define RCC_MEMRSTCR_FLEXRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_FLEXRAMRSTC_Pos) /*!< 0x00000200 */
#define RCC_MEMRSTCR_FLEXRAMRSTC RCC_MEMRSTCR_FLEXRAMRSTC_Msk /*!< FLEXRAM reset */
#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos (10U)
#define RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_CACHEAXIRAMRSTC_Pos) /*!< 0x00000400 */
#define RCC_MEMRSTCR_CACHEAXIRAMRSTC RCC_MEMRSTCR_CACHEAXIRAMRSTC_Msk /*!< CACHEAXIRAM reset */
#define RCC_MEMRSTCR_VENCRAMRSTC_Pos (11U)
#define RCC_MEMRSTCR_VENCRAMRSTC_Msk (0x1UL << RCC_MEMRSTCR_VENCRAMRSTC_Pos) /*!< 0x00000800 */
#define RCC_MEMRSTCR_VENCRAMRSTC RCC_MEMRSTCR_VENCRAMRSTC_Msk /*!< VENCRAM reset */
#define RCC_MEMRSTCR_BOOTROMRSTC_Pos (12U)
#define RCC_MEMRSTCR_BOOTROMRSTC_Msk (0x1UL << RCC_MEMRSTCR_BOOTROMRSTC_Pos) /*!< 0x00001000 */
#define RCC_MEMRSTCR_BOOTROMRSTC RCC_MEMRSTCR_BOOTROMRSTC_Msk /*!< Boot ROM reset */
/**************** Bit definition for RCC_AHB1RSTCR register *****************/
#define RCC_AHB1RSTCR_GPDMA1RSTC_Pos (4U)
#define RCC_AHB1RSTCR_GPDMA1RSTC_Msk (0x1UL << RCC_AHB1RSTCR_GPDMA1RSTC_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTCR_GPDMA1RSTC RCC_AHB1RSTCR_GPDMA1RSTC_Msk /*!< GPDMA1 reset */
#define RCC_AHB1RSTCR_ADC12RSTC_Pos (5U)
#define RCC_AHB1RSTCR_ADC12RSTC_Msk (0x1UL << RCC_AHB1RSTCR_ADC12RSTC_Pos)/*!< 0x00000020 */
#define RCC_AHB1RSTCR_ADC12RSTC RCC_AHB1RSTCR_ADC12RSTC_Msk /*!< ADC12 reset */
/**************** Bit definition for RCC_AHB2RSTCR register *****************/
#define RCC_AHB2RSTCR_RAMCFGRSTC_Pos (12U)
#define RCC_AHB2RSTCR_RAMCFGRSTC_Msk (0x1UL << RCC_AHB2RSTCR_RAMCFGRSTC_Pos) /*!< 0x00001000 */
#define RCC_AHB2RSTCR_RAMCFGRSTC RCC_AHB2RSTCR_RAMCFGRSTC_Msk /*!< RAMCFG reset */
#define RCC_AHB2RSTCR_MDF1RSTC_Pos (16U)
#define RCC_AHB2RSTCR_MDF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_MDF1RSTC_Pos) /*!< 0x00010000 */
#define RCC_AHB2RSTCR_MDF1RSTC RCC_AHB2RSTCR_MDF1RSTC_Msk /*!< MDF1 reset */
#define RCC_AHB2RSTCR_ADF1RSTC_Pos (17U)
#define RCC_AHB2RSTCR_ADF1RSTC_Msk (0x1UL << RCC_AHB2RSTCR_ADF1RSTC_Pos) /*!< 0x00020000 */
#define RCC_AHB2RSTCR_ADF1RSTC RCC_AHB2RSTCR_ADF1RSTC_Msk /*!< ADF1 reset */
/**************** Bit definition for RCC_AHB3RSTCR register *****************/
#define RCC_AHB3RSTCR_RNGRSTC_Pos (0U)
#define RCC_AHB3RSTCR_RNGRSTC_Msk (0x1UL << RCC_AHB3RSTCR_RNGRSTC_Pos) /*!< 0x00000001 */
#define RCC_AHB3RSTCR_RNGRSTC RCC_AHB3RSTCR_RNGRSTC_Msk /*!< RNG reset */
#define RCC_AHB3RSTCR_HASHRSTC_Pos (1U)
#define RCC_AHB3RSTCR_HASHRSTC_Msk (0x1UL << RCC_AHB3RSTCR_HASHRSTC_Pos) /*!< 0x00000002 */
#define RCC_AHB3RSTCR_HASHRSTC RCC_AHB3RSTCR_HASHRSTC_Msk /*!< HASH reset */
#define RCC_AHB3RSTCR_CRYPRSTC_Pos (2U)
#define RCC_AHB3RSTCR_CRYPRSTC_Msk (0x1UL << RCC_AHB3RSTCR_CRYPRSTC_Pos) /*!< 0x00000004 */
#define RCC_AHB3RSTCR_CRYPRSTC RCC_AHB3RSTCR_CRYPRSTC_Msk /*!< CRYP reset */
#define RCC_AHB3RSTCR_SAESRSTC_Pos (4U)
#define RCC_AHB3RSTCR_SAESRSTC_Msk (0x1UL << RCC_AHB3RSTCR_SAESRSTC_Pos) /*!< 0x00000010 */
#define RCC_AHB3RSTCR_SAESRSTC RCC_AHB3RSTCR_SAESRSTC_Msk /*!< SAES reset */
#define RCC_AHB3RSTCR_PKARSTC_Pos (8U)
#define RCC_AHB3RSTCR_PKARSTC_Msk (0x1UL << RCC_AHB3RSTCR_PKARSTC_Pos) /*!< 0x00000100 */
#define RCC_AHB3RSTCR_PKARSTC RCC_AHB3RSTCR_PKARSTC_Msk /*!< PKA reset */
#define RCC_AHB3RSTCR_IACRSTC_Pos (10U)
#define RCC_AHB3RSTCR_IACRSTC_Msk (0x1UL << RCC_AHB3RSTCR_IACRSTC_Pos) /*!< 0x00000400 */
#define RCC_AHB3RSTCR_IACRSTC RCC_AHB3RSTCR_IACRSTC_Msk /*!< IAC reset */
/**************** Bit definition for RCC_AHB4RSTCR register *****************/
#define RCC_AHB4RSTCR_GPIOARSTC_Pos (0U)
#define RCC_AHB4RSTCR_GPIOARSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOARSTC_Pos)/*!< 0x00000001 */
#define RCC_AHB4RSTCR_GPIOARSTC RCC_AHB4RSTCR_GPIOARSTC_Msk /*!< GPIO A reset */
#define RCC_AHB4RSTCR_GPIOBRSTC_Pos (1U)
#define RCC_AHB4RSTCR_GPIOBRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOBRSTC_Pos)/*!< 0x00000002 */
#define RCC_AHB4RSTCR_GPIOBRSTC RCC_AHB4RSTCR_GPIOBRSTC_Msk /*!< GPIO B reset */
#define RCC_AHB4RSTCR_GPIOCRSTC_Pos (2U)
#define RCC_AHB4RSTCR_GPIOCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOCRSTC_Pos)/*!< 0x00000004 */
#define RCC_AHB4RSTCR_GPIOCRSTC RCC_AHB4RSTCR_GPIOCRSTC_Msk /*!< GPIO C reset */
#define RCC_AHB4RSTCR_GPIODRSTC_Pos (3U)
#define RCC_AHB4RSTCR_GPIODRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIODRSTC_Pos)/*!< 0x00000008 */
#define RCC_AHB4RSTCR_GPIODRSTC RCC_AHB4RSTCR_GPIODRSTC_Msk /*!< GPIO D reset */
#define RCC_AHB4RSTCR_GPIOERSTC_Pos (4U)
#define RCC_AHB4RSTCR_GPIOERSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOERSTC_Pos)/*!< 0x00000010 */
#define RCC_AHB4RSTCR_GPIOERSTC RCC_AHB4RSTCR_GPIOERSTC_Msk /*!< GPIO E reset */
#define RCC_AHB4RSTCR_GPIOFRSTC_Pos (5U)
#define RCC_AHB4RSTCR_GPIOFRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOFRSTC_Pos)/*!< 0x00000020 */
#define RCC_AHB4RSTCR_GPIOFRSTC RCC_AHB4RSTCR_GPIOFRSTC_Msk /*!< GPIO F reset */
#define RCC_AHB4RSTCR_GPIOGRSTC_Pos (6U)
#define RCC_AHB4RSTCR_GPIOGRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOGRSTC_Pos)/*!< 0x00000040 */
#define RCC_AHB4RSTCR_GPIOGRSTC RCC_AHB4RSTCR_GPIOGRSTC_Msk /*!< GPIO G reset */
#define RCC_AHB4RSTCR_GPIOHRSTC_Pos (7U)
#define RCC_AHB4RSTCR_GPIOHRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOHRSTC_Pos)/*!< 0x00000080 */
#define RCC_AHB4RSTCR_GPIOHRSTC RCC_AHB4RSTCR_GPIOHRSTC_Msk /*!< GPIO H reset */
#define RCC_AHB4RSTCR_GPIONRSTC_Pos (13U)
#define RCC_AHB4RSTCR_GPIONRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIONRSTC_Pos)/*!< 0x00002000 */
#define RCC_AHB4RSTCR_GPIONRSTC RCC_AHB4RSTCR_GPIONRSTC_Msk /*!< GPIO N reset */
#define RCC_AHB4RSTCR_GPIOORSTC_Pos (14U)
#define RCC_AHB4RSTCR_GPIOORSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOORSTC_Pos)/*!< 0x00004000 */
#define RCC_AHB4RSTCR_GPIOORSTC RCC_AHB4RSTCR_GPIOORSTC_Msk /*!< GPIO O reset */
#define RCC_AHB4RSTCR_GPIOPRSTC_Pos (15U)
#define RCC_AHB4RSTCR_GPIOPRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOPRSTC_Pos)/*!< 0x00008000 */
#define RCC_AHB4RSTCR_GPIOPRSTC RCC_AHB4RSTCR_GPIOPRSTC_Msk /*!< GPIO P reset */
#define RCC_AHB4RSTCR_GPIOQRSTC_Pos (16U)
#define RCC_AHB4RSTCR_GPIOQRSTC_Msk (0x1UL << RCC_AHB4RSTCR_GPIOQRSTC_Pos)/*!< 0x00010000 */
#define RCC_AHB4RSTCR_GPIOQRSTC RCC_AHB4RSTCR_GPIOQRSTC_Msk /*!< GPIO Q reset */
#define RCC_AHB4RSTCR_PWRRSTC_Pos (18U)
#define RCC_AHB4RSTCR_PWRRSTC_Msk (0x1UL << RCC_AHB4RSTCR_PWRRSTC_Pos) /*!< 0x00040000 */
#define RCC_AHB4RSTCR_PWRRSTC RCC_AHB4RSTCR_PWRRSTC_Msk /*!< PWR reset */
#define RCC_AHB4RSTCR_CRCRSTC_Pos (19U)
#define RCC_AHB4RSTCR_CRCRSTC_Msk (0x1UL << RCC_AHB4RSTCR_CRCRSTC_Pos) /*!< 0x00080000 */
#define RCC_AHB4RSTCR_CRCRSTC RCC_AHB4RSTCR_CRCRSTC_Msk /*!< CRC reset */
/**************** Bit definition for RCC_AHB5RSTCR register *****************/
#define RCC_AHB5RSTCR_HPDMA1RSTC_Pos (0U)
#define RCC_AHB5RSTCR_HPDMA1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_HPDMA1RSTC_Pos) /*!< 0x00000001 */
#define RCC_AHB5RSTCR_HPDMA1RSTC RCC_AHB5RSTCR_HPDMA1RSTC_Msk /*!< HPDMA1 reset */
#define RCC_AHB5RSTCR_DMA2DRSTC_Pos (1U)
#define RCC_AHB5RSTCR_DMA2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_DMA2DRSTC_Pos)/*!< 0x00000002 */
#define RCC_AHB5RSTCR_DMA2DRSTC RCC_AHB5RSTCR_DMA2DRSTC_Msk /*!< DMA2D reset */
#define RCC_AHB5RSTCR_JPEGRSTC_Pos (3U)
#define RCC_AHB5RSTCR_JPEGRSTC_Msk (0x1UL << RCC_AHB5RSTCR_JPEGRSTC_Pos) /*!< 0x00000008 */
#define RCC_AHB5RSTCR_JPEGRSTC RCC_AHB5RSTCR_JPEGRSTC_Msk /*!< JPEG reset */
#define RCC_AHB5RSTCR_FMCRSTC_Pos (4U)
#define RCC_AHB5RSTCR_FMCRSTC_Msk (0x1UL << RCC_AHB5RSTCR_FMCRSTC_Pos) /*!< 0x00000010 */
#define RCC_AHB5RSTCR_FMCRSTC RCC_AHB5RSTCR_FMCRSTC_Msk /*!< FMC reset */
#define RCC_AHB5RSTCR_XSPI1RSTC_Pos (5U)
#define RCC_AHB5RSTCR_XSPI1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI1RSTC_Pos)/*!< 0x00000020 */
#define RCC_AHB5RSTCR_XSPI1RSTC RCC_AHB5RSTCR_XSPI1RSTC_Msk /*!< XSPI1 reset */
#define RCC_AHB5RSTCR_PSSIRSTC_Pos (6U)
#define RCC_AHB5RSTCR_PSSIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_PSSIRSTC_Pos) /*!< 0x00000040 */
#define RCC_AHB5RSTCR_PSSIRSTC RCC_AHB5RSTCR_PSSIRSTC_Msk /*!< PSSI reset */
#define RCC_AHB5RSTCR_SDMMC2RSTC_Pos (7U)
#define RCC_AHB5RSTCR_SDMMC2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC2RSTC_Pos) /*!< 0x00000080 */
#define RCC_AHB5RSTCR_SDMMC2RSTC RCC_AHB5RSTCR_SDMMC2RSTC_Msk /*!< SDMMC2 reset */
#define RCC_AHB5RSTCR_SDMMC1RSTC_Pos (8U)
#define RCC_AHB5RSTCR_SDMMC1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_SDMMC1RSTC_Pos) /*!< 0x00000100 */
#define RCC_AHB5RSTCR_SDMMC1RSTC RCC_AHB5RSTCR_SDMMC1RSTC_Msk /*!< SDMMC1 reset */
#define RCC_AHB5RSTCR_XSPI2RSTC_Pos (12U)
#define RCC_AHB5RSTCR_XSPI2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI2RSTC_Pos)/*!< 0x00001000 */
#define RCC_AHB5RSTCR_XSPI2RSTC RCC_AHB5RSTCR_XSPI2RSTC_Msk /*!< XSPI2 reset */
#define RCC_AHB5RSTCR_XSPIMRSTC_Pos (13U)
#define RCC_AHB5RSTCR_XSPIMRSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPIMRSTC_Pos)/*!< 0x00002000 */
#define RCC_AHB5RSTCR_XSPIMRSTC RCC_AHB5RSTCR_XSPIMRSTC_Msk /*!< XSPIM reset */
#define RCC_AHB5RSTCR_XSPI3RSTC_Pos (17U)
#define RCC_AHB5RSTCR_XSPI3RSTC_Msk (0x1UL << RCC_AHB5RSTCR_XSPI3RSTC_Pos)/*!< 0x00020000 */
#define RCC_AHB5RSTCR_XSPI3RSTC RCC_AHB5RSTCR_XSPI3RSTC_Msk /*!< XSPI3 reset */
#define RCC_AHB5RSTCR_GFXMMURSTC_Pos (19U)
#define RCC_AHB5RSTCR_GFXMMURSTC_Msk (0x1UL << RCC_AHB5RSTCR_GFXMMURSTC_Pos) /*!< 0x00080000 */
#define RCC_AHB5RSTCR_GFXMMURSTC RCC_AHB5RSTCR_GFXMMURSTC_Msk /*!< GFXMMU reset */
#define RCC_AHB5RSTCR_GPU2DRSTC_Pos (20U)
#define RCC_AHB5RSTCR_GPU2DRSTC_Msk (0x1UL << RCC_AHB5RSTCR_GPU2DRSTC_Pos)/*!< 0x00100000 */
#define RCC_AHB5RSTCR_GPU2DRSTC RCC_AHB5RSTCR_GPU2DRSTC_Msk /*!< GPU2D reset */
#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos (23U)
#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Pos) /*!< 0x00800000 */
#define RCC_AHB5RSTCR_OTG1PHYCTLRSTC RCC_AHB5RSTCR_OTG1PHYCTLRSTC_Msk /*!< OTG1PHYCTL reset */
#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos (24U)
#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Pos) /*!< 0x01000000 */
#define RCC_AHB5RSTCR_OTG2PHYCTLRSTC RCC_AHB5RSTCR_OTG2PHYCTLRSTC_Msk /*!< OTG2PHYCTL reset */
#define RCC_AHB5RSTCR_ETH1RSTC_Pos (25U)
#define RCC_AHB5RSTCR_ETH1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_ETH1RSTC_Pos) /*!< 0x02000000 */
#define RCC_AHB5RSTCR_ETH1RSTC RCC_AHB5RSTCR_ETH1RSTC_Msk /*!< ETH1 reset */
#define RCC_AHB5RSTCR_OTG1RSTC_Pos (26U)
#define RCC_AHB5RSTCR_OTG1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG1RSTC_Pos) /*!< 0x04000000 */
#define RCC_AHB5RSTCR_OTG1RSTC RCC_AHB5RSTCR_OTG1RSTC_Msk /*!< OTG1 reset */
#define RCC_AHB5RSTCR_OTGPHY1RSTC_Pos (27U)
#define RCC_AHB5RSTCR_OTGPHY1RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY1RSTC_Pos) /*!< 0x08000000 */
#define RCC_AHB5RSTCR_OTGPHY1RSTC RCC_AHB5RSTCR_OTGPHY1RSTC_Msk /*!< OTGPHY1 reset */
#define RCC_AHB5RSTCR_OTGPHY2RSTC_Pos (28U)
#define RCC_AHB5RSTCR_OTGPHY2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTGPHY2RSTC_Pos) /*!< 0x10000000 */
#define RCC_AHB5RSTCR_OTGPHY2RSTC RCC_AHB5RSTCR_OTGPHY2RSTC_Msk /*!< OTGPHY2 reset */
#define RCC_AHB5RSTCR_OTG2RSTC_Pos (29U)
#define RCC_AHB5RSTCR_OTG2RSTC_Msk (0x1UL << RCC_AHB5RSTCR_OTG2RSTC_Pos) /*!< 0x20000000 */
#define RCC_AHB5RSTCR_OTG2RSTC RCC_AHB5RSTCR_OTG2RSTC_Msk /*!< OTG2 reset */
#define RCC_AHB5RSTCR_CACHEAXIRSTC_Pos (30U)
#define RCC_AHB5RSTCR_CACHEAXIRSTC_Msk (0x1UL << RCC_AHB5RSTCR_CACHEAXIRSTC_Pos) /*!< 0x40000000 */
#define RCC_AHB5RSTCR_CACHEAXIRSTC RCC_AHB5RSTCR_CACHEAXIRSTC_Msk /*!< CACHEAXI reset */
#define RCC_AHB5RSTCR_NPURSTC_Pos (31U)
#define RCC_AHB5RSTCR_NPURSTC_Msk (0x1UL << RCC_AHB5RSTCR_NPURSTC_Pos) /*!< 0x80000000 */
#define RCC_AHB5RSTCR_NPURSTC RCC_AHB5RSTCR_NPURSTC_Msk /*!< NPU reset */
/**************** Bit definition for RCC_APB1RSTCR1 register ****************/
#define RCC_APB1RSTCR1_TIM2RSTC_Pos (0U)
#define RCC_APB1RSTCR1_TIM2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM2RSTC_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTCR1_TIM2RSTC RCC_APB1RSTCR1_TIM2RSTC_Msk /*!< TIM2 reset */
#define RCC_APB1RSTCR1_TIM3RSTC_Pos (1U)
#define RCC_APB1RSTCR1_TIM3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM3RSTC_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTCR1_TIM3RSTC RCC_APB1RSTCR1_TIM3RSTC_Msk /*!< TIM3 reset */
#define RCC_APB1RSTCR1_TIM4RSTC_Pos (2U)
#define RCC_APB1RSTCR1_TIM4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM4RSTC_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTCR1_TIM4RSTC RCC_APB1RSTCR1_TIM4RSTC_Msk /*!< TIM4 reset */
#define RCC_APB1RSTCR1_TIM5RSTC_Pos (3U)
#define RCC_APB1RSTCR1_TIM5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM5RSTC_Pos)/*!< 0x00000008 */
#define RCC_APB1RSTCR1_TIM5RSTC RCC_APB1RSTCR1_TIM5RSTC_Msk /*!< TIM5 reset */
#define RCC_APB1RSTCR1_TIM6RSTC_Pos (4U)
#define RCC_APB1RSTCR1_TIM6RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM6RSTC_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTCR1_TIM6RSTC RCC_APB1RSTCR1_TIM6RSTC_Msk /*!< TIM6 reset */
#define RCC_APB1RSTCR1_TIM7RSTC_Pos (5U)
#define RCC_APB1RSTCR1_TIM7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM7RSTC_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTCR1_TIM7RSTC RCC_APB1RSTCR1_TIM7RSTC_Msk /*!< TIM7 reset */
#define RCC_APB1RSTCR1_TIM12RSTC_Pos (6U)
#define RCC_APB1RSTCR1_TIM12RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM12RSTC_Pos) /*!< 0x00000040 */
#define RCC_APB1RSTCR1_TIM12RSTC RCC_APB1RSTCR1_TIM12RSTC_Msk /*!< TIM12 reset */
#define RCC_APB1RSTCR1_TIM13RSTC_Pos (7U)
#define RCC_APB1RSTCR1_TIM13RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM13RSTC_Pos) /*!< 0x00000080 */
#define RCC_APB1RSTCR1_TIM13RSTC RCC_APB1RSTCR1_TIM13RSTC_Msk /*!< TIM13 reset */
#define RCC_APB1RSTCR1_TIM14RSTC_Pos (8U)
#define RCC_APB1RSTCR1_TIM14RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM14RSTC_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTCR1_TIM14RSTC RCC_APB1RSTCR1_TIM14RSTC_Msk /*!< TIM14 reset */
#define RCC_APB1RSTCR1_LPTIM1RSTC_Pos (9U)
#define RCC_APB1RSTCR1_LPTIM1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_LPTIM1RSTC_Pos) /*!< 0x00000200 */
#define RCC_APB1RSTCR1_LPTIM1RSTC RCC_APB1RSTCR1_LPTIM1RSTC_Msk /*!< LPTIM1 reset */
#define RCC_APB1RSTCR1_WWDGRSTC_Pos (11U)
#define RCC_APB1RSTCR1_WWDGRSTC_Msk (0x1UL << RCC_APB1RSTCR1_WWDGRSTC_Pos)/*!< 0x00000800 */
#define RCC_APB1RSTCR1_WWDGRSTC RCC_APB1RSTCR1_WWDGRSTC_Msk /*!< WWDG reset */
#define RCC_APB1RSTCR1_TIM10RSTC_Pos (12U)
#define RCC_APB1RSTCR1_TIM10RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM10RSTC_Pos) /*!< 0x00001000 */
#define RCC_APB1RSTCR1_TIM10RSTC RCC_APB1RSTCR1_TIM10RSTC_Msk /*!< TIM10 reset */
#define RCC_APB1RSTCR1_TIM11RSTC_Pos (13U)
#define RCC_APB1RSTCR1_TIM11RSTC_Msk (0x1UL << RCC_APB1RSTCR1_TIM11RSTC_Pos) /*!< 0x00002000 */
#define RCC_APB1RSTCR1_TIM11RSTC RCC_APB1RSTCR1_TIM11RSTC_Msk /*!< TIM11 reset */
#define RCC_APB1RSTCR1_SPI2RSTC_Pos (14U)
#define RCC_APB1RSTCR1_SPI2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI2RSTC_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTCR1_SPI2RSTC RCC_APB1RSTCR1_SPI2RSTC_Msk /*!< SPI2 reset */
#define RCC_APB1RSTCR1_SPI3RSTC_Pos (15U)
#define RCC_APB1RSTCR1_SPI3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPI3RSTC_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTCR1_SPI3RSTC RCC_APB1RSTCR1_SPI3RSTC_Msk /*!< SPI3 reset */
#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos (16U)
#define RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_SPDIFRX1RSTC_Pos) /*!< 0x00010000 */
#define RCC_APB1RSTCR1_SPDIFRX1RSTC RCC_APB1RSTCR1_SPDIFRX1RSTC_Msk /*!< SPDIFRX1 reset */
#define RCC_APB1RSTCR1_USART2RSTC_Pos (17U)
#define RCC_APB1RSTCR1_USART2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART2RSTC_Pos) /*!< 0x00020000 */
#define RCC_APB1RSTCR1_USART2RSTC RCC_APB1RSTCR1_USART2RSTC_Msk /*!< USART2 reset */
#define RCC_APB1RSTCR1_USART3RSTC_Pos (18U)
#define RCC_APB1RSTCR1_USART3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_USART3RSTC_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTCR1_USART3RSTC RCC_APB1RSTCR1_USART3RSTC_Msk /*!< USART3 reset */
#define RCC_APB1RSTCR1_UART4RSTC_Pos (19U)
#define RCC_APB1RSTCR1_UART4RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART4RSTC_Pos) /*!< 0x00080000 */
#define RCC_APB1RSTCR1_UART4RSTC RCC_APB1RSTCR1_UART4RSTC_Msk /*!< UART4 reset */
#define RCC_APB1RSTCR1_UART5RSTC_Pos (20U)
#define RCC_APB1RSTCR1_UART5RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART5RSTC_Pos) /*!< 0x00100000 */
#define RCC_APB1RSTCR1_UART5RSTC RCC_APB1RSTCR1_UART5RSTC_Msk /*!< UART5 reset */
#define RCC_APB1RSTCR1_I2C1RSTC_Pos (21U)
#define RCC_APB1RSTCR1_I2C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C1RSTC_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTCR1_I2C1RSTC RCC_APB1RSTCR1_I2C1RSTC_Msk /*!< I2C1 reset */
#define RCC_APB1RSTCR1_I2C2RSTC_Pos (22U)
#define RCC_APB1RSTCR1_I2C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C2RSTC_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTCR1_I2C2RSTC RCC_APB1RSTCR1_I2C2RSTC_Msk /*!< I2C2 reset */
#define RCC_APB1RSTCR1_I2C3RSTC_Pos (23U)
#define RCC_APB1RSTCR1_I2C3RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I2C3RSTC_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTCR1_I2C3RSTC RCC_APB1RSTCR1_I2C3RSTC_Msk /*!< I2C3 reset */
#define RCC_APB1RSTCR1_I3C1RSTC_Pos (24U)
#define RCC_APB1RSTCR1_I3C1RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C1RSTC_Pos)/*!< 0x01000000 */
#define RCC_APB1RSTCR1_I3C1RSTC RCC_APB1RSTCR1_I3C1RSTC_Msk /*!< I3C1 reset */
#define RCC_APB1RSTCR1_I3C2RSTC_Pos (25U)
#define RCC_APB1RSTCR1_I3C2RSTC_Msk (0x1UL << RCC_APB1RSTCR1_I3C2RSTC_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTCR1_I3C2RSTC RCC_APB1RSTCR1_I3C2RSTC_Msk /*!< I3C2 reset */
#define RCC_APB1RSTCR1_UART7RSTC_Pos (30U)
#define RCC_APB1RSTCR1_UART7RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART7RSTC_Pos) /*!< 0x40000000 */
#define RCC_APB1RSTCR1_UART7RSTC RCC_APB1RSTCR1_UART7RSTC_Msk /*!< UART7 reset */
#define RCC_APB1RSTCR1_UART8RSTC_Pos (31U)
#define RCC_APB1RSTCR1_UART8RSTC_Msk (0x1UL << RCC_APB1RSTCR1_UART8RSTC_Pos) /*!< 0x80000000 */
#define RCC_APB1RSTCR1_UART8RSTC RCC_APB1RSTCR1_UART8RSTC_Msk /*!< UART8 reset */
/**************** Bit definition for RCC_APB1RSTCR2 register ****************/
#define RCC_APB1RSTCR2_MDIOSRSTC_Pos (5U)
#define RCC_APB1RSTCR2_MDIOSRSTC_Msk (0x1UL << RCC_APB1RSTCR2_MDIOSRSTC_Pos) /*!< 0x00000020 */
#define RCC_APB1RSTCR2_MDIOSRSTC RCC_APB1RSTCR2_MDIOSRSTC_Msk /*!< MDIOS reset */
#define RCC_APB1RSTCR2_FDCANRSTC_Pos (8U)
#define RCC_APB1RSTCR2_FDCANRSTC_Msk (0x1UL << RCC_APB1RSTCR2_FDCANRSTC_Pos) /*!< 0x00000100 */
#define RCC_APB1RSTCR2_FDCANRSTC RCC_APB1RSTCR2_FDCANRSTC_Msk /*!< FDCAN reset */
#define RCC_APB1RSTCR2_UCPD1RSTC_Pos (18U)
#define RCC_APB1RSTCR2_UCPD1RSTC_Msk (0x1UL << RCC_APB1RSTCR2_UCPD1RSTC_Pos) /*!< 0x00040000 */
#define RCC_APB1RSTCR2_UCPD1RSTC RCC_APB1RSTCR2_UCPD1RSTC_Msk /*!< UCPD1 reset */
/**************** Bit definition for RCC_APB2RSTCR register *****************/
#define RCC_APB2RSTCR_TIM1RSTC_Pos (0U)
#define RCC_APB2RSTCR_TIM1RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM1RSTC_Pos) /*!< 0x00000001 */
#define RCC_APB2RSTCR_TIM1RSTC RCC_APB2RSTCR_TIM1RSTC_Msk /*!< TIM1 reset */
#define RCC_APB2RSTCR_TIM8RSTC_Pos (1U)
#define RCC_APB2RSTCR_TIM8RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM8RSTC_Pos) /*!< 0x00000002 */
#define RCC_APB2RSTCR_TIM8RSTC RCC_APB2RSTCR_TIM8RSTC_Msk /*!< TIM8 reset */
#define RCC_APB2RSTCR_USART1RSTC_Pos (4U)
#define RCC_APB2RSTCR_USART1RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART1RSTC_Pos) /*!< 0x00000010 */
#define RCC_APB2RSTCR_USART1RSTC RCC_APB2RSTCR_USART1RSTC_Msk /*!< USART1 reset */
#define RCC_APB2RSTCR_USART6RSTC_Pos (5U)
#define RCC_APB2RSTCR_USART6RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART6RSTC_Pos) /*!< 0x00000020 */
#define RCC_APB2RSTCR_USART6RSTC RCC_APB2RSTCR_USART6RSTC_Msk /*!< USART6 reset */
#define RCC_APB2RSTCR_UART9RSTC_Pos (6U)
#define RCC_APB2RSTCR_UART9RSTC_Msk (0x1UL << RCC_APB2RSTCR_UART9RSTC_Pos)/*!< 0x00000040 */
#define RCC_APB2RSTCR_UART9RSTC RCC_APB2RSTCR_UART9RSTC_Msk /*!< UART9 reset */
#define RCC_APB2RSTCR_USART10RSTC_Pos (7U)
#define RCC_APB2RSTCR_USART10RSTC_Msk (0x1UL << RCC_APB2RSTCR_USART10RSTC_Pos) /*!< 0x00000080 */
#define RCC_APB2RSTCR_USART10RSTC RCC_APB2RSTCR_USART10RSTC_Msk /*!< USART10 reset */
#define RCC_APB2RSTCR_SPI1RSTC_Pos (12U)
#define RCC_APB2RSTCR_SPI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI1RSTC_Pos) /*!< 0x00001000 */
#define RCC_APB2RSTCR_SPI1RSTC RCC_APB2RSTCR_SPI1RSTC_Msk /*!< SPI1 reset */
#define RCC_APB2RSTCR_SPI4RSTC_Pos (13U)
#define RCC_APB2RSTCR_SPI4RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI4RSTC_Pos) /*!< 0x00002000 */
#define RCC_APB2RSTCR_SPI4RSTC RCC_APB2RSTCR_SPI4RSTC_Msk /*!< SPI4 reset */
#define RCC_APB2RSTCR_TIM18RSTC_Pos (15U)
#define RCC_APB2RSTCR_TIM18RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM18RSTC_Pos)/*!< 0x00008000 */
#define RCC_APB2RSTCR_TIM18RSTC RCC_APB2RSTCR_TIM18RSTC_Msk /*!< TIM18 reset */
#define RCC_APB2RSTCR_TIM15RSTC_Pos (16U)
#define RCC_APB2RSTCR_TIM15RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM15RSTC_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTCR_TIM15RSTC RCC_APB2RSTCR_TIM15RSTC_Msk /*!< TIM15 reset */
#define RCC_APB2RSTCR_TIM16RSTC_Pos (17U)
#define RCC_APB2RSTCR_TIM16RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM16RSTC_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTCR_TIM16RSTC RCC_APB2RSTCR_TIM16RSTC_Msk /*!< TIM16 reset */
#define RCC_APB2RSTCR_TIM17RSTC_Pos (18U)
#define RCC_APB2RSTCR_TIM17RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM17RSTC_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTCR_TIM17RSTC RCC_APB2RSTCR_TIM17RSTC_Msk /*!< TIM17 reset */
#define RCC_APB2RSTCR_TIM9RSTC_Pos (19U)
#define RCC_APB2RSTCR_TIM9RSTC_Msk (0x1UL << RCC_APB2RSTCR_TIM9RSTC_Pos) /*!< 0x00080000 */
#define RCC_APB2RSTCR_TIM9RSTC RCC_APB2RSTCR_TIM9RSTC_Msk /*!< TIM9 reset */
#define RCC_APB2RSTCR_SPI5RSTC_Pos (20U)
#define RCC_APB2RSTCR_SPI5RSTC_Msk (0x1UL << RCC_APB2RSTCR_SPI5RSTC_Pos) /*!< 0x00100000 */
#define RCC_APB2RSTCR_SPI5RSTC RCC_APB2RSTCR_SPI5RSTC_Msk /*!< SPI5 reset */
#define RCC_APB2RSTCR_SAI1RSTC_Pos (21U)
#define RCC_APB2RSTCR_SAI1RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI1RSTC_Pos) /*!< 0x00200000 */
#define RCC_APB2RSTCR_SAI1RSTC RCC_APB2RSTCR_SAI1RSTC_Msk /*!< SAI1 reset */
#define RCC_APB2RSTCR_SAI2RSTC_Pos (22U)
#define RCC_APB2RSTCR_SAI2RSTC_Msk (0x1UL << RCC_APB2RSTCR_SAI2RSTC_Pos) /*!< 0x00400000 */
#define RCC_APB2RSTCR_SAI2RSTC RCC_APB2RSTCR_SAI2RSTC_Msk /*!< SAI2 reset */
/**************** Bit definition for RCC_APB4RSTCR1 register ****************/
#define RCC_APB4RSTCR1_HDPRSTC_Pos (2U)
#define RCC_APB4RSTCR1_HDPRSTC_Msk (0x1UL << RCC_APB4RSTCR1_HDPRSTC_Pos) /*!< 0x00000004 */
#define RCC_APB4RSTCR1_HDPRSTC RCC_APB4RSTCR1_HDPRSTC_Msk /*!< HDP reset */
#define RCC_APB4RSTCR1_LPUART1RSTC_Pos (3U)
#define RCC_APB4RSTCR1_LPUART1RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPUART1RSTC_Pos) /*!< 0x00000008 */
#define RCC_APB4RSTCR1_LPUART1RSTC RCC_APB4RSTCR1_LPUART1RSTC_Msk /*!< LPUART1 reset */
#define RCC_APB4RSTCR1_SPI6RSTC_Pos (5U)
#define RCC_APB4RSTCR1_SPI6RSTC_Msk (0x1UL << RCC_APB4RSTCR1_SPI6RSTC_Pos)/*!< 0x00000020 */
#define RCC_APB4RSTCR1_SPI6RSTC RCC_APB4RSTCR1_SPI6RSTC_Msk /*!< SPI6 reset */
#define RCC_APB4RSTCR1_I2C4RSTC_Pos (7U)
#define RCC_APB4RSTCR1_I2C4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_I2C4RSTC_Pos)/*!< 0x00000080 */
#define RCC_APB4RSTCR1_I2C4RSTC RCC_APB4RSTCR1_I2C4RSTC_Msk /*!< I2C4 reset */
#define RCC_APB4RSTCR1_LPTIM2RSTC_Pos (9U)
#define RCC_APB4RSTCR1_LPTIM2RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM2RSTC_Pos) /*!< 0x00000200 */
#define RCC_APB4RSTCR1_LPTIM2RSTC RCC_APB4RSTCR1_LPTIM2RSTC_Msk /*!< LPTIM2 reset */
#define RCC_APB4RSTCR1_LPTIM3RSTC_Pos (10U)
#define RCC_APB4RSTCR1_LPTIM3RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM3RSTC_Pos) /*!< 0x00000400 */
#define RCC_APB4RSTCR1_LPTIM3RSTC RCC_APB4RSTCR1_LPTIM3RSTC_Msk /*!< LPTIM3 reset */
#define RCC_APB4RSTCR1_LPTIM4RSTC_Pos (11U)
#define RCC_APB4RSTCR1_LPTIM4RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM4RSTC_Pos) /*!< 0x00000800 */
#define RCC_APB4RSTCR1_LPTIM4RSTC RCC_APB4RSTCR1_LPTIM4RSTC_Msk /*!< LPTIM4 reset */
#define RCC_APB4RSTCR1_LPTIM5RSTC_Pos (12U)
#define RCC_APB4RSTCR1_LPTIM5RSTC_Msk (0x1UL << RCC_APB4RSTCR1_LPTIM5RSTC_Pos) /*!< 0x00001000 */
#define RCC_APB4RSTCR1_LPTIM5RSTC RCC_APB4RSTCR1_LPTIM5RSTC_Msk /*!< LPTIM5 reset */
#define RCC_APB4RSTCR1_VREFBUFRSTC_Pos (15U)
#define RCC_APB4RSTCR1_VREFBUFRSTC_Msk (0x1UL << RCC_APB4RSTCR1_VREFBUFRSTC_Pos) /*!< 0x00008000 */
#define RCC_APB4RSTCR1_VREFBUFRSTC RCC_APB4RSTCR1_VREFBUFRSTC_Msk /*!< VREFBUF reset */
#define RCC_APB4RSTCR1_RTCRSTC_Pos (16U)
#define RCC_APB4RSTCR1_RTCRSTC_Msk (0x1UL << RCC_APB4RSTCR1_RTCRSTC_Pos) /*!< 0x00010000 */
#define RCC_APB4RSTCR1_RTCRSTC RCC_APB4RSTCR1_RTCRSTC_Msk /*!< RTC reset */
/**************** Bit definition for RCC_APB4RSTCR2 register ****************/
#define RCC_APB4RSTCR2_SYSCFGRSTC_Pos (0U)
#define RCC_APB4RSTCR2_SYSCFGRSTC_Msk (0x1UL << RCC_APB4RSTCR2_SYSCFGRSTC_Pos) /*!< 0x00000001 */
#define RCC_APB4RSTCR2_SYSCFGRSTC RCC_APB4RSTCR2_SYSCFGRSTC_Msk /*!< SYSCFG reset */
#define RCC_APB4RSTCR2_DTSRSTC_Pos (2U)
#define RCC_APB4RSTCR2_DTSRSTC_Msk (0x1UL << RCC_APB4RSTCR2_DTSRSTC_Pos) /*!< 0x00000004 */
#define RCC_APB4RSTCR2_DTSRSTC RCC_APB4RSTCR2_DTSRSTC_Msk /*!< DTS reset */
/**************** Bit definition for RCC_APB5RSTCR register *****************/
#define RCC_APB5RSTCR_LTDCRSTC_Pos (1U)
#define RCC_APB5RSTCR_LTDCRSTC_Msk (0x1UL << RCC_APB5RSTCR_LTDCRSTC_Pos) /*!< 0x00000002 */
#define RCC_APB5RSTCR_LTDCRSTC RCC_APB5RSTCR_LTDCRSTC_Msk /*!< LTDC reset */
#define RCC_APB5RSTCR_DCMIPPRSTC_Pos (2U)
#define RCC_APB5RSTCR_DCMIPPRSTC_Msk (0x1UL << RCC_APB5RSTCR_DCMIPPRSTC_Pos) /*!< 0x00000004 */
#define RCC_APB5RSTCR_DCMIPPRSTC RCC_APB5RSTCR_DCMIPPRSTC_Msk /*!< DCMIPP reset */
#define RCC_APB5RSTCR_GFXTIMRSTC_Pos (4U)
#define RCC_APB5RSTCR_GFXTIMRSTC_Msk (0x1UL << RCC_APB5RSTCR_GFXTIMRSTC_Pos) /*!< 0x00000010 */
#define RCC_APB5RSTCR_GFXTIMRSTC RCC_APB5RSTCR_GFXTIMRSTC_Msk /*!< GFXTIM reset */
#define RCC_APB5RSTCR_VENCRSTC_Pos (5U)
#define RCC_APB5RSTCR_VENCRSTC_Msk (0x1UL << RCC_APB5RSTCR_VENCRSTC_Pos) /*!< 0x00000020 */
#define RCC_APB5RSTCR_VENCRSTC RCC_APB5RSTCR_VENCRSTC_Msk /*!< VENC reset */
#define RCC_APB5RSTCR_CSIRSTC_Pos (6U)
#define RCC_APB5RSTCR_CSIRSTC_Msk (0x1UL << RCC_APB5RSTCR_CSIRSTC_Pos) /*!< 0x00000040 */
#define RCC_APB5RSTCR_CSIRSTC RCC_APB5RSTCR_CSIRSTC_Msk /*!< CSI reset */
/***************** Bit definition for RCC_DIVENCR register ******************/
#define RCC_DIVENCR_IC1ENC_Pos (0U)
#define RCC_DIVENCR_IC1ENC_Msk (0x1UL << RCC_DIVENCR_IC1ENC_Pos) /*!< 0x00000001 */
#define RCC_DIVENCR_IC1ENC RCC_DIVENCR_IC1ENC_Msk /*!< IC1 enable */
#define RCC_DIVENCR_IC2ENC_Pos (1U)
#define RCC_DIVENCR_IC2ENC_Msk (0x1UL << RCC_DIVENCR_IC2ENC_Pos) /*!< 0x00000002 */
#define RCC_DIVENCR_IC2ENC RCC_DIVENCR_IC2ENC_Msk /*!< IC2 enable */
#define RCC_DIVENCR_IC3ENC_Pos (2U)
#define RCC_DIVENCR_IC3ENC_Msk (0x1UL << RCC_DIVENCR_IC3ENC_Pos) /*!< 0x00000004 */
#define RCC_DIVENCR_IC3ENC RCC_DIVENCR_IC3ENC_Msk /*!< IC3 enable */
#define RCC_DIVENCR_IC4ENC_Pos (3U)
#define RCC_DIVENCR_IC4ENC_Msk (0x1UL << RCC_DIVENCR_IC4ENC_Pos) /*!< 0x00000008 */
#define RCC_DIVENCR_IC4ENC RCC_DIVENCR_IC4ENC_Msk /*!< IC4 enable */
#define RCC_DIVENCR_IC5ENC_Pos (4U)
#define RCC_DIVENCR_IC5ENC_Msk (0x1UL << RCC_DIVENCR_IC5ENC_Pos) /*!< 0x00000010 */
#define RCC_DIVENCR_IC5ENC RCC_DIVENCR_IC5ENC_Msk /*!< IC5 enable */
#define RCC_DIVENCR_IC6ENC_Pos (5U)
#define RCC_DIVENCR_IC6ENC_Msk (0x1UL << RCC_DIVENCR_IC6ENC_Pos) /*!< 0x00000020 */
#define RCC_DIVENCR_IC6ENC RCC_DIVENCR_IC6ENC_Msk /*!< IC6 enable */
#define RCC_DIVENCR_IC7ENC_Pos (6U)
#define RCC_DIVENCR_IC7ENC_Msk (0x1UL << RCC_DIVENCR_IC7ENC_Pos) /*!< 0x00000040 */
#define RCC_DIVENCR_IC7ENC RCC_DIVENCR_IC7ENC_Msk /*!< IC7 enable */
#define RCC_DIVENCR_IC8ENC_Pos (7U)
#define RCC_DIVENCR_IC8ENC_Msk (0x1UL << RCC_DIVENCR_IC8ENC_Pos) /*!< 0x00000080 */
#define RCC_DIVENCR_IC8ENC RCC_DIVENCR_IC8ENC_Msk /*!< IC8 enable */
#define RCC_DIVENCR_IC9ENC_Pos (8U)
#define RCC_DIVENCR_IC9ENC_Msk (0x1UL << RCC_DIVENCR_IC9ENC_Pos) /*!< 0x00000100 */
#define RCC_DIVENCR_IC9ENC RCC_DIVENCR_IC9ENC_Msk /*!< IC9 enable */
#define RCC_DIVENCR_IC10ENC_Pos (9U)
#define RCC_DIVENCR_IC10ENC_Msk (0x1UL << RCC_DIVENCR_IC10ENC_Pos) /*!< 0x00000200 */
#define RCC_DIVENCR_IC10ENC RCC_DIVENCR_IC10ENC_Msk /*!< IC10 enable */
#define RCC_DIVENCR_IC11ENC_Pos (10U)
#define RCC_DIVENCR_IC11ENC_Msk (0x1UL << RCC_DIVENCR_IC11ENC_Pos) /*!< 0x00000400 */
#define RCC_DIVENCR_IC11ENC RCC_DIVENCR_IC11ENC_Msk /*!< IC11 enable */
#define RCC_DIVENCR_IC12ENC_Pos (11U)
#define RCC_DIVENCR_IC12ENC_Msk (0x1UL << RCC_DIVENCR_IC12ENC_Pos) /*!< 0x00000800 */
#define RCC_DIVENCR_IC12ENC RCC_DIVENCR_IC12ENC_Msk /*!< IC12 enable */
#define RCC_DIVENCR_IC13ENC_Pos (12U)
#define RCC_DIVENCR_IC13ENC_Msk (0x1UL << RCC_DIVENCR_IC13ENC_Pos) /*!< 0x00001000 */
#define RCC_DIVENCR_IC13ENC RCC_DIVENCR_IC13ENC_Msk /*!< IC13 enable */
#define RCC_DIVENCR_IC14ENC_Pos (13U)
#define RCC_DIVENCR_IC14ENC_Msk (0x1UL << RCC_DIVENCR_IC14ENC_Pos) /*!< 0x00002000 */
#define RCC_DIVENCR_IC14ENC RCC_DIVENCR_IC14ENC_Msk /*!< IC14 enable */
#define RCC_DIVENCR_IC15ENC_Pos (14U)
#define RCC_DIVENCR_IC15ENC_Msk (0x1UL << RCC_DIVENCR_IC15ENC_Pos) /*!< 0x00004000 */
#define RCC_DIVENCR_IC15ENC RCC_DIVENCR_IC15ENC_Msk /*!< IC15 enable */
#define RCC_DIVENCR_IC16ENC_Pos (15U)
#define RCC_DIVENCR_IC16ENC_Msk (0x1UL << RCC_DIVENCR_IC16ENC_Pos) /*!< 0x00008000 */
#define RCC_DIVENCR_IC16ENC RCC_DIVENCR_IC16ENC_Msk /*!< IC16 enable */
#define RCC_DIVENCR_IC17ENC_Pos (16U)
#define RCC_DIVENCR_IC17ENC_Msk (0x1UL << RCC_DIVENCR_IC17ENC_Pos) /*!< 0x00010000 */
#define RCC_DIVENCR_IC17ENC RCC_DIVENCR_IC17ENC_Msk /*!< IC17 enable */
#define RCC_DIVENCR_IC18ENC_Pos (17U)
#define RCC_DIVENCR_IC18ENC_Msk (0x1UL << RCC_DIVENCR_IC18ENC_Pos) /*!< 0x00020000 */
#define RCC_DIVENCR_IC18ENC RCC_DIVENCR_IC18ENC_Msk /*!< IC18 enable */
#define RCC_DIVENCR_IC19ENC_Pos (18U)
#define RCC_DIVENCR_IC19ENC_Msk (0x1UL << RCC_DIVENCR_IC19ENC_Pos) /*!< 0x00040000 */
#define RCC_DIVENCR_IC19ENC RCC_DIVENCR_IC19ENC_Msk /*!< IC19 enable */
#define RCC_DIVENCR_IC20ENC_Pos (19U)
#define RCC_DIVENCR_IC20ENC_Msk (0x1UL << RCC_DIVENCR_IC20ENC_Pos) /*!< 0x00080000 */
#define RCC_DIVENCR_IC20ENC RCC_DIVENCR_IC20ENC_Msk /*!< IC20 enable */
/***************** Bit definition for RCC_BUSENCR register ******************/
#define RCC_BUSENCR_ACLKNENC_Pos (0U)
#define RCC_BUSENCR_ACLKNENC_Msk (0x1UL << RCC_BUSENCR_ACLKNENC_Pos) /*!< 0x00000001 */
#define RCC_BUSENCR_ACLKNENC RCC_BUSENCR_ACLKNENC_Msk /*!< ACLKN enable */
#define RCC_BUSENCR_ACLKNCENC_Pos (1U)
#define RCC_BUSENCR_ACLKNCENC_Msk (0x1UL << RCC_BUSENCR_ACLKNCENC_Pos) /*!< 0x00000002 */
#define RCC_BUSENCR_ACLKNCENC RCC_BUSENCR_ACLKNCENC_Msk /*!< ACLKNC enable */
#define RCC_BUSENCR_AHBMENC_Pos (2U)
#define RCC_BUSENCR_AHBMENC_Msk (0x1UL << RCC_BUSENCR_AHBMENC_Pos) /*!< 0x00000004 */
#define RCC_BUSENCR_AHBMENC RCC_BUSENCR_AHBMENC_Msk /*!< AHBM enable */
#define RCC_BUSENCR_AHB1ENC_Pos (3U)
#define RCC_BUSENCR_AHB1ENC_Msk (0x1UL << RCC_BUSENCR_AHB1ENC_Pos) /*!< 0x00000008 */
#define RCC_BUSENCR_AHB1ENC RCC_BUSENCR_AHB1ENC_Msk /*!< AHB1 enable */
#define RCC_BUSENCR_AHB2ENC_Pos (4U)
#define RCC_BUSENCR_AHB2ENC_Msk (0x1UL << RCC_BUSENCR_AHB2ENC_Pos) /*!< 0x00000010 */
#define RCC_BUSENCR_AHB2ENC RCC_BUSENCR_AHB2ENC_Msk /*!< AHB2 enable */
#define RCC_BUSENCR_AHB3ENC_Pos (5U)
#define RCC_BUSENCR_AHB3ENC_Msk (0x1UL << RCC_BUSENCR_AHB3ENC_Pos) /*!< 0x00000020 */
#define RCC_BUSENCR_AHB3ENC RCC_BUSENCR_AHB3ENC_Msk /*!< AHB3 enable */
#define RCC_BUSENCR_AHB4ENC_Pos (6U)
#define RCC_BUSENCR_AHB4ENC_Msk (0x1UL << RCC_BUSENCR_AHB4ENC_Pos) /*!< 0x00000040 */
#define RCC_BUSENCR_AHB4ENC RCC_BUSENCR_AHB4ENC_Msk /*!< AHB4 enable */
#define RCC_BUSENCR_AHB5ENC_Pos (7U)
#define RCC_BUSENCR_AHB5ENC_Msk (0x1UL << RCC_BUSENCR_AHB5ENC_Pos) /*!< 0x00000080 */
#define RCC_BUSENCR_AHB5ENC RCC_BUSENCR_AHB5ENC_Msk /*!< AHB5 enable */
#define RCC_BUSENCR_APB1ENC_Pos (8U)
#define RCC_BUSENCR_APB1ENC_Msk (0x1UL << RCC_BUSENCR_APB1ENC_Pos) /*!< 0x00000100 */
#define RCC_BUSENCR_APB1ENC RCC_BUSENCR_APB1ENC_Msk /*!< APB1 enable */
#define RCC_BUSENCR_APB2ENC_Pos (9U)
#define RCC_BUSENCR_APB2ENC_Msk (0x1UL << RCC_BUSENCR_APB2ENC_Pos) /*!< 0x00000200 */
#define RCC_BUSENCR_APB2ENC RCC_BUSENCR_APB2ENC_Msk /*!< APB2 enable */
#define RCC_BUSENCR_APB3ENC_Pos (10U)
#define RCC_BUSENCR_APB3ENC_Msk (0x1UL << RCC_BUSENCR_APB3ENC_Pos) /*!< 0x00000400 */
#define RCC_BUSENCR_APB3ENC RCC_BUSENCR_APB3ENC_Msk /*!< APB3 enable */
#define RCC_BUSENCR_APB4ENC_Pos (11U)
#define RCC_BUSENCR_APB4ENC_Msk (0x1UL << RCC_BUSENCR_APB4ENC_Pos) /*!< 0x00000800 */
#define RCC_BUSENCR_APB4ENC RCC_BUSENCR_APB4ENC_Msk /*!< APB4 enable */
#define RCC_BUSENCR_APB5ENC_Pos (12U)
#define RCC_BUSENCR_APB5ENC_Msk (0x1UL << RCC_BUSENCR_APB5ENC_Pos) /*!< 0x00001000 */
#define RCC_BUSENCR_APB5ENC RCC_BUSENCR_APB5ENC_Msk /*!< APB5 enable */
/***************** Bit definition for RCC_MISCENCR register *****************/
#define RCC_MISCENCR_DBGENC_Pos (0U)
#define RCC_MISCENCR_DBGENC_Msk (0x1UL << RCC_MISCENCR_DBGENC_Pos) /*!< 0x00000001 */
#define RCC_MISCENCR_DBGENC RCC_MISCENCR_DBGENC_Msk /*!< DBG enable */
#define RCC_MISCENCR_MCO1ENC_Pos (1U)
#define RCC_MISCENCR_MCO1ENC_Msk (0x1UL << RCC_MISCENCR_MCO1ENC_Pos) /*!< 0x00000002 */
#define RCC_MISCENCR_MCO1ENC RCC_MISCENCR_MCO1ENC_Msk /*!< MCO1 enable */
#define RCC_MISCENCR_MCO2ENC_Pos (2U)
#define RCC_MISCENCR_MCO2ENC_Msk (0x1UL << RCC_MISCENCR_MCO2ENC_Pos) /*!< 0x00000004 */
#define RCC_MISCENCR_MCO2ENC RCC_MISCENCR_MCO2ENC_Msk /*!< MCO2 enable */
#define RCC_MISCENCR_XSPIPHYCOMPENC_Pos (3U)
#define RCC_MISCENCR_XSPIPHYCOMPENC_Msk (0x1UL << RCC_MISCENCR_XSPIPHYCOMPENC_Pos) /*!< 0x00000008 */
#define RCC_MISCENCR_XSPIPHYCOMPENC RCC_MISCENCR_XSPIPHYCOMPENC_Msk /*!< XSPIPHYCOMP enable */
#define RCC_MISCENCR_PERENC_Pos (6U)
#define RCC_MISCENCR_PERENC_Msk (0x1UL << RCC_MISCENCR_PERENC_Pos) /*!< 0x00000040 */
#define RCC_MISCENCR_PERENC RCC_MISCENCR_PERENC_Msk /*!< PER enable */
/***************** Bit definition for RCC_MEMENCR register ******************/
#define RCC_MEMENCR_AXISRAM3ENC_Pos (0U)
#define RCC_MEMENCR_AXISRAM3ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM3ENC_Pos)/*!< 0x00000001 */
#define RCC_MEMENCR_AXISRAM3ENC RCC_MEMENCR_AXISRAM3ENC_Msk /*!< AXISRAM3 enable */
#define RCC_MEMENCR_AXISRAM4ENC_Pos (1U)
#define RCC_MEMENCR_AXISRAM4ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM4ENC_Pos)/*!< 0x00000002 */
#define RCC_MEMENCR_AXISRAM4ENC RCC_MEMENCR_AXISRAM4ENC_Msk /*!< AXISRAM4 enable */
#define RCC_MEMENCR_AXISRAM5ENC_Pos (2U)
#define RCC_MEMENCR_AXISRAM5ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM5ENC_Pos)/*!< 0x00000004 */
#define RCC_MEMENCR_AXISRAM5ENC RCC_MEMENCR_AXISRAM5ENC_Msk /*!< AXISRAM5 enable */
#define RCC_MEMENCR_AXISRAM6ENC_Pos (3U)
#define RCC_MEMENCR_AXISRAM6ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM6ENC_Pos)/*!< 0x00000008 */
#define RCC_MEMENCR_AXISRAM6ENC RCC_MEMENCR_AXISRAM6ENC_Msk /*!< AXISRAM6 enable */
#define RCC_MEMENCR_AHBSRAM1ENC_Pos (4U)
#define RCC_MEMENCR_AHBSRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM1ENC_Pos)/*!< 0x00000010 */
#define RCC_MEMENCR_AHBSRAM1ENC RCC_MEMENCR_AHBSRAM1ENC_Msk /*!< AHBSRAM1 enable */
#define RCC_MEMENCR_AHBSRAM2ENC_Pos (5U)
#define RCC_MEMENCR_AHBSRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AHBSRAM2ENC_Pos)/*!< 0x00000020 */
#define RCC_MEMENCR_AHBSRAM2ENC RCC_MEMENCR_AHBSRAM2ENC_Msk /*!< AHBSRAM2 enable */
#define RCC_MEMENCR_BKPSRAMENC_Pos (6U)
#define RCC_MEMENCR_BKPSRAMENC_Msk (0x1UL << RCC_MEMENCR_BKPSRAMENC_Pos) /*!< 0x00000040 */
#define RCC_MEMENCR_BKPSRAMENC RCC_MEMENCR_BKPSRAMENC_Msk /*!< BKPSRAM enable */
#define RCC_MEMENCR_AXISRAM1ENC_Pos (7U)
#define RCC_MEMENCR_AXISRAM1ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM1ENC_Pos)/*!< 0x00000080 */
#define RCC_MEMENCR_AXISRAM1ENC RCC_MEMENCR_AXISRAM1ENC_Msk /*!< AXISRAM1 enable */
#define RCC_MEMENCR_AXISRAM2ENC_Pos (8U)
#define RCC_MEMENCR_AXISRAM2ENC_Msk (0x1UL << RCC_MEMENCR_AXISRAM2ENC_Pos)/*!< 0x00000100 */
#define RCC_MEMENCR_AXISRAM2ENC RCC_MEMENCR_AXISRAM2ENC_Msk /*!< AXISRAM2 enable */
#define RCC_MEMENCR_FLEXRAMENC_Pos (9U)
#define RCC_MEMENCR_FLEXRAMENC_Msk (0x1UL << RCC_MEMENCR_FLEXRAMENC_Pos) /*!< 0x00000200 */
#define RCC_MEMENCR_FLEXRAMENC RCC_MEMENCR_FLEXRAMENC_Msk /*!< FLEXRAM enable */
#define RCC_MEMENCR_CACHEAXIRAMENC_Pos (10U)
#define RCC_MEMENCR_CACHEAXIRAMENC_Msk (0x1UL << RCC_MEMENCR_CACHEAXIRAMENC_Pos) /*!< 0x00000400 */
#define RCC_MEMENCR_CACHEAXIRAMENC RCC_MEMENCR_CACHEAXIRAMENC_Msk /*!< CACHEAXIRAM enable */
#define RCC_MEMENCR_VENCRAMENC_Pos (11U)
#define RCC_MEMENCR_VENCRAMENC_Msk (0x1UL << RCC_MEMENCR_VENCRAMENC_Pos) /*!< 0x00000800 */
#define RCC_MEMENCR_VENCRAMENC RCC_MEMENCR_VENCRAMENC_Msk /*!< VENCRAM enable */
#define RCC_MEMENCR_BOOTROMENC_Pos (12U)
#define RCC_MEMENCR_BOOTROMENC_Msk (0x1UL << RCC_MEMENCR_BOOTROMENC_Pos) /*!< 0x00001000 */
#define RCC_MEMENCR_BOOTROMENC RCC_MEMENCR_BOOTROMENC_Msk /*!< Boot ROM enable */
/***************** Bit definition for RCC_AHB1ENCR register *****************/
#define RCC_AHB1ENCR_GPDMA1ENC_Pos (4U)
#define RCC_AHB1ENCR_GPDMA1ENC_Msk (0x1UL << RCC_AHB1ENCR_GPDMA1ENC_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENCR_GPDMA1ENC RCC_AHB1ENCR_GPDMA1ENC_Msk /*!< GPDMA1 enable */
#define RCC_AHB1ENCR_ADC12ENC_Pos (5U)
#define RCC_AHB1ENCR_ADC12ENC_Msk (0x1UL << RCC_AHB1ENCR_ADC12ENC_Pos) /*!< 0x00000020 */
#define RCC_AHB1ENCR_ADC12ENC RCC_AHB1ENCR_ADC12ENC_Msk /*!< ADC12 enable */
/***************** Bit definition for RCC_AHB2ENCR register *****************/
#define RCC_AHB2ENCR_RAMCFGENC_Pos (12U)
#define RCC_AHB2ENCR_RAMCFGENC_Msk (0x1UL << RCC_AHB2ENCR_RAMCFGENC_Pos) /*!< 0x00001000 */
#define RCC_AHB2ENCR_RAMCFGENC RCC_AHB2ENCR_RAMCFGENC_Msk /*!< RAMCFG enable */
#define RCC_AHB2ENCR_MDF1ENC_Pos (16U)
#define RCC_AHB2ENCR_MDF1ENC_Msk (0x1UL << RCC_AHB2ENCR_MDF1ENC_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENCR_MDF1ENC RCC_AHB2ENCR_MDF1ENC_Msk /*!< MDF1 enable */
#define RCC_AHB2ENCR_ADF1ENC_Pos (17U)
#define RCC_AHB2ENCR_ADF1ENC_Msk (0x1UL << RCC_AHB2ENCR_ADF1ENC_Pos) /*!< 0x00020000 */
#define RCC_AHB2ENCR_ADF1ENC RCC_AHB2ENCR_ADF1ENC_Msk /*!< ADF1 enable */
/***************** Bit definition for RCC_AHB3ENCR register *****************/
#define RCC_AHB3ENCR_RNGENC_Pos (0U)
#define RCC_AHB3ENCR_RNGENC_Msk (0x1UL << RCC_AHB3ENCR_RNGENC_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENCR_RNGENC RCC_AHB3ENCR_RNGENC_Msk /*!< RNG enable */
#define RCC_AHB3ENCR_HASHENC_Pos (1U)
#define RCC_AHB3ENCR_HASHENC_Msk (0x1UL << RCC_AHB3ENCR_HASHENC_Pos) /*!< 0x00000002 */
#define RCC_AHB3ENCR_HASHENC RCC_AHB3ENCR_HASHENC_Msk /*!< HASH enable */
#define RCC_AHB3ENCR_CRYPENC_Pos (2U)
#define RCC_AHB3ENCR_CRYPENC_Msk (0x1UL << RCC_AHB3ENCR_CRYPENC_Pos) /*!< 0x00000004 */
#define RCC_AHB3ENCR_CRYPENC RCC_AHB3ENCR_CRYPENC_Msk /*!< CRYP enable */
#define RCC_AHB3ENCR_SAESENC_Pos (4U)
#define RCC_AHB3ENCR_SAESENC_Msk (0x1UL << RCC_AHB3ENCR_SAESENC_Pos) /*!< 0x00000010 */
#define RCC_AHB3ENCR_SAESENC RCC_AHB3ENCR_SAESENC_Msk /*!< SAES enable */
#define RCC_AHB3ENCR_PKAENC_Pos (8U)
#define RCC_AHB3ENCR_PKAENC_Msk (0x1UL << RCC_AHB3ENCR_PKAENC_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENCR_PKAENC RCC_AHB3ENCR_PKAENC_Msk /*!< PKA enable */
#define RCC_AHB3ENCR_RIFSCENC_Pos (9U)
#define RCC_AHB3ENCR_RIFSCENC_Msk (0x1UL << RCC_AHB3ENCR_RIFSCENC_Pos) /*!< 0x00000200 */
#define RCC_AHB3ENCR_RIFSCENC RCC_AHB3ENCR_RIFSCENC_Msk /*!< RIFSC enable */
#define RCC_AHB3ENCR_IACENC_Pos (10U)
#define RCC_AHB3ENCR_IACENC_Msk (0x1UL << RCC_AHB3ENCR_IACENC_Pos) /*!< 0x00000400 */
#define RCC_AHB3ENCR_IACENC RCC_AHB3ENCR_IACENC_Msk /*!< IAC enable */
#define RCC_AHB3ENCR_RISAFENC_Pos (14U)
#define RCC_AHB3ENCR_RISAFENC_Msk (0x1UL << RCC_AHB3ENCR_RISAFENC_Pos) /*!< 0x00004000 */
#define RCC_AHB3ENCR_RISAFENC RCC_AHB3ENCR_RISAFENC_Msk /*!< RISAF enable */
/***************** Bit definition for RCC_AHB4ENCR register *****************/
#define RCC_AHB4ENCR_GPIOAENC_Pos (0U)
#define RCC_AHB4ENCR_GPIOAENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOAENC_Pos) /*!< 0x00000001 */
#define RCC_AHB4ENCR_GPIOAENC RCC_AHB4ENCR_GPIOAENC_Msk /*!< GPIO A enable */
#define RCC_AHB4ENCR_GPIOBENC_Pos (1U)
#define RCC_AHB4ENCR_GPIOBENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOBENC_Pos) /*!< 0x00000002 */
#define RCC_AHB4ENCR_GPIOBENC RCC_AHB4ENCR_GPIOBENC_Msk /*!< GPIO B enable */
#define RCC_AHB4ENCR_GPIOCENC_Pos (2U)
#define RCC_AHB4ENCR_GPIOCENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOCENC_Pos) /*!< 0x00000004 */
#define RCC_AHB4ENCR_GPIOCENC RCC_AHB4ENCR_GPIOCENC_Msk /*!< GPIO C enable */
#define RCC_AHB4ENCR_GPIODENC_Pos (3U)
#define RCC_AHB4ENCR_GPIODENC_Msk (0x1UL << RCC_AHB4ENCR_GPIODENC_Pos) /*!< 0x00000008 */
#define RCC_AHB4ENCR_GPIODENC RCC_AHB4ENCR_GPIODENC_Msk /*!< GPIO D enable */
#define RCC_AHB4ENCR_GPIOEENC_Pos (4U)
#define RCC_AHB4ENCR_GPIOEENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOEENC_Pos) /*!< 0x00000010 */
#define RCC_AHB4ENCR_GPIOEENC RCC_AHB4ENCR_GPIOEENC_Msk /*!< GPIO E enable */
#define RCC_AHB4ENCR_GPIOFENC_Pos (5U)
#define RCC_AHB4ENCR_GPIOFENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOFENC_Pos) /*!< 0x00000020 */
#define RCC_AHB4ENCR_GPIOFENC RCC_AHB4ENCR_GPIOFENC_Msk /*!< GPIO F enable */
#define RCC_AHB4ENCR_GPIOGENC_Pos (6U)
#define RCC_AHB4ENCR_GPIOGENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOGENC_Pos) /*!< 0x00000040 */
#define RCC_AHB4ENCR_GPIOGENC RCC_AHB4ENCR_GPIOGENC_Msk /*!< GPIO G enable */
#define RCC_AHB4ENCR_GPIOHENC_Pos (7U)
#define RCC_AHB4ENCR_GPIOHENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOHENC_Pos) /*!< 0x00000080 */
#define RCC_AHB4ENCR_GPIOHENC RCC_AHB4ENCR_GPIOHENC_Msk /*!< GPIO H enable */
#define RCC_AHB4ENCR_GPIONENC_Pos (13U)
#define RCC_AHB4ENCR_GPIONENC_Msk (0x1UL << RCC_AHB4ENCR_GPIONENC_Pos) /*!< 0x00002000 */
#define RCC_AHB4ENCR_GPIONENC RCC_AHB4ENCR_GPIONENC_Msk /*!< GPIO N enable */
#define RCC_AHB4ENCR_GPIOOENC_Pos (14U)
#define RCC_AHB4ENCR_GPIOOENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOOENC_Pos) /*!< 0x00004000 */
#define RCC_AHB4ENCR_GPIOOENC RCC_AHB4ENCR_GPIOOENC_Msk /*!< GPIO O enable */
#define RCC_AHB4ENCR_GPIOPENC_Pos (15U)
#define RCC_AHB4ENCR_GPIOPENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOPENC_Pos) /*!< 0x00008000 */
#define RCC_AHB4ENCR_GPIOPENC RCC_AHB4ENCR_GPIOPENC_Msk /*!< GPIO P enable */
#define RCC_AHB4ENCR_GPIOQENC_Pos (16U)
#define RCC_AHB4ENCR_GPIOQENC_Msk (0x1UL << RCC_AHB4ENCR_GPIOQENC_Pos) /*!< 0x00010000 */
#define RCC_AHB4ENCR_GPIOQENC RCC_AHB4ENCR_GPIOQENC_Msk /*!< GPIO Q enable */
#define RCC_AHB4ENCR_PWRENC_Pos (18U)
#define RCC_AHB4ENCR_PWRENC_Msk (0x1UL << RCC_AHB4ENCR_PWRENC_Pos) /*!< 0x00040000 */
#define RCC_AHB4ENCR_PWRENC RCC_AHB4ENCR_PWRENC_Msk /*!< PWR enable */
#define RCC_AHB4ENCR_CRCENC_Pos (19U)
#define RCC_AHB4ENCR_CRCENC_Msk (0x1UL << RCC_AHB4ENCR_CRCENC_Pos) /*!< 0x00080000 */
#define RCC_AHB4ENCR_CRCENC RCC_AHB4ENCR_CRCENC_Msk /*!< CRC enable */
/***************** Bit definition for RCC_AHB5ENCR register *****************/
#define RCC_AHB5ENCR_HPDMA1ENC_Pos (0U)
#define RCC_AHB5ENCR_HPDMA1ENC_Msk (0x1UL << RCC_AHB5ENCR_HPDMA1ENC_Pos) /*!< 0x00000001 */
#define RCC_AHB5ENCR_HPDMA1ENC RCC_AHB5ENCR_HPDMA1ENC_Msk /*!< HPDMA1 enable */
#define RCC_AHB5ENCR_DMA2DENC_Pos (1U)
#define RCC_AHB5ENCR_DMA2DENC_Msk (0x1UL << RCC_AHB5ENCR_DMA2DENC_Pos) /*!< 0x00000002 */
#define RCC_AHB5ENCR_DMA2DENC RCC_AHB5ENCR_DMA2DENC_Msk /*!< DMA2D enable */
#define RCC_AHB5ENCR_JPEGENC_Pos (3U)
#define RCC_AHB5ENCR_JPEGENC_Msk (0x1UL << RCC_AHB5ENCR_JPEGENC_Pos) /*!< 0x00000008 */
#define RCC_AHB5ENCR_JPEGENC RCC_AHB5ENCR_JPEGENC_Msk /*!< JPEG enable */
#define RCC_AHB5ENCR_FMCENC_Pos (4U)
#define RCC_AHB5ENCR_FMCENC_Msk (0x1UL << RCC_AHB5ENCR_FMCENC_Pos) /*!< 0x00000010 */
#define RCC_AHB5ENCR_FMCENC RCC_AHB5ENCR_FMCENC_Msk /*!< FMC enable */
#define RCC_AHB5ENCR_XSPI1ENC_Pos (5U)
#define RCC_AHB5ENCR_XSPI1ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI1ENC_Pos) /*!< 0x00000020 */
#define RCC_AHB5ENCR_XSPI1ENC RCC_AHB5ENCR_XSPI1ENC_Msk /*!< XSPI1 enable */
#define RCC_AHB5ENCR_PSSIENC_Pos (6U)
#define RCC_AHB5ENCR_PSSIENC_Msk (0x1UL << RCC_AHB5ENCR_PSSIENC_Pos) /*!< 0x00000040 */
#define RCC_AHB5ENCR_PSSIENC RCC_AHB5ENCR_PSSIENC_Msk /*!< PSSI enable */
#define RCC_AHB5ENCR_SDMMC2ENC_Pos (7U)
#define RCC_AHB5ENCR_SDMMC2ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC2ENC_Pos) /*!< 0x00000080 */
#define RCC_AHB5ENCR_SDMMC2ENC RCC_AHB5ENCR_SDMMC2ENC_Msk /*!< SDMMC2 enable */
#define RCC_AHB5ENCR_SDMMC1ENC_Pos (8U)
#define RCC_AHB5ENCR_SDMMC1ENC_Msk (0x1UL << RCC_AHB5ENCR_SDMMC1ENC_Pos) /*!< 0x00000100 */
#define RCC_AHB5ENCR_SDMMC1ENC RCC_AHB5ENCR_SDMMC1ENC_Msk /*!< SDMMC1 enable */
#define RCC_AHB5ENCR_XSPI2ENC_Pos (12U)
#define RCC_AHB5ENCR_XSPI2ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI2ENC_Pos) /*!< 0x00001000 */
#define RCC_AHB5ENCR_XSPI2ENC RCC_AHB5ENCR_XSPI2ENC_Msk /*!< XSPI2 enable */
#define RCC_AHB5ENCR_XSPIMENC_Pos (13U)
#define RCC_AHB5ENCR_XSPIMENC_Msk (0x1UL << RCC_AHB5ENCR_XSPIMENC_Pos) /*!< 0x00002000 */
#define RCC_AHB5ENCR_XSPIMENC RCC_AHB5ENCR_XSPIMENC_Msk /*!< XSPIM enable */
#define RCC_AHB5ENCR_MCE1ENC_Pos (14U)
#define RCC_AHB5ENCR_MCE1ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE1ENC_Pos) /*!< 0x00004000 */
#define RCC_AHB5ENCR_MCE1ENC RCC_AHB5ENCR_MCE1ENC_Msk /*!< MCE1 enable */
#define RCC_AHB5ENCR_MCE2ENC_Pos (15U)
#define RCC_AHB5ENCR_MCE2ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE2ENC_Pos) /*!< 0x00008000 */
#define RCC_AHB5ENCR_MCE2ENC RCC_AHB5ENCR_MCE2ENC_Msk /*!< MCE2 enable */
#define RCC_AHB5ENCR_MCE3ENC_Pos (16U)
#define RCC_AHB5ENCR_MCE3ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE3ENC_Pos) /*!< 0x00010000 */
#define RCC_AHB5ENCR_MCE3ENC RCC_AHB5ENCR_MCE3ENC_Msk /*!< MCE3 enable */
#define RCC_AHB5ENCR_XSPI3ENC_Pos (17U)
#define RCC_AHB5ENCR_XSPI3ENC_Msk (0x1UL << RCC_AHB5ENCR_XSPI3ENC_Pos) /*!< 0x00020000 */
#define RCC_AHB5ENCR_XSPI3ENC RCC_AHB5ENCR_XSPI3ENC_Msk /*!< XSPI3 enable */
#define RCC_AHB5ENCR_MCE4ENC_Pos (18U)
#define RCC_AHB5ENCR_MCE4ENC_Msk (0x1UL << RCC_AHB5ENCR_MCE4ENC_Pos) /*!< 0x00040000 */
#define RCC_AHB5ENCR_MCE4ENC RCC_AHB5ENCR_MCE4ENC_Msk /*!< MCE4 enable */
#define RCC_AHB5ENCR_GFXMMUENC_Pos (19U)
#define RCC_AHB5ENCR_GFXMMUENC_Msk (0x1UL << RCC_AHB5ENCR_GFXMMUENC_Pos) /*!< 0x00080000 */
#define RCC_AHB5ENCR_GFXMMUENC RCC_AHB5ENCR_GFXMMUENC_Msk /*!< GFXMMU enable */
#define RCC_AHB5ENCR_GPU2DENC_Pos (20U)
#define RCC_AHB5ENCR_GPU2DENC_Msk (0x1UL << RCC_AHB5ENCR_GPU2DENC_Pos) /*!< 0x00100000 */
#define RCC_AHB5ENCR_GPU2DENC RCC_AHB5ENCR_GPU2DENC_Msk /*!< GPU2D enable */
#define RCC_AHB5ENCR_ETH1MACENC_Pos (22U)
#define RCC_AHB5ENCR_ETH1MACENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1MACENC_Pos)/*!< 0x00400000 */
#define RCC_AHB5ENCR_ETH1MACENC RCC_AHB5ENCR_ETH1MACENC_Msk /*!< ETH1MAC enable */
#define RCC_AHB5ENCR_ETH1TXENC_Pos (23U)
#define RCC_AHB5ENCR_ETH1TXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1TXENC_Pos) /*!< 0x00800000 */
#define RCC_AHB5ENCR_ETH1TXENC RCC_AHB5ENCR_ETH1TXENC_Msk /*!< ETH1TX enable */
#define RCC_AHB5ENCR_ETH1RXENC_Pos (24U)
#define RCC_AHB5ENCR_ETH1RXENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1RXENC_Pos) /*!< 0x01000000 */
#define RCC_AHB5ENCR_ETH1RXENC RCC_AHB5ENCR_ETH1RXENC_Msk /*!< ETH1RX enable */
#define RCC_AHB5ENCR_ETH1ENC_Pos (25U)
#define RCC_AHB5ENCR_ETH1ENC_Msk (0x1UL << RCC_AHB5ENCR_ETH1ENC_Pos) /*!< 0x02000000 */
#define RCC_AHB5ENCR_ETH1ENC RCC_AHB5ENCR_ETH1ENC_Msk /*!< ETH1 enable */
#define RCC_AHB5ENCR_OTG1ENC_Pos (26U)
#define RCC_AHB5ENCR_OTG1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG1ENC_Pos) /*!< 0x04000000 */
#define RCC_AHB5ENCR_OTG1ENC RCC_AHB5ENCR_OTG1ENC_Msk /*!< OTG1 enable */
#define RCC_AHB5ENCR_OTGPHY1ENC_Pos (27U)
#define RCC_AHB5ENCR_OTGPHY1ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY1ENC_Pos)/*!< 0x08000000 */
#define RCC_AHB5ENCR_OTGPHY1ENC RCC_AHB5ENCR_OTGPHY1ENC_Msk /*!< OTGPHY1 enable */
#define RCC_AHB5ENCR_OTGPHY2ENC_Pos (28U)
#define RCC_AHB5ENCR_OTGPHY2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTGPHY2ENC_Pos)/*!< 0x10000000 */
#define RCC_AHB5ENCR_OTGPHY2ENC RCC_AHB5ENCR_OTGPHY2ENC_Msk /*!< OTGPHY2 enable */
#define RCC_AHB5ENCR_OTG2ENC_Pos (29U)
#define RCC_AHB5ENCR_OTG2ENC_Msk (0x1UL << RCC_AHB5ENCR_OTG2ENC_Pos) /*!< 0x20000000 */
#define RCC_AHB5ENCR_OTG2ENC RCC_AHB5ENCR_OTG2ENC_Msk /*!< OTG2 enable */
#define RCC_AHB5ENCR_CACHEAXIENC_Pos (30U)
#define RCC_AHB5ENCR_CACHEAXIENC_Msk (0x1UL << RCC_AHB5ENCR_CACHEAXIENC_Pos) /*!< 0x40000000 */
#define RCC_AHB5ENCR_CACHEAXIENC RCC_AHB5ENCR_CACHEAXIENC_Msk /*!< CACHEAXI enable */
#define RCC_AHB5ENCR_NPUENC_Pos (31U)
#define RCC_AHB5ENCR_NPUENC_Msk (0x1UL << RCC_AHB5ENCR_NPUENC_Pos) /*!< 0x80000000 */
#define RCC_AHB5ENCR_NPUENC RCC_AHB5ENCR_NPUENC_Msk /*!< NPU enable */
/**************** Bit definition for RCC_APB1ENCR1 register *****************/
#define RCC_APB1ENCR1_TIM2ENC_Pos (0U)
#define RCC_APB1ENCR1_TIM2ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM2ENC_Pos) /*!< 0x00000001 */
#define RCC_APB1ENCR1_TIM2ENC RCC_APB1ENCR1_TIM2ENC_Msk /*!< TIM2 enable */
#define RCC_APB1ENCR1_TIM3ENC_Pos (1U)
#define RCC_APB1ENCR1_TIM3ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM3ENC_Pos) /*!< 0x00000002 */
#define RCC_APB1ENCR1_TIM3ENC RCC_APB1ENCR1_TIM3ENC_Msk /*!< TIM3 enable */
#define RCC_APB1ENCR1_TIM4ENC_Pos (2U)
#define RCC_APB1ENCR1_TIM4ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM4ENC_Pos) /*!< 0x00000004 */
#define RCC_APB1ENCR1_TIM4ENC RCC_APB1ENCR1_TIM4ENC_Msk /*!< TIM4 enable */
#define RCC_APB1ENCR1_TIM5ENC_Pos (3U)
#define RCC_APB1ENCR1_TIM5ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM5ENC_Pos) /*!< 0x00000008 */
#define RCC_APB1ENCR1_TIM5ENC RCC_APB1ENCR1_TIM5ENC_Msk /*!< TIM5 enable */
#define RCC_APB1ENCR1_TIM6ENC_Pos (4U)
#define RCC_APB1ENCR1_TIM6ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM6ENC_Pos) /*!< 0x00000010 */
#define RCC_APB1ENCR1_TIM6ENC RCC_APB1ENCR1_TIM6ENC_Msk /*!< TIM6 enable */
#define RCC_APB1ENCR1_TIM7ENC_Pos (5U)
#define RCC_APB1ENCR1_TIM7ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM7ENC_Pos) /*!< 0x00000020 */
#define RCC_APB1ENCR1_TIM7ENC RCC_APB1ENCR1_TIM7ENC_Msk /*!< TIM7 enable */
#define RCC_APB1ENCR1_TIM12ENC_Pos (6U)
#define RCC_APB1ENCR1_TIM12ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM12ENC_Pos) /*!< 0x00000040 */
#define RCC_APB1ENCR1_TIM12ENC RCC_APB1ENCR1_TIM12ENC_Msk /*!< TIM12 enable */
#define RCC_APB1ENCR1_TIM13ENC_Pos (7U)
#define RCC_APB1ENCR1_TIM13ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM13ENC_Pos) /*!< 0x00000080 */
#define RCC_APB1ENCR1_TIM13ENC RCC_APB1ENCR1_TIM13ENC_Msk /*!< TIM13 enable */
#define RCC_APB1ENCR1_TIM14ENC_Pos (8U)
#define RCC_APB1ENCR1_TIM14ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM14ENC_Pos) /*!< 0x00000100 */
#define RCC_APB1ENCR1_TIM14ENC RCC_APB1ENCR1_TIM14ENC_Msk /*!< TIM14 enable */
#define RCC_APB1ENCR1_LPTIM1ENC_Pos (9U)
#define RCC_APB1ENCR1_LPTIM1ENC_Msk (0x1UL << RCC_APB1ENCR1_LPTIM1ENC_Pos)/*!< 0x00000200 */
#define RCC_APB1ENCR1_LPTIM1ENC RCC_APB1ENCR1_LPTIM1ENC_Msk /*!< LPTIM1 enable */
#define RCC_APB1ENCR1_TIM10ENC_Pos (12U)
#define RCC_APB1ENCR1_TIM10ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM10ENC_Pos) /*!< 0x00001000 */
#define RCC_APB1ENCR1_TIM10ENC RCC_APB1ENCR1_TIM10ENC_Msk /*!< TIM10 enable */
#define RCC_APB1ENCR1_TIM11ENC_Pos (13U)
#define RCC_APB1ENCR1_TIM11ENC_Msk (0x1UL << RCC_APB1ENCR1_TIM11ENC_Pos) /*!< 0x00002000 */
#define RCC_APB1ENCR1_TIM11ENC RCC_APB1ENCR1_TIM11ENC_Msk /*!< TIM11 enable */
#define RCC_APB1ENCR1_SPI2ENC_Pos (14U)
#define RCC_APB1ENCR1_SPI2ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI2ENC_Pos) /*!< 0x00004000 */
#define RCC_APB1ENCR1_SPI2ENC RCC_APB1ENCR1_SPI2ENC_Msk /*!< SPI2 enable */
#define RCC_APB1ENCR1_SPI3ENC_Pos (15U)
#define RCC_APB1ENCR1_SPI3ENC_Msk (0x1UL << RCC_APB1ENCR1_SPI3ENC_Pos) /*!< 0x00008000 */
#define RCC_APB1ENCR1_SPI3ENC RCC_APB1ENCR1_SPI3ENC_Msk /*!< SPI3 enable */
#define RCC_APB1ENCR1_SPDIFRX1ENC_Pos (16U)
#define RCC_APB1ENCR1_SPDIFRX1ENC_Msk (0x1UL << RCC_APB1ENCR1_SPDIFRX1ENC_Pos) /*!< 0x00010000 */
#define RCC_APB1ENCR1_SPDIFRX1ENC RCC_APB1ENCR1_SPDIFRX1ENC_Msk /*!< SPDIFRX1 enable */
#define RCC_APB1ENCR1_USART2ENC_Pos (17U)
#define RCC_APB1ENCR1_USART2ENC_Msk (0x1UL << RCC_APB1ENCR1_USART2ENC_Pos)/*!< 0x00020000 */
#define RCC_APB1ENCR1_USART2ENC RCC_APB1ENCR1_USART2ENC_Msk /*!< USART2 enable */
#define RCC_APB1ENCR1_USART3ENC_Pos (18U)
#define RCC_APB1ENCR1_USART3ENC_Msk (0x1UL << RCC_APB1ENCR1_USART3ENC_Pos)/*!< 0x00040000 */
#define RCC_APB1ENCR1_USART3ENC RCC_APB1ENCR1_USART3ENC_Msk /*!< USART3 enable */
#define RCC_APB1ENCR1_UART4ENC_Pos (19U)
#define RCC_APB1ENCR1_UART4ENC_Msk (0x1UL << RCC_APB1ENCR1_UART4ENC_Pos) /*!< 0x00080000 */
#define RCC_APB1ENCR1_UART4ENC RCC_APB1ENCR1_UART4ENC_Msk /*!< UART4 enable */
#define RCC_APB1ENCR1_UART5ENC_Pos (20U)
#define RCC_APB1ENCR1_UART5ENC_Msk (0x1UL << RCC_APB1ENCR1_UART5ENC_Pos) /*!< 0x00100000 */
#define RCC_APB1ENCR1_UART5ENC RCC_APB1ENCR1_UART5ENC_Msk /*!< UART5 enable */
#define RCC_APB1ENCR1_I2C1ENC_Pos (21U)
#define RCC_APB1ENCR1_I2C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C1ENC_Pos) /*!< 0x00200000 */
#define RCC_APB1ENCR1_I2C1ENC RCC_APB1ENCR1_I2C1ENC_Msk /*!< I2C1 enable */
#define RCC_APB1ENCR1_I2C2ENC_Pos (22U)
#define RCC_APB1ENCR1_I2C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C2ENC_Pos) /*!< 0x00400000 */
#define RCC_APB1ENCR1_I2C2ENC RCC_APB1ENCR1_I2C2ENC_Msk /*!< I2C2 enable */
#define RCC_APB1ENCR1_I2C3ENC_Pos (23U)
#define RCC_APB1ENCR1_I2C3ENC_Msk (0x1UL << RCC_APB1ENCR1_I2C3ENC_Pos) /*!< 0x00800000 */
#define RCC_APB1ENCR1_I2C3ENC RCC_APB1ENCR1_I2C3ENC_Msk /*!< I2C3 enable */
#define RCC_APB1ENCR1_I3C1ENC_Pos (24U)
#define RCC_APB1ENCR1_I3C1ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C1ENC_Pos) /*!< 0x01000000 */
#define RCC_APB1ENCR1_I3C1ENC RCC_APB1ENCR1_I3C1ENC_Msk /*!< I3C1 enable */
#define RCC_APB1ENCR1_I3C2ENC_Pos (25U)
#define RCC_APB1ENCR1_I3C2ENC_Msk (0x1UL << RCC_APB1ENCR1_I3C2ENC_Pos) /*!< 0x02000000 */
#define RCC_APB1ENCR1_I3C2ENC RCC_APB1ENCR1_I3C2ENC_Msk /*!< I3C2 enable */
#define RCC_APB1ENCR1_UART7ENC_Pos (30U)
#define RCC_APB1ENCR1_UART7ENC_Msk (0x1UL << RCC_APB1ENCR1_UART7ENC_Pos) /*!< 0x40000000 */
#define RCC_APB1ENCR1_UART7ENC RCC_APB1ENCR1_UART7ENC_Msk /*!< UART7 enable */
#define RCC_APB1ENCR1_UART8ENC_Pos (31U)
#define RCC_APB1ENCR1_UART8ENC_Msk (0x1UL << RCC_APB1ENCR1_UART8ENC_Pos) /*!< 0x80000000 */
#define RCC_APB1ENCR1_UART8ENC RCC_APB1ENCR1_UART8ENC_Msk /*!< UART8 enable */
/**************** Bit definition for RCC_APB1ENCR2 register *****************/
#define RCC_APB1ENCR2_MDIOSENC_Pos (5U)
#define RCC_APB1ENCR2_MDIOSENC_Msk (0x1UL << RCC_APB1ENCR2_MDIOSENC_Pos) /*!< 0x00000020 */
#define RCC_APB1ENCR2_MDIOSENC RCC_APB1ENCR2_MDIOSENC_Msk /*!< MDIOS enable */
#define RCC_APB1ENCR2_FDCANENC_Pos (8U)
#define RCC_APB1ENCR2_FDCANENC_Msk (0x1UL << RCC_APB1ENCR2_FDCANENC_Pos) /*!< 0x00000100 */
#define RCC_APB1ENCR2_FDCANENC RCC_APB1ENCR2_FDCANENC_Msk /*!< FDCAN enable */
#define RCC_APB1ENCR2_UCPD1ENC_Pos (18U)
#define RCC_APB1ENCR2_UCPD1ENC_Msk (0x1UL << RCC_APB1ENCR2_UCPD1ENC_Pos) /*!< 0x00040000 */
#define RCC_APB1ENCR2_UCPD1ENC RCC_APB1ENCR2_UCPD1ENC_Msk /*!< UCPD1 enable */
/***************** Bit definition for RCC_APB2ENCR register *****************/
#define RCC_APB2ENCR_TIM1ENC_Pos (0U)
#define RCC_APB2ENCR_TIM1ENC_Msk (0x1UL << RCC_APB2ENCR_TIM1ENC_Pos) /*!< 0x00000001 */
#define RCC_APB2ENCR_TIM1ENC RCC_APB2ENCR_TIM1ENC_Msk /*!< TIM1 enable */
#define RCC_APB2ENCR_TIM8ENC_Pos (1U)
#define RCC_APB2ENCR_TIM8ENC_Msk (0x1UL << RCC_APB2ENCR_TIM8ENC_Pos) /*!< 0x00000002 */
#define RCC_APB2ENCR_TIM8ENC RCC_APB2ENCR_TIM8ENC_Msk /*!< TIM8 enable */
#define RCC_APB2ENCR_USART1ENC_Pos (4U)
#define RCC_APB2ENCR_USART1ENC_Msk (0x1UL << RCC_APB2ENCR_USART1ENC_Pos) /*!< 0x00000010 */
#define RCC_APB2ENCR_USART1ENC RCC_APB2ENCR_USART1ENC_Msk /*!< USART1 enable */
#define RCC_APB2ENCR_USART6ENC_Pos (5U)
#define RCC_APB2ENCR_USART6ENC_Msk (0x1UL << RCC_APB2ENCR_USART6ENC_Pos) /*!< 0x00000020 */
#define RCC_APB2ENCR_USART6ENC RCC_APB2ENCR_USART6ENC_Msk /*!< USART6 enable */
#define RCC_APB2ENCR_UART9ENC_Pos (6U)
#define RCC_APB2ENCR_UART9ENC_Msk (0x1UL << RCC_APB2ENCR_UART9ENC_Pos) /*!< 0x00000040 */
#define RCC_APB2ENCR_UART9ENC RCC_APB2ENCR_UART9ENC_Msk /*!< UART9 enable */
#define RCC_APB2ENCR_USART10ENC_Pos (7U)
#define RCC_APB2ENCR_USART10ENC_Msk (0x1UL << RCC_APB2ENCR_USART10ENC_Pos)/*!< 0x00000080 */
#define RCC_APB2ENCR_USART10ENC RCC_APB2ENCR_USART10ENC_Msk /*!< USART10 enable */
#define RCC_APB2ENCR_SPI1ENC_Pos (12U)
#define RCC_APB2ENCR_SPI1ENC_Msk (0x1UL << RCC_APB2ENCR_SPI1ENC_Pos) /*!< 0x00001000 */
#define RCC_APB2ENCR_SPI1ENC RCC_APB2ENCR_SPI1ENC_Msk /*!< SPI1 enable */
#define RCC_APB2ENCR_SPI4ENC_Pos (13U)
#define RCC_APB2ENCR_SPI4ENC_Msk (0x1UL << RCC_APB2ENCR_SPI4ENC_Pos) /*!< 0x00002000 */
#define RCC_APB2ENCR_SPI4ENC RCC_APB2ENCR_SPI4ENC_Msk /*!< SPI4 enable */
#define RCC_APB2ENCR_TIM18ENC_Pos (15U)
#define RCC_APB2ENCR_TIM18ENC_Msk (0x1UL << RCC_APB2ENCR_TIM18ENC_Pos) /*!< 0x00008000 */
#define RCC_APB2ENCR_TIM18ENC RCC_APB2ENCR_TIM18ENC_Msk /*!< TIM18 enable */
#define RCC_APB2ENCR_TIM15ENC_Pos (16U)
#define RCC_APB2ENCR_TIM15ENC_Msk (0x1UL << RCC_APB2ENCR_TIM15ENC_Pos) /*!< 0x00010000 */
#define RCC_APB2ENCR_TIM15ENC RCC_APB2ENCR_TIM15ENC_Msk /*!< TIM15 enable */
#define RCC_APB2ENCR_TIM16ENC_Pos (17U)
#define RCC_APB2ENCR_TIM16ENC_Msk (0x1UL << RCC_APB2ENCR_TIM16ENC_Pos) /*!< 0x00020000 */
#define RCC_APB2ENCR_TIM16ENC RCC_APB2ENCR_TIM16ENC_Msk /*!< TIM16 enable */
#define RCC_APB2ENCR_TIM17ENC_Pos (18U)
#define RCC_APB2ENCR_TIM17ENC_Msk (0x1UL << RCC_APB2ENCR_TIM17ENC_Pos) /*!< 0x00040000 */
#define RCC_APB2ENCR_TIM17ENC RCC_APB2ENCR_TIM17ENC_Msk /*!< TIM17 enable */
#define RCC_APB2ENCR_TIM9ENC_Pos (19U)
#define RCC_APB2ENCR_TIM9ENC_Msk (0x1UL << RCC_APB2ENCR_TIM9ENC_Pos) /*!< 0x00080000 */
#define RCC_APB2ENCR_TIM9ENC RCC_APB2ENCR_TIM9ENC_Msk /*!< TIM9 enable */
#define RCC_APB2ENCR_SPI5ENC_Pos (20U)
#define RCC_APB2ENCR_SPI5ENC_Msk (0x1UL << RCC_APB2ENCR_SPI5ENC_Pos) /*!< 0x00100000 */
#define RCC_APB2ENCR_SPI5ENC RCC_APB2ENCR_SPI5ENC_Msk /*!< SPI5 enable */
#define RCC_APB2ENCR_SAI1ENC_Pos (21U)
#define RCC_APB2ENCR_SAI1ENC_Msk (0x1UL << RCC_APB2ENCR_SAI1ENC_Pos) /*!< 0x00200000 */
#define RCC_APB2ENCR_SAI1ENC RCC_APB2ENCR_SAI1ENC_Msk /*!< SAI1 enable */
#define RCC_APB2ENCR_SAI2ENC_Pos (22U)
#define RCC_APB2ENCR_SAI2ENC_Msk (0x1UL << RCC_APB2ENCR_SAI2ENC_Pos) /*!< 0x00400000 */
#define RCC_APB2ENCR_SAI2ENC RCC_APB2ENCR_SAI2ENC_Msk /*!< SAI2 enable */
/***************** Bit definition for RCC_APB3ENCR register *****************/
#define RCC_APB3ENCR_DFTENC_Pos (2U)
#define RCC_APB3ENCR_DFTENC_Msk (0x1UL << RCC_APB3ENCR_DFTENC_Pos) /*!< 0x00000004 */
#define RCC_APB3ENCR_DFTENC RCC_APB3ENCR_DFTENC_Msk /*!< DFT enable */
/**************** Bit definition for RCC_APB4ENCR1 register *****************/
#define RCC_APB4ENCR1_HDPENC_Pos (2U)
#define RCC_APB4ENCR1_HDPENC_Msk (0x1UL << RCC_APB4ENCR1_HDPENC_Pos) /*!< 0x00000004 */
#define RCC_APB4ENCR1_HDPENC RCC_APB4ENCR1_HDPENC_Msk /*!< HDP enable */
#define RCC_APB4ENCR1_LPUART1ENC_Pos (3U)
#define RCC_APB4ENCR1_LPUART1ENC_Msk (0x1UL << RCC_APB4ENCR1_LPUART1ENC_Pos) /*!< 0x00000008 */
#define RCC_APB4ENCR1_LPUART1ENC RCC_APB4ENCR1_LPUART1ENC_Msk /*!< LPUART1 enable */
#define RCC_APB4ENCR1_SPI6ENC_Pos (5U)
#define RCC_APB4ENCR1_SPI6ENC_Msk (0x1UL << RCC_APB4ENCR1_SPI6ENC_Pos) /*!< 0x00000020 */
#define RCC_APB4ENCR1_SPI6ENC RCC_APB4ENCR1_SPI6ENC_Msk /*!< SPI6 enable */
#define RCC_APB4ENCR1_I2C4ENC_Pos (7U)
#define RCC_APB4ENCR1_I2C4ENC_Msk (0x1UL << RCC_APB4ENCR1_I2C4ENC_Pos) /*!< 0x00000080 */
#define RCC_APB4ENCR1_I2C4ENC RCC_APB4ENCR1_I2C4ENC_Msk /*!< I2C4 enable */
#define RCC_APB4ENCR1_LPTIM2ENC_Pos (9U)
#define RCC_APB4ENCR1_LPTIM2ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM2ENC_Pos)/*!< 0x00000200 */
#define RCC_APB4ENCR1_LPTIM2ENC RCC_APB4ENCR1_LPTIM2ENC_Msk /*!< LPTIM2 enable */
#define RCC_APB4ENCR1_LPTIM3ENC_Pos (10U)
#define RCC_APB4ENCR1_LPTIM3ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM3ENC_Pos)/*!< 0x00000400 */
#define RCC_APB4ENCR1_LPTIM3ENC RCC_APB4ENCR1_LPTIM3ENC_Msk /*!< LPTIM3 enable */
#define RCC_APB4ENCR1_LPTIM4ENC_Pos (11U)
#define RCC_APB4ENCR1_LPTIM4ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM4ENC_Pos)/*!< 0x00000800 */
#define RCC_APB4ENCR1_LPTIM4ENC RCC_APB4ENCR1_LPTIM4ENC_Msk /*!< LPTIM4 enable */
#define RCC_APB4ENCR1_LPTIM5ENC_Pos (12U)
#define RCC_APB4ENCR1_LPTIM5ENC_Msk (0x1UL << RCC_APB4ENCR1_LPTIM5ENC_Pos)/*!< 0x00001000 */
#define RCC_APB4ENCR1_LPTIM5ENC RCC_APB4ENCR1_LPTIM5ENC_Msk /*!< LPTIM5 enable */
#define RCC_APB4ENCR1_VREFBUFENC_Pos (15U)
#define RCC_APB4ENCR1_VREFBUFENC_Msk (0x1UL << RCC_APB4ENCR1_VREFBUFENC_Pos) /*!< 0x00008000 */
#define RCC_APB4ENCR1_VREFBUFENC RCC_APB4ENCR1_VREFBUFENC_Msk /*!< VREFBUF enable */
#define RCC_APB4ENCR1_RTCENC_Pos (16U)
#define RCC_APB4ENCR1_RTCENC_Msk (0x1UL << RCC_APB4ENCR1_RTCENC_Pos) /*!< 0x00010000 */
#define RCC_APB4ENCR1_RTCENC RCC_APB4ENCR1_RTCENC_Msk /*!< RTC enable */
#define RCC_APB4ENCR1_RTCAPBENC_Pos (17U)
#define RCC_APB4ENCR1_RTCAPBENC_Msk (0x1UL << RCC_APB4ENCR1_RTCAPBENC_Pos)/*!< 0x00020000 */
#define RCC_APB4ENCR1_RTCAPBENC RCC_APB4ENCR1_RTCAPBENC_Msk /*!< RTCAPB enable */
/**************** Bit definition for RCC_APB4ENCR2 register *****************/
#define RCC_APB4ENCR2_SYSCFGENC_Pos (0U)
#define RCC_APB4ENCR2_SYSCFGENC_Msk (0x1UL << RCC_APB4ENCR2_SYSCFGENC_Pos)/*!< 0x00000001 */
#define RCC_APB4ENCR2_SYSCFGENC RCC_APB4ENCR2_SYSCFGENC_Msk /*!< SYSCFG enable */
#define RCC_APB4ENCR2_BSECENC_Pos (1U)
#define RCC_APB4ENCR2_BSECENC_Msk (0x1UL << RCC_APB4ENCR2_BSECENC_Pos) /*!< 0x00000002 */
#define RCC_APB4ENCR2_BSECENC RCC_APB4ENCR2_BSECENC_Msk /*!< BSEC enable */
#define RCC_APB4ENCR2_DTSENC_Pos (2U)
#define RCC_APB4ENCR2_DTSENC_Msk (0x1UL << RCC_APB4ENCR2_DTSENC_Pos) /*!< 0x00000004 */
#define RCC_APB4ENCR2_DTSENC RCC_APB4ENCR2_DTSENC_Msk /*!< DTS enable */
/***************** Bit definition for RCC_APB5ENCR register *****************/
#define RCC_APB5ENCR_LTDCENC_Pos (1U)
#define RCC_APB5ENCR_LTDCENC_Msk (0x1UL << RCC_APB5ENCR_LTDCENC_Pos) /*!< 0x00000002 */
#define RCC_APB5ENCR_LTDCENC RCC_APB5ENCR_LTDCENC_Msk /*!< LTDC enable */
#define RCC_APB5ENCR_DCMIPPENC_Pos (2U)
#define RCC_APB5ENCR_DCMIPPENC_Msk (0x1UL << RCC_APB5ENCR_DCMIPPENC_Pos) /*!< 0x00000004 */
#define RCC_APB5ENCR_DCMIPPENC RCC_APB5ENCR_DCMIPPENC_Msk /*!< DCMIPP enable */
#define RCC_APB5ENCR_GFXTIMENC_Pos (4U)
#define RCC_APB5ENCR_GFXTIMENC_Msk (0x1UL << RCC_APB5ENCR_GFXTIMENC_Pos) /*!< 0x00000010 */
#define RCC_APB5ENCR_GFXTIMENC RCC_APB5ENCR_GFXTIMENC_Msk /*!< GFXTIM enable */
#define RCC_APB5ENCR_VENCENC_Pos (5U)
#define RCC_APB5ENCR_VENCENC_Msk (0x1UL << RCC_APB5ENCR_VENCENC_Pos) /*!< 0x00000020 */
#define RCC_APB5ENCR_VENCENC RCC_APB5ENCR_VENCENC_Msk /*!< VENC enable */
#define RCC_APB5ENCR_CSIENC_Pos (6U)
#define RCC_APB5ENCR_CSIENC_Msk (0x1UL << RCC_APB5ENCR_CSIENC_Pos) /*!< 0x00000040 */
#define RCC_APB5ENCR_CSIENC RCC_APB5ENCR_CSIENC_Msk /*!< CSI enable */
/**************** Bit definition for RCC_BUSLPENCR register *****************/
#define RCC_BUSLPENCR_ACLKNLPENC_Pos (0U)
#define RCC_BUSLPENCR_ACLKNLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNLPENC_Pos) /*!< 0x00000001 */
#define RCC_BUSLPENCR_ACLKNLPENC RCC_BUSLPENCR_ACLKNLPENC_Msk /*!< ACLKN enable in Sleep mode */
#define RCC_BUSLPENCR_ACLKNCLPENC_Pos (1U)
#define RCC_BUSLPENCR_ACLKNCLPENC_Msk (0x1UL << RCC_BUSLPENCR_ACLKNCLPENC_Pos) /*!< 0x00000002 */
#define RCC_BUSLPENCR_ACLKNCLPENC RCC_BUSLPENCR_ACLKNCLPENC_Msk /*!< ACLKNC enable in Sleep mode */
/**************** Bit definition for RCC_MISCLPENCR register ****************/
#define RCC_MISCLPENCR_DBGLPENC_Pos (0U)
#define RCC_MISCLPENCR_DBGLPENC_Msk (0x1UL << RCC_MISCLPENCR_DBGLPENC_Pos)/*!< 0x00000001 */
#define RCC_MISCLPENCR_DBGLPENC RCC_MISCLPENCR_DBGLPENC_Msk /*!< DBG enable in Sleep mode */
#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos (3U)
#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk (0x1UL << RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Pos) /*!< 0x00000008 */
#define RCC_MISCLPENCR_XSPIPHYCOMPLPENC RCC_MISCLPENCR_XSPIPHYCOMPLPENC_Msk /*!< XSPIPHYCOMP enable in Sleep mode */
#define RCC_MISCLPENCR_PERLPENC_Pos (6U)
#define RCC_MISCLPENCR_PERLPENC_Msk (0x1UL << RCC_MISCLPENCR_PERLPENC_Pos)/*!< 0x00000040 */
#define RCC_MISCLPENCR_PERLPENC RCC_MISCLPENCR_PERLPENC_Msk /*!< PER enable in Sleep mode */
/**************** Bit definition for RCC_MEMLPENCR register *****************/
#define RCC_MEMLPENCR_AXISRAM3LPENC_Pos (0U)
#define RCC_MEMLPENCR_AXISRAM3LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM3LPENC_Pos) /*!< 0x00000001 */
#define RCC_MEMLPENCR_AXISRAM3LPENC RCC_MEMLPENCR_AXISRAM3LPENC_Msk /*!< AXISRAM3 enable in Sleep mode */
#define RCC_MEMLPENCR_AXISRAM4LPENC_Pos (1U)
#define RCC_MEMLPENCR_AXISRAM4LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM4LPENC_Pos) /*!< 0x00000002 */
#define RCC_MEMLPENCR_AXISRAM4LPENC RCC_MEMLPENCR_AXISRAM4LPENC_Msk /*!< AXISRAM4 enable in Sleep mode */
#define RCC_MEMLPENCR_AXISRAM5LPENC_Pos (2U)
#define RCC_MEMLPENCR_AXISRAM5LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM5LPENC_Pos) /*!< 0x00000004 */
#define RCC_MEMLPENCR_AXISRAM5LPENC RCC_MEMLPENCR_AXISRAM5LPENC_Msk /*!< AXISRAM5 enable in Sleep mode */
#define RCC_MEMLPENCR_AXISRAM6LPENC_Pos (3U)
#define RCC_MEMLPENCR_AXISRAM6LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM6LPENC_Pos) /*!< 0x00000008 */
#define RCC_MEMLPENCR_AXISRAM6LPENC RCC_MEMLPENCR_AXISRAM6LPENC_Msk /*!< AXISRAM6 enable in Sleep mode */
#define RCC_MEMLPENCR_AHBSRAM1LPENC_Pos (4U)
#define RCC_MEMLPENCR_AHBSRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM1LPENC_Pos) /*!< 0x00000010 */
#define RCC_MEMLPENCR_AHBSRAM1LPENC RCC_MEMLPENCR_AHBSRAM1LPENC_Msk /*!< AHBSRAM1 enable in Sleep mode */
#define RCC_MEMLPENCR_AHBSRAM2LPENC_Pos (5U)
#define RCC_MEMLPENCR_AHBSRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AHBSRAM2LPENC_Pos) /*!< 0x00000020 */
#define RCC_MEMLPENCR_AHBSRAM2LPENC RCC_MEMLPENCR_AHBSRAM2LPENC_Msk /*!< AHBSRAM2 enable in Sleep mode */
#define RCC_MEMLPENCR_BKPSRAMLPENC_Pos (6U)
#define RCC_MEMLPENCR_BKPSRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BKPSRAMLPENC_Pos) /*!< 0x00000040 */
#define RCC_MEMLPENCR_BKPSRAMLPENC RCC_MEMLPENCR_BKPSRAMLPENC_Msk /*!< BKPSRAM enable in Sleep mode */
#define RCC_MEMLPENCR_AXISRAM1LPENC_Pos (7U)
#define RCC_MEMLPENCR_AXISRAM1LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM1LPENC_Pos) /*!< 0x00000080 */
#define RCC_MEMLPENCR_AXISRAM1LPENC RCC_MEMLPENCR_AXISRAM1LPENC_Msk /*!< AXISRAM1 enable in Sleep mode */
#define RCC_MEMLPENCR_AXISRAM2LPENC_Pos (8U)
#define RCC_MEMLPENCR_AXISRAM2LPENC_Msk (0x1UL << RCC_MEMLPENCR_AXISRAM2LPENC_Pos) /*!< 0x00000100 */
#define RCC_MEMLPENCR_AXISRAM2LPENC RCC_MEMLPENCR_AXISRAM2LPENC_Msk /*!< AXISRAM2 enable in Sleep mode */
#define RCC_MEMLPENCR_FLEXRAMLPENC_Pos (9U)
#define RCC_MEMLPENCR_FLEXRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_FLEXRAMLPENC_Pos) /*!< 0x00000200 */
#define RCC_MEMLPENCR_FLEXRAMLPENC RCC_MEMLPENCR_FLEXRAMLPENC_Msk /*!< FLEXRAM enable in Sleep mode */
#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos (10U)
#define RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_CACHEAXIRAMLPENC_Pos) /*!< 0x00000400 */
#define RCC_MEMLPENCR_CACHEAXIRAMLPENC RCC_MEMLPENCR_CACHEAXIRAMLPENC_Msk /*!< CACHEAXIRAM enable in Sleep mode */
#define RCC_MEMLPENCR_VENCRAMLPENC_Pos (11U)
#define RCC_MEMLPENCR_VENCRAMLPENC_Msk (0x1UL << RCC_MEMLPENCR_VENCRAMLPENC_Pos) /*!< 0x00000800 */
#define RCC_MEMLPENCR_VENCRAMLPENC RCC_MEMLPENCR_VENCRAMLPENC_Msk /*!< VENCRAM enable in Sleep mode */
#define RCC_MEMLPENCR_BOOTROMLPENC_Pos (12U)
#define RCC_MEMLPENCR_BOOTROMLPENC_Msk (0x1UL << RCC_MEMLPENCR_BOOTROMLPENC_Pos) /*!< 0x00001000 */
#define RCC_MEMLPENCR_BOOTROMLPENC RCC_MEMLPENCR_BOOTROMLPENC_Msk /*!< Boot ROM enable in Sleep mode */
/**************** Bit definition for RCC_AHB1LPENCR register ****************/
#define RCC_AHB1LPENCR_GPDMA1LPENC_Pos (4U)
#define RCC_AHB1LPENCR_GPDMA1LPENC_Msk (0x1UL << RCC_AHB1LPENCR_GPDMA1LPENC_Pos) /*!< 0x00000010 */
#define RCC_AHB1LPENCR_GPDMA1LPENC RCC_AHB1LPENCR_GPDMA1LPENC_Msk /*!< GPDMA1 enable in Sleep mode */
#define RCC_AHB1LPENCR_ADC12LPENC_Pos (5U)
#define RCC_AHB1LPENCR_ADC12LPENC_Msk (0x1UL << RCC_AHB1LPENCR_ADC12LPENC_Pos) /*!< 0x00000020 */
#define RCC_AHB1LPENCR_ADC12LPENC RCC_AHB1LPENCR_ADC12LPENC_Msk /*!< ADC12 enable in Sleep mode */
/**************** Bit definition for RCC_AHB2LPENCR register ****************/
#define RCC_AHB2LPENCR_RAMCFGLPENC_Pos (12U)
#define RCC_AHB2LPENCR_RAMCFGLPENC_Msk (0x1UL << RCC_AHB2LPENCR_RAMCFGLPENC_Pos) /*!< 0x00001000 */
#define RCC_AHB2LPENCR_RAMCFGLPENC RCC_AHB2LPENCR_RAMCFGLPENC_Msk /*!< RAMCFG enable in Sleep mode */
#define RCC_AHB2LPENCR_MDF1LPENC_Pos (16U)
#define RCC_AHB2LPENCR_MDF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_MDF1LPENC_Pos) /*!< 0x00010000 */
#define RCC_AHB2LPENCR_MDF1LPENC RCC_AHB2LPENCR_MDF1LPENC_Msk /*!< MDF1 enable in Sleep mode */
#define RCC_AHB2LPENCR_ADF1LPENC_Pos (17U)
#define RCC_AHB2LPENCR_ADF1LPENC_Msk (0x1UL << RCC_AHB2LPENCR_ADF1LPENC_Pos) /*!< 0x00020000 */
#define RCC_AHB2LPENCR_ADF1LPENC RCC_AHB2LPENCR_ADF1LPENC_Msk /*!< ADF1 enable in Sleep mode */
/**************** Bit definition for RCC_AHB3LPENCR register ****************/
#define RCC_AHB3LPENCR_RNGLPENC_Pos (0U)
#define RCC_AHB3LPENCR_RNGLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RNGLPENC_Pos)/*!< 0x00000001 */
#define RCC_AHB3LPENCR_RNGLPENC RCC_AHB3LPENCR_RNGLPENC_Msk /*!< RNG enable in Sleep mode */
#define RCC_AHB3LPENCR_HASHLPENC_Pos (1U)
#define RCC_AHB3LPENCR_HASHLPENC_Msk (0x1UL << RCC_AHB3LPENCR_HASHLPENC_Pos) /*!< 0x00000002 */
#define RCC_AHB3LPENCR_HASHLPENC RCC_AHB3LPENCR_HASHLPENC_Msk /*!< HASH enable in Sleep mode */
#define RCC_AHB3LPENCR_CRYPLPENC_Pos (2U)
#define RCC_AHB3LPENCR_CRYPLPENC_Msk (0x1UL << RCC_AHB3LPENCR_CRYPLPENC_Pos) /*!< 0x00000004 */
#define RCC_AHB3LPENCR_CRYPLPENC RCC_AHB3LPENCR_CRYPLPENC_Msk /*!< CRYP enable in Sleep mode */
#define RCC_AHB3LPENCR_SAESLPENC_Pos (4U)
#define RCC_AHB3LPENCR_SAESLPENC_Msk (0x1UL << RCC_AHB3LPENCR_SAESLPENC_Pos) /*!< 0x00000010 */
#define RCC_AHB3LPENCR_SAESLPENC RCC_AHB3LPENCR_SAESLPENC_Msk /*!< SAES enable in Sleep mode */
#define RCC_AHB3LPENCR_PKALPENC_Pos (8U)
#define RCC_AHB3LPENCR_PKALPENC_Msk (0x1UL << RCC_AHB3LPENCR_PKALPENC_Pos)/*!< 0x00000100 */
#define RCC_AHB3LPENCR_PKALPENC RCC_AHB3LPENCR_PKALPENC_Msk /*!< PKA enable in Sleep mode */
#define RCC_AHB3LPENCR_RIFSCLPENC_Pos (9U)
#define RCC_AHB3LPENCR_RIFSCLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RIFSCLPENC_Pos) /*!< 0x00000200 */
#define RCC_AHB3LPENCR_RIFSCLPENC RCC_AHB3LPENCR_RIFSCLPENC_Msk /*!< RIFSC enable in Sleep mode */
#define RCC_AHB3LPENCR_IACLPENC_Pos (10U)
#define RCC_AHB3LPENCR_IACLPENC_Msk (0x1UL << RCC_AHB3LPENCR_IACLPENC_Pos)/*!< 0x00000400 */
#define RCC_AHB3LPENCR_IACLPENC RCC_AHB3LPENCR_IACLPENC_Msk /*!< IAC enable in Sleep mode */
#define RCC_AHB3LPENCR_RISAFLPENC_Pos (14U)
#define RCC_AHB3LPENCR_RISAFLPENC_Msk (0x1UL << RCC_AHB3LPENCR_RISAFLPENC_Pos) /*!< 0x00004000 */
#define RCC_AHB3LPENCR_RISAFLPENC RCC_AHB3LPENCR_RISAFLPENC_Msk /*!< RISAF enable in Sleep mode */
/**************** Bit definition for RCC_AHB4LPENCR register ****************/
#define RCC_AHB4LPENCR_GPIOALPENC_Pos (0U)
#define RCC_AHB4LPENCR_GPIOALPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOALPENC_Pos) /*!< 0x00000001 */
#define RCC_AHB4LPENCR_GPIOALPENC RCC_AHB4LPENCR_GPIOALPENC_Msk /*!< GPIO A enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOBLPENC_Pos (1U)
#define RCC_AHB4LPENCR_GPIOBLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOBLPENC_Pos) /*!< 0x00000002 */
#define RCC_AHB4LPENCR_GPIOBLPENC RCC_AHB4LPENCR_GPIOBLPENC_Msk /*!< GPIO B enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOCLPENC_Pos (2U)
#define RCC_AHB4LPENCR_GPIOCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOCLPENC_Pos) /*!< 0x00000004 */
#define RCC_AHB4LPENCR_GPIOCLPENC RCC_AHB4LPENCR_GPIOCLPENC_Msk /*!< GPIO C enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIODLPENC_Pos (3U)
#define RCC_AHB4LPENCR_GPIODLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIODLPENC_Pos) /*!< 0x00000008 */
#define RCC_AHB4LPENCR_GPIODLPENC RCC_AHB4LPENCR_GPIODLPENC_Msk /*!< GPIO D enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOELPENC_Pos (4U)
#define RCC_AHB4LPENCR_GPIOELPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOELPENC_Pos) /*!< 0x00000010 */
#define RCC_AHB4LPENCR_GPIOELPENC RCC_AHB4LPENCR_GPIOELPENC_Msk /*!< GPIO E enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOFLPENC_Pos (5U)
#define RCC_AHB4LPENCR_GPIOFLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOFLPENC_Pos) /*!< 0x00000020 */
#define RCC_AHB4LPENCR_GPIOFLPENC RCC_AHB4LPENCR_GPIOFLPENC_Msk /*!< GPIO F enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOGLPENC_Pos (6U)
#define RCC_AHB4LPENCR_GPIOGLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOGLPENC_Pos) /*!< 0x00000040 */
#define RCC_AHB4LPENCR_GPIOGLPENC RCC_AHB4LPENCR_GPIOGLPENC_Msk /*!< GPIO G enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOHLPENC_Pos (7U)
#define RCC_AHB4LPENCR_GPIOHLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOHLPENC_Pos) /*!< 0x00000080 */
#define RCC_AHB4LPENCR_GPIOHLPENC RCC_AHB4LPENCR_GPIOHLPENC_Msk /*!< GPIO H enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIONLPENC_Pos (13U)
#define RCC_AHB4LPENCR_GPIONLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIONLPENC_Pos) /*!< 0x00002000 */
#define RCC_AHB4LPENCR_GPIONLPENC RCC_AHB4LPENCR_GPIONLPENC_Msk /*!< GPIO N enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOOLPENC_Pos (14U)
#define RCC_AHB4LPENCR_GPIOOLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOOLPENC_Pos) /*!< 0x00004000 */
#define RCC_AHB4LPENCR_GPIOOLPENC RCC_AHB4LPENCR_GPIOOLPENC_Msk /*!< GPIO O enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOPLPENC_Pos (15U)
#define RCC_AHB4LPENCR_GPIOPLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOPLPENC_Pos) /*!< 0x00008000 */
#define RCC_AHB4LPENCR_GPIOPLPENC RCC_AHB4LPENCR_GPIOPLPENC_Msk /*!< GPIO P enable in Sleep mode */
#define RCC_AHB4LPENCR_GPIOQLPENC_Pos (16U)
#define RCC_AHB4LPENCR_GPIOQLPENC_Msk (0x1UL << RCC_AHB4LPENCR_GPIOQLPENC_Pos) /*!< 0x00010000 */
#define RCC_AHB4LPENCR_GPIOQLPENC RCC_AHB4LPENCR_GPIOQLPENC_Msk /*!< GPIO Q enable in Sleep mode */
#define RCC_AHB4LPENCR_PWRLPENC_Pos (18U)
#define RCC_AHB4LPENCR_PWRLPENC_Msk (0x1UL << RCC_AHB4LPENCR_PWRLPENC_Pos)/*!< 0x00040000 */
#define RCC_AHB4LPENCR_PWRLPENC RCC_AHB4LPENCR_PWRLPENC_Msk /*!< PWR enable in Sleep mode */
#define RCC_AHB4LPENCR_CRCLPENC_Pos (19U)
#define RCC_AHB4LPENCR_CRCLPENC_Msk (0x1UL << RCC_AHB4LPENCR_CRCLPENC_Pos)/*!< 0x00080000 */
#define RCC_AHB4LPENCR_CRCLPENC RCC_AHB4LPENCR_CRCLPENC_Msk /*!< CRC enable in Sleep mode */
/**************** Bit definition for RCC_AHB5LPENCR register ****************/
#define RCC_AHB5LPENCR_HPDMA1LPENC_Pos (0U)
#define RCC_AHB5LPENCR_HPDMA1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_HPDMA1LPENC_Pos) /*!< 0x00000001 */
#define RCC_AHB5LPENCR_HPDMA1LPENC RCC_AHB5LPENCR_HPDMA1LPENC_Msk /*!< HPDMA1 enable in Sleep mode */
#define RCC_AHB5LPENCR_DMA2DLPENC_Pos (1U)
#define RCC_AHB5LPENCR_DMA2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_DMA2DLPENC_Pos) /*!< 0x00000002 */
#define RCC_AHB5LPENCR_DMA2DLPENC RCC_AHB5LPENCR_DMA2DLPENC_Msk /*!< DMA2D enable in Sleep mode */
#define RCC_AHB5LPENCR_JPEGLPENC_Pos (3U)
#define RCC_AHB5LPENCR_JPEGLPENC_Msk (0x1UL << RCC_AHB5LPENCR_JPEGLPENC_Pos) /*!< 0x00000008 */
#define RCC_AHB5LPENCR_JPEGLPENC RCC_AHB5LPENCR_JPEGLPENC_Msk /*!< JPEG enable in Sleep mode */
#define RCC_AHB5LPENCR_FMCLPENC_Pos (4U)
#define RCC_AHB5LPENCR_FMCLPENC_Msk (0x1UL << RCC_AHB5LPENCR_FMCLPENC_Pos)/*!< 0x00000010 */
#define RCC_AHB5LPENCR_FMCLPENC RCC_AHB5LPENCR_FMCLPENC_Msk /*!< FMC enable in Sleep mode */
#define RCC_AHB5LPENCR_XSPI1LPENC_Pos (5U)
#define RCC_AHB5LPENCR_XSPI1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI1LPENC_Pos) /*!< 0x00000020 */
#define RCC_AHB5LPENCR_XSPI1LPENC RCC_AHB5LPENCR_XSPI1LPENC_Msk /*!< XSPI1 enable in Sleep mode */
#define RCC_AHB5LPENCR_PSSILPENC_Pos (6U)
#define RCC_AHB5LPENCR_PSSILPENC_Msk (0x1UL << RCC_AHB5LPENCR_PSSILPENC_Pos) /*!< 0x00000040 */
#define RCC_AHB5LPENCR_PSSILPENC RCC_AHB5LPENCR_PSSILPENC_Msk /*!< PSSI enable in Sleep mode */
#define RCC_AHB5LPENCR_SDMMC2LPENC_Pos (7U)
#define RCC_AHB5LPENCR_SDMMC2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC2LPENC_Pos) /*!< 0x00000080 */
#define RCC_AHB5LPENCR_SDMMC2LPENC RCC_AHB5LPENCR_SDMMC2LPENC_Msk /*!< SDMMC2 enable in Sleep mode */
#define RCC_AHB5LPENCR_SDMMC1LPENC_Pos (8U)
#define RCC_AHB5LPENCR_SDMMC1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_SDMMC1LPENC_Pos) /*!< 0x00000100 */
#define RCC_AHB5LPENCR_SDMMC1LPENC RCC_AHB5LPENCR_SDMMC1LPENC_Msk /*!< SDMMC1 enable in Sleep mode */
#define RCC_AHB5LPENCR_XSPI2LPENC_Pos (12U)
#define RCC_AHB5LPENCR_XSPI2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI2LPENC_Pos) /*!< 0x00001000 */
#define RCC_AHB5LPENCR_XSPI2LPENC RCC_AHB5LPENCR_XSPI2LPENC_Msk /*!< XSPI2 enable in Sleep mode */
#define RCC_AHB5LPENCR_XSPIMLPENC_Pos (13U)
#define RCC_AHB5LPENCR_XSPIMLPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPIMLPENC_Pos) /*!< 0x00002000 */
#define RCC_AHB5LPENCR_XSPIMLPENC RCC_AHB5LPENCR_XSPIMLPENC_Msk /*!< XSPIM enable in Sleep mode */
#define RCC_AHB5LPENCR_MCE1LPENC_Pos (14U)
#define RCC_AHB5LPENCR_MCE1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE1LPENC_Pos) /*!< 0x00004000 */
#define RCC_AHB5LPENCR_MCE1LPENC RCC_AHB5LPENCR_MCE1LPENC_Msk /*!< MCE1 enable in Sleep mode */
#define RCC_AHB5LPENCR_MCE2LPENC_Pos (15U)
#define RCC_AHB5LPENCR_MCE2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE2LPENC_Pos) /*!< 0x00008000 */
#define RCC_AHB5LPENCR_MCE2LPENC RCC_AHB5LPENCR_MCE2LPENC_Msk /*!< MCE2 enable in Sleep mode */
#define RCC_AHB5LPENCR_MCE3LPENC_Pos (16U)
#define RCC_AHB5LPENCR_MCE3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE3LPENC_Pos) /*!< 0x00010000 */
#define RCC_AHB5LPENCR_MCE3LPENC RCC_AHB5LPENCR_MCE3LPENC_Msk /*!< MCE3 enable in Sleep mode */
#define RCC_AHB5LPENCR_XSPI3LPENC_Pos (17U)
#define RCC_AHB5LPENCR_XSPI3LPENC_Msk (0x1UL << RCC_AHB5LPENCR_XSPI3LPENC_Pos) /*!< 0x00020000 */
#define RCC_AHB5LPENCR_XSPI3LPENC RCC_AHB5LPENCR_XSPI3LPENC_Msk /*!< XSPI3 enable in Sleep mode */
#define RCC_AHB5LPENCR_MCE4LPENC_Pos (18U)
#define RCC_AHB5LPENCR_MCE4LPENC_Msk (0x1UL << RCC_AHB5LPENCR_MCE4LPENC_Pos) /*!< 0x00040000 */
#define RCC_AHB5LPENCR_MCE4LPENC RCC_AHB5LPENCR_MCE4LPENC_Msk /*!< MCE4 enable in Sleep mode */
#define RCC_AHB5LPENCR_GFXMMULPENC_Pos (19U)
#define RCC_AHB5LPENCR_GFXMMULPENC_Msk (0x1UL << RCC_AHB5LPENCR_GFXMMULPENC_Pos) /*!< 0x00080000 */
#define RCC_AHB5LPENCR_GFXMMULPENC RCC_AHB5LPENCR_GFXMMULPENC_Msk /*!< GFXMMU enable in Sleep mode */
#define RCC_AHB5LPENCR_GPU2DLPENC_Pos (20U)
#define RCC_AHB5LPENCR_GPU2DLPENC_Msk (0x1UL << RCC_AHB5LPENCR_GPU2DLPENC_Pos) /*!< 0x00100000 */
#define RCC_AHB5LPENCR_GPU2DLPENC RCC_AHB5LPENCR_GPU2DLPENC_Msk /*!< GPU2D enable in Sleep mode */
#define RCC_AHB5LPENCR_ETH1MACLPENC_Pos (22U)
#define RCC_AHB5LPENCR_ETH1MACLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1MACLPENC_Pos) /*!< 0x00400000 */
#define RCC_AHB5LPENCR_ETH1MACLPENC RCC_AHB5LPENCR_ETH1MACLPENC_Msk /*!< ETH1MAC enable in Sleep mode */
#define RCC_AHB5LPENCR_ETH1TXLPENC_Pos (23U)
#define RCC_AHB5LPENCR_ETH1TXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1TXLPENC_Pos) /*!< 0x00800000 */
#define RCC_AHB5LPENCR_ETH1TXLPENC RCC_AHB5LPENCR_ETH1TXLPENC_Msk /*!< ETH1TX enable in Sleep mode */
#define RCC_AHB5LPENCR_ETH1RXLPENC_Pos (24U)
#define RCC_AHB5LPENCR_ETH1RXLPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1RXLPENC_Pos) /*!< 0x01000000 */
#define RCC_AHB5LPENCR_ETH1RXLPENC RCC_AHB5LPENCR_ETH1RXLPENC_Msk /*!< ETH1RX enable in Sleep mode */
#define RCC_AHB5LPENCR_ETH1LPENC_Pos (25U)
#define RCC_AHB5LPENCR_ETH1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_ETH1LPENC_Pos) /*!< 0x02000000 */
#define RCC_AHB5LPENCR_ETH1LPENC RCC_AHB5LPENCR_ETH1LPENC_Msk /*!< ETH1 enable in Sleep mode */
#define RCC_AHB5LPENCR_OTG1LPENC_Pos (26U)
#define RCC_AHB5LPENCR_OTG1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG1LPENC_Pos) /*!< 0x04000000 */
#define RCC_AHB5LPENCR_OTG1LPENC RCC_AHB5LPENCR_OTG1LPENC_Msk /*!< OTG1 enable in Sleep mode */
#define RCC_AHB5LPENCR_OTGPHY1LPENC_Pos (27U)
#define RCC_AHB5LPENCR_OTGPHY1LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY1LPENC_Pos) /*!< 0x08000000 */
#define RCC_AHB5LPENCR_OTGPHY1LPENC RCC_AHB5LPENCR_OTGPHY1LPENC_Msk /*!< OTGPHY1 enable in Sleep mode */
#define RCC_AHB5LPENCR_OTGPHY2LPENC_Pos (28U)
#define RCC_AHB5LPENCR_OTGPHY2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTGPHY2LPENC_Pos) /*!< 0x10000000 */
#define RCC_AHB5LPENCR_OTGPHY2LPENC RCC_AHB5LPENCR_OTGPHY2LPENC_Msk /*!< OTGPHY2 enable in Sleep mode */
#define RCC_AHB5LPENCR_OTG2LPENC_Pos (29U)
#define RCC_AHB5LPENCR_OTG2LPENC_Msk (0x1UL << RCC_AHB5LPENCR_OTG2LPENC_Pos) /*!< 0x20000000 */
#define RCC_AHB5LPENCR_OTG2LPENC RCC_AHB5LPENCR_OTG2LPENC_Msk /*!< OTG2 enable in Sleep mode */
#define RCC_AHB5LPENCR_CACHEAXILPENC_Pos (30U)
#define RCC_AHB5LPENCR_CACHEAXILPENC_Msk (0x1UL << RCC_AHB5LPENCR_CACHEAXILPENC_Pos) /*!< 0x40000000 */
#define RCC_AHB5LPENCR_CACHEAXILPENC RCC_AHB5LPENCR_CACHEAXILPENC_Msk /*!< CACHEAXI enable in Sleep mode */
#define RCC_AHB5LPENCR_NPULPENC_Pos (31U)
#define RCC_AHB5LPENCR_NPULPENC_Msk (0x1UL << RCC_AHB5LPENCR_NPULPENC_Pos)/*!< 0x80000000 */
#define RCC_AHB5LPENCR_NPULPENC RCC_AHB5LPENCR_NPULPENC_Msk /*!< NPU enable in Sleep mode */
/*************** Bit definition for RCC_APB1LPENCR1 register ****************/
#define RCC_APB1LPENCR1_TIM2LPENC_Pos (0U)
#define RCC_APB1LPENCR1_TIM2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM2LPENC_Pos) /*!< 0x00000001 */
#define RCC_APB1LPENCR1_TIM2LPENC RCC_APB1LPENCR1_TIM2LPENC_Msk /*!< TIM2 enable */
#define RCC_APB1LPENCR1_TIM3LPENC_Pos (1U)
#define RCC_APB1LPENCR1_TIM3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM3LPENC_Pos) /*!< 0x00000002 */
#define RCC_APB1LPENCR1_TIM3LPENC RCC_APB1LPENCR1_TIM3LPENC_Msk /*!< TIM3 enable */
#define RCC_APB1LPENCR1_TIM4LPENC_Pos (2U)
#define RCC_APB1LPENCR1_TIM4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM4LPENC_Pos) /*!< 0x00000004 */
#define RCC_APB1LPENCR1_TIM4LPENC RCC_APB1LPENCR1_TIM4LPENC_Msk /*!< TIM4 enable */
#define RCC_APB1LPENCR1_TIM5LPENC_Pos (3U)
#define RCC_APB1LPENCR1_TIM5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM5LPENC_Pos) /*!< 0x00000008 */
#define RCC_APB1LPENCR1_TIM5LPENC RCC_APB1LPENCR1_TIM5LPENC_Msk /*!< TIM5 enable */
#define RCC_APB1LPENCR1_TIM6LPENC_Pos (4U)
#define RCC_APB1LPENCR1_TIM6LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM6LPENC_Pos) /*!< 0x00000010 */
#define RCC_APB1LPENCR1_TIM6LPENC RCC_APB1LPENCR1_TIM6LPENC_Msk /*!< TIM6 enable */
#define RCC_APB1LPENCR1_TIM7LPENC_Pos (5U)
#define RCC_APB1LPENCR1_TIM7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM7LPENC_Pos) /*!< 0x00000020 */
#define RCC_APB1LPENCR1_TIM7LPENC RCC_APB1LPENCR1_TIM7LPENC_Msk /*!< TIM7 enable */
#define RCC_APB1LPENCR1_TIM12LPENC_Pos (6U)
#define RCC_APB1LPENCR1_TIM12LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM12LPENC_Pos) /*!< 0x00000040 */
#define RCC_APB1LPENCR1_TIM12LPENC RCC_APB1LPENCR1_TIM12LPENC_Msk /*!< TIM12 enable */
#define RCC_APB1LPENCR1_TIM13LPENC_Pos (7U)
#define RCC_APB1LPENCR1_TIM13LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM13LPENC_Pos) /*!< 0x00000080 */
#define RCC_APB1LPENCR1_TIM13LPENC RCC_APB1LPENCR1_TIM13LPENC_Msk /*!< TIM13 enable */
#define RCC_APB1LPENCR1_TIM14LPENC_Pos (8U)
#define RCC_APB1LPENCR1_TIM14LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM14LPENC_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENCR1_TIM14LPENC RCC_APB1LPENCR1_TIM14LPENC_Msk /*!< TIM14 enable */
#define RCC_APB1LPENCR1_LPTIM1LPENC_Pos (9U)
#define RCC_APB1LPENCR1_LPTIM1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_LPTIM1LPENC_Pos) /*!< 0x00000200 */
#define RCC_APB1LPENCR1_LPTIM1LPENC RCC_APB1LPENCR1_LPTIM1LPENC_Msk /*!< LPTIM1 enable */
#define RCC_APB1LPENCR1_WWDGLPENC_Pos (11U)
#define RCC_APB1LPENCR1_WWDGLPENC_Msk (0x1UL << RCC_APB1LPENCR1_WWDGLPENC_Pos) /*!< 0x00000800 */
#define RCC_APB1LPENCR1_WWDGLPENC RCC_APB1LPENCR1_WWDGLPENC_Msk /*!< WWDG enable */
#define RCC_APB1LPENCR1_TIM10LPENC_Pos (12U)
#define RCC_APB1LPENCR1_TIM10LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM10LPENC_Pos) /*!< 0x00001000 */
#define RCC_APB1LPENCR1_TIM10LPENC RCC_APB1LPENCR1_TIM10LPENC_Msk /*!< TIM10 enable */
#define RCC_APB1LPENCR1_TIM11LPENC_Pos (13U)
#define RCC_APB1LPENCR1_TIM11LPENC_Msk (0x1UL << RCC_APB1LPENCR1_TIM11LPENC_Pos) /*!< 0x00002000 */
#define RCC_APB1LPENCR1_TIM11LPENC RCC_APB1LPENCR1_TIM11LPENC_Msk /*!< TIM11 enable */
#define RCC_APB1LPENCR1_SPI2LPENC_Pos (14U)
#define RCC_APB1LPENCR1_SPI2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI2LPENC_Pos) /*!< 0x00004000 */
#define RCC_APB1LPENCR1_SPI2LPENC RCC_APB1LPENCR1_SPI2LPENC_Msk /*!< SPI2 enable */
#define RCC_APB1LPENCR1_SPI3LPENC_Pos (15U)
#define RCC_APB1LPENCR1_SPI3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPI3LPENC_Pos) /*!< 0x00008000 */
#define RCC_APB1LPENCR1_SPI3LPENC RCC_APB1LPENCR1_SPI3LPENC_Msk /*!< SPI3 enable */
#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos (16U)
#define RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_SPDIFRX1LPENC_Pos) /*!< 0x00010000 */
#define RCC_APB1LPENCR1_SPDIFRX1LPENC RCC_APB1LPENCR1_SPDIFRX1LPENC_Msk /*!< SPDIFRX1 enable */
#define RCC_APB1LPENCR1_USART2LPENC_Pos (17U)
#define RCC_APB1LPENCR1_USART2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART2LPENC_Pos) /*!< 0x00020000 */
#define RCC_APB1LPENCR1_USART2LPENC RCC_APB1LPENCR1_USART2LPENC_Msk /*!< USART2 enable */
#define RCC_APB1LPENCR1_USART3LPENC_Pos (18U)
#define RCC_APB1LPENCR1_USART3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_USART3LPENC_Pos) /*!< 0x00040000 */
#define RCC_APB1LPENCR1_USART3LPENC RCC_APB1LPENCR1_USART3LPENC_Msk /*!< USART3 enable */
#define RCC_APB1LPENCR1_UART4LPENC_Pos (19U)
#define RCC_APB1LPENCR1_UART4LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART4LPENC_Pos) /*!< 0x00080000 */
#define RCC_APB1LPENCR1_UART4LPENC RCC_APB1LPENCR1_UART4LPENC_Msk /*!< UART4 enable */
#define RCC_APB1LPENCR1_UART5LPENC_Pos (20U)
#define RCC_APB1LPENCR1_UART5LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART5LPENC_Pos) /*!< 0x00100000 */
#define RCC_APB1LPENCR1_UART5LPENC RCC_APB1LPENCR1_UART5LPENC_Msk /*!< UART5 enable */
#define RCC_APB1LPENCR1_I2C1LPENC_Pos (21U)
#define RCC_APB1LPENCR1_I2C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C1LPENC_Pos) /*!< 0x00200000 */
#define RCC_APB1LPENCR1_I2C1LPENC RCC_APB1LPENCR1_I2C1LPENC_Msk /*!< I2C1 enable */
#define RCC_APB1LPENCR1_I2C2LPENC_Pos (22U)
#define RCC_APB1LPENCR1_I2C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C2LPENC_Pos) /*!< 0x00400000 */
#define RCC_APB1LPENCR1_I2C2LPENC RCC_APB1LPENCR1_I2C2LPENC_Msk /*!< I2C2 enable */
#define RCC_APB1LPENCR1_I2C3LPENC_Pos (23U)
#define RCC_APB1LPENCR1_I2C3LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I2C3LPENC_Pos) /*!< 0x00800000 */
#define RCC_APB1LPENCR1_I2C3LPENC RCC_APB1LPENCR1_I2C3LPENC_Msk /*!< I2C3 enable */
#define RCC_APB1LPENCR1_I3C1LPENC_Pos (24U)
#define RCC_APB1LPENCR1_I3C1LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C1LPENC_Pos) /*!< 0x01000000 */
#define RCC_APB1LPENCR1_I3C1LPENC RCC_APB1LPENCR1_I3C1LPENC_Msk /*!< I3C1 enable */
#define RCC_APB1LPENCR1_I3C2LPENC_Pos (25U)
#define RCC_APB1LPENCR1_I3C2LPENC_Msk (0x1UL << RCC_APB1LPENCR1_I3C2LPENC_Pos) /*!< 0x02000000 */
#define RCC_APB1LPENCR1_I3C2LPENC RCC_APB1LPENCR1_I3C2LPENC_Msk /*!< I3C2 enable */
#define RCC_APB1LPENCR1_UART7LPENC_Pos (30U)
#define RCC_APB1LPENCR1_UART7LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART7LPENC_Pos) /*!< 0x40000000 */
#define RCC_APB1LPENCR1_UART7LPENC RCC_APB1LPENCR1_UART7LPENC_Msk /*!< UART7 enable */
#define RCC_APB1LPENCR1_UART8LPENC_Pos (31U)
#define RCC_APB1LPENCR1_UART8LPENC_Msk (0x1UL << RCC_APB1LPENCR1_UART8LPENC_Pos) /*!< 0x80000000 */
#define RCC_APB1LPENCR1_UART8LPENC RCC_APB1LPENCR1_UART8LPENC_Msk /*!< UART8 enable */
/*************** Bit definition for RCC_APB1LPENCR2 register ****************/
#define RCC_APB1LPENCR2_MDIOSLPENC_Pos (5U)
#define RCC_APB1LPENCR2_MDIOSLPENC_Msk (0x1UL << RCC_APB1LPENCR2_MDIOSLPENC_Pos) /*!< 0x00000020 */
#define RCC_APB1LPENCR2_MDIOSLPENC RCC_APB1LPENCR2_MDIOSLPENC_Msk /*!< MDIOS enable */
#define RCC_APB1LPENCR2_FDCANLPENC_Pos (8U)
#define RCC_APB1LPENCR2_FDCANLPENC_Msk (0x1UL << RCC_APB1LPENCR2_FDCANLPENC_Pos) /*!< 0x00000100 */
#define RCC_APB1LPENCR2_FDCANLPENC RCC_APB1LPENCR2_FDCANLPENC_Msk /*!< FDCAN enable */
#define RCC_APB1LPENCR2_UCPD1LPENC_Pos (18U)
#define RCC_APB1LPENCR2_UCPD1LPENC_Msk (0x1UL << RCC_APB1LPENCR2_UCPD1LPENC_Pos) /*!< 0x00040000 */
#define RCC_APB1LPENCR2_UCPD1LPENC RCC_APB1LPENCR2_UCPD1LPENC_Msk /*!< UCPD1 enable */
/**************** Bit definition for RCC_APB2LPENCR register ****************/
#define RCC_APB2LPENCR_TIM1LPENC_Pos (0U)
#define RCC_APB2LPENCR_TIM1LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM1LPENC_Pos) /*!< 0x00000001 */
#define RCC_APB2LPENCR_TIM1LPENC RCC_APB2LPENCR_TIM1LPENC_Msk /*!< TIM1 enable */
#define RCC_APB2LPENCR_TIM8LPENC_Pos (1U)
#define RCC_APB2LPENCR_TIM8LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM8LPENC_Pos) /*!< 0x00000002 */
#define RCC_APB2LPENCR_TIM8LPENC RCC_APB2LPENCR_TIM8LPENC_Msk /*!< TIM8 enable */
#define RCC_APB2LPENCR_USART1LPENC_Pos (4U)
#define RCC_APB2LPENCR_USART1LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART1LPENC_Pos) /*!< 0x00000010 */
#define RCC_APB2LPENCR_USART1LPENC RCC_APB2LPENCR_USART1LPENC_Msk /*!< USART1 enable */
#define RCC_APB2LPENCR_USART6LPENC_Pos (5U)
#define RCC_APB2LPENCR_USART6LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART6LPENC_Pos) /*!< 0x00000020 */
#define RCC_APB2LPENCR_USART6LPENC RCC_APB2LPENCR_USART6LPENC_Msk /*!< USART6 enable */
#define RCC_APB2LPENCR_UART9LPENC_Pos (6U)
#define RCC_APB2LPENCR_UART9LPENC_Msk (0x1UL << RCC_APB2LPENCR_UART9LPENC_Pos) /*!< 0x00000040 */
#define RCC_APB2LPENCR_UART9LPENC RCC_APB2LPENCR_UART9LPENC_Msk /*!< UART9 enable */
#define RCC_APB2LPENCR_USART10LPENC_Pos (7U)
#define RCC_APB2LPENCR_USART10LPENC_Msk (0x1UL << RCC_APB2LPENCR_USART10LPENC_Pos) /*!< 0x00000080 */
#define RCC_APB2LPENCR_USART10LPENC RCC_APB2LPENCR_USART10LPENC_Msk /*!< USART10 enable */
#define RCC_APB2LPENCR_SPI1LPENC_Pos (12U)
#define RCC_APB2LPENCR_SPI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI1LPENC_Pos) /*!< 0x00001000 */
#define RCC_APB2LPENCR_SPI1LPENC RCC_APB2LPENCR_SPI1LPENC_Msk /*!< SPI1 enable */
#define RCC_APB2LPENCR_SPI4LPENC_Pos (13U)
#define RCC_APB2LPENCR_SPI4LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI4LPENC_Pos) /*!< 0x00002000 */
#define RCC_APB2LPENCR_SPI4LPENC RCC_APB2LPENCR_SPI4LPENC_Msk /*!< SPI4 enable */
#define RCC_APB2LPENCR_TIM18LPENC_Pos (15U)
#define RCC_APB2LPENCR_TIM18LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM18LPENC_Pos) /*!< 0x00008000 */
#define RCC_APB2LPENCR_TIM18LPENC RCC_APB2LPENCR_TIM18LPENC_Msk /*!< TIM18 enable */
#define RCC_APB2LPENCR_TIM15LPENC_Pos (16U)
#define RCC_APB2LPENCR_TIM15LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM15LPENC_Pos) /*!< 0x00010000 */
#define RCC_APB2LPENCR_TIM15LPENC RCC_APB2LPENCR_TIM15LPENC_Msk /*!< TIM15 enable */
#define RCC_APB2LPENCR_TIM16LPENC_Pos (17U)
#define RCC_APB2LPENCR_TIM16LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM16LPENC_Pos) /*!< 0x00020000 */
#define RCC_APB2LPENCR_TIM16LPENC RCC_APB2LPENCR_TIM16LPENC_Msk /*!< TIM16 enable */
#define RCC_APB2LPENCR_TIM17LPENC_Pos (18U)
#define RCC_APB2LPENCR_TIM17LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM17LPENC_Pos) /*!< 0x00040000 */
#define RCC_APB2LPENCR_TIM17LPENC RCC_APB2LPENCR_TIM17LPENC_Msk /*!< TIM17 enable */
#define RCC_APB2LPENCR_TIM9LPENC_Pos (19U)
#define RCC_APB2LPENCR_TIM9LPENC_Msk (0x1UL << RCC_APB2LPENCR_TIM9LPENC_Pos) /*!< 0x00080000 */
#define RCC_APB2LPENCR_TIM9LPENC RCC_APB2LPENCR_TIM9LPENC_Msk /*!< TIM9 enable */
#define RCC_APB2LPENCR_SPI5LPENC_Pos (20U)
#define RCC_APB2LPENCR_SPI5LPENC_Msk (0x1UL << RCC_APB2LPENCR_SPI5LPENC_Pos) /*!< 0x00100000 */
#define RCC_APB2LPENCR_SPI5LPENC RCC_APB2LPENCR_SPI5LPENC_Msk /*!< SPI5 enable */
#define RCC_APB2LPENCR_SAI1LPENC_Pos (21U)
#define RCC_APB2LPENCR_SAI1LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI1LPENC_Pos) /*!< 0x00200000 */
#define RCC_APB2LPENCR_SAI1LPENC RCC_APB2LPENCR_SAI1LPENC_Msk /*!< SAI1 enable */
#define RCC_APB2LPENCR_SAI2LPENC_Pos (22U)
#define RCC_APB2LPENCR_SAI2LPENC_Msk (0x1UL << RCC_APB2LPENCR_SAI2LPENC_Pos) /*!< 0x00400000 */
#define RCC_APB2LPENCR_SAI2LPENC RCC_APB2LPENCR_SAI2LPENC_Msk /*!< SAI2 enable */
/**************** Bit definition for RCC_APB3LPENCR register ****************/
#define RCC_APB3LPENCR_DFTLPENC_Pos (2U)
#define RCC_APB3LPENCR_DFTLPENC_Msk (0x1UL << RCC_APB3LPENCR_DFTLPENC_Pos)/*!< 0x00000004 */
#define RCC_APB3LPENCR_DFTLPENC RCC_APB3LPENCR_DFTLPENC_Msk /*!< DFT enable */
/*************** Bit definition for RCC_APB4LPENCR1 register ****************/
#define RCC_APB4LPENCR1_HDPLPENC_Pos (2U)
#define RCC_APB4LPENCR1_HDPLPENC_Msk (0x1UL << RCC_APB4LPENCR1_HDPLPENC_Pos) /*!< 0x00000004 */
#define RCC_APB4LPENCR1_HDPLPENC RCC_APB4LPENCR1_HDPLPENC_Msk /*!< HDP enable */
#define RCC_APB4LPENCR1_LPUART1LPENC_Pos (3U)
#define RCC_APB4LPENCR1_LPUART1LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPUART1LPENC_Pos) /*!< 0x00000008 */
#define RCC_APB4LPENCR1_LPUART1LPENC RCC_APB4LPENCR1_LPUART1LPENC_Msk /*!< LPUART1 enable */
#define RCC_APB4LPENCR1_SPI6LPENC_Pos (5U)
#define RCC_APB4LPENCR1_SPI6LPENC_Msk (0x1UL << RCC_APB4LPENCR1_SPI6LPENC_Pos) /*!< 0x00000020 */
#define RCC_APB4LPENCR1_SPI6LPENC RCC_APB4LPENCR1_SPI6LPENC_Msk /*!< SPI6 enable */
#define RCC_APB4LPENCR1_I2C4LPENC_Pos (7U)
#define RCC_APB4LPENCR1_I2C4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_I2C4LPENC_Pos) /*!< 0x00000080 */
#define RCC_APB4LPENCR1_I2C4LPENC RCC_APB4LPENCR1_I2C4LPENC_Msk /*!< I2C4 enable */
#define RCC_APB4LPENCR1_LPTIM2LPENC_Pos (9U)
#define RCC_APB4LPENCR1_LPTIM2LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM2LPENC_Pos) /*!< 0x00000200 */
#define RCC_APB4LPENCR1_LPTIM2LPENC RCC_APB4LPENCR1_LPTIM2LPENC_Msk /*!< LPTIM2 enable */
#define RCC_APB4LPENCR1_LPTIM3LPENC_Pos (10U)
#define RCC_APB4LPENCR1_LPTIM3LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM3LPENC_Pos) /*!< 0x00000400 */
#define RCC_APB4LPENCR1_LPTIM3LPENC RCC_APB4LPENCR1_LPTIM3LPENC_Msk /*!< LPTIM3 enable */
#define RCC_APB4LPENCR1_LPTIM4LPENC_Pos (11U)
#define RCC_APB4LPENCR1_LPTIM4LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM4LPENC_Pos) /*!< 0x00000800 */
#define RCC_APB4LPENCR1_LPTIM4LPENC RCC_APB4LPENCR1_LPTIM4LPENC_Msk /*!< LPTIM4 enable */
#define RCC_APB4LPENCR1_LPTIM5LPENC_Pos (12U)
#define RCC_APB4LPENCR1_LPTIM5LPENC_Msk (0x1UL << RCC_APB4LPENCR1_LPTIM5LPENC_Pos) /*!< 0x00001000 */
#define RCC_APB4LPENCR1_LPTIM5LPENC RCC_APB4LPENCR1_LPTIM5LPENC_Msk /*!< LPTIM5 enable */
#define RCC_APB4LPENCR1_VREFBUFLPENC_Pos (15U)
#define RCC_APB4LPENCR1_VREFBUFLPENC_Msk (0x1UL << RCC_APB4LPENCR1_VREFBUFLPENC_Pos) /*!< 0x00008000 */
#define RCC_APB4LPENCR1_VREFBUFLPENC RCC_APB4LPENCR1_VREFBUFLPENC_Msk /*!< VREFBUF enable */
#define RCC_APB4LPENCR1_RTCLPENC_Pos (16U)
#define RCC_APB4LPENCR1_RTCLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCLPENC_Pos) /*!< 0x00010000 */
#define RCC_APB4LPENCR1_RTCLPENC RCC_APB4LPENCR1_RTCLPENC_Msk /*!< RTC enable */
#define RCC_APB4LPENCR1_RTCAPBLPENC_Pos (17U)
#define RCC_APB4LPENCR1_RTCAPBLPENC_Msk (0x1UL << RCC_APB4LPENCR1_RTCAPBLPENC_Pos) /*!< 0x00020000 */
#define RCC_APB4LPENCR1_RTCAPBLPENC RCC_APB4LPENCR1_RTCAPBLPENC_Msk /*!< RTCAPB enable */
/*************** Bit definition for RCC_APB4LPENCR2 register ****************/
#define RCC_APB4LPENCR2_SYSCFGLPENC_Pos (0U)
#define RCC_APB4LPENCR2_SYSCFGLPENC_Msk (0x1UL << RCC_APB4LPENCR2_SYSCFGLPENC_Pos) /*!< 0x00000001 */
#define RCC_APB4LPENCR2_SYSCFGLPENC RCC_APB4LPENCR2_SYSCFGLPENC_Msk /*!< SYSCFG enable */
#define RCC_APB4LPENCR2_BSECLPENC_Pos (1U)
#define RCC_APB4LPENCR2_BSECLPENC_Msk (0x1UL << RCC_APB4LPENCR2_BSECLPENC_Pos) /*!< 0x00000002 */
#define RCC_APB4LPENCR2_BSECLPENC RCC_APB4LPENCR2_BSECLPENC_Msk /*!< BSEC enable */
#define RCC_APB4LPENCR2_DTSLPENC_Pos (2U)
#define RCC_APB4LPENCR2_DTSLPENC_Msk (0x1UL << RCC_APB4LPENCR2_DTSLPENC_Pos) /*!< 0x00000004 */
#define RCC_APB4LPENCR2_DTSLPENC RCC_APB4LPENCR2_DTSLPENC_Msk /*!< DTS enable */
/**************** Bit definition for RCC_APB5LPENCR register ****************/
#define RCC_APB5LPENCR_LTDCLPENC_Pos (1U)
#define RCC_APB5LPENCR_LTDCLPENC_Msk (0x1UL << RCC_APB5LPENCR_LTDCLPENC_Pos) /*!< 0x00000002 */
#define RCC_APB5LPENCR_LTDCLPENC RCC_APB5LPENCR_LTDCLPENC_Msk /*!< LTDC sleep enable */
#define RCC_APB5LPENCR_DCMIPPLPENC_Pos (2U)
#define RCC_APB5LPENCR_DCMIPPLPENC_Msk (0x1UL << RCC_APB5LPENCR_DCMIPPLPENC_Pos) /*!< 0x00000004 */
#define RCC_APB5LPENCR_DCMIPPLPENC RCC_APB5LPENCR_DCMIPPLPENC_Msk /*!< DCMIPP sleep enable */
#define RCC_APB5LPENCR_GFXTIMLPENC_Pos (4U)
#define RCC_APB5LPENCR_GFXTIMLPENC_Msk (0x1UL << RCC_APB5LPENCR_GFXTIMLPENC_Pos) /*!< 0x00000010 */
#define RCC_APB5LPENCR_GFXTIMLPENC RCC_APB5LPENCR_GFXTIMLPENC_Msk /*!< GFXTIM sleep enable */
#define RCC_APB5LPENCR_VENCLPENC_Pos (5U)
#define RCC_APB5LPENCR_VENCLPENC_Msk (0x1UL << RCC_APB5LPENCR_VENCLPENC_Pos) /*!< 0x00000020 */
#define RCC_APB5LPENCR_VENCLPENC RCC_APB5LPENCR_VENCLPENC_Msk /*!< VENC sleep enable */
#define RCC_APB5LPENCR_CSILPENC_Pos (6U)
#define RCC_APB5LPENCR_CSILPENC_Msk (0x1UL << RCC_APB5LPENCR_CSILPENC_Pos)/*!< 0x00000040 */
#define RCC_APB5LPENCR_CSILPENC RCC_APB5LPENCR_CSILPENC_Msk /*!< CSI sleep enable */
/**************** Bit definition for RCC_PRIVCFGCR0 register ****************/
#define RCC_PRIVCFGCR0_LSIPRIVC_Pos (0U)
#define RCC_PRIVCFGCR0_LSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSIPRIVC_Pos)/*!< 0x00000001 */
#define RCC_PRIVCFGCR0_LSIPRIVC RCC_PRIVCFGCR0_LSIPRIVC_Msk /*!< Privileged protection of LSI configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR0_LSEPRIVC_Pos (1U)
#define RCC_PRIVCFGCR0_LSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_LSEPRIVC_Pos)/*!< 0x00000002 */
#define RCC_PRIVCFGCR0_LSEPRIVC RCC_PRIVCFGCR0_LSEPRIVC_Msk /*!< Privileged protection of LSE configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR0_MSIPRIVC_Pos (2U)
#define RCC_PRIVCFGCR0_MSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_MSIPRIVC_Pos)/*!< 0x00000004 */
#define RCC_PRIVCFGCR0_MSIPRIVC RCC_PRIVCFGCR0_MSIPRIVC_Msk /*!< Privileged protection of MSI configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR0_HSIPRIVC_Pos (3U)
#define RCC_PRIVCFGCR0_HSIPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSIPRIVC_Pos)/*!< 0x00000008 */
#define RCC_PRIVCFGCR0_HSIPRIVC RCC_PRIVCFGCR0_HSIPRIVC_Msk /*!< Privileged protection of HSI configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR0_HSEPRIVC_Pos (4U)
#define RCC_PRIVCFGCR0_HSEPRIVC_Msk (0x1UL << RCC_PRIVCFGCR0_HSEPRIVC_Pos)/*!< 0x00000010 */
#define RCC_PRIVCFGCR0_HSEPRIVC RCC_PRIVCFGCR0_HSEPRIVC_Msk /*!< Privileged protection of HSE configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGCR0 register *****************/
#define RCC_PUBCFGCR0_LSIPUBC_Pos (0U)
#define RCC_PUBCFGCR0_LSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSIPUBC_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGCR0_LSIPUBC RCC_PUBCFGCR0_LSIPUBC_Msk /*!< Public protection of LSI configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR0_LSEPUBC_Pos (1U)
#define RCC_PUBCFGCR0_LSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_LSEPUBC_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGCR0_LSEPUBC RCC_PUBCFGCR0_LSEPUBC_Msk /*!< Public protection of LSE configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR0_MSIPUBC_Pos (2U)
#define RCC_PUBCFGCR0_MSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_MSIPUBC_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGCR0_MSIPUBC RCC_PUBCFGCR0_MSIPUBC_Msk /*!< Public protection of MSI configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR0_HSIPUBC_Pos (3U)
#define RCC_PUBCFGCR0_HSIPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSIPUBC_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGCR0_HSIPUBC RCC_PUBCFGCR0_HSIPUBC_Msk /*!< Public protection of HSI configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR0_HSEPUBC_Pos (4U)
#define RCC_PUBCFGCR0_HSEPUBC_Msk (0x1UL << RCC_PUBCFGCR0_HSEPUBC_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGCR0_HSEPUBC RCC_PUBCFGCR0_HSEPUBC_Msk /*!< Public protection of HSE configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGCR1 register ****************/
#define RCC_PRIVCFGCR1_PLL1PRIVC_Pos (0U)
#define RCC_PRIVCFGCR1_PLL1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL1PRIVC_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGCR1_PLL1PRIVC RCC_PRIVCFGCR1_PLL1PRIVC_Msk /*!< Privileged protection of PLL1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR1_PLL2PRIVC_Pos (1U)
#define RCC_PRIVCFGCR1_PLL2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL2PRIVC_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGCR1_PLL2PRIVC RCC_PRIVCFGCR1_PLL2PRIVC_Msk /*!< Privileged protection of PLL2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR1_PLL3PRIVC_Pos (2U)
#define RCC_PRIVCFGCR1_PLL3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL3PRIVC_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGCR1_PLL3PRIVC RCC_PRIVCFGCR1_PLL3PRIVC_Msk /*!< Privileged protection of PLL3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR1_PLL4PRIVC_Pos (3U)
#define RCC_PRIVCFGCR1_PLL4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR1_PLL4PRIVC_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGCR1_PLL4PRIVC RCC_PRIVCFGCR1_PLL4PRIVC_Msk /*!< Privileged protection of PLL4 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGCR1 register *****************/
#define RCC_PUBCFGCR1_PLL1PUBC_Pos (0U)
#define RCC_PUBCFGCR1_PLL1PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL1PUBC_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGCR1_PLL1PUBC RCC_PUBCFGCR1_PLL1PUBC_Msk /*!< Public protection of th PLL1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR1_PLL2PUBC_Pos (1U)
#define RCC_PUBCFGCR1_PLL2PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL2PUBC_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGCR1_PLL2PUBC RCC_PUBCFGCR1_PLL2PUBC_Msk /*!< Public protection of te PLL2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR1_PLL3PUBC_Pos (2U)
#define RCC_PUBCFGCR1_PLL3PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL3PUBC_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGCR1_PLL3PUBC RCC_PUBCFGCR1_PLL3PUBC_Msk /*!< Public protection of PLL3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR1_PLL4PUBC_Pos (3U)
#define RCC_PUBCFGCR1_PLL4PUBC_Msk (0x1UL << RCC_PUBCFGCR1_PLL4PUBC_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGCR1_PLL4PUBC RCC_PUBCFGCR1_PLL4PUBC_Msk /*!< Public protection of PLL4 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGCR2 register ****************/
#define RCC_PRIVCFGCR2_IC1PRIVC_Pos (0U)
#define RCC_PRIVCFGCR2_IC1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC1PRIVC_Pos)/*!< 0x00000001 */
#define RCC_PRIVCFGCR2_IC1PRIVC RCC_PRIVCFGCR2_IC1PRIVC_Msk /*!< Privileged protection of the IC1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC2PRIVC_Pos (1U)
#define RCC_PRIVCFGCR2_IC2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC2PRIVC_Pos)/*!< 0x00000002 */
#define RCC_PRIVCFGCR2_IC2PRIVC RCC_PRIVCFGCR2_IC2PRIVC_Msk /*!< Privileged protection of the IC2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC3PRIVC_Pos (2U)
#define RCC_PRIVCFGCR2_IC3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC3PRIVC_Pos)/*!< 0x00000004 */
#define RCC_PRIVCFGCR2_IC3PRIVC RCC_PRIVCFGCR2_IC3PRIVC_Msk /*!< Privileged protection of the IC3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC4PRIVC_Pos (3U)
#define RCC_PRIVCFGCR2_IC4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC4PRIVC_Pos)/*!< 0x00000008 */
#define RCC_PRIVCFGCR2_IC4PRIVC RCC_PRIVCFGCR2_IC4PRIVC_Msk /*!< Privileged protection of the IC4 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC5PRIVC_Pos (4U)
#define RCC_PRIVCFGCR2_IC5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC5PRIVC_Pos)/*!< 0x00000010 */
#define RCC_PRIVCFGCR2_IC5PRIVC RCC_PRIVCFGCR2_IC5PRIVC_Msk /*!< Privileged protection of the IC5 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC6PRIVC_Pos (5U)
#define RCC_PRIVCFGCR2_IC6PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC6PRIVC_Pos)/*!< 0x00000020 */
#define RCC_PRIVCFGCR2_IC6PRIVC RCC_PRIVCFGCR2_IC6PRIVC_Msk /*!< Privileged protection of IC6 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC7PRIVC_Pos (6U)
#define RCC_PRIVCFGCR2_IC7PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC7PRIVC_Pos)/*!< 0x00000040 */
#define RCC_PRIVCFGCR2_IC7PRIVC RCC_PRIVCFGCR2_IC7PRIVC_Msk /*!< Privileged protection of IC7 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC8PRIVC_Pos (7U)
#define RCC_PRIVCFGCR2_IC8PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC8PRIVC_Pos)/*!< 0x00000080 */
#define RCC_PRIVCFGCR2_IC8PRIVC RCC_PRIVCFGCR2_IC8PRIVC_Msk /*!< Privileged protection of IC8 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC9PRIVC_Pos (8U)
#define RCC_PRIVCFGCR2_IC9PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC9PRIVC_Pos)/*!< 0x00000100 */
#define RCC_PRIVCFGCR2_IC9PRIVC RCC_PRIVCFGCR2_IC9PRIVC_Msk /*!< Privileged protection of IC9 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC10PRIVC_Pos (9U)
#define RCC_PRIVCFGCR2_IC10PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC10PRIVC_Pos) /*!< 0x00000200 */
#define RCC_PRIVCFGCR2_IC10PRIVC RCC_PRIVCFGCR2_IC10PRIVC_Msk /*!< Privileged protection of IC10 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC11PRIVC_Pos (10U)
#define RCC_PRIVCFGCR2_IC11PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC11PRIVC_Pos) /*!< 0x00000400 */
#define RCC_PRIVCFGCR2_IC11PRIVC RCC_PRIVCFGCR2_IC11PRIVC_Msk /*!< Privileged protection of IC11 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC12PRIVC_Pos (11U)
#define RCC_PRIVCFGCR2_IC12PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC12PRIVC_Pos) /*!< 0x00000800 */
#define RCC_PRIVCFGCR2_IC12PRIVC RCC_PRIVCFGCR2_IC12PRIVC_Msk /*!< Privileged protection of IC12 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC13PRIVC_Pos (12U)
#define RCC_PRIVCFGCR2_IC13PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC13PRIVC_Pos) /*!< 0x00001000 */
#define RCC_PRIVCFGCR2_IC13PRIVC RCC_PRIVCFGCR2_IC13PRIVC_Msk /*!< Privileged protection of IC13 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC14PRIVC_Pos (13U)
#define RCC_PRIVCFGCR2_IC14PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC14PRIVC_Pos) /*!< 0x00002000 */
#define RCC_PRIVCFGCR2_IC14PRIVC RCC_PRIVCFGCR2_IC14PRIVC_Msk /*!< Privileged protection of IC14 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC15PRIVC_Pos (14U)
#define RCC_PRIVCFGCR2_IC15PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC15PRIVC_Pos) /*!< 0x00004000 */
#define RCC_PRIVCFGCR2_IC15PRIVC RCC_PRIVCFGCR2_IC15PRIVC_Msk /*!< Privileged protection of IC15 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC16PRIVC_Pos (15U)
#define RCC_PRIVCFGCR2_IC16PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC16PRIVC_Pos) /*!< 0x00008000 */
#define RCC_PRIVCFGCR2_IC16PRIVC RCC_PRIVCFGCR2_IC16PRIVC_Msk /*!< Privileged protection of IC16 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC17PRIVC_Pos (16U)
#define RCC_PRIVCFGCR2_IC17PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC17PRIVC_Pos) /*!< 0x00010000 */
#define RCC_PRIVCFGCR2_IC17PRIVC RCC_PRIVCFGCR2_IC17PRIVC_Msk /*!< Privileged protection of IC17 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC18PRIVC_Pos (17U)
#define RCC_PRIVCFGCR2_IC18PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC18PRIVC_Pos) /*!< 0x00020000 */
#define RCC_PRIVCFGCR2_IC18PRIVC RCC_PRIVCFGCR2_IC18PRIVC_Msk /*!< Privileged protection of IC18 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC19PRIVC_Pos (18U)
#define RCC_PRIVCFGCR2_IC19PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC19PRIVC_Pos) /*!< 0x00040000 */
#define RCC_PRIVCFGCR2_IC19PRIVC RCC_PRIVCFGCR2_IC19PRIVC_Msk /*!< Privileged protection of IC19 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR2_IC20PRIVC_Pos (19U)
#define RCC_PRIVCFGCR2_IC20PRIVC_Msk (0x1UL << RCC_PRIVCFGCR2_IC20PRIVC_Pos) /*!< 0x00080000 */
#define RCC_PRIVCFGCR2_IC20PRIVC RCC_PRIVCFGCR2_IC20PRIVC_Msk /*!< Privileged protection of IC20 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGCR2 register *****************/
#define RCC_PUBCFGCR2_IC1PUBC_Pos (0U)
#define RCC_PUBCFGCR2_IC1PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC1PUBC_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGCR2_IC1PUBC RCC_PUBCFGCR2_IC1PUBC_Msk /*!< Public protection of IC1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC2PUBC_Pos (1U)
#define RCC_PUBCFGCR2_IC2PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC2PUBC_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGCR2_IC2PUBC RCC_PUBCFGCR2_IC2PUBC_Msk /*!< Public protection of IC2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC3PUBC_Pos (2U)
#define RCC_PUBCFGCR2_IC3PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC3PUBC_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGCR2_IC3PUBC RCC_PUBCFGCR2_IC3PUBC_Msk /*!< Public protection of IC3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC4PUBC_Pos (3U)
#define RCC_PUBCFGCR2_IC4PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC4PUBC_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGCR2_IC4PUBC RCC_PUBCFGCR2_IC4PUBC_Msk /*!< Public protection of IC4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC5PUBC_Pos (4U)
#define RCC_PUBCFGCR2_IC5PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC5PUBC_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGCR2_IC5PUBC RCC_PUBCFGCR2_IC5PUBC_Msk /*!< Public protection of IC5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC6PUBC_Pos (5U)
#define RCC_PUBCFGCR2_IC6PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC6PUBC_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGCR2_IC6PUBC RCC_PUBCFGCR2_IC6PUBC_Msk /*!< Public protection of IC6 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC7PUBC_Pos (6U)
#define RCC_PUBCFGCR2_IC7PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC7PUBC_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGCR2_IC7PUBC RCC_PUBCFGCR2_IC7PUBC_Msk /*!< Public protection of IC7 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC8PUBC_Pos (7U)
#define RCC_PUBCFGCR2_IC8PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC8PUBC_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGCR2_IC8PUBC RCC_PUBCFGCR2_IC8PUBC_Msk /*!< Public protection of IC8 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC9PUBC_Pos (8U)
#define RCC_PUBCFGCR2_IC9PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC9PUBC_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGCR2_IC9PUBC RCC_PUBCFGCR2_IC9PUBC_Msk /*!< Public protection of IC9 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC10PUBC_Pos (9U)
#define RCC_PUBCFGCR2_IC10PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC10PUBC_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGCR2_IC10PUBC RCC_PUBCFGCR2_IC10PUBC_Msk /*!< Public protection of IC10 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC11PUBC_Pos (10U)
#define RCC_PUBCFGCR2_IC11PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC11PUBC_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGCR2_IC11PUBC RCC_PUBCFGCR2_IC11PUBC_Msk /*!< Public protection of IC11 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC12PUBC_Pos (11U)
#define RCC_PUBCFGCR2_IC12PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC12PUBC_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGCR2_IC12PUBC RCC_PUBCFGCR2_IC12PUBC_Msk /*!< Public protection of IC12 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC13PUBC_Pos (12U)
#define RCC_PUBCFGCR2_IC13PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC13PUBC_Pos) /*!< 0x00001000 */
#define RCC_PUBCFGCR2_IC13PUBC RCC_PUBCFGCR2_IC13PUBC_Msk /*!< Public protection of IC13 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC14PUBC_Pos (13U)
#define RCC_PUBCFGCR2_IC14PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC14PUBC_Pos) /*!< 0x00002000 */
#define RCC_PUBCFGCR2_IC14PUBC RCC_PUBCFGCR2_IC14PUBC_Msk /*!< Public protection of IC14 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC15PUBC_Pos (14U)
#define RCC_PUBCFGCR2_IC15PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC15PUBC_Pos) /*!< 0x00004000 */
#define RCC_PUBCFGCR2_IC15PUBC RCC_PUBCFGCR2_IC15PUBC_Msk /*!< Public protection of IC15 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC16PUBC_Pos (15U)
#define RCC_PUBCFGCR2_IC16PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC16PUBC_Pos) /*!< 0x00008000 */
#define RCC_PUBCFGCR2_IC16PUBC RCC_PUBCFGCR2_IC16PUBC_Msk /*!< Public protection of IC16 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC17PUBC_Pos (16U)
#define RCC_PUBCFGCR2_IC17PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC17PUBC_Pos) /*!< 0x00010000 */
#define RCC_PUBCFGCR2_IC17PUBC RCC_PUBCFGCR2_IC17PUBC_Msk /*!< Public protection of IC17 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC18PUBC_Pos (17U)
#define RCC_PUBCFGCR2_IC18PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC18PUBC_Pos) /*!< 0x00020000 */
#define RCC_PUBCFGCR2_IC18PUBC RCC_PUBCFGCR2_IC18PUBC_Msk /*!< Public protection of IC18 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC19PUBC_Pos (18U)
#define RCC_PUBCFGCR2_IC19PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC19PUBC_Pos) /*!< 0x00040000 */
#define RCC_PUBCFGCR2_IC19PUBC RCC_PUBCFGCR2_IC19PUBC_Msk /*!< Public protection of IC19 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR2_IC20PUBC_Pos (19U)
#define RCC_PUBCFGCR2_IC20PUBC_Msk (0x1UL << RCC_PUBCFGCR2_IC20PUBC_Pos) /*!< 0x00080000 */
#define RCC_PUBCFGCR2_IC20PUBC RCC_PUBCFGCR2_IC20PUBC_Msk /*!< Public protection of IC20 configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGCR3 register ****************/
#define RCC_PRIVCFGCR3_MODPRIVC_Pos (0U)
#define RCC_PRIVCFGCR3_MODPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_MODPRIVC_Pos)/*!< 0x00000001 */
#define RCC_PRIVCFGCR3_MODPRIVC RCC_PRIVCFGCR3_MODPRIVC_Msk /*!< Privileged protection of MOD configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR3_SYSPRIVC_Pos (1U)
#define RCC_PRIVCFGCR3_SYSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_SYSPRIVC_Pos)/*!< 0x00000002 */
#define RCC_PRIVCFGCR3_SYSPRIVC RCC_PRIVCFGCR3_SYSPRIVC_Msk /*!< Privileged protection of SYS configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR3_BUSPRIVC_Pos (2U)
#define RCC_PRIVCFGCR3_BUSPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_BUSPRIVC_Pos)/*!< 0x00000004 */
#define RCC_PRIVCFGCR3_BUSPRIVC RCC_PRIVCFGCR3_BUSPRIVC_Msk /*!< Privileged protection of BUS configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR3_PERPRIVC_Pos (3U)
#define RCC_PRIVCFGCR3_PERPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_PERPRIVC_Pos)/*!< 0x00000008 */
#define RCC_PRIVCFGCR3_PERPRIVC RCC_PRIVCFGCR3_PERPRIVC_Msk /*!< Privileged protection of PER configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR3_INTPRIVC_Pos (4U)
#define RCC_PRIVCFGCR3_INTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_INTPRIVC_Pos)/*!< 0x00000010 */
#define RCC_PRIVCFGCR3_INTPRIVC RCC_PRIVCFGCR3_INTPRIVC_Msk /*!< Privileged protection of INT configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR3_RSTPRIVC_Pos (5U)
#define RCC_PRIVCFGCR3_RSTPRIVC_Msk (0x1UL << RCC_PRIVCFGCR3_RSTPRIVC_Pos)/*!< 0x00000020 */
#define RCC_PRIVCFGCR3_RSTPRIVC RCC_PRIVCFGCR3_RSTPRIVC_Msk /*!< Privileged protection of RST configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGCR3 register *****************/
#define RCC_PUBCFGCR3_MODPUBC_Pos (0U)
#define RCC_PUBCFGCR3_MODPUBC_Msk (0x1UL << RCC_PUBCFGCR3_MODPUBC_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGCR3_MODPUBC RCC_PUBCFGCR3_MODPUBC_Msk /*!< Public protection of MOD configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR3_SYSPUBC_Pos (1U)
#define RCC_PUBCFGCR3_SYSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_SYSPUBC_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGCR3_SYSPUBC RCC_PUBCFGCR3_SYSPUBC_Msk /*!< Public protection of SYS configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR3_BUSPUBC_Pos (2U)
#define RCC_PUBCFGCR3_BUSPUBC_Msk (0x1UL << RCC_PUBCFGCR3_BUSPUBC_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGCR3_BUSPUBC RCC_PUBCFGCR3_BUSPUBC_Msk /*!< Public protection of BUS configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR3_PERPUBC_Pos (3U)
#define RCC_PUBCFGCR3_PERPUBC_Msk (0x1UL << RCC_PUBCFGCR3_PERPUBC_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGCR3_PERPUBC RCC_PUBCFGCR3_PERPUBC_Msk /*!< Public protection of PER configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR3_INTPUBC_Pos (4U)
#define RCC_PUBCFGCR3_INTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_INTPUBC_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGCR3_INTPUBC RCC_PUBCFGCR3_INTPUBC_Msk /*!< Public protection of INT configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR3_RSTPUBC_Pos (5U)
#define RCC_PUBCFGCR3_RSTPUBC_Msk (0x1UL << RCC_PUBCFGCR3_RSTPUBC_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGCR3_RSTPUBC RCC_PUBCFGCR3_RSTPUBC_Msk /*!< Public protection of RST configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PRIVCFGCR4 register ****************/
#define RCC_PRIVCFGCR4_ACLKNPRIVC_Pos (0U)
#define RCC_PRIVCFGCR4_ACLKNPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNPRIVC_Pos) /*!< 0x00000001 */
#define RCC_PRIVCFGCR4_ACLKNPRIVC RCC_PRIVCFGCR4_ACLKNPRIVC_Msk /*!< Privileged protection of ACLKN configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos (1U)
#define RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_ACLKNCPRIVC_Pos) /*!< 0x00000002 */
#define RCC_PRIVCFGCR4_ACLKNCPRIVC RCC_PRIVCFGCR4_ACLKNCPRIVC_Msk /*!< Privileged protection of ACLKNC configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_AHBMPRIVC_Pos (2U)
#define RCC_PRIVCFGCR4_AHBMPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHBMPRIVC_Pos) /*!< 0x00000004 */
#define RCC_PRIVCFGCR4_AHBMPRIVC RCC_PRIVCFGCR4_AHBMPRIVC_Msk /*!< Privileged protection of AHBM configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_AHB1PRIVC_Pos (3U)
#define RCC_PRIVCFGCR4_AHB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB1PRIVC_Pos) /*!< 0x00000008 */
#define RCC_PRIVCFGCR4_AHB1PRIVC RCC_PRIVCFGCR4_AHB1PRIVC_Msk /*!< Privileged protection of AHB1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_AHB2PRIVC_Pos (4U)
#define RCC_PRIVCFGCR4_AHB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB2PRIVC_Pos) /*!< 0x00000010 */
#define RCC_PRIVCFGCR4_AHB2PRIVC RCC_PRIVCFGCR4_AHB2PRIVC_Msk /*!< Privileged protection of AHB2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_AHB3PRIVC_Pos (5U)
#define RCC_PRIVCFGCR4_AHB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB3PRIVC_Pos) /*!< 0x00000020 */
#define RCC_PRIVCFGCR4_AHB3PRIVC RCC_PRIVCFGCR4_AHB3PRIVC_Msk /*!< Privileged protection of AHB3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_AHB4PRIVC_Pos (6U)
#define RCC_PRIVCFGCR4_AHB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB4PRIVC_Pos) /*!< 0x00000040 */
#define RCC_PRIVCFGCR4_AHB4PRIVC RCC_PRIVCFGCR4_AHB4PRIVC_Msk /*!< Privileged protection of AHB4 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_AHB5PRIVC_Pos (7U)
#define RCC_PRIVCFGCR4_AHB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_AHB5PRIVC_Pos) /*!< 0x00000080 */
#define RCC_PRIVCFGCR4_AHB5PRIVC RCC_PRIVCFGCR4_AHB5PRIVC_Msk /*!< Privileged protection of AHB5 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_APB1PRIVC_Pos (8U)
#define RCC_PRIVCFGCR4_APB1PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB1PRIVC_Pos) /*!< 0x00000100 */
#define RCC_PRIVCFGCR4_APB1PRIVC RCC_PRIVCFGCR4_APB1PRIVC_Msk /*!< Privileged protection of APB1 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_APB2PRIVC_Pos (9U)
#define RCC_PRIVCFGCR4_APB2PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB2PRIVC_Pos) /*!< 0x00000200 */
#define RCC_PRIVCFGCR4_APB2PRIVC RCC_PRIVCFGCR4_APB2PRIVC_Msk /*!< Privileged protection of APB2 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_APB3PRIVC_Pos (10U)
#define RCC_PRIVCFGCR4_APB3PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB3PRIVC_Pos) /*!< 0x00000400 */
#define RCC_PRIVCFGCR4_APB3PRIVC RCC_PRIVCFGCR4_APB3PRIVC_Msk /*!< Privileged protection of APB3 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_APB4PRIVC_Pos (11U)
#define RCC_PRIVCFGCR4_APB4PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB4PRIVC_Pos) /*!< 0x00000800 */
#define RCC_PRIVCFGCR4_APB4PRIVC RCC_PRIVCFGCR4_APB4PRIVC_Msk /*!< Privileged protection of APB4 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_APB5PRIVC_Pos (12U)
#define RCC_PRIVCFGCR4_APB5PRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_APB5PRIVC_Pos) /*!< 0x00001000 */
#define RCC_PRIVCFGCR4_APB5PRIVC RCC_PRIVCFGCR4_APB5PRIVC_Msk /*!< Privileged protection of APB5 configuration bits (enable, ready, divider) */
#define RCC_PRIVCFGCR4_NOCPRIVC_Pos (13U)
#define RCC_PRIVCFGCR4_NOCPRIVC_Msk (0x1UL << RCC_PRIVCFGCR4_NOCPRIVC_Pos)/*!< 0x00002000 */
#define RCC_PRIVCFGCR4_NOCPRIVC RCC_PRIVCFGCR4_NOCPRIVC_Msk /*!< Privileged protection of NOC configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGCR4 register *****************/
#define RCC_PUBCFGCR4_ACLKNPUBC_Pos (0U)
#define RCC_PUBCFGCR4_ACLKNPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNPUBC_Pos)/*!< 0x00000001 */
#define RCC_PUBCFGCR4_ACLKNPUBC RCC_PUBCFGCR4_ACLKNPUBC_Msk /*!< Public protection of ACLKN configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_ACLKNCPUBC_Pos (1U)
#define RCC_PUBCFGCR4_ACLKNCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_ACLKNCPUBC_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGCR4_ACLKNCPUBC RCC_PUBCFGCR4_ACLKNCPUBC_Msk /*!< Public protection of ACLKNC configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_AHBMPUBC_Pos (2U)
#define RCC_PUBCFGCR4_AHBMPUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHBMPUBC_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGCR4_AHBMPUBC RCC_PUBCFGCR4_AHBMPUBC_Msk /*!< Public protection of AHBM configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_AHB1PUBC_Pos (3U)
#define RCC_PUBCFGCR4_AHB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB1PUBC_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGCR4_AHB1PUBC RCC_PUBCFGCR4_AHB1PUBC_Msk /*!< Public protection of AHB1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_AHB2PUBC_Pos (4U)
#define RCC_PUBCFGCR4_AHB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB2PUBC_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGCR4_AHB2PUBC RCC_PUBCFGCR4_AHB2PUBC_Msk /*!< Public protection of AHB2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_AHB3PUBC_Pos (5U)
#define RCC_PUBCFGCR4_AHB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB3PUBC_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGCR4_AHB3PUBC RCC_PUBCFGCR4_AHB3PUBC_Msk /*!< Public protection of AHB3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_AHB4PUBC_Pos (6U)
#define RCC_PUBCFGCR4_AHB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB4PUBC_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGCR4_AHB4PUBC RCC_PUBCFGCR4_AHB4PUBC_Msk /*!< Public protection of AHB4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_AHB5PUBC_Pos (7U)
#define RCC_PUBCFGCR4_AHB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_AHB5PUBC_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGCR4_AHB5PUBC RCC_PUBCFGCR4_AHB5PUBC_Msk /*!< Public protection of AHB5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_APB1PUBC_Pos (8U)
#define RCC_PUBCFGCR4_APB1PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB1PUBC_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGCR4_APB1PUBC RCC_PUBCFGCR4_APB1PUBC_Msk /*!< Public protection of APB1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_APB2PUBC_Pos (9U)
#define RCC_PUBCFGCR4_APB2PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB2PUBC_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGCR4_APB2PUBC RCC_PUBCFGCR4_APB2PUBC_Msk /*!< Public protection of APB2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_APB3PUBC_Pos (10U)
#define RCC_PUBCFGCR4_APB3PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB3PUBC_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGCR4_APB3PUBC RCC_PUBCFGCR4_APB3PUBC_Msk /*!< Public protection of APB3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_APB4PUBC_Pos (11U)
#define RCC_PUBCFGCR4_APB4PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB4PUBC_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGCR4_APB4PUBC RCC_PUBCFGCR4_APB4PUBC_Msk /*!< Public protection of APB4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_APB5PUBC_Pos (12U)
#define RCC_PUBCFGCR4_APB5PUBC_Msk (0x1UL << RCC_PUBCFGCR4_APB5PUBC_Pos) /*!< 0x00001000 */
#define RCC_PUBCFGCR4_APB5PUBC RCC_PUBCFGCR4_APB5PUBC_Msk /*!< Public protection of APB5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR4_NOCPUBC_Pos (13U)
#define RCC_PUBCFGCR4_NOCPUBC_Msk (0x1UL << RCC_PUBCFGCR4_NOCPUBC_Pos) /*!< 0x00002000 */
#define RCC_PUBCFGCR4_NOCPUBC RCC_PUBCFGCR4_NOCPUBC_Msk /*!< Public protection of NOC configuration bits (enable, ready, divider) */
/**************** Bit definition for RCC_PUBCFGCR5 register *****************/
#define RCC_PUBCFGCR5_AXISRAM3PUBC_Pos (0U)
#define RCC_PUBCFGCR5_AXISRAM3PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM3PUBC_Pos) /*!< 0x00000001 */
#define RCC_PUBCFGCR5_AXISRAM3PUBC RCC_PUBCFGCR5_AXISRAM3PUBC_Msk /*!< Public protection of AXISRAM3 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_AXISRAM4PUBC_Pos (1U)
#define RCC_PUBCFGCR5_AXISRAM4PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM4PUBC_Pos) /*!< 0x00000002 */
#define RCC_PUBCFGCR5_AXISRAM4PUBC RCC_PUBCFGCR5_AXISRAM4PUBC_Msk /*!< Public protection of AXISRAM4 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_AXISRAM5PUBC_Pos (2U)
#define RCC_PUBCFGCR5_AXISRAM5PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM5PUBC_Pos) /*!< 0x00000004 */
#define RCC_PUBCFGCR5_AXISRAM5PUBC RCC_PUBCFGCR5_AXISRAM5PUBC_Msk /*!< Public protection of AXISRAM5 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_AXISRAM6PUBC_Pos (3U)
#define RCC_PUBCFGCR5_AXISRAM6PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM6PUBC_Pos) /*!< 0x00000008 */
#define RCC_PUBCFGCR5_AXISRAM6PUBC RCC_PUBCFGCR5_AXISRAM6PUBC_Msk /*!< Public protection of AXISRAM6 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos (4U)
#define RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM1PUBC_Pos) /*!< 0x00000010 */
#define RCC_PUBCFGCR5_AHBSRAM1PUBC RCC_PUBCFGCR5_AHBSRAM1PUBC_Msk /*!< Public protection of AHBSRAM1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos (5U)
#define RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AHBSRAM2PUBC_Pos) /*!< 0x00000020 */
#define RCC_PUBCFGCR5_AHBSRAM2PUBC RCC_PUBCFGCR5_AHBSRAM2PUBC_Msk /*!< Public protection of AHBSRAM2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_BKPSRAMPUBC_Pos (6U)
#define RCC_PUBCFGCR5_BKPSRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_BKPSRAMPUBC_Pos) /*!< 0x00000040 */
#define RCC_PUBCFGCR5_BKPSRAMPUBC RCC_PUBCFGCR5_BKPSRAMPUBC_Msk /*!< Public protection of BKPSRAM configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_AXISRAM1PUBC_Pos (7U)
#define RCC_PUBCFGCR5_AXISRAM1PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM1PUBC_Pos) /*!< 0x00000080 */
#define RCC_PUBCFGCR5_AXISRAM1PUBC RCC_PUBCFGCR5_AXISRAM1PUBC_Msk /*!< Public protection of AXISRAM1 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_AXISRAM2PUBC_Pos (8U)
#define RCC_PUBCFGCR5_AXISRAM2PUBC_Msk (0x1UL << RCC_PUBCFGCR5_AXISRAM2PUBC_Pos) /*!< 0x00000100 */
#define RCC_PUBCFGCR5_AXISRAM2PUBC RCC_PUBCFGCR5_AXISRAM2PUBC_Msk /*!< Public protection of AXISRAM2 configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_FLEXRAMPUBC_Pos (9U)
#define RCC_PUBCFGCR5_FLEXRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_FLEXRAMPUBC_Pos) /*!< 0x00000200 */
#define RCC_PUBCFGCR5_FLEXRAMPUBC RCC_PUBCFGCR5_FLEXRAMPUBC_Msk /*!< Public protection of FLEXRAM configuration bits (enable, ready, divider) */
#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos (10U)
#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Pos) /*!< 0x00000400 */
#define RCC_PUBCFGCR5_CACHEAXIRAMPUBC RCC_PUBCFGCR5_CACHEAXIRAMPUBC_Msk /*!< Public protection of CACHEAXIRAM configuration bits */
#define RCC_PUBCFGCR5_VENCRAMPUBC_Pos (11U)
#define RCC_PUBCFGCR5_VENCRAMPUBC_Msk (0x1UL << RCC_PUBCFGCR5_VENCRAMPUBC_Pos) /*!< 0x00000800 */
#define RCC_PUBCFGCR5_VENCRAMPUBC RCC_PUBCFGCR5_VENCRAMPUBC_Msk /*!< Public protection of VENCRAM configuration bits (enable, ready, divider) */
/******************************************************************************/
/* */
/* Resource Isolation Framework Security Controller (RIFSC) */
/* */
/******************************************************************************/
/**************** Bit definition for RIFSC_RISC_CR register *****************/
#define RIFSC_RISC_CR_GLOCK_Pos (0UL)
#define RIFSC_RISC_CR_GLOCK_Msk (0x1UL << RIFSC_RISC_CR_GLOCK_Pos) /*!< 0x00000001 */
#define RIFSC_RISC_CR_GLOCK RIFSC_RISC_CR_GLOCK_Msk /*!< Global lock */
/************* Bit definition for RIFSC_RISC_SECCFGRx register **************/
#define RIFSC_RISC_SECCFGRx_SEC0_Pos (0U)
#define RIFSC_RISC_SECCFGRx_SEC0_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC0_Pos) /*!< 0x00000001 */
#define RIFSC_RISC_SECCFGRx_SEC0 RIFSC_RISC_SECCFGRx_SEC0_Msk /*!< Security configuration for peripheral 0 */
#define RIFSC_RISC_SECCFGRx_SEC1_Pos (1U)
#define RIFSC_RISC_SECCFGRx_SEC1_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC1_Pos) /*!< 0x00000002 */
#define RIFSC_RISC_SECCFGRx_SEC1 RIFSC_RISC_SECCFGRx_SEC1_Msk /*!< Security configuration for peripheral 1 */
#define RIFSC_RISC_SECCFGRx_SEC2_Pos (2U)
#define RIFSC_RISC_SECCFGRx_SEC2_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC2_Pos) /*!< 0x00000004 */
#define RIFSC_RISC_SECCFGRx_SEC2 RIFSC_RISC_SECCFGRx_SEC2_Msk /*!< Security configuration for peripheral 2 */
#define RIFSC_RISC_SECCFGRx_SEC3_Pos (3U)
#define RIFSC_RISC_SECCFGRx_SEC3_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC3_Pos) /*!< 0x00000008 */
#define RIFSC_RISC_SECCFGRx_SEC3 RIFSC_RISC_SECCFGRx_SEC3_Msk /*!< Security configuration for peripheral 3 */
#define RIFSC_RISC_SECCFGRx_SEC4_Pos (4U)
#define RIFSC_RISC_SECCFGRx_SEC4_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC4_Pos) /*!< 0x00000010 */
#define RIFSC_RISC_SECCFGRx_SEC4 RIFSC_RISC_SECCFGRx_SEC4_Msk /*!< Security configuration for peripheral 4 */
#define RIFSC_RISC_SECCFGRx_SEC5_Pos (5U)
#define RIFSC_RISC_SECCFGRx_SEC5_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC5_Pos) /*!< 0x00000020 */
#define RIFSC_RISC_SECCFGRx_SEC5 RIFSC_RISC_SECCFGRx_SEC5_Msk /*!< Security configuration for peripheral 5 */
#define RIFSC_RISC_SECCFGRx_SEC6_Pos (6U)
#define RIFSC_RISC_SECCFGRx_SEC6_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC6_Pos) /*!< 0x00000040 */
#define RIFSC_RISC_SECCFGRx_SEC6 RIFSC_RISC_SECCFGRx_SEC6_Msk /*!< Security configuration for peripheral 6 */
#define RIFSC_RISC_SECCFGRx_SEC7_Pos (7U)
#define RIFSC_RISC_SECCFGRx_SEC7_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC7_Pos) /*!< 0x00000080 */
#define RIFSC_RISC_SECCFGRx_SEC7 RIFSC_RISC_SECCFGRx_SEC7_Msk /*!< Security configuration for peripheral 7 */
#define RIFSC_RISC_SECCFGRx_SEC8_Pos (8U)
#define RIFSC_RISC_SECCFGRx_SEC8_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC8_Pos) /*!< 0x00000100 */
#define RIFSC_RISC_SECCFGRx_SEC8 RIFSC_RISC_SECCFGRx_SEC8_Msk /*!< Security configuration for peripheral 8 */
#define RIFSC_RISC_SECCFGRx_SEC9_Pos (9U)
#define RIFSC_RISC_SECCFGRx_SEC9_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC9_Pos) /*!< 0x00000200 */
#define RIFSC_RISC_SECCFGRx_SEC9 RIFSC_RISC_SECCFGRx_SEC9_Msk /*!< Security configuration for peripheral 9 */
#define RIFSC_RISC_SECCFGRx_SEC10_Pos (10U)
#define RIFSC_RISC_SECCFGRx_SEC10_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC10_Pos) /*!< 0x00000400 */
#define RIFSC_RISC_SECCFGRx_SEC10 RIFSC_RISC_SECCFGRx_SEC10_Msk /*!< Security configuration for peripheral 10 */
#define RIFSC_RISC_SECCFGRx_SEC11_Pos (11U)
#define RIFSC_RISC_SECCFGRx_SEC11_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC11_Pos) /*!< 0x00000800 */
#define RIFSC_RISC_SECCFGRx_SEC11 RIFSC_RISC_SECCFGRx_SEC11_Msk /*!< Security configuration for peripheral 11 */
#define RIFSC_RISC_SECCFGRx_SEC12_Pos (12U)
#define RIFSC_RISC_SECCFGRx_SEC12_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC12_Pos) /*!< 0x00001000 */
#define RIFSC_RISC_SECCFGRx_SEC12 RIFSC_RISC_SECCFGRx_SEC12_Msk /*!< Security configuration for peripheral 12 */
#define RIFSC_RISC_SECCFGRx_SEC13_Pos (13U)
#define RIFSC_RISC_SECCFGRx_SEC13_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC13_Pos) /*!< 0x00002000 */
#define RIFSC_RISC_SECCFGRx_SEC13 RIFSC_RISC_SECCFGRx_SEC13_Msk /*!< Security configuration for peripheral 13 */
#define RIFSC_RISC_SECCFGRx_SEC14_Pos (14U)
#define RIFSC_RISC_SECCFGRx_SEC14_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC14_Pos) /*!< 0x00004000 */
#define RIFSC_RISC_SECCFGRx_SEC14 RIFSC_RISC_SECCFGRx_SEC14_Msk /*!< Security configuration for peripheral 14 */
#define RIFSC_RISC_SECCFGRx_SEC15_Pos (15U)
#define RIFSC_RISC_SECCFGRx_SEC15_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC15_Pos) /*!< 0x00008000 */
#define RIFSC_RISC_SECCFGRx_SEC15 RIFSC_RISC_SECCFGRx_SEC15_Msk /*!< Security configuration for peripheral 15 */
#define RIFSC_RISC_SECCFGRx_SEC16_Pos (16U)
#define RIFSC_RISC_SECCFGRx_SEC16_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC16_Pos) /*!< 0x00010000 */
#define RIFSC_RISC_SECCFGRx_SEC16 RIFSC_RISC_SECCFGRx_SEC16_Msk /*!< Security configuration for peripheral 16 */
#define RIFSC_RISC_SECCFGRx_SEC17_Pos (17U)
#define RIFSC_RISC_SECCFGRx_SEC17_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC17_Pos) /*!< 0x00020000 */
#define RIFSC_RISC_SECCFGRx_SEC17 RIFSC_RISC_SECCFGRx_SEC17_Msk /*!< Security configuration for peripheral 17 */
#define RIFSC_RISC_SECCFGRx_SEC18_Pos (18U)
#define RIFSC_RISC_SECCFGRx_SEC18_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC18_Pos) /*!< 0x00040000 */
#define RIFSC_RISC_SECCFGRx_SEC18 RIFSC_RISC_SECCFGRx_SEC18_Msk /*!< Security configuration for peripheral 18 */
#define RIFSC_RISC_SECCFGRx_SEC19_Pos (19U)
#define RIFSC_RISC_SECCFGRx_SEC19_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC19_Pos) /*!< 0x00080000 */
#define RIFSC_RISC_SECCFGRx_SEC19 RIFSC_RISC_SECCFGRx_SEC19_Msk /*!< Security configuration for peripheral 19 */
#define RIFSC_RISC_SECCFGRx_SEC20_Pos (20U)
#define RIFSC_RISC_SECCFGRx_SEC20_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC20_Pos) /*!< 0x00100000 */
#define RIFSC_RISC_SECCFGRx_SEC20 RIFSC_RISC_SECCFGRx_SEC20_Msk /*!< Security configuration for peripheral 20 */
#define RIFSC_RISC_SECCFGRx_SEC21_Pos (21U)
#define RIFSC_RISC_SECCFGRx_SEC21_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC21_Pos) /*!< 0x00200000 */
#define RIFSC_RISC_SECCFGRx_SEC21 RIFSC_RISC_SECCFGRx_SEC21_Msk /*!< Security configuration for peripheral 21 */
#define RIFSC_RISC_SECCFGRx_SEC22_Pos (22U)
#define RIFSC_RISC_SECCFGRx_SEC22_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC22_Pos) /*!< 0x00400000 */
#define RIFSC_RISC_SECCFGRx_SEC22 RIFSC_RISC_SECCFGRx_SEC22_Msk /*!< Security configuration for peripheral 22 */
#define RIFSC_RISC_SECCFGRx_SEC23_Pos (23U)
#define RIFSC_RISC_SECCFGRx_SEC23_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC23_Pos) /*!< 0x00800000 */
#define RIFSC_RISC_SECCFGRx_SEC23 RIFSC_RISC_SECCFGRx_SEC23_Msk /*!< Security configuration for peripheral 23 */
#define RIFSC_RISC_SECCFGRx_SEC24_Pos (24U)
#define RIFSC_RISC_SECCFGRx_SEC24_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC24_Pos) /*!< 0x01000000 */
#define RIFSC_RISC_SECCFGRx_SEC24 RIFSC_RISC_SECCFGRx_SEC24_Msk /*!< Security configuration for peripheral 24 */
#define RIFSC_RISC_SECCFGRx_SEC25_Pos (25U)
#define RIFSC_RISC_SECCFGRx_SEC25_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC25_Pos) /*!< 0x02000000 */
#define RIFSC_RISC_SECCFGRx_SEC25 RIFSC_RISC_SECCFGRx_SEC25_Msk /*!< Security configuration for peripheral 25 */
#define RIFSC_RISC_SECCFGRx_SEC26_Pos (26U)
#define RIFSC_RISC_SECCFGRx_SEC26_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC26_Pos) /*!< 0x04000000 */
#define RIFSC_RISC_SECCFGRx_SEC26 RIFSC_RISC_SECCFGRx_SEC26_Msk /*!< Security configuration for peripheral 26 */
#define RIFSC_RISC_SECCFGRx_SEC27_Pos (27U)
#define RIFSC_RISC_SECCFGRx_SEC27_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC27_Pos) /*!< 0x08000000 */
#define RIFSC_RISC_SECCFGRx_SEC27 RIFSC_RISC_SECCFGRx_SEC27_Msk /*!< Security configuration for peripheral 27 */
#define RIFSC_RISC_SECCFGRx_SEC28_Pos (28U)
#define RIFSC_RISC_SECCFGRx_SEC28_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC28_Pos) /*!< 0x10000000 */
#define RIFSC_RISC_SECCFGRx_SEC28 RIFSC_RISC_SECCFGRx_SEC28_Msk /*!< Security configuration for peripheral 28 */
#define RIFSC_RISC_SECCFGRx_SEC29_Pos (29U)
#define RIFSC_RISC_SECCFGRx_SEC29_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC29_Pos) /*!< 0x20000000 */
#define RIFSC_RISC_SECCFGRx_SEC29 RIFSC_RISC_SECCFGRx_SEC29_Msk /*!< Security configuration for peripheral 29 */
#define RIFSC_RISC_SECCFGRx_SEC30_Pos (30U)
#define RIFSC_RISC_SECCFGRx_SEC30_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC30_Pos) /*!< 0x40000000 */
#define RIFSC_RISC_SECCFGRx_SEC30 RIFSC_RISC_SECCFGRx_SEC30_Msk /*!< Security configuration for peripheral 30 */
#define RIFSC_RISC_SECCFGRx_SEC31_Pos (31U)
#define RIFSC_RISC_SECCFGRx_SEC31_Msk (0x1UL << RIFSC_RISC_SECCFGRx_SEC31_Pos) /*!< 0x80000000 */
#define RIFSC_RISC_SECCFGRx_SEC31 RIFSC_RISC_SECCFGRx_SEC31_Msk /*!< Security configuration for peripheral 31 */
/************* Bit definition for RIFSC_RISC_PRIVCFGRx register *************/
#define RIFSC_RISC_PRIVCFGRx_PRIV0_Pos (0U)
#define RIFSC_RISC_PRIVCFGRx_PRIV0_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV0_Pos) /*!< 0x00000001 */
#define RIFSC_RISC_PRIVCFGRx_PRIV0 RIFSC_RISC_PRIVCFGRx_PRIV0_Msk /*!< privileged-only access permission for peripheral 0 */
#define RIFSC_RISC_PRIVCFGRx_PRIV1_Pos (1U)
#define RIFSC_RISC_PRIVCFGRx_PRIV1_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV1_Pos) /*!< 0x00000002 */
#define RIFSC_RISC_PRIVCFGRx_PRIV1 RIFSC_RISC_PRIVCFGRx_PRIV1_Msk /*!< privileged-only access permission for peripheral 1 */
#define RIFSC_RISC_PRIVCFGRx_PRIV2_Pos (2U)
#define RIFSC_RISC_PRIVCFGRx_PRIV2_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV2_Pos) /*!< 0x00000004 */
#define RIFSC_RISC_PRIVCFGRx_PRIV2 RIFSC_RISC_PRIVCFGRx_PRIV2_Msk /*!< privileged-only access permission for peripheral 2 */
#define RIFSC_RISC_PRIVCFGRx_PRIV3_Pos (3U)
#define RIFSC_RISC_PRIVCFGRx_PRIV3_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV3_Pos) /*!< 0x00000008 */
#define RIFSC_RISC_PRIVCFGRx_PRIV3 RIFSC_RISC_PRIVCFGRx_PRIV3_Msk /*!< privileged-only access permission for peripheral 3 */
#define RIFSC_RISC_PRIVCFGRx_PRIV4_Pos (4U)
#define RIFSC_RISC_PRIVCFGRx_PRIV4_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV4_Pos) /*!< 0x00000010 */
#define RIFSC_RISC_PRIVCFGRx_PRIV4 RIFSC_RISC_PRIVCFGRx_PRIV4_Msk /*!< privileged-only access permission for peripheral 4 */
#define RIFSC_RISC_PRIVCFGRx_PRIV5_Pos (5U)
#define RIFSC_RISC_PRIVCFGRx_PRIV5_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV5_Pos) /*!< 0x00000020 */
#define RIFSC_RISC_PRIVCFGRx_PRIV5 RIFSC_RISC_PRIVCFGRx_PRIV5_Msk /*!< privileged-only access permission for peripheral 5 */
#define RIFSC_RISC_PRIVCFGRx_PRIV6_Pos (6U)
#define RIFSC_RISC_PRIVCFGRx_PRIV6_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV6_Pos) /*!< 0x00000040 */
#define RIFSC_RISC_PRIVCFGRx_PRIV6 RIFSC_RISC_PRIVCFGRx_PRIV6_Msk /*!< privileged-only access permission for peripheral 6 */
#define RIFSC_RISC_PRIVCFGRx_PRIV7_Pos (7U)
#define RIFSC_RISC_PRIVCFGRx_PRIV7_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV7_Pos) /*!< 0x00000080 */
#define RIFSC_RISC_PRIVCFGRx_PRIV7 RIFSC_RISC_PRIVCFGRx_PRIV7_Msk /*!< privileged-only access permission for peripheral 7 */
#define RIFSC_RISC_PRIVCFGRx_PRIV8_Pos (8U)
#define RIFSC_RISC_PRIVCFGRx_PRIV8_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV8_Pos) /*!< 0x00000100 */
#define RIFSC_RISC_PRIVCFGRx_PRIV8 RIFSC_RISC_PRIVCFGRx_PRIV8_Msk /*!< privileged-only access permission for peripheral 8 */
#define RIFSC_RISC_PRIVCFGRx_PRIV9_Pos (9U)
#define RIFSC_RISC_PRIVCFGRx_PRIV9_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV9_Pos) /*!< 0x00000200 */
#define RIFSC_RISC_PRIVCFGRx_PRIV9 RIFSC_RISC_PRIVCFGRx_PRIV9_Msk /*!< privileged-only access permission for peripheral 9 */
#define RIFSC_RISC_PRIVCFGRx_PRIV10_Pos (10U)
#define RIFSC_RISC_PRIVCFGRx_PRIV10_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV10_Pos) /*!< 0x00000400 */
#define RIFSC_RISC_PRIVCFGRx_PRIV10 RIFSC_RISC_PRIVCFGRx_PRIV10_Msk /*!< privileged-only access permission for peripheral 10 */
#define RIFSC_RISC_PRIVCFGRx_PRIV11_Pos (11U)
#define RIFSC_RISC_PRIVCFGRx_PRIV11_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV11_Pos) /*!< 0x00000800 */
#define RIFSC_RISC_PRIVCFGRx_PRIV11 RIFSC_RISC_PRIVCFGRx_PRIV11_Msk /*!< privileged-only access permission for peripheral 11 */
#define RIFSC_RISC_PRIVCFGRx_PRIV12_Pos (12U)
#define RIFSC_RISC_PRIVCFGRx_PRIV12_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV12_Pos) /*!< 0x00001000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV12 RIFSC_RISC_PRIVCFGRx_PRIV12_Msk /*!< privileged-only access permission for peripheral 12 */
#define RIFSC_RISC_PRIVCFGRx_PRIV13_Pos (13U)
#define RIFSC_RISC_PRIVCFGRx_PRIV13_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV13_Pos) /*!< 0x00002000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV13 RIFSC_RISC_PRIVCFGRx_PRIV13_Msk /*!< privileged-only access permission for peripheral 13 */
#define RIFSC_RISC_PRIVCFGRx_PRIV14_Pos (14U)
#define RIFSC_RISC_PRIVCFGRx_PRIV14_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV14_Pos) /*!< 0x00004000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV14 RIFSC_RISC_PRIVCFGRx_PRIV14_Msk /*!< privileged-only access permission for peripheral 14 */
#define RIFSC_RISC_PRIVCFGRx_PRIV15_Pos (15U)
#define RIFSC_RISC_PRIVCFGRx_PRIV15_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV15_Pos) /*!< 0x00008000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV15 RIFSC_RISC_PRIVCFGRx_PRIV15_Msk /*!< privileged-only access permission for peripheral 15 */
#define RIFSC_RISC_PRIVCFGRx_PRIV16_Pos (16U)
#define RIFSC_RISC_PRIVCFGRx_PRIV16_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV16_Pos) /*!< 0x00010000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV16 RIFSC_RISC_PRIVCFGRx_PRIV16_Msk /*!< privileged-only access permission for peripheral 16 */
#define RIFSC_RISC_PRIVCFGRx_PRIV17_Pos (17U)
#define RIFSC_RISC_PRIVCFGRx_PRIV17_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV17_Pos) /*!< 0x00020000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV17 RIFSC_RISC_PRIVCFGRx_PRIV17_Msk /*!< privileged-only access permission for peripheral 17 */
#define RIFSC_RISC_PRIVCFGRx_PRIV18_Pos (18U)
#define RIFSC_RISC_PRIVCFGRx_PRIV18_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV18_Pos) /*!< 0x00040000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV18 RIFSC_RISC_PRIVCFGRx_PRIV18_Msk /*!< privileged-only access permission for peripheral 18 */
#define RIFSC_RISC_PRIVCFGRx_PRIV19_Pos (19U)
#define RIFSC_RISC_PRIVCFGRx_PRIV19_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV19_Pos) /*!< 0x00080000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV19 RIFSC_RISC_PRIVCFGRx_PRIV19_Msk /*!< privileged-only access permission for peripheral 19 */
#define RIFSC_RISC_PRIVCFGRx_PRIV20_Pos (20U)
#define RIFSC_RISC_PRIVCFGRx_PRIV20_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV20_Pos) /*!< 0x00100000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV20 RIFSC_RISC_PRIVCFGRx_PRIV20_Msk /*!< privileged-only access permission for peripheral 20 */
#define RIFSC_RISC_PRIVCFGRx_PRIV21_Pos (21U)
#define RIFSC_RISC_PRIVCFGRx_PRIV21_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV21_Pos) /*!< 0x00200000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV21 RIFSC_RISC_PRIVCFGRx_PRIV21_Msk /*!< privileged-only access permission for peripheral 21 */
#define RIFSC_RISC_PRIVCFGRx_PRIV22_Pos (22U)
#define RIFSC_RISC_PRIVCFGRx_PRIV22_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV22_Pos) /*!< 0x00400000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV22 RIFSC_RISC_PRIVCFGRx_PRIV22_Msk /*!< privileged-only access permission for peripheral 22 */
#define RIFSC_RISC_PRIVCFGRx_PRIV23_Pos (23U)
#define RIFSC_RISC_PRIVCFGRx_PRIV23_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV23_Pos) /*!< 0x00800000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV23 RIFSC_RISC_PRIVCFGRx_PRIV23_Msk /*!< privileged-only access permission for peripheral 23 */
#define RIFSC_RISC_PRIVCFGRx_PRIV24_Pos (24U)
#define RIFSC_RISC_PRIVCFGRx_PRIV24_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV24_Pos) /*!< 0x01000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV24 RIFSC_RISC_PRIVCFGRx_PRIV24_Msk /*!< privileged-only access permission for peripheral 24 */
#define RIFSC_RISC_PRIVCFGRx_PRIV25_Pos (25U)
#define RIFSC_RISC_PRIVCFGRx_PRIV25_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV25_Pos) /*!< 0x02000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV25 RIFSC_RISC_PRIVCFGRx_PRIV25_Msk /*!< privileged-only access permission for peripheral 25 */
#define RIFSC_RISC_PRIVCFGRx_PRIV26_Pos (26U)
#define RIFSC_RISC_PRIVCFGRx_PRIV26_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV26_Pos) /*!< 0x04000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV26 RIFSC_RISC_PRIVCFGRx_PRIV26_Msk /*!< privileged-only access permission for peripheral 26 */
#define RIFSC_RISC_PRIVCFGRx_PRIV27_Pos (27U)
#define RIFSC_RISC_PRIVCFGRx_PRIV27_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV27_Pos) /*!< 0x08000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV27 RIFSC_RISC_PRIVCFGRx_PRIV27_Msk /*!< privileged-only access permission for peripheral 27 */
#define RIFSC_RISC_PRIVCFGRx_PRIV28_Pos (28U)
#define RIFSC_RISC_PRIVCFGRx_PRIV28_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV28_Pos) /*!< 0x10000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV28 RIFSC_RISC_PRIVCFGRx_PRIV28_Msk /*!< privileged-only access permission for peripheral 28 */
#define RIFSC_RISC_PRIVCFGRx_PRIV29_Pos (29U)
#define RIFSC_RISC_PRIVCFGRx_PRIV29_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV29_Pos) /*!< 0x20000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV29 RIFSC_RISC_PRIVCFGRx_PRIV29_Msk /*!< privileged-only access permission for peripheral 29 */
#define RIFSC_RISC_PRIVCFGRx_PRIV30_Pos (30U)
#define RIFSC_RISC_PRIVCFGRx_PRIV30_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV30_Pos) /*!< 0x40000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV30 RIFSC_RISC_PRIVCFGRx_PRIV30_Msk /*!< privileged-only access permission for peripheral 30 */
#define RIFSC_RISC_PRIVCFGRx_PRIV31_Pos (31U)
#define RIFSC_RISC_PRIVCFGRx_PRIV31_Msk (0x1UL << RIFSC_RISC_PRIVCFGRx_PRIV31_Pos) /*!< 0x80000000 */
#define RIFSC_RISC_PRIVCFGRx_PRIV31 RIFSC_RISC_PRIVCFGRx_PRIV31_Msk /*!< privileged-only access permission for peripheral 31 */
/************* Bit definition for RIFSC_RISC_RCFGLOCKRx register *************/
#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos (0U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK0_Pos) /*!< 0x00000001 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK0 RIFSC_RISC_RCFGLOCKRx_RLOCK0_Msk /*!< Resource lock for peripheral 0 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos (1U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK1_Pos) /*!< 0x00000002 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK1 RIFSC_RISC_RCFGLOCKRx_RLOCK1_Msk /*!< Resource lock for peripheral 1 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos (2U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK2_Pos) /*!< 0x00000004 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK2 RIFSC_RISC_RCFGLOCKRx_RLOCK2_Msk /*!< Resource lock for peripheral 2 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos (3U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK3_Pos) /*!< 0x00000008 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK3 RIFSC_RISC_RCFGLOCKRx_RLOCK3_Msk /*!< Resource lock for peripheral 3 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos (4U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK4_Pos) /*!< 0x00000010 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK4 RIFSC_RISC_RCFGLOCKRx_RLOCK4_Msk /*!< Resource lock for peripheral 4 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos (5U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK5_Pos) /*!< 0x00000020 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK5 RIFSC_RISC_RCFGLOCKRx_RLOCK5_Msk /*!< Resource lock for peripheral 5 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos (6U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK6_Pos) /*!< 0x00000040 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK6 RIFSC_RISC_RCFGLOCKRx_RLOCK6_Msk /*!< Resource lock for peripheral 6 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos (7U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK7_Pos) /*!< 0x00000080 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK7 RIFSC_RISC_RCFGLOCKRx_RLOCK7_Msk /*!< Resource lock for peripheral 7 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos (8U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK8_Pos) /*!< 0x00000100 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK8 RIFSC_RISC_RCFGLOCKRx_RLOCK8_Msk /*!< Resource lock for peripheral 8 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos (9U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK9_Pos) /*!< 0x00000200 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK9 RIFSC_RISC_RCFGLOCKRx_RLOCK9_Msk /*!< Resource lock for peripheral 9 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos (10U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK10_Pos) /*!< 0x00000400 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK10 RIFSC_RISC_RCFGLOCKRx_RLOCK10_Msk /*!< Resource lock for peripheral 10 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos (11U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK11_Pos) /*!< 0x00000800 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK11 RIFSC_RISC_RCFGLOCKRx_RLOCK11_Msk /*!< Resource lock for peripheral 11 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos (12U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK12_Pos) /*!< 0x00001000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK12 RIFSC_RISC_RCFGLOCKRx_RLOCK12_Msk /*!< Resource lock for peripheral 12 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos (13U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK13_Pos) /*!< 0x00002000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK13 RIFSC_RISC_RCFGLOCKRx_RLOCK13_Msk /*!< Resource lock for peripheral 13 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos (14U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK14_Pos) /*!< 0x00004000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK14 RIFSC_RISC_RCFGLOCKRx_RLOCK14_Msk /*!< Resource lock for peripheral 14 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos (15U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK15_Pos) /*!< 0x00008000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK15 RIFSC_RISC_RCFGLOCKRx_RLOCK15_Msk /*!< Resource lock for peripheral 15 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos (16U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK16_Pos) /*!< 0x00010000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK16 RIFSC_RISC_RCFGLOCKRx_RLOCK16_Msk /*!< Resource lock for peripheral 16 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos (17U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK17_Pos) /*!< 0x00020000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK17 RIFSC_RISC_RCFGLOCKRx_RLOCK17_Msk /*!< Resource lock for peripheral 17 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos (18U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK18_Pos) /*!< 0x00040000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK18 RIFSC_RISC_RCFGLOCKRx_RLOCK18_Msk /*!< Resource lock for peripheral 18 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos (19U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK19_Pos) /*!< 0x00080000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK19 RIFSC_RISC_RCFGLOCKRx_RLOCK19_Msk /*!< Resource lock for peripheral 19 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos (20U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK20_Pos) /*!< 0x00100000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK20 RIFSC_RISC_RCFGLOCKRx_RLOCK20_Msk /*!< Resource lock for peripheral 20 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos (21U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK21_Pos) /*!< 0x00200000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK21 RIFSC_RISC_RCFGLOCKRx_RLOCK21_Msk /*!< Resource lock for peripheral 21 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos (22U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK22_Pos) /*!< 0x00400000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK22 RIFSC_RISC_RCFGLOCKRx_RLOCK22_Msk /*!< Resource lock for peripheral 22 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos (23U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK23_Pos) /*!< 0x00800000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK23 RIFSC_RISC_RCFGLOCKRx_RLOCK23_Msk /*!< Resource lock for peripheral 23 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos (24U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK24_Pos) /*!< 0x01000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK24 RIFSC_RISC_RCFGLOCKRx_RLOCK24_Msk /*!< Resource lock for peripheral 24 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos (25U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK25_Pos) /*!< 0x02000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK25 RIFSC_RISC_RCFGLOCKRx_RLOCK25_Msk /*!< Resource lock for peripheral 25 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos (26U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK26_Pos) /*!< 0x04000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK26 RIFSC_RISC_RCFGLOCKRx_RLOCK26_Msk /*!< Resource lock for peripheral 26 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos (27U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK27_Pos) /*!< 0x08000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK27 RIFSC_RISC_RCFGLOCKRx_RLOCK27_Msk /*!< Resource lock for peripheral 27 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos (28U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK28_Pos) /*!< 0x10000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK28 RIFSC_RISC_RCFGLOCKRx_RLOCK28_Msk /*!< Resource lock for peripheral 28 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos (29U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK29_Pos) /*!< 0x20000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK29 RIFSC_RISC_RCFGLOCKRx_RLOCK29_Msk /*!< Resource lock for peripheral 29 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos (30U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK30_Pos) /*!< 0x40000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK30 RIFSC_RISC_RCFGLOCKRx_RLOCK30_Msk /*!< Resource lock for peripheral 30 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos (31U)
#define RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk (0x1UL << RIFSC_RISC_RCFGLOCKRx_RLOCK31_Pos) /*!< 0x80000000 */
#define RIFSC_RISC_RCFGLOCKRx_RLOCK31 RIFSC_RISC_RCFGLOCKRx_RLOCK31_Msk /*!< Resource lock for peripheral 31 */
/**************** Bit definition for RIFSC_RIMC_CR register *****************/
#define RIFSC_RIMC_CR_GLOCK_Pos (0U)
#define RIFSC_RIMC_CR_GLOCK_Msk (0x1UL << RIFSC_RIMC_CR_GLOCK_Pos) /*!< 0x00000001 */
#define RIFSC_RIMC_CR_GLOCK RIFSC_RIMC_CR_GLOCK_Msk /*!< Global lock */
#define RIFSC_RIMC_CR_DAPCID_Pos (8U)
#define RIFSC_RIMC_CR_DAPCID_Msk (0x7UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000700 */
#define RIFSC_RIMC_CR_DAPCID RIFSC_RIMC_CR_DAPCID_Msk /*!< Debug access port compartment ID */
#define RIFSC_RIMC_CR_DAPCID_0 (0x1UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000100 */
#define RIFSC_RIMC_CR_DAPCID_1 (0x2UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000200 */
#define RIFSC_RIMC_CR_DAPCID_2 (0x4UL << RIFSC_RIMC_CR_DAPCID_Pos) /*!< 0x00000400 */
/*************** Bit definition for RIFSC_RIMC_ATTRx register ***************/
#define RIFSC_RIMC_ATTRx_MCID_Pos (4U)
#define RIFSC_RIMC_ATTRx_MCID_Msk (0x7UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000070 */
#define RIFSC_RIMC_ATTRx_MCID RIFSC_RIMC_ATTRx_MCID_Msk /*!< Master CID */
#define RIFSC_RIMC_ATTRx_MCID_0 (0x1UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000010 */
#define RIFSC_RIMC_ATTRx_MCID_1 (0x2UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000020 */
#define RIFSC_RIMC_ATTRx_MCID_2 (0x4UL << RIFSC_RIMC_ATTRx_MCID_Pos) /*!< 0x00000040 */
#define RIFSC_RIMC_ATTRx_MSEC_Pos (8U)
#define RIFSC_RIMC_ATTRx_MSEC_Msk (0x1UL << RIFSC_RIMC_ATTRx_MSEC_Pos) /*!< 0x00000100 */
#define RIFSC_RIMC_ATTRx_MSEC RIFSC_RIMC_ATTRx_MSEC_Msk /*!< Master secure */
#define RIFSC_RIMC_ATTRx_MPRIV_Pos (9U)
#define RIFSC_RIMC_ATTRx_MPRIV_Msk (0x1UL << RIFSC_RIMC_ATTRx_MPRIV_Pos) /*!< 0x00000200 */
#define RIFSC_RIMC_ATTRx_MPRIV RIFSC_RIMC_ATTRx_MPRIV_Msk /*!< Master privileged */
/******************************************************************************/
/* */
/* Resource Isolation Slave unit for Address space protection (RISAF) */
/* */
/******************************************************************************/
/******************* Bit definition for RISAF_CR register *******************/
#define RISAF_CR_GLOCK_Pos (0U)
#define RISAF_CR_GLOCK_Msk (0x1UL << RISAF_CR_GLOCK_Pos) /*!< 0x00000001 */
#define RISAF_CR_GLOCK RISAF_CR_GLOCK_Msk /*!< Global lock */
/****************** Bit definition for RISAF_IASR register ******************/
#define RISAF_IASR_CAEF_Pos (0U)
#define RISAF_IASR_CAEF_Msk (0x1UL << RISAF_IASR_CAEF_Pos) /*!< 0x00000001 */
#define RISAF_IASR_CAEF RISAF_IASR_CAEF_Msk /*!< Configuration access error flag */
#define RISAF_IASR_IAEF_Pos (1U)
#define RISAF_IASR_IAEF_Msk (0x1UL << RISAF_IASR_IAEF_Pos) /*!< 0x00000002 */
#define RISAF_IASR_IAEF RISAF_IASR_IAEF_Msk /*!< Illegal access error flag */
/****************** Bit definition for RISAF_IACR register ******************/
#define RISAF_IACR_CAEF_Pos (0U)
#define RISAF_IACR_CAEF_Msk (0x1UL << RISAF_IACR_CAEF_Pos) /*!< 0x00000001 */
#define RISAF_IACR_CAEF RISAF_IACR_CAEF_Msk /*!< Configuration access error flag */
#define RISAF_IACR_IAEF_Pos (1U)
#define RISAF_IACR_IAEF_Msk (0x1UL << RISAF_IACR_IAEF_Pos) /*!< 0x00000002 */
#define RISAF_IACR_IAEF RISAF_IACR_IAEF_Msk /*!< Illegal access error flag */
/***************** Bit definition for RISAF_IAESR register *****************/
#define RISAF_IAESR_IACID_Pos (0U)
#define RISAF_IAESR_IACID_Msk (0x7UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000007 */
#define RISAF_IAESR_IACID RISAF_IAESR_IACID_Msk /*!< Illegal access compartment ID */
#define RISAF_IAESR_IACID_0 (0x1UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000001 */
#define RISAF_IAESR_IACID_1 (0x2UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000002 */
#define RISAF_IAESR_IACID_2 (0x4UL << RISAF_IAESR_IACID_Pos) /*!< 0x00000004 */
#define RISAF_IAESR_IAPRIV_Pos (4U)
#define RISAF_IAESR_IAPRIV_Msk (0x1UL << RISAF_IAESR_IAPRIV_Pos) /*!< 0x00000010 */
#define RISAF_IAESR_IAPRIV RISAF_IAESR_IAPRIV_Msk /*!< Illegal access privileged */
#define RISAF_IAESR_IASEC_Pos (5U)
#define RISAF_IAESR_IASEC_Msk (0x1UL << RISAF_IAESR_IASEC_Pos) /*!< 0x00000020 */
#define RISAF_IAESR_IASEC RISAF_IAESR_IASEC_Msk /*!< Illegal access security */
#define RISAF_IAESR_IANRW_Pos (7U)
#define RISAF_IAESR_IANRW_Msk (0x1UL << RISAF_IAESR_IANRW_Pos) /*!< 0x00000080 */
#define RISAF_IAESR_IANRW RISAF_IAESR_IANRW_Msk /*!< Illegal access read/write */
/***************** Bit definition for RISAF_IADDR register *****************/
#define RISAF_IADDR_IADD_Pos (0U)
#define RISAF_IADDR_IADD_Msk (0xFFFFFFFFUL << RISAF_IADDR_IADD_Pos) /*!< 0xFFFFFFFF */
#define RISAF_IADDR_IADD RISAF_IADDR_IADD_Msk /*!< Illegal address */
#define RISAF_IADDR_IADD_0 (0x1UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000001 */
#define RISAF_IADDR_IADD_1 (0x2UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000002 */
#define RISAF_IADDR_IADD_2 (0x4UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000004 */
#define RISAF_IADDR_IADD_3 (0x8UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000008 */
#define RISAF_IADDR_IADD_4 (0x10UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000010 */
#define RISAF_IADDR_IADD_5 (0x20UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000020 */
#define RISAF_IADDR_IADD_6 (0x40UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000040 */
#define RISAF_IADDR_IADD_7 (0x80UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000080 */
#define RISAF_IADDR_IADD_8 (0x100UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000100 */
#define RISAF_IADDR_IADD_9 (0x200UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000200 */
#define RISAF_IADDR_IADD_10 (0x400UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000400 */
#define RISAF_IADDR_IADD_11 (0x800UL << RISAF_IADDR_IADD_Pos) /*!< 0x00000800 */
#define RISAF_IADDR_IADD_12 (0x1000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00001000 */
#define RISAF_IADDR_IADD_13 (0x2000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00002000 */
#define RISAF_IADDR_IADD_14 (0x4000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00004000 */
#define RISAF_IADDR_IADD_15 (0x8000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00008000 */
#define RISAF_IADDR_IADD_16 (0x10000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00010000 */
#define RISAF_IADDR_IADD_17 (0x20000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00020000 */
#define RISAF_IADDR_IADD_18 (0x40000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00040000 */
#define RISAF_IADDR_IADD_19 (0x80000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00080000 */
#define RISAF_IADDR_IADD_20 (0x100000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00100000 */
#define RISAF_IADDR_IADD_21 (0x200000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00200000 */
#define RISAF_IADDR_IADD_22 (0x400000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00400000 */
#define RISAF_IADDR_IADD_23 (0x800000UL << RISAF_IADDR_IADD_Pos) /*!< 0x00800000 */
#define RISAF_IADDR_IADD_24 (0x1000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x01000000 */
#define RISAF_IADDR_IADD_25 (0x2000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x02000000 */
#define RISAF_IADDR_IADD_26 (0x4000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x04000000 */
#define RISAF_IADDR_IADD_27 (0x8000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x08000000 */
#define RISAF_IADDR_IADD_28 (0x10000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x10000000 */
#define RISAF_IADDR_IADD_29 (0x20000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x20000000 */
#define RISAF_IADDR_IADD_30 (0x40000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x40000000 */
#define RISAF_IADDR_IADD_31 (0x80000000UL << RISAF_IADDR_IADD_Pos) /*!< 0x80000000 */
/*************** Bit definition for RISAF_REGx_CFGR register ****************/
#define RISAF_REGx_CFGR_BREN_Pos (0U)
#define RISAF_REGx_CFGR_BREN_Msk (0x1UL << RISAF_REGx_CFGR_BREN_Pos) /*!< 0x00000001 */
#define RISAF_REGx_CFGR_BREN RISAF_REGx_CFGR_BREN_Msk /*!< Base region enable */
#define RISAF_REGx_CFGR_SEC_Pos (8U)
#define RISAF_REGx_CFGR_SEC_Msk (0x1UL << RISAF_REGx_CFGR_SEC_Pos) /*!< 0x00000100 */
#define RISAF_REGx_CFGR_SEC RISAF_REGx_CFGR_SEC_Msk /*!< Secure region */
#define RISAF_REGx_CFGR_PRIVC0_Pos (16U)
#define RISAF_REGx_CFGR_PRIVC0_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC0_Pos) /*!< 0x00010000 */
#define RISAF_REGx_CFGR_PRIVC0 RISAF_REGx_CFGR_PRIVC0_Msk /*!< Privileged access for compartment 0 */
#define RISAF_REGx_CFGR_PRIVC1_Pos (17U)
#define RISAF_REGx_CFGR_PRIVC1_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC1_Pos) /*!< 0x00020000 */
#define RISAF_REGx_CFGR_PRIVC1 RISAF_REGx_CFGR_PRIVC1_Msk /*!< Privileged access for compartment 1 */
#define RISAF_REGx_CFGR_PRIVC2_Pos (18U)
#define RISAF_REGx_CFGR_PRIVC2_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC2_Pos) /*!< 0x00040000 */
#define RISAF_REGx_CFGR_PRIVC2 RISAF_REGx_CFGR_PRIVC2_Msk /*!< Privileged access for compartment 2 */
#define RISAF_REGx_CFGR_PRIVC3_Pos (19U)
#define RISAF_REGx_CFGR_PRIVC3_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC3_Pos) /*!< 0x00080000 */
#define RISAF_REGx_CFGR_PRIVC3 RISAF_REGx_CFGR_PRIVC3_Msk /*!< Privileged access for compartment 3 */
#define RISAF_REGx_CFGR_PRIVC4_Pos (20U)
#define RISAF_REGx_CFGR_PRIVC4_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC4_Pos) /*!< 0x00100000 */
#define RISAF_REGx_CFGR_PRIVC4 RISAF_REGx_CFGR_PRIVC4_Msk /*!< Privileged access for compartment 4 */
#define RISAF_REGx_CFGR_PRIVC5_Pos (21U)
#define RISAF_REGx_CFGR_PRIVC5_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC5_Pos) /*!< 0x00200000 */
#define RISAF_REGx_CFGR_PRIVC5 RISAF_REGx_CFGR_PRIVC5_Msk /*!< Privileged access for compartment 5 */
#define RISAF_REGx_CFGR_PRIVC6_Pos (22U)
#define RISAF_REGx_CFGR_PRIVC6_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC6_Pos) /*!< 0x00400000 */
#define RISAF_REGx_CFGR_PRIVC6 RISAF_REGx_CFGR_PRIVC6_Msk /*!< Privileged access for compartment 6 */
#define RISAF_REGx_CFGR_PRIVC7_Pos (23U)
#define RISAF_REGx_CFGR_PRIVC7_Msk (0x1UL << RISAF_REGx_CFGR_PRIVC7_Pos) /*!< 0x00800000 */
#define RISAF_REGx_CFGR_PRIVC7 RISAF_REGx_CFGR_PRIVC7_Msk /*!< Privileged access for compartment 7 */
/************** Bit definition for RISAF_REGx_STARTR register ***************/
#define RISAF_REGx_STARTR_BADDSTART_Pos (0U)
#define RISAF_REGx_STARTR_BADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0xFFFFFFFF */
#define RISAF_REGx_STARTR_BADDSTART RISAF_REGx_STARTR_BADDSTART_Msk /*!< Base region address start */
#define RISAF_REGx_STARTR_BADDSTART_0 (0x1UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000001 */
#define RISAF_REGx_STARTR_BADDSTART_1 (0x2UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000002 */
#define RISAF_REGx_STARTR_BADDSTART_2 (0x4UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000004 */
#define RISAF_REGx_STARTR_BADDSTART_3 (0x8UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000008 */
#define RISAF_REGx_STARTR_BADDSTART_4 (0x10UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000010 */
#define RISAF_REGx_STARTR_BADDSTART_5 (0x20UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000020 */
#define RISAF_REGx_STARTR_BADDSTART_6 (0x40UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000040 */
#define RISAF_REGx_STARTR_BADDSTART_7 (0x80UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000080 */
#define RISAF_REGx_STARTR_BADDSTART_8 (0x100UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000100 */
#define RISAF_REGx_STARTR_BADDSTART_9 (0x200UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000200 */
#define RISAF_REGx_STARTR_BADDSTART_10 (0x400UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000400 */
#define RISAF_REGx_STARTR_BADDSTART_11 (0x800UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00000800 */
#define RISAF_REGx_STARTR_BADDSTART_12 (0x1000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00001000 */
#define RISAF_REGx_STARTR_BADDSTART_13 (0x2000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00002000 */
#define RISAF_REGx_STARTR_BADDSTART_14 (0x4000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00004000 */
#define RISAF_REGx_STARTR_BADDSTART_15 (0x8000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00008000 */
#define RISAF_REGx_STARTR_BADDSTART_16 (0x10000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00010000 */
#define RISAF_REGx_STARTR_BADDSTART_17 (0x20000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00020000 */
#define RISAF_REGx_STARTR_BADDSTART_18 (0x40000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00040000 */
#define RISAF_REGx_STARTR_BADDSTART_19 (0x80000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00080000 */
#define RISAF_REGx_STARTR_BADDSTART_20 (0x100000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00100000 */
#define RISAF_REGx_STARTR_BADDSTART_21 (0x200000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00200000 */
#define RISAF_REGx_STARTR_BADDSTART_22 (0x400000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00400000 */
#define RISAF_REGx_STARTR_BADDSTART_23 (0x800000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x00800000 */
#define RISAF_REGx_STARTR_BADDSTART_24 (0x1000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x01000000 */
#define RISAF_REGx_STARTR_BADDSTART_25 (0x2000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x02000000 */
#define RISAF_REGx_STARTR_BADDSTART_26 (0x4000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x04000000 */
#define RISAF_REGx_STARTR_BADDSTART_27 (0x8000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x08000000 */
#define RISAF_REGx_STARTR_BADDSTART_28 (0x10000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x10000000 */
#define RISAF_REGx_STARTR_BADDSTART_29 (0x20000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x20000000 */
#define RISAF_REGx_STARTR_BADDSTART_30 (0x40000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x40000000 */
#define RISAF_REGx_STARTR_BADDSTART_31 (0x80000000UL << RISAF_REGx_STARTR_BADDSTART_Pos) /*!< 0x80000000 */
/*************** Bit definition for RISAF_REGx_ENDR register ****************/
#define RISAF_REGx_ENDR_BADDEND_Pos (0U)
#define RISAF_REGx_ENDR_BADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0xFFFFFFFF */
#define RISAF_REGx_ENDR_BADDEND RISAF_REGx_ENDR_BADDEND_Msk /*!< Base region address end */
#define RISAF_REGx_ENDR_BADDEND_0 (0x1UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000001 */
#define RISAF_REGx_ENDR_BADDEND_1 (0x2UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000002 */
#define RISAF_REGx_ENDR_BADDEND_2 (0x4UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000004 */
#define RISAF_REGx_ENDR_BADDEND_3 (0x8UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000008 */
#define RISAF_REGx_ENDR_BADDEND_4 (0x10UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000010 */
#define RISAF_REGx_ENDR_BADDEND_5 (0x20UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000020 */
#define RISAF_REGx_ENDR_BADDEND_6 (0x40UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000040 */
#define RISAF_REGx_ENDR_BADDEND_7 (0x80UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000080 */
#define RISAF_REGx_ENDR_BADDEND_8 (0x100UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000100 */
#define RISAF_REGx_ENDR_BADDEND_9 (0x200UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000200 */
#define RISAF_REGx_ENDR_BADDEND_10 (0x400UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000400 */
#define RISAF_REGx_ENDR_BADDEND_11 (0x800UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00000800 */
#define RISAF_REGx_ENDR_BADDEND_12 (0x1000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00001000 */
#define RISAF_REGx_ENDR_BADDEND_13 (0x2000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00002000 */
#define RISAF_REGx_ENDR_BADDEND_14 (0x4000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00004000 */
#define RISAF_REGx_ENDR_BADDEND_15 (0x8000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00008000 */
#define RISAF_REGx_ENDR_BADDEND_16 (0x10000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00010000 */
#define RISAF_REGx_ENDR_BADDEND_17 (0x20000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00020000 */
#define RISAF_REGx_ENDR_BADDEND_18 (0x40000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00040000 */
#define RISAF_REGx_ENDR_BADDEND_19 (0x80000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00080000 */
#define RISAF_REGx_ENDR_BADDEND_20 (0x100000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00100000 */
#define RISAF_REGx_ENDR_BADDEND_21 (0x200000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00200000 */
#define RISAF_REGx_ENDR_BADDEND_22 (0x400000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00400000 */
#define RISAF_REGx_ENDR_BADDEND_23 (0x800000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x00800000 */
#define RISAF_REGx_ENDR_BADDEND_24 (0x1000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x01000000 */
#define RISAF_REGx_ENDR_BADDEND_25 (0x2000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x02000000 */
#define RISAF_REGx_ENDR_BADDEND_26 (0x4000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x04000000 */
#define RISAF_REGx_ENDR_BADDEND_27 (0x8000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x08000000 */
#define RISAF_REGx_ENDR_BADDEND_28 (0x10000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x10000000 */
#define RISAF_REGx_ENDR_BADDEND_29 (0x20000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x20000000 */
#define RISAF_REGx_ENDR_BADDEND_30 (0x40000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x40000000 */
#define RISAF_REGx_ENDR_BADDEND_31 (0x80000000UL << RISAF_REGx_ENDR_BADDEND_Pos) /*!< 0x80000000 */
/************** Bit definition for RISAF_REGx_CIDCFGR register **************/
#define RISAF_REGx_CIDCFGR_RDENC0_Pos (0U)
#define RISAF_REGx_CIDCFGR_RDENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC0_Pos) /*!< 0x00000001 */
#define RISAF_REGx_CIDCFGR_RDENC0 RISAF_REGx_CIDCFGR_RDENC0_Msk /*!< Read enable for compartment 0 */
#define RISAF_REGx_CIDCFGR_RDENC1_Pos (1U)
#define RISAF_REGx_CIDCFGR_RDENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC1_Pos) /*!< 0x00000002 */
#define RISAF_REGx_CIDCFGR_RDENC1 RISAF_REGx_CIDCFGR_RDENC1_Msk /*!< Read enable for compartment 1 */
#define RISAF_REGx_CIDCFGR_RDENC2_Pos (2U)
#define RISAF_REGx_CIDCFGR_RDENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC2_Pos) /*!< 0x00000004 */
#define RISAF_REGx_CIDCFGR_RDENC2 RISAF_REGx_CIDCFGR_RDENC2_Msk /*!< Read enable for compartment 2 */
#define RISAF_REGx_CIDCFGR_RDENC3_Pos (3U)
#define RISAF_REGx_CIDCFGR_RDENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC3_Pos) /*!< 0x00000008 */
#define RISAF_REGx_CIDCFGR_RDENC3 RISAF_REGx_CIDCFGR_RDENC3_Msk /*!< Read enable for compartment 3 */
#define RISAF_REGx_CIDCFGR_RDENC4_Pos (4U)
#define RISAF_REGx_CIDCFGR_RDENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC4_Pos) /*!< 0x00000010 */
#define RISAF_REGx_CIDCFGR_RDENC4 RISAF_REGx_CIDCFGR_RDENC4_Msk /*!< Read enable for compartment 4 */
#define RISAF_REGx_CIDCFGR_RDENC5_Pos (5U)
#define RISAF_REGx_CIDCFGR_RDENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC5_Pos) /*!< 0x00000020 */
#define RISAF_REGx_CIDCFGR_RDENC5 RISAF_REGx_CIDCFGR_RDENC5_Msk /*!< Read enable for compartment 5 */
#define RISAF_REGx_CIDCFGR_RDENC6_Pos (6U)
#define RISAF_REGx_CIDCFGR_RDENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC6_Pos) /*!< 0x00000040 */
#define RISAF_REGx_CIDCFGR_RDENC6 RISAF_REGx_CIDCFGR_RDENC6_Msk /*!< Read enable for compartment 6 */
#define RISAF_REGx_CIDCFGR_RDENC7_Pos (7U)
#define RISAF_REGx_CIDCFGR_RDENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_RDENC7_Pos) /*!< 0x00000080 */
#define RISAF_REGx_CIDCFGR_RDENC7 RISAF_REGx_CIDCFGR_RDENC7_Msk /*!< Read enable for compartment 7 */
#define RISAF_REGx_CIDCFGR_WRENC0_Pos (16U)
#define RISAF_REGx_CIDCFGR_WRENC0_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC0_Pos) /*!< 0x00010000 */
#define RISAF_REGx_CIDCFGR_WRENC0 RISAF_REGx_CIDCFGR_WRENC0_Msk /*!< Write enable for compartment 0 */
#define RISAF_REGx_CIDCFGR_WRENC1_Pos (17U)
#define RISAF_REGx_CIDCFGR_WRENC1_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC1_Pos) /*!< 0x00020000 */
#define RISAF_REGx_CIDCFGR_WRENC1 RISAF_REGx_CIDCFGR_WRENC1_Msk /*!< Write enable for compartment 1 */
#define RISAF_REGx_CIDCFGR_WRENC2_Pos (18U)
#define RISAF_REGx_CIDCFGR_WRENC2_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC2_Pos) /*!< 0x00040000 */
#define RISAF_REGx_CIDCFGR_WRENC2 RISAF_REGx_CIDCFGR_WRENC2_Msk /*!< Write enable for compartment 2 */
#define RISAF_REGx_CIDCFGR_WRENC3_Pos (19U)
#define RISAF_REGx_CIDCFGR_WRENC3_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC3_Pos) /*!< 0x00080000 */
#define RISAF_REGx_CIDCFGR_WRENC3 RISAF_REGx_CIDCFGR_WRENC3_Msk /*!< Write enable for compartment 3 */
#define RISAF_REGx_CIDCFGR_WRENC4_Pos (20U)
#define RISAF_REGx_CIDCFGR_WRENC4_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC4_Pos) /*!< 0x00100000 */
#define RISAF_REGx_CIDCFGR_WRENC4 RISAF_REGx_CIDCFGR_WRENC4_Msk /*!< Write enable for compartment 4 */
#define RISAF_REGx_CIDCFGR_WRENC5_Pos (21U)
#define RISAF_REGx_CIDCFGR_WRENC5_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC5_Pos) /*!< 0x00200000 */
#define RISAF_REGx_CIDCFGR_WRENC5 RISAF_REGx_CIDCFGR_WRENC5_Msk /*!< Write enable for compartment 5 */
#define RISAF_REGx_CIDCFGR_WRENC6_Pos (22U)
#define RISAF_REGx_CIDCFGR_WRENC6_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC6_Pos) /*!< 0x00400000 */
#define RISAF_REGx_CIDCFGR_WRENC6 RISAF_REGx_CIDCFGR_WRENC6_Msk /*!< Write enable for compartment 6 */
#define RISAF_REGx_CIDCFGR_WRENC7_Pos (23U)
#define RISAF_REGx_CIDCFGR_WRENC7_Msk (0x1UL << RISAF_REGx_CIDCFGR_WRENC7_Pos) /*!< 0x00800000 */
#define RISAF_REGx_CIDCFGR_WRENC7 RISAF_REGx_CIDCFGR_WRENC7_Msk /*!< Write enable for compartment 7 */
/*************** Bit definition for RISAF_REGx_zCFGR register ***************/
#define RISAF_REGx_zCFGR_SREN_Pos (0U)
#define RISAF_REGx_zCFGR_SREN_Msk (0x1UL << RISAF_REGx_zCFGR_SREN_Pos) /*!< 0x00000001 */
#define RISAF_REGx_zCFGR_SREN RISAF_REGx_zCFGR_SREN_Msk /*!< Subregion enable */
#define RISAF_REGx_zCFGR_RLOCK_Pos (1U)
#define RISAF_REGx_zCFGR_RLOCK_Msk (0x1UL << RISAF_REGx_zCFGR_RLOCK_Pos) /*!< 0x00000002 */
#define RISAF_REGx_zCFGR_RLOCK RISAF_REGx_zCFGR_RLOCK_Msk /*!< Resource lock */
#define RISAF_REGx_zCFGR_SRCID_Pos (4U)
#define RISAF_REGx_zCFGR_SRCID_Msk (0x7UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000070 */
#define RISAF_REGx_zCFGR_SRCID RISAF_REGx_zCFGR_SRCID_Msk /*!< Subregion CID */
#define RISAF_REGx_zCFGR_SRCID_0 (0x1UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000010 */
#define RISAF_REGx_zCFGR_SRCID_1 (0x2UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000020 */
#define RISAF_REGx_zCFGR_SRCID_2 (0x4UL << RISAF_REGx_zCFGR_SRCID_Pos) /*!< 0x00000040 */
#define RISAF_REGx_zCFGR_SEC_Pos (8U)
#define RISAF_REGx_zCFGR_SEC_Msk (0x1UL << RISAF_REGx_zCFGR_SEC_Pos) /*!< 0x00000100 */
#define RISAF_REGx_zCFGR_SEC RISAF_REGx_zCFGR_SEC_Msk /*!< Secure subregion */
#define RISAF_REGx_zCFGR_PRIV_Pos (9U)
#define RISAF_REGx_zCFGR_PRIV_Msk (0x1UL << RISAF_REGx_zCFGR_PRIV_Pos) /*!< 0x00000200 */
#define RISAF_REGx_zCFGR_PRIV RISAF_REGx_zCFGR_PRIV_Msk /*!< Privileged subregion */
#define RISAF_REGx_zCFGR_RDEN_Pos (12U)
#define RISAF_REGx_zCFGR_RDEN_Msk (0x1UL << RISAF_REGx_zCFGR_RDEN_Pos) /*!< 0x00001000 */
#define RISAF_REGx_zCFGR_RDEN RISAF_REGx_zCFGR_RDEN_Msk /*!< Read enable */
#define RISAF_REGx_zCFGR_WREN_Pos (13U)
#define RISAF_REGx_zCFGR_WREN_Msk (0x1UL << RISAF_REGx_zCFGR_WREN_Pos) /*!< 0x00002000 */
#define RISAF_REGx_zCFGR_WREN RISAF_REGx_zCFGR_WREN_Msk /*!< Write enable */
/************** Bit definition for RISAF_REGx_zSTARTR register **************/
#define RISAF_REGx_zSTARTR_SADDSTART_Pos (0U)
#define RISAF_REGx_zSTARTR_SADDSTART_Msk (0xFFFFFFFFUL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0xFFFFFFFF */
#define RISAF_REGx_zSTARTR_SADDSTART RISAF_REGx_zSTARTR_SADDSTART_Msk /*!< Subregion address start */
#define RISAF_REGx_zSTARTR_SADDSTART_0 (0x1UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000001 */
#define RISAF_REGx_zSTARTR_SADDSTART_1 (0x2UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000002 */
#define RISAF_REGx_zSTARTR_SADDSTART_2 (0x4UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000004 */
#define RISAF_REGx_zSTARTR_SADDSTART_3 (0x8UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000008 */
#define RISAF_REGx_zSTARTR_SADDSTART_4 (0x10UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000010 */
#define RISAF_REGx_zSTARTR_SADDSTART_5 (0x20UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000020 */
#define RISAF_REGx_zSTARTR_SADDSTART_6 (0x40UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000040 */
#define RISAF_REGx_zSTARTR_SADDSTART_7 (0x80UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000080 */
#define RISAF_REGx_zSTARTR_SADDSTART_8 (0x100UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000100 */
#define RISAF_REGx_zSTARTR_SADDSTART_9 (0x200UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000200 */
#define RISAF_REGx_zSTARTR_SADDSTART_10 (0x400UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000400 */
#define RISAF_REGx_zSTARTR_SADDSTART_11 (0x800UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00000800 */
#define RISAF_REGx_zSTARTR_SADDSTART_12 (0x1000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00001000 */
#define RISAF_REGx_zSTARTR_SADDSTART_13 (0x2000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00002000 */
#define RISAF_REGx_zSTARTR_SADDSTART_14 (0x4000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00004000 */
#define RISAF_REGx_zSTARTR_SADDSTART_15 (0x8000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00008000 */
#define RISAF_REGx_zSTARTR_SADDSTART_16 (0x10000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00010000 */
#define RISAF_REGx_zSTARTR_SADDSTART_17 (0x20000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00020000 */
#define RISAF_REGx_zSTARTR_SADDSTART_18 (0x40000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00040000 */
#define RISAF_REGx_zSTARTR_SADDSTART_19 (0x80000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00080000 */
#define RISAF_REGx_zSTARTR_SADDSTART_20 (0x100000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00100000 */
#define RISAF_REGx_zSTARTR_SADDSTART_21 (0x200000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00200000 */
#define RISAF_REGx_zSTARTR_SADDSTART_22 (0x400000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00400000 */
#define RISAF_REGx_zSTARTR_SADDSTART_23 (0x800000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x00800000 */
#define RISAF_REGx_zSTARTR_SADDSTART_24 (0x1000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x01000000 */
#define RISAF_REGx_zSTARTR_SADDSTART_25 (0x2000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x02000000 */
#define RISAF_REGx_zSTARTR_SADDSTART_26 (0x4000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x04000000 */
#define RISAF_REGx_zSTARTR_SADDSTART_27 (0x8000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x08000000 */
#define RISAF_REGx_zSTARTR_SADDSTART_28 (0x10000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x10000000 */
#define RISAF_REGx_zSTARTR_SADDSTART_29 (0x20000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x20000000 */
#define RISAF_REGx_zSTARTR_SADDSTART_30 (0x40000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x40000000 */
#define RISAF_REGx_zSTARTR_SADDSTART_31 (0x80000000UL << RISAF_REGx_zSTARTR_SADDSTART_Pos) /*!< 0x80000000 */
/*************** Bit definition for RISAF_REGx_zENDR register ***************/
#define RISAF_REGx_zENDR_SADDEND_Pos (0U)
#define RISAF_REGx_zENDR_SADDEND_Msk (0xFFFFFFFFUL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0xFFFFFFFF */
#define RISAF_REGx_zENDR_SADDEND RISAF_REGx_zENDR_SADDEND_Msk /*!< Subregion address end */
#define RISAF_REGx_zENDR_SADDEND_0 (0x1UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000001 */
#define RISAF_REGx_zENDR_SADDEND_1 (0x2UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000002 */
#define RISAF_REGx_zENDR_SADDEND_2 (0x4UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000004 */
#define RISAF_REGx_zENDR_SADDEND_3 (0x8UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000008 */
#define RISAF_REGx_zENDR_SADDEND_4 (0x10UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000010 */
#define RISAF_REGx_zENDR_SADDEND_5 (0x20UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000020 */
#define RISAF_REGx_zENDR_SADDEND_6 (0x40UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000040 */
#define RISAF_REGx_zENDR_SADDEND_7 (0x80UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000080 */
#define RISAF_REGx_zENDR_SADDEND_8 (0x100UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000100 */
#define RISAF_REGx_zENDR_SADDEND_9 (0x200UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000200 */
#define RISAF_REGx_zENDR_SADDEND_10 (0x400UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000400 */
#define RISAF_REGx_zENDR_SADDEND_11 (0x800UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00000800 */
#define RISAF_REGx_zENDR_SADDEND_12 (0x1000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00001000 */
#define RISAF_REGx_zENDR_SADDEND_13 (0x2000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00002000 */
#define RISAF_REGx_zENDR_SADDEND_14 (0x4000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00004000 */
#define RISAF_REGx_zENDR_SADDEND_15 (0x8000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00008000 */
#define RISAF_REGx_zENDR_SADDEND_16 (0x10000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00010000 */
#define RISAF_REGx_zENDR_SADDEND_17 (0x20000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00020000 */
#define RISAF_REGx_zENDR_SADDEND_18 (0x40000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00040000 */
#define RISAF_REGx_zENDR_SADDEND_19 (0x80000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00080000 */
#define RISAF_REGx_zENDR_SADDEND_20 (0x100000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00100000 */
#define RISAF_REGx_zENDR_SADDEND_21 (0x200000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00200000 */
#define RISAF_REGx_zENDR_SADDEND_22 (0x400000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00400000 */
#define RISAF_REGx_zENDR_SADDEND_23 (0x800000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x00800000 */
#define RISAF_REGx_zENDR_SADDEND_24 (0x1000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x01000000 */
#define RISAF_REGx_zENDR_SADDEND_25 (0x2000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x02000000 */
#define RISAF_REGx_zENDR_SADDEND_26 (0x4000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x04000000 */
#define RISAF_REGx_zENDR_SADDEND_27 (0x8000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x08000000 */
#define RISAF_REGx_zENDR_SADDEND_28 (0x10000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x10000000 */
#define RISAF_REGx_zENDR_SADDEND_29 (0x20000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x20000000 */
#define RISAF_REGx_zENDR_SADDEND_30 (0x40000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x40000000 */
#define RISAF_REGx_zENDR_SADDEND_31 (0x80000000UL << RISAF_REGx_zENDR_SADDEND_Pos) /*!< 0x80000000 */
/************** Bit definition for RISAF_REGx_zNESTR register ***************/
#define RISAF_REGx_zNESTR_DCEN_Pos (2U)
#define RISAF_REGx_zNESTR_DCEN_Msk (0x1UL << RISAF_REGx_zNESTR_DCEN_Pos) /*!< 0x00000004 */
#define RISAF_REGx_zNESTR_DCEN RISAF_REGx_zNESTR_DCEN_Msk /*!< Delegated configuration enable */
#define RISAF_REGx_zNESTR_DCCID_Pos (4U)
#define RISAF_REGx_zNESTR_DCCID_Msk (0x7UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000070 */
#define RISAF_REGx_zNESTR_DCCID RISAF_REGx_zNESTR_DCCID_Msk /*!< Delegated configuration CID */
#define RISAF_REGx_zNESTR_DCCID_0 (0x1UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000010 */
#define RISAF_REGx_zNESTR_DCCID_1 (0x2UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000020 */
#define RISAF_REGx_zNESTR_DCCID_2 (0x4UL << RISAF_REGx_zNESTR_DCCID_Pos) /*!< 0x00000040 */
/******************************************************************************/
/* */
/* (IAC) */
/* */
/******************************************************************************/
/******************* Bit definition for IAC_IER0 register *******************/
#define IAC_IERx_IAIE0_Pos (0U)
#define IAC_IERx_IAIE0_Msk (0x1UL << IAC_IERx_IAIE0_Pos) /*!< 0x00000001 */
#define IAC_IERx_IAIE0 IAC_IERx_IAIE0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
#define IAC_IERx_IAIE1_Pos (1U)
#define IAC_IERx_IAIE1_Msk (0x1UL << IAC_IERx_IAIE1_Pos) /*!< 0x00000002 */
#define IAC_IERx_IAIE1 IAC_IERx_IAIE1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
#define IAC_IERx_IAIE2_Pos (2U)
#define IAC_IERx_IAIE2_Msk (0x1UL << IAC_IERx_IAIE2_Pos) /*!< 0x00000004 */
#define IAC_IERx_IAIE2 IAC_IERx_IAIE2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
#define IAC_IERx_IAIE3_Pos (3U)
#define IAC_IERx_IAIE3_Msk (0x1UL << IAC_IERx_IAIE3_Pos) /*!< 0x00000008 */
#define IAC_IERx_IAIE3 IAC_IERx_IAIE3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
#define IAC_IERx_IAIE4_Pos (4U)
#define IAC_IERx_IAIE4_Msk (0x1UL << IAC_IERx_IAIE4_Pos) /*!< 0x00000010 */
#define IAC_IERx_IAIE4 IAC_IERx_IAIE4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
#define IAC_IERx_IAIE5_Pos (5U)
#define IAC_IERx_IAIE5_Msk (0x1UL << IAC_IERx_IAIE5_Pos) /*!< 0x00000020 */
#define IAC_IERx_IAIE5 IAC_IERx_IAIE5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
#define IAC_IERx_IAIE6_Pos (6U)
#define IAC_IERx_IAIE6_Msk (0x1UL << IAC_IERx_IAIE6_Pos) /*!< 0x00000040 */
#define IAC_IERx_IAIE6 IAC_IERx_IAIE6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
#define IAC_IERx_IAIE7_Pos (7U)
#define IAC_IERx_IAIE7_Msk (0x1UL << IAC_IERx_IAIE7_Pos) /*!< 0x00000080 */
#define IAC_IERx_IAIE7 IAC_IERx_IAIE7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
#define IAC_IERx_IAIE8_Pos (8U)
#define IAC_IERx_IAIE8_Msk (0x1UL << IAC_IERx_IAIE8_Pos) /*!< 0x00000100 */
#define IAC_IERx_IAIE8 IAC_IERx_IAIE8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
#define IAC_IERx_IAIE9_Pos (9U)
#define IAC_IERx_IAIE9_Msk (0x1UL << IAC_IERx_IAIE9_Pos) /*!< 0x00000200 */
#define IAC_IERx_IAIE9 IAC_IERx_IAIE9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
#define IAC_IERx_IAIE10_Pos (10U)
#define IAC_IERx_IAIE10_Msk (0x1UL << IAC_IERx_IAIE10_Pos) /*!< 0x00000400 */
#define IAC_IERx_IAIE10 IAC_IERx_IAIE10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
#define IAC_IERx_IAIE11_Pos (11U)
#define IAC_IERx_IAIE11_Msk (0x1UL << IAC_IERx_IAIE11_Pos) /*!< 0x00000800 */
#define IAC_IERx_IAIE11 IAC_IERx_IAIE11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
#define IAC_IERx_IAIE12_Pos (12U)
#define IAC_IERx_IAIE12_Msk (0x1UL << IAC_IERx_IAIE12_Pos) /*!< 0x00001000 */
#define IAC_IERx_IAIE12 IAC_IERx_IAIE12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
#define IAC_IERx_IAIE13_Pos (13U)
#define IAC_IERx_IAIE13_Msk (0x1UL << IAC_IERx_IAIE13_Pos) /*!< 0x00002000 */
#define IAC_IERx_IAIE13 IAC_IERx_IAIE13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
#define IAC_IERx_IAIE14_Pos (14U)
#define IAC_IERx_IAIE14_Msk (0x1UL << IAC_IERx_IAIE14_Pos) /*!< 0x00004000 */
#define IAC_IERx_IAIE14 IAC_IERx_IAIE14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
#define IAC_IERx_IAIE15_Pos (15U)
#define IAC_IERx_IAIE15_Msk (0x1UL << IAC_IERx_IAIE15_Pos) /*!< 0x00008000 */
#define IAC_IERx_IAIE15 IAC_IERx_IAIE15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
#define IAC_IERx_IAIE16_Pos (16U)
#define IAC_IERx_IAIE16_Msk (0x1UL << IAC_IERx_IAIE16_Pos) /*!< 0x00010000 */
#define IAC_IERx_IAIE16 IAC_IERx_IAIE16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
#define IAC_IERx_IAIE17_Pos (17U)
#define IAC_IERx_IAIE17_Msk (0x1UL << IAC_IERx_IAIE17_Pos) /*!< 0x00020000 */
#define IAC_IERx_IAIE17 IAC_IERx_IAIE17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
#define IAC_IERx_IAIE18_Pos (18U)
#define IAC_IERx_IAIE18_Msk (0x1UL << IAC_IERx_IAIE18_Pos) /*!< 0x00040000 */
#define IAC_IERx_IAIE18 IAC_IERx_IAIE18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
#define IAC_IERx_IAIE19_Pos (19U)
#define IAC_IERx_IAIE19_Msk (0x1UL << IAC_IERx_IAIE19_Pos) /*!< 0x00080000 */
#define IAC_IERx_IAIE19 IAC_IERx_IAIE19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
#define IAC_IERx_IAIE20_Pos (20U)
#define IAC_IERx_IAIE20_Msk (0x1UL << IAC_IERx_IAIE20_Pos) /*!< 0x00100000 */
#define IAC_IERx_IAIE20 IAC_IERx_IAIE20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
#define IAC_IERx_IAIE21_Pos (21U)
#define IAC_IERx_IAIE21_Msk (0x1UL << IAC_IERx_IAIE21_Pos) /*!< 0x00200000 */
#define IAC_IERx_IAIE21 IAC_IERx_IAIE21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
#define IAC_IERx_IAIE22_Pos (22U)
#define IAC_IERx_IAIE22_Msk (0x1UL << IAC_IERx_IAIE22_Pos) /*!< 0x00400000 */
#define IAC_IERx_IAIE22 IAC_IERx_IAIE22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
#define IAC_IERx_IAIE23_Pos (23U)
#define IAC_IERx_IAIE23_Msk (0x1UL << IAC_IERx_IAIE23_Pos) /*!< 0x00800000 */
#define IAC_IERx_IAIE23 IAC_IERx_IAIE23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
#define IAC_IERx_IAIE24_Pos (24U)
#define IAC_IERx_IAIE24_Msk (0x1UL << IAC_IERx_IAIE24_Pos) /*!< 0x01000000 */
#define IAC_IERx_IAIE24 IAC_IERx_IAIE24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
#define IAC_IERx_IAIE25_Pos (25U)
#define IAC_IERx_IAIE25_Msk (0x1UL << IAC_IERx_IAIE25_Pos) /*!< 0x02000000 */
#define IAC_IERx_IAIE25 IAC_IERx_IAIE25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
#define IAC_IERx_IAIE26_Pos (26U)
#define IAC_IERx_IAIE26_Msk (0x1UL << IAC_IERx_IAIE26_Pos) /*!< 0x04000000 */
#define IAC_IERx_IAIE26 IAC_IERx_IAIE26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
#define IAC_IERx_IAIE27_Pos (27U)
#define IAC_IERx_IAIE27_Msk (0x1UL << IAC_IERx_IAIE27_Pos) /*!< 0x08000000 */
#define IAC_IERx_IAIE27 IAC_IERx_IAIE27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
#define IAC_IERx_IAIE28_Pos (28U)
#define IAC_IERx_IAIE28_Msk (0x1UL << IAC_IERx_IAIE28_Pos) /*!< 0x10000000 */
#define IAC_IERx_IAIE28 IAC_IERx_IAIE28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
#define IAC_IERx_IAIE29_Pos (29U)
#define IAC_IERx_IAIE29_Msk (0x1UL << IAC_IERx_IAIE29_Pos) /*!< 0x20000000 */
#define IAC_IERx_IAIE29 IAC_IERx_IAIE29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
#define IAC_IERx_IAIE30_Pos (30U)
#define IAC_IERx_IAIE30_Msk (0x1UL << IAC_IERx_IAIE30_Pos) /*!< 0x40000000 */
#define IAC_IERx_IAIE30 IAC_IERx_IAIE30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
#define IAC_IERx_IAIE31_Pos (31U)
#define IAC_IERx_IAIE31_Msk (0x1UL << IAC_IERx_IAIE31_Pos) /*!< 0x80000000 */
#define IAC_IERx_IAIE31 IAC_IERx_IAIE31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
/******************* Bit definition for IAC_ISRx register *******************/
#define IAC_ISRx_IAF0_Pos (0U)
#define IAC_ISRx_IAF0_Msk (0x1UL << IAC_ISRx_IAF0_Pos) /*!< 0x00000001 */
#define IAC_ISRx_IAF0 IAC_ISRx_IAF0_Msk /*!< illegal access interrupt enable for peripheral 0 (i = 0 to 31) */
#define IAC_ISRx_IAF1_Pos (1U)
#define IAC_ISRx_IAF1_Msk (0x1UL << IAC_ISRx_IAF1_Pos) /*!< 0x00000002 */
#define IAC_ISRx_IAF1 IAC_ISRx_IAF1_Msk /*!< illegal access interrupt enable for peripheral 1 (i = 0 to 31) */
#define IAC_ISRx_IAF2_Pos (2U)
#define IAC_ISRx_IAF2_Msk (0x1UL << IAC_ISRx_IAF2_Pos) /*!< 0x00000004 */
#define IAC_ISRx_IAF2 IAC_ISRx_IAF2_Msk /*!< illegal access interrupt enable for peripheral 2 (i = 0 to 31) */
#define IAC_ISRx_IAF3_Pos (3U)
#define IAC_ISRx_IAF3_Msk (0x1UL << IAC_ISRx_IAF3_Pos) /*!< 0x00000008 */
#define IAC_ISRx_IAF3 IAC_ISRx_IAF3_Msk /*!< illegal access interrupt enable for peripheral 3 (i = 0 to 31) */
#define IAC_ISRx_IAF4_Pos (4U)
#define IAC_ISRx_IAF4_Msk (0x1UL << IAC_ISRx_IAF4_Pos) /*!< 0x00000010 */
#define IAC_ISRx_IAF4 IAC_ISRx_IAF4_Msk /*!< illegal access interrupt enable for peripheral 4 (i = 0 to 31) */
#define IAC_ISRx_IAF5_Pos (5U)
#define IAC_ISRx_IAF5_Msk (0x1UL << IAC_ISRx_IAF5_Pos) /*!< 0x00000020 */
#define IAC_ISRx_IAF5 IAC_ISRx_IAF5_Msk /*!< illegal access interrupt enable for peripheral 5 (i = 0 to 31) */
#define IAC_ISRx_IAF6_Pos (6U)
#define IAC_ISRx_IAF6_Msk (0x1UL << IAC_ISRx_IAF6_Pos) /*!< 0x00000040 */
#define IAC_ISRx_IAF6 IAC_ISRx_IAF6_Msk /*!< illegal access interrupt enable for peripheral 6 (i = 0 to 31) */
#define IAC_ISRx_IAF7_Pos (7U)
#define IAC_ISRx_IAF7_Msk (0x1UL << IAC_ISRx_IAF7_Pos) /*!< 0x00000080 */
#define IAC_ISRx_IAF7 IAC_ISRx_IAF7_Msk /*!< illegal access interrupt enable for peripheral 7 (i = 0 to 31) */
#define IAC_ISRx_IAF8_Pos (8U)
#define IAC_ISRx_IAF8_Msk (0x1UL << IAC_ISRx_IAF8_Pos) /*!< 0x00000100 */
#define IAC_ISRx_IAF8 IAC_ISRx_IAF8_Msk /*!< illegal access interrupt enable for peripheral 8 (i = 0 to 31) */
#define IAC_ISRx_IAF9_Pos (9U)
#define IAC_ISRx_IAF9_Msk (0x1UL << IAC_ISRx_IAF9_Pos) /*!< 0x00000200 */
#define IAC_ISRx_IAF9 IAC_ISRx_IAF9_Msk /*!< illegal access interrupt enable for peripheral 9 (i = 0 to 31) */
#define IAC_ISRx_IAF10_Pos (10U)
#define IAC_ISRx_IAF10_Msk (0x1UL << IAC_ISRx_IAF10_Pos) /*!< 0x00000400 */
#define IAC_ISRx_IAF10 IAC_ISRx_IAF10_Msk /*!< illegal access interrupt enable for peripheral 10 (i = 0 to 31) */
#define IAC_ISRx_IAF11_Pos (11U)
#define IAC_ISRx_IAF11_Msk (0x1UL << IAC_ISRx_IAF11_Pos) /*!< 0x00000800 */
#define IAC_ISRx_IAF11 IAC_ISRx_IAF11_Msk /*!< illegal access interrupt enable for peripheral 11 (i = 0 to 31) */
#define IAC_ISRx_IAF12_Pos (12U)
#define IAC_ISRx_IAF12_Msk (0x1UL << IAC_ISRx_IAF12_Pos) /*!< 0x00001000 */
#define IAC_ISRx_IAF12 IAC_ISRx_IAF12_Msk /*!< illegal access interrupt enable for peripheral 12 (i = 0 to 31) */
#define IAC_ISRx_IAF13_Pos (13U)
#define IAC_ISRx_IAF13_Msk (0x1UL << IAC_ISRx_IAF13_Pos) /*!< 0x00002000 */
#define IAC_ISRx_IAF13 IAC_ISRx_IAF13_Msk /*!< illegal access interrupt enable for peripheral 13 (i = 0 to 31) */
#define IAC_ISRx_IAF14_Pos (14U)
#define IAC_ISRx_IAF14_Msk (0x1UL << IAC_ISRx_IAF14_Pos) /*!< 0x00004000 */
#define IAC_ISRx_IAF14 IAC_ISRx_IAF14_Msk /*!< illegal access interrupt enable for peripheral 14 (i = 0 to 31) */
#define IAC_ISRx_IAF15_Pos (15U)
#define IAC_ISRx_IAF15_Msk (0x1UL << IAC_ISRx_IAF15_Pos) /*!< 0x00008000 */
#define IAC_ISRx_IAF15 IAC_ISRx_IAF15_Msk /*!< illegal access interrupt enable for peripheral 15 (i = 0 to 31) */
#define IAC_ISRx_IAF16_Pos (16U)
#define IAC_ISRx_IAF16_Msk (0x1UL << IAC_ISRx_IAF16_Pos) /*!< 0x00010000 */
#define IAC_ISRx_IAF16 IAC_ISRx_IAF16_Msk /*!< illegal access interrupt enable for peripheral 16 (i = 0 to 31) */
#define IAC_ISRx_IAF17_Pos (17U)
#define IAC_ISRx_IAF17_Msk (0x1UL << IAC_ISRx_IAF17_Pos) /*!< 0x00020000 */
#define IAC_ISRx_IAF17 IAC_ISRx_IAF17_Msk /*!< illegal access interrupt enable for peripheral 17 (i = 0 to 31) */
#define IAC_ISRx_IAF18_Pos (18U)
#define IAC_ISRx_IAF18_Msk (0x1UL << IAC_ISRx_IAF18_Pos) /*!< 0x00040000 */
#define IAC_ISRx_IAF18 IAC_ISRx_IAF18_Msk /*!< illegal access interrupt enable for peripheral 18 (i = 0 to 31) */
#define IAC_ISRx_IAF19_Pos (19U)
#define IAC_ISRx_IAF19_Msk (0x1UL << IAC_ISRx_IAF19_Pos) /*!< 0x00080000 */
#define IAC_ISRx_IAF19 IAC_ISRx_IAF19_Msk /*!< illegal access interrupt enable for peripheral 19 (i = 0 to 31) */
#define IAC_ISRx_IAF20_Pos (20U)
#define IAC_ISRx_IAF20_Msk (0x1UL << IAC_ISRx_IAF20_Pos) /*!< 0x00100000 */
#define IAC_ISRx_IAF20 IAC_ISRx_IAF20_Msk /*!< illegal access interrupt enable for peripheral 20 (i = 0 to 31) */
#define IAC_ISRx_IAF21_Pos (21U)
#define IAC_ISRx_IAF21_Msk (0x1UL << IAC_ISRx_IAF21_Pos) /*!< 0x00200000 */
#define IAC_ISRx_IAF21 IAC_ISRx_IAF21_Msk /*!< illegal access interrupt enable for peripheral 21 (i = 0 to 31) */
#define IAC_ISRx_IAF22_Pos (22U)
#define IAC_ISRx_IAF22_Msk (0x1UL << IAC_ISRx_IAF22_Pos) /*!< 0x00400000 */
#define IAC_ISRx_IAF22 IAC_ISRx_IAF22_Msk /*!< illegal access interrupt enable for peripheral 22 (i = 0 to 31) */
#define IAC_ISRx_IAF23_Pos (23U)
#define IAC_ISRx_IAF23_Msk (0x1UL << IAC_ISRx_IAF23_Pos) /*!< 0x00800000 */
#define IAC_ISRx_IAF23 IAC_ISRx_IAF23_Msk /*!< illegal access interrupt enable for peripheral 23 (i = 0 to 31) */
#define IAC_ISRx_IAF24_Pos (24U)
#define IAC_ISRx_IAF24_Msk (0x1UL << IAC_ISRx_IAF24_Pos) /*!< 0x01000000 */
#define IAC_ISRx_IAF24 IAC_ISRx_IAF24_Msk /*!< illegal access interrupt enable for peripheral 24 (i = 0 to 31) */
#define IAC_ISRx_IAF25_Pos (25U)
#define IAC_ISRx_IAF25_Msk (0x1UL << IAC_ISRx_IAF25_Pos) /*!< 0x02000000 */
#define IAC_ISRx_IAF25 IAC_ISRx_IAF25_Msk /*!< illegal access interrupt enable for peripheral 25 (i = 0 to 31) */
#define IAC_ISRx_IAF26_Pos (26U)
#define IAC_ISRx_IAF26_Msk (0x1UL << IAC_ISRx_IAF26_Pos) /*!< 0x04000000 */
#define IAC_ISRx_IAF26 IAC_ISRx_IAF26_Msk /*!< illegal access interrupt enable for peripheral 26 (i = 0 to 31) */
#define IAC_ISRx_IAF27_Pos (27U)
#define IAC_ISRx_IAF27_Msk (0x1UL << IAC_ISRx_IAF27_Pos) /*!< 0x08000000 */
#define IAC_ISRx_IAF27 IAC_ISRx_IAF27_Msk /*!< illegal access interrupt enable for peripheral 27 (i = 0 to 31) */
#define IAC_ISRx_IAF28_Pos (28U)
#define IAC_ISRx_IAF28_Msk (0x1UL << IAC_ISRx_IAF28_Pos) /*!< 0x10000000 */
#define IAC_ISRx_IAF28 IAC_ISRx_IAF28_Msk /*!< illegal access interrupt enable for peripheral 28 (i = 0 to 31) */
#define IAC_ISRx_IAF29_Pos (29U)
#define IAC_ISRx_IAF29_Msk (0x1UL << IAC_ISRx_IAF29_Pos) /*!< 0x20000000 */
#define IAC_ISRx_IAF29 IAC_ISRx_IAF29_Msk /*!< illegal access interrupt enable for peripheral 29 (i = 0 to 31) */
#define IAC_ISRx_IAF30_Pos (30U)
#define IAC_ISRx_IAF30_Msk (0x1UL << IAC_ISRx_IAF30_Pos) /*!< 0x40000000 */
#define IAC_ISRx_IAF30 IAC_ISRx_IAF30_Msk /*!< illegal access interrupt enable for peripheral 30 (i = 0 to 31) */
#define IAC_ISRx_IAF31_Pos (31U)
#define IAC_ISRx_IAF31_Msk (0x1UL << IAC_ISRx_IAF31_Pos) /*!< 0x80000000 */
#define IAC_ISRx_IAF31 IAC_ISRx_IAF31_Msk /*!< illegal access interrupt enable for peripheral 31 (i = 0 to 31) */
/******************* Bit definition for IAC_ICRx register *******************/
#define IAC_ICRx_IAF0_Pos (0U)
#define IAC_ICRx_IAF0_Msk (0x1UL << IAC_ICRx_IAF0_Pos) /*!< 0x00000001 */
#define IAC_ICRx_IAF0 IAC_ICRx_IAF0_Msk /*!< illegal access flag clear for peripheral 0 (i = 0 to 31) */
#define IAC_ICRx_IAF1_Pos (1U)
#define IAC_ICRx_IAF1_Msk (0x1UL << IAC_ICRx_IAF1_Pos) /*!< 0x00000002 */
#define IAC_ICRx_IAF1 IAC_ICRx_IAF1_Msk /*!< illegal access flag clear for peripheral 1 (i = 0 to 31) */
#define IAC_ICRx_IAF2_Pos (2U)
#define IAC_ICRx_IAF2_Msk (0x1UL << IAC_ICRx_IAF2_Pos) /*!< 0x00000004 */
#define IAC_ICRx_IAF2 IAC_ICRx_IAF2_Msk /*!< illegal access flag clear for peripheral 2 (i = 0 to 31) */
#define IAC_ICRx_IAF3_Pos (3U)
#define IAC_ICRx_IAF3_Msk (0x1UL << IAC_ICRx_IAF3_Pos) /*!< 0x00000008 */
#define IAC_ICRx_IAF3 IAC_ICRx_IAF3_Msk /*!< illegal access flag clear for peripheral 3 (i = 0 to 31) */
#define IAC_ICRx_IAF4_Pos (4U)
#define IAC_ICRx_IAF4_Msk (0x1UL << IAC_ICRx_IAF4_Pos) /*!< 0x00000010 */
#define IAC_ICRx_IAF4 IAC_ICRx_IAF4_Msk /*!< illegal access flag clear for peripheral 4 (i = 0 to 31) */
#define IAC_ICRx_IAF5_Pos (5U)
#define IAC_ICRx_IAF5_Msk (0x1UL << IAC_ICRx_IAF5_Pos) /*!< 0x00000020 */
#define IAC_ICRx_IAF5 IAC_ICRx_IAF5_Msk /*!< illegal access flag clear for peripheral 5 (i = 0 to 31) */
#define IAC_ICRx_IAF6_Pos (6U)
#define IAC_ICRx_IAF6_Msk (0x1UL << IAC_ICRx_IAF6_Pos) /*!< 0x00000040 */
#define IAC_ICRx_IAF6 IAC_ICRx_IAF6_Msk /*!< illegal access flag clear for peripheral 6 (i = 0 to 31) */
#define IAC_ICRx_IAF7_Pos (7U)
#define IAC_ICRx_IAF7_Msk (0x1UL << IAC_ICRx_IAF7_Pos) /*!< 0x00000080 */
#define IAC_ICRx_IAF7 IAC_ICRx_IAF7_Msk /*!< illegal access flag clear for peripheral 7 (i = 0 to 31) */
#define IAC_ICRx_IAF8_Pos (8U)
#define IAC_ICRx_IAF8_Msk (0x1UL << IAC_ICRx_IAF8_Pos) /*!< 0x00000100 */
#define IAC_ICRx_IAF8 IAC_ICRx_IAF8_Msk /*!< illegal access flag clear for peripheral 8 (i = 0 to 31) */
#define IAC_ICRx_IAF9_Pos (9U)
#define IAC_ICRx_IAF9_Msk (0x1UL << IAC_ICRx_IAF9_Pos) /*!< 0x00000200 */
#define IAC_ICRx_IAF9 IAC_ICRx_IAF9_Msk /*!< illegal access flag clear for peripheral 9 (i = 0 to 31) */
#define IAC_ICRx_IAF10_Pos (10U)
#define IAC_ICRx_IAF10_Msk (0x1UL << IAC_ICRx_IAF10_Pos) /*!< 0x00000400 */
#define IAC_ICRx_IAF10 IAC_ICRx_IAF10_Msk /*!< illegal access flag clear for peripheral 10 (i = 0 to 31) */
#define IAC_ICRx_IAF11_Pos (11U)
#define IAC_ICRx_IAF11_Msk (0x1UL << IAC_ICRx_IAF11_Pos) /*!< 0x00000800 */
#define IAC_ICRx_IAF11 IAC_ICRx_IAF11_Msk /*!< illegal access flag clear for peripheral 11 (i = 0 to 31) */
#define IAC_ICRx_IAF12_Pos (12U)
#define IAC_ICRx_IAF12_Msk (0x1UL << IAC_ICRx_IAF12_Pos) /*!< 0x00001000 */
#define IAC_ICRx_IAF12 IAC_ICRx_IAF12_Msk /*!< illegal access flag clear for peripheral 12 (i = 0 to 31) */
#define IAC_ICRx_IAF13_Pos (13U)
#define IAC_ICRx_IAF13_Msk (0x1UL << IAC_ICRx_IAF13_Pos) /*!< 0x00002000 */
#define IAC_ICRx_IAF13 IAC_ICRx_IAF13_Msk /*!< illegal access flag clear for peripheral 13 (i = 0 to 31) */
#define IAC_ICRx_IAF14_Pos (14U)
#define IAC_ICRx_IAF14_Msk (0x1UL << IAC_ICRx_IAF14_Pos) /*!< 0x00004000 */
#define IAC_ICRx_IAF14 IAC_ICRx_IAF14_Msk /*!< illegal access flag clear for peripheral 14 (i = 0 to 31) */
#define IAC_ICRx_IAF15_Pos (15U)
#define IAC_ICRx_IAF15_Msk (0x1UL << IAC_ICRx_IAF15_Pos) /*!< 0x00008000 */
#define IAC_ICRx_IAF15 IAC_ICRx_IAF15_Msk /*!< illegal access flag clear for peripheral 15 (i = 0 to 31) */
#define IAC_ICRx_IAF16_Pos (16U)
#define IAC_ICRx_IAF16_Msk (0x1UL << IAC_ICRx_IAF16_Pos) /*!< 0x00010000 */
#define IAC_ICRx_IAF16 IAC_ICRx_IAF16_Msk /*!< illegal access flag clear for peripheral 16 (i = 0 to 31) */
#define IAC_ICRx_IAF17_Pos (17U)
#define IAC_ICRx_IAF17_Msk (0x1UL << IAC_ICRx_IAF17_Pos) /*!< 0x00020000 */
#define IAC_ICRx_IAF17 IAC_ICRx_IAF17_Msk /*!< illegal access flag clear for peripheral 17 (i = 0 to 31) */
#define IAC_ICRx_IAF18_Pos (18U)
#define IAC_ICRx_IAF18_Msk (0x1UL << IAC_ICRx_IAF18_Pos) /*!< 0x00040000 */
#define IAC_ICRx_IAF18 IAC_ICRx_IAF18_Msk /*!< illegal access flag clear for peripheral 18 (i = 0 to 31) */
#define IAC_ICRx_IAF19_Pos (19U)
#define IAC_ICRx_IAF19_Msk (0x1UL << IAC_ICRx_IAF19_Pos) /*!< 0x00080000 */
#define IAC_ICRx_IAF19 IAC_ICRx_IAF19_Msk /*!< illegal access flag clear for peripheral 19 (i = 0 to 31) */
#define IAC_ICRx_IAF20_Pos (20U)
#define IAC_ICRx_IAF20_Msk (0x1UL << IAC_ICRx_IAF20_Pos) /*!< 0x00100000 */
#define IAC_ICRx_IAF20 IAC_ICRx_IAF20_Msk /*!< illegal access flag clear for peripheral 20 (i = 0 to 31) */
#define IAC_ICRx_IAF21_Pos (21U)
#define IAC_ICRx_IAF21_Msk (0x1UL << IAC_ICRx_IAF21_Pos) /*!< 0x00200000 */
#define IAC_ICRx_IAF21 IAC_ICRx_IAF21_Msk /*!< illegal access flag clear for peripheral 21 (i = 0 to 31) */
#define IAC_ICRx_IAF22_Pos (22U)
#define IAC_ICRx_IAF22_Msk (0x1UL << IAC_ICRx_IAF22_Pos) /*!< 0x00400000 */
#define IAC_ICRx_IAF22 IAC_ICRx_IAF22_Msk /*!< illegal access flag clear for peripheral 22 (i = 0 to 31) */
#define IAC_ICRx_IAF23_Pos (23U)
#define IAC_ICRx_IAF23_Msk (0x1UL << IAC_ICRx_IAF23_Pos) /*!< 0x00800000 */
#define IAC_ICRx_IAF23 IAC_ICRx_IAF23_Msk /*!< illegal access flag clear for peripheral 23 (i = 0 to 31) */
#define IAC_ICRx_IAF24_Pos (24U)
#define IAC_ICRx_IAF24_Msk (0x1UL << IAC_ICRx_IAF24_Pos) /*!< 0x01000000 */
#define IAC_ICRx_IAF24 IAC_ICRx_IAF24_Msk /*!< illegal access flag clear for peripheral 24 (i = 0 to 31) */
#define IAC_ICRx_IAF25_Pos (25U)
#define IAC_ICRx_IAF25_Msk (0x1UL << IAC_ICRx_IAF25_Pos) /*!< 0x02000000 */
#define IAC_ICRx_IAF25 IAC_ICRx_IAF25_Msk /*!< illegal access flag clear for peripheral 25 (i = 0 to 31) */
#define IAC_ICRx_IAF26_Pos (26U)
#define IAC_ICRx_IAF26_Msk (0x1UL << IAC_ICRx_IAF26_Pos) /*!< 0x04000000 */
#define IAC_ICRx_IAF26 IAC_ICRx_IAF26_Msk /*!< illegal access flag clear for peripheral 26 (i = 0 to 31) */
#define IAC_ICRx_IAF27_Pos (27U)
#define IAC_ICRx_IAF27_Msk (0x1UL << IAC_ICRx_IAF27_Pos) /*!< 0x08000000 */
#define IAC_ICRx_IAF27 IAC_ICRx_IAF27_Msk /*!< illegal access flag clear for peripheral 27 (i = 0 to 31) */
#define IAC_ICRx_IAF28_Pos (28U)
#define IAC_ICRx_IAF28_Msk (0x1UL << IAC_ICRx_IAF28_Pos) /*!< 0x10000000 */
#define IAC_ICRx_IAF28 IAC_ICRx_IAF28_Msk /*!< illegal access flag clear for peripheral 28 (i = 0 to 31) */
#define IAC_ICRx_IAF29_Pos (29U)
#define IAC_ICRx_IAF29_Msk (0x1UL << IAC_ICRx_IAF29_Pos) /*!< 0x20000000 */
#define IAC_ICRx_IAF29 IAC_ICRx_IAF29_Msk /*!< illegal access flag clear for peripheral 29 (i = 0 to 31) */
#define IAC_ICRx_IAF30_Pos (30U)
#define IAC_ICRx_IAF30_Msk (0x1UL << IAC_ICRx_IAF30_Pos) /*!< 0x40000000 */
#define IAC_ICRx_IAF30 IAC_ICRx_IAF30_Msk /*!< illegal access flag clear for peripheral 30 (i = 0 to 31) */
#define IAC_ICRx_IAF31_Pos (31U)
#define IAC_ICRx_IAF31_Msk (0x1UL << IAC_ICRx_IAF31_Pos) /*!< 0x80000000 */
#define IAC_ICRx_IAF31 IAC_ICRx_IAF31_Msk /*!< illegal access flag clear for peripheral 31 (i = 0 to 31) */
/****************** Bit definition for IAC_IISRx register *******************/
#define IAC_IISRx_ILACIN0_Pos (0U)
#define IAC_IISRx_ILACIN0_Msk (0x1UL << IAC_IISRx_ILACIN0_Pos) /*!< 0x00000001 */
#define IAC_IISRx_ILACIN0 IAC_IISRx_ILACIN0_Msk /*!< illegal access input 0 (i = 0 to 31) */
#define IAC_IISRx_ILACIN1_Pos (1U)
#define IAC_IISRx_ILACIN1_Msk (0x1UL << IAC_IISRx_ILACIN1_Pos) /*!< 0x00000002 */
#define IAC_IISRx_ILACIN1 IAC_IISRx_ILACIN1_Msk /*!< illegal access input 1 (i = 0 to 31) */
#define IAC_IISRx_ILACIN2_Pos (2U)
#define IAC_IISRx_ILACIN2_Msk (0x1UL << IAC_IISRx_ILACIN2_Pos) /*!< 0x00000004 */
#define IAC_IISRx_ILACIN2 IAC_IISRx_ILACIN2_Msk /*!< illegal access input 2 (i = 0 to 31) */
#define IAC_IISRx_ILACIN3_Pos (3U)
#define IAC_IISRx_ILACIN3_Msk (0x1UL << IAC_IISRx_ILACIN3_Pos) /*!< 0x00000008 */
#define IAC_IISRx_ILACIN3 IAC_IISRx_ILACIN3_Msk /*!< illegal access input 3 (i = 0 to 31) */
#define IAC_IISRx_ILACIN4_Pos (4U)
#define IAC_IISRx_ILACIN4_Msk (0x1UL << IAC_IISRx_ILACIN4_Pos) /*!< 0x00000010 */
#define IAC_IISRx_ILACIN4 IAC_IISRx_ILACIN4_Msk /*!< illegal access input 4 (i = 0 to 31) */
#define IAC_IISRx_ILACIN5_Pos (5U)
#define IAC_IISRx_ILACIN5_Msk (0x1UL << IAC_IISRx_ILACIN5_Pos) /*!< 0x00000020 */
#define IAC_IISRx_ILACIN5 IAC_IISRx_ILACIN5_Msk /*!< illegal access input 5 (i = 0 to 31) */
#define IAC_IISRx_ILACIN6_Pos (6U)
#define IAC_IISRx_ILACIN6_Msk (0x1UL << IAC_IISRx_ILACIN6_Pos) /*!< 0x00000040 */
#define IAC_IISRx_ILACIN6 IAC_IISRx_ILACIN6_Msk /*!< illegal access input 6 (i = 0 to 31) */
#define IAC_IISRx_ILACIN7_Pos (7U)
#define IAC_IISRx_ILACIN7_Msk (0x1UL << IAC_IISRx_ILACIN7_Pos) /*!< 0x00000080 */
#define IAC_IISRx_ILACIN7 IAC_IISRx_ILACIN7_Msk /*!< illegal access input 7 (i = 0 to 31) */
#define IAC_IISRx_ILACIN8_Pos (8U)
#define IAC_IISRx_ILACIN8_Msk (0x1UL << IAC_IISRx_ILACIN8_Pos) /*!< 0x00000100 */
#define IAC_IISRx_ILACIN8 IAC_IISRx_ILACIN8_Msk /*!< illegal access input 8 (i = 0 to 31) */
#define IAC_IISRx_ILACIN9_Pos (9U)
#define IAC_IISRx_ILACIN9_Msk (0x1UL << IAC_IISRx_ILACIN9_Pos) /*!< 0x00000200 */
#define IAC_IISRx_ILACIN9 IAC_IISRx_ILACIN9_Msk /*!< illegal access input 9 (i = 0 to 31) */
#define IAC_IISRx_ILACIN10_Pos (10U)
#define IAC_IISRx_ILACIN10_Msk (0x1UL << IAC_IISRx_ILACIN10_Pos) /*!< 0x00000400 */
#define IAC_IISRx_ILACIN10 IAC_IISRx_ILACIN10_Msk /*!< illegal access input 10 (i = 0 to 31) */
#define IAC_IISRx_ILACIN11_Pos (11U)
#define IAC_IISRx_ILACIN11_Msk (0x1UL << IAC_IISRx_ILACIN11_Pos) /*!< 0x00000800 */
#define IAC_IISRx_ILACIN11 IAC_IISRx_ILACIN11_Msk /*!< illegal access input 11 (i = 0 to 31) */
#define IAC_IISRx_ILACIN12_Pos (12U)
#define IAC_IISRx_ILACIN12_Msk (0x1UL << IAC_IISRx_ILACIN12_Pos) /*!< 0x00001000 */
#define IAC_IISRx_ILACIN12 IAC_IISRx_ILACIN12_Msk /*!< illegal access input 12 (i = 0 to 31) */
#define IAC_IISRx_ILACIN13_Pos (13U)
#define IAC_IISRx_ILACIN13_Msk (0x1UL << IAC_IISRx_ILACIN13_Pos) /*!< 0x00002000 */
#define IAC_IISRx_ILACIN13 IAC_IISRx_ILACIN13_Msk /*!< illegal access input 13 (i = 0 to 31) */
#define IAC_IISRx_ILACIN14_Pos (14U)
#define IAC_IISRx_ILACIN14_Msk (0x1UL << IAC_IISRx_ILACIN14_Pos) /*!< 0x00004000 */
#define IAC_IISRx_ILACIN14 IAC_IISRx_ILACIN14_Msk /*!< illegal access input 14 (i = 0 to 31) */
#define IAC_IISRx_ILACIN15_Pos (15U)
#define IAC_IISRx_ILACIN15_Msk (0x1UL << IAC_IISRx_ILACIN15_Pos) /*!< 0x00008000 */
#define IAC_IISRx_ILACIN15 IAC_IISRx_ILACIN15_Msk /*!< illegal access input 15 (i = 0 to 31) */
#define IAC_IISRx_ILACIN16_Pos (16U)
#define IAC_IISRx_ILACIN16_Msk (0x1UL << IAC_IISRx_ILACIN16_Pos) /*!< 0x00010000 */
#define IAC_IISRx_ILACIN16 IAC_IISRx_ILACIN16_Msk /*!< illegal access input 16 (i = 0 to 31) */
#define IAC_IISRx_ILACIN17_Pos (17U)
#define IAC_IISRx_ILACIN17_Msk (0x1UL << IAC_IISRx_ILACIN17_Pos) /*!< 0x00020000 */
#define IAC_IISRx_ILACIN17 IAC_IISRx_ILACIN17_Msk /*!< illegal access input 17 (i = 0 to 31) */
#define IAC_IISRx_ILACIN18_Pos (18U)
#define IAC_IISRx_ILACIN18_Msk (0x1UL << IAC_IISRx_ILACIN18_Pos) /*!< 0x00040000 */
#define IAC_IISRx_ILACIN18 IAC_IISRx_ILACIN18_Msk /*!< illegal access input 18 (i = 0 to 31) */
#define IAC_IISRx_ILACIN19_Pos (19U)
#define IAC_IISRx_ILACIN19_Msk (0x1UL << IAC_IISRx_ILACIN19_Pos) /*!< 0x00080000 */
#define IAC_IISRx_ILACIN19 IAC_IISRx_ILACIN19_Msk /*!< illegal access input 19 (i = 0 to 31) */
#define IAC_IISRx_ILACIN20_Pos (20U)
#define IAC_IISRx_ILACIN20_Msk (0x1UL << IAC_IISRx_ILACIN20_Pos) /*!< 0x00100000 */
#define IAC_IISRx_ILACIN20 IAC_IISRx_ILACIN20_Msk /*!< illegal access input 20 (i = 0 to 31) */
#define IAC_IISRx_ILACIN21_Pos (21U)
#define IAC_IISRx_ILACIN21_Msk (0x1UL << IAC_IISRx_ILACIN21_Pos) /*!< 0x00200000 */
#define IAC_IISRx_ILACIN21 IAC_IISRx_ILACIN21_Msk /*!< illegal access input 21 (i = 0 to 31) */
#define IAC_IISRx_ILACIN22_Pos (22U)
#define IAC_IISRx_ILACIN22_Msk (0x1UL << IAC_IISRx_ILACIN22_Pos) /*!< 0x00400000 */
#define IAC_IISRx_ILACIN22 IAC_IISRx_ILACIN22_Msk /*!< illegal access input 22 (i = 0 to 31) */
#define IAC_IISRx_ILACIN23_Pos (23U)
#define IAC_IISRx_ILACIN23_Msk (0x1UL << IAC_IISRx_ILACIN23_Pos) /*!< 0x00800000 */
#define IAC_IISRx_ILACIN23 IAC_IISRx_ILACIN23_Msk /*!< illegal access input 23 (i = 0 to 31) */
#define IAC_IISRx_ILACIN24_Pos (24U)
#define IAC_IISRx_ILACIN24_Msk (0x1UL << IAC_IISRx_ILACIN24_Pos) /*!< 0x01000000 */
#define IAC_IISRx_ILACIN24 IAC_IISRx_ILACIN24_Msk /*!< illegal access input 24 (i = 0 to 31) */
#define IAC_IISRx_ILACIN25_Pos (25U)
#define IAC_IISRx_ILACIN25_Msk (0x1UL << IAC_IISRx_ILACIN25_Pos) /*!< 0x02000000 */
#define IAC_IISRx_ILACIN25 IAC_IISRx_ILACIN25_Msk /*!< illegal access input 25 (i = 0 to 31) */
#define IAC_IISRx_ILACIN26_Pos (26U)
#define IAC_IISRx_ILACIN26_Msk (0x1UL << IAC_IISRx_ILACIN26_Pos) /*!< 0x04000000 */
#define IAC_IISRx_ILACIN26 IAC_IISRx_ILACIN26_Msk /*!< illegal access input 26 (i = 0 to 31) */
#define IAC_IISRx_ILACIN27_Pos (27U)
#define IAC_IISRx_ILACIN27_Msk (0x1UL << IAC_IISRx_ILACIN27_Pos) /*!< 0x08000000 */
#define IAC_IISRx_ILACIN27 IAC_IISRx_ILACIN27_Msk /*!< illegal access input 27 (i = 0 to 31) */
#define IAC_IISRx_ILACIN28_Pos (28U)
#define IAC_IISRx_ILACIN28_Msk (0x1UL << IAC_IISRx_ILACIN28_Pos) /*!< 0x10000000 */
#define IAC_IISRx_ILACIN28 IAC_IISRx_ILACIN28_Msk /*!< illegal access input 28 (i = 0 to 31) */
#define IAC_IISRx_ILACIN29_Pos (29U)
#define IAC_IISRx_ILACIN29_Msk (0x1UL << IAC_IISRx_ILACIN29_Pos) /*!< 0x20000000 */
#define IAC_IISRx_ILACIN29 IAC_IISRx_ILACIN29_Msk /*!< illegal access input 29 (i = 0 to 31) */
#define IAC_IISRx_ILACIN30_Pos (30U)
#define IAC_IISRx_ILACIN30_Msk (0x1UL << IAC_IISRx_ILACIN30_Pos) /*!< 0x40000000 */
#define IAC_IISRx_ILACIN30 IAC_IISRx_ILACIN30_Msk /*!< illegal access input 30 (i = 0 to 31) */
#define IAC_IISRx_ILACIN31_Pos (31U)
#define IAC_IISRx_ILACIN31_Msk (0x1UL << IAC_IISRx_ILACIN31_Pos) /*!< 0x80000000 */
#define IAC_IISRx_ILACIN31 IAC_IISRx_ILACIN31_Msk /*!< illegal access input 31 (i = 0 to 31) */
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_CED_Msk
#define RNG_CR_ARDIS_Pos (7U)
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
#define RNG_CR_RNG_CONFIG3_Pos (8U)
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
#define RNG_CR_NISTC_Pos (12U)
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
#define RNG_CR_NISTC RNG_CR_NISTC_Msk
#define RNG_CR_RNG_CONFIG2_Pos (13U)
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
#define RNG_CR_CLKDIV_Pos (16U)
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
#define RNG_CR_RNG_CONFIG1_Pos (20U)
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
#define RNG_CR_CONDRST_Pos (30U)
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
#define RNG_CR_CONFIGLOCK_Pos (31U)
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************** Bits definition for RNG_HTCR register *******************/
#define RNG_HTCR_HTCFG_Pos (0U)
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) /*!< 0xFFFFFFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_BIN_Pos (8U)
#define RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) /*!< 0x00000300 */
#define RTC_ICSR_BIN RTC_ICSR_BIN_Msk
#define RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) /*!< 0x00000100 */
#define RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) /*!< 0x00000200 */
#define RTC_ICSR_BCDU_Pos (10U)
#define RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001C00 */
#define RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk
#define RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000400 */
#define RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) /*!< 0x00000800 */
#define RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) /*!< 0x00001000 */
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
#define RTC_WUTR_WUTOCLR_Pos (16U)
#define RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_SSRUIE_Pos (7U)
#define RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) /*!< 0x00000080 */
#define RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_ALRAFCLR_Pos (27U)
#define RTC_CR_ALRAFCLR_Msk (0x1UL << RTC_CR_ALRAFCLR_Pos) /*!< 0x8000000 */
#define RTC_CR_ALRAFCLR RTC_CR_ALRAFCLR_Msk /*!<Alarm A mask */
#define RTC_CR_ALRBFCLR_Pos (28U)
#define RTC_CR_ALRBFCLR_Msk (0x1UL << RTC_CR_ALRBFCLR_Pos) /*!< 0x10000000 */
#define RTC_CR_ALRBFCLR RTC_CR_ALRBFCLR_Msk /*!<Alarm B mask */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
/******************** Bits definition for RTC_PRIVCFGR register *****************/
#define RTC_PRIVCFGR_ALRAPRIV_Pos (0U)
#define RTC_PRIVCFGR_ALRAPRIV_Msk (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos) /*!< 0x00000001 */
#define RTC_PRIVCFGR_ALRAPRIV RTC_PRIVCFGR_ALRAPRIV_Msk
#define RTC_PRIVCFGR_ALRBPRIV_Pos (1U)
#define RTC_PRIVCFGR_ALRBPRIV_Msk (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos) /*!< 0x00000002 */
#define RTC_PRIVCFGR_ALRBPRIV RTC_PRIVCFGR_ALRBPRIV_Msk
#define RTC_PRIVCFGR_WUTPRIV_Pos (2U)
#define RTC_PRIVCFGR_WUTPRIV_Msk (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos) /*!< 0x00000004 */
#define RTC_PRIVCFGR_WUTPRIV RTC_PRIVCFGR_WUTPRIV_Msk
#define RTC_PRIVCFGR_TSPRIV_Pos (3U)
#define RTC_PRIVCFGR_TSPRIV_Msk (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos) /*!< 0x00000008 */
#define RTC_PRIVCFGR_TSPRIV RTC_PRIVCFGR_TSPRIV_Msk
#define RTC_PRIVCFGR_CALPRIV_Pos (13U)
#define RTC_PRIVCFGR_CALPRIV_Msk (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos) /*!< 0x00002000 */
#define RTC_PRIVCFGR_CALPRIV RTC_PRIVCFGR_CALPRIV_Msk
#define RTC_PRIVCFGR_INITPRIV_Pos (14U)
#define RTC_PRIVCFGR_INITPRIV_Msk (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos) /*!< 0x00004000 */
#define RTC_PRIVCFGR_INITPRIV RTC_PRIVCFGR_INITPRIV_Msk
#define RTC_PRIVCFGR_PRIV_Pos (15U)
#define RTC_PRIVCFGR_PRIV_Msk (0x1UL << RTC_PRIVCFGR_PRIV_Pos) /*!< 0x00008000 */
#define RTC_PRIVCFGR_PRIV RTC_PRIVCFGR_PRIV_Msk
/******************** Bits definition for RTC_SECCFGR register ******************/
#define RTC_SECCFGR_ALRASEC_Pos (0U)
#define RTC_SECCFGR_ALRASEC_Msk (0x1UL << RTC_SECCFGR_ALRASEC_Pos) /*!< 0x00000001 */
#define RTC_SECCFGR_ALRASEC RTC_SECCFGR_ALRASEC_Msk
#define RTC_SECCFGR_ALRBSEC_Pos (1U)
#define RTC_SECCFGR_ALRBSEC_Msk (0x1UL << RTC_SECCFGR_ALRBSEC_Pos) /*!< 0x00000002 */
#define RTC_SECCFGR_ALRBSEC RTC_SECCFGR_ALRBSEC_Msk
#define RTC_SECCFGR_WUTSEC_Pos (2U)
#define RTC_SECCFGR_WUTSEC_Msk (0x1UL << RTC_SECCFGR_WUTSEC_Pos) /*!< 0x00000004 */
#define RTC_SECCFGR_WUTSEC RTC_SECCFGR_WUTSEC_Msk
#define RTC_SECCFGR_TSSEC_Pos (3U)
#define RTC_SECCFGR_TSSEC_Msk (0x1UL << RTC_SECCFGR_TSSEC_Pos) /*!< 0x00000008 */
#define RTC_SECCFGR_TSSEC RTC_SECCFGR_TSSEC_Msk
#define RTC_SECCFGR_CALSEC_Pos (13U)
#define RTC_SECCFGR_CALSEC_Msk (0x1UL << RTC_SECCFGR_CALSEC_Pos) /*!< 0x00002000 */
#define RTC_SECCFGR_CALSEC RTC_SECCFGR_CALSEC_Msk
#define RTC_SECCFGR_INITSEC_Pos (14U)
#define RTC_SECCFGR_INITSEC_Msk (0x1UL << RTC_SECCFGR_INITSEC_Pos) /*!< 0x00004000 */
#define RTC_SECCFGR_INITSEC RTC_SECCFGR_INITSEC_Msk
#define RTC_SECCFGR_SEC_Pos (15U)
#define RTC_SECCFGR_SEC_Msk (0x1UL << RTC_SECCFGR_SEC_Pos) /*!< 0x00008000 */
#define RTC_SECCFGR_SEC RTC_SECCFGR_SEC_Msk
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
#define RTC_CALR_LPCAL_Pos (12U)
#define RTC_CALR_LPCAL_Msk (0x1UL << RTC_CALR_LPCAL_Pos) /*!< 0x00001000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_LPCAL RTC_CALR_LPCAL_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0xFFFFFFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< rtc timestamp sub second > */
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */
#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */
#define RTC_ALRMASSR_SSCLR_Pos (31U)
#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */
#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
/******************** Bits definition for RTC_ALRMBSSR register *************/
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */
#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */
#define RTC_ALRMBSSR_SSCLR_Pos (31U)
#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */
#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_SSRUF_Pos (6U)
#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */
#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_SSRUMF_Pos (6U)
#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */
#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk
/******************** Bits definition for RTC_SMISR register *****************/
#define RTC_SMISR_ALRAMF_Pos (0U)
#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk
#define RTC_SMISR_ALRBMF_Pos (1U)
#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk
#define RTC_SMISR_WUTMF_Pos (2U)
#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk
#define RTC_SMISR_TSMF_Pos (3U)
#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk
#define RTC_SMISR_TSOVMF_Pos (4U)
#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk
#define RTC_SMISR_ITSMF_Pos (5U)
#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk
#define RTC_SMISR_SSRUMF_Pos (6U)
#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */
#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CSSRUF_Pos (6U)
#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */
#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk
/******************** Bits definition for RTC_ALRABINR register ******************/
#define RTC_ALRABINR_SS_Pos (0U)
#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */
#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk
/******************** Bits definition for RTC_ALRBBINR register ******************/
#define RTC_ALRBBINR_SS_Pos (0U)
#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */
#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk
/******************************************************************************/
/* */
/* Secure Advanced Encryption Standard (SAES) */
/* */
/******************************************************************************/
/******************* Bits definition for SAES_CR register *********************/
#define SAES_CR_EN_Pos (0U)
#define SAES_CR_EN_Msk (0x1UL << SAES_CR_EN_Pos) /*!< 0x00000001 */
#define SAES_CR_EN SAES_CR_EN_Msk /*!< SAES Enable */
#define SAES_CR_DATATYPE_Pos (1U)
#define SAES_CR_DATATYPE_Msk (0x3UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000006 */
#define SAES_CR_DATATYPE SAES_CR_DATATYPE_Msk /*!< Data type selection */
#define SAES_CR_DATATYPE_0 (0x1UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000002 */
#define SAES_CR_DATATYPE_1 (0x2UL << SAES_CR_DATATYPE_Pos) /*!< 0x00000004 */
#define SAES_CR_MODE_Pos (3U)
#define SAES_CR_MODE_Msk (0x3UL << SAES_CR_MODE_Pos) /*!< 0x00000018 */
#define SAES_CR_MODE SAES_CR_MODE_Msk /*!< SAES Mode Of Operation */
#define SAES_CR_MODE_0 (0x1UL << SAES_CR_MODE_Pos) /*!< 0x00000008 */
#define SAES_CR_MODE_1 (0x2UL << SAES_CR_MODE_Pos) /*!< 0x00000010 */
#define SAES_CR_CHMOD_Pos (5U)
#define SAES_CR_CHMOD_Msk (0x803UL << SAES_CR_CHMOD_Pos) /*!< 0x00010060 */
#define SAES_CR_CHMOD SAES_CR_CHMOD_Msk /*!< SAES Chaining Mode */
#define SAES_CR_CHMOD_0 (0x1UL << SAES_CR_CHMOD_Pos) /*!< 0x00000020*/
#define SAES_CR_CHMOD_1 (0x2UL << SAES_CR_CHMOD_Pos) /*!< 0x00000040 */
#define SAES_CR_CHMOD_2 (0x800UL << SAES_CR_CHMOD_Pos) /*!< 0x00010000 */
#define SAES_CR_DMAINEN_Pos (11U)
#define SAES_CR_DMAINEN_Msk (0x1UL << SAES_CR_DMAINEN_Pos) /*!< 0x00000800 */
#define SAES_CR_DMAINEN SAES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
#define SAES_CR_DMAOUTEN_Pos (12U)
#define SAES_CR_DMAOUTEN_Msk (0x1UL << SAES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
#define SAES_CR_DMAOUTEN SAES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
#define SAES_CR_GCMPH_Pos (13U)
#define SAES_CR_GCMPH_Msk (0x3UL << SAES_CR_GCMPH_Pos) /*!< 0x0006000 */
#define SAES_CR_GCMPH SAES_CR_GCMPH_Msk /*!< GCM or CCM phase selection */
#define SAES_CR_GCMPH_0 (0x1UL << SAES_CR_GCMPH_Pos) /*!< 0x00020000 */
#define SAES_CR_GCMPH_1 (0x2UL << SAES_CR_GCMPH_Pos) /*!< 0x00040000 */
#define SAES_CR_KEYSIZE_Pos (18U)
#define SAES_CR_KEYSIZE_Msk (0x1UL << SAES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
#define SAES_CR_KEYSIZE SAES_CR_KEYSIZE_Msk /*!< Key size selection */
#define SAES_CR_KEYPROT_Pos (19U)
#define SAES_CR_KEYPROT_Msk (0x1UL << SAES_CR_KEYPROT_Pos) /*!< 0x00080000 */
#define SAES_CR_KEYPROT SAES_CR_KEYPROT_Msk /*!< Key protection */
#define SAES_CR_NPBLB_Pos (20U)
#define SAES_CR_NPBLB_Msk (0xFUL << SAES_CR_NPBLB_Pos) /*!< 0x00F00000 */
#define SAES_CR_NPBLB SAES_CR_NPBLB_Msk /*!< Number of padding bytes in last block */
#define SAES_CR_NPBLB_0 (0x1UL << SAES_CR_NPBLB_Pos) /*!< 0x00100000 */
#define SAES_CR_NPBLB_1 (0x2UL << SAES_CR_NPBLB_Pos) /*!< 0x00200000 */
#define SAES_CR_NPBLB_2 (0x4UL << SAES_CR_NPBLB_Pos) /*!< 0x00400000 */
#define SAES_CR_NPBLB_3 (0x8UL << SAES_CR_NPBLB_Pos) /*!< 0x00800000 */
#define SAES_CR_KMOD_Pos (24U)
#define SAES_CR_KMOD_Msk (0x3UL << SAES_CR_KMOD_Pos) /*!< 0x03000000 */
#define SAES_CR_KMOD SAES_CR_KMOD_Msk /*!< Key mode selection */
#define SAES_CR_KMOD_0 (0x1UL << SAES_CR_KMOD_Pos) /*!< 0x01000000 */
#define SAES_CR_KMOD_1 (0x2UL << SAES_CR_KMOD_Pos) /*!< 0x02000000 */
#define SAES_CR_KSHAREID_Pos (26U)
#define SAES_CR_KSHAREID_Msk (0x3UL << SAES_CR_KSHAREID_Pos) /*!< 0x0C000000 */
#define SAES_CR_KSHAREID SAES_CR_KSHAREID_Msk /*!< Key Shared ID */
#define SAES_CR_KSHAREID_0 (0x1UL << SAES_CR_KSHAREID_Pos) /*!< 0x04000000 */
#define SAES_CR_KSHAREID_1 (0x2UL << SAES_CR_KSHAREID_Pos) /*!< 0x08000000 */
#define SAES_CR_KEYSEL_Pos (28U)
#define SAES_CR_KEYSEL_Msk (0x7UL << SAES_CR_KEYSEL_Pos) /*!< 0x70000000 */
#define SAES_CR_KEYSEL SAES_CR_KEYSEL_Msk /*!< Key Selection */
#define SAES_CR_KEYSEL_0 (0x1UL << SAES_CR_KEYSEL_Pos) /*!< 0x10000000 */
#define SAES_CR_KEYSEL_1 (0x2UL << SAES_CR_KEYSEL_Pos) /*!< 0x20000000 */
#define SAES_CR_KEYSEL_2 (0x4UL << SAES_CR_KEYSEL_Pos) /*!< 0x40000000 */
#define SAES_CR_IPRST_Pos (31U)
#define SAES_CR_IPRST_Msk (0x1UL << SAES_CR_IPRST_Pos) /*!< 0x80000000 */
#define SAES_CR_IPRST SAES_CR_IPRST_Msk /*!< SAES IP software reset */
/******************* Bits definition for SAES_SR register *********************/
#define SAES_SR_CCF_Pos (0U)
#define SAES_SR_CCF_Msk (0x1UL << SAES_SR_CCF_Pos) /*!< 0x00000001 */
#define SAES_SR_CCF SAES_SR_CCF_Msk /*!< Computation Complete Flag */
#define SAES_SR_RDERR_Pos (1U)
#define SAES_SR_RDERR_Msk (0x1UL << SAES_SR_RDERR_Pos) /*!< 0x00000002 */
#define SAES_SR_RDERR SAES_SR_RDERR_Msk /*!< Read Error Flag */
#define SAES_SR_WRERR_Pos (2U)
#define SAES_SR_WRERR_Msk (0x1UL << SAES_SR_WRERR_Pos) /*!< 0x00000004 */
#define SAES_SR_WRERR SAES_SR_WRERR_Msk /*!< Write Error Flag */
#define SAES_SR_BUSY_Pos (3U)
#define SAES_SR_BUSY_Msk (0x1UL << SAES_SR_BUSY_Pos) /*!< 0x00000008 */
#define SAES_SR_BUSY SAES_SR_BUSY_Msk /*!< Busy Flag */
#define SAES_SR_KEYVALID_Pos (7U)
#define SAES_SR_KEYVALID_Msk (0x1UL << SAES_SR_KEYVALID_Pos) /*!< 0x00000080 */
#define SAES_SR_KEYVALID SAES_SR_KEYVALID_Msk /*!< Key valid Flag */
/******************* Bits definition for SAES_DINR register *******************/
#define SAES_DINR_Pos (0U)
#define SAES_DINR_Msk (0xFFFFFFFFUL << SAES_DINR_Pos) /*!< 0xFFFFFFFF */
#define SAES_DINR SAES_DINR_Msk /*!< SAES Data Input Register */
/******************* Bits definition for SAES_DOUTR register ******************/
#define SAES_DOUTR_Pos (0U)
#define SAES_DOUTR_Msk (0xFFFFFFFFUL << SAES_DOUTR_Pos) /*!< 0xFFFFFFFF */
#define SAES_DOUTR SAES_DOUTR_Msk /*!< SAES Data Output Register */
/******************* Bits definition for SAES_KEYR0 register ******************/
#define SAES_KEYR0_Pos (0U)
#define SAES_KEYR0_Msk (0xFFFFFFFFUL << SAES_KEYR0_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR0 SAES_KEYR0_Msk /*!< SAES cryptographic key, bits [31:0] */
/******************* Bits definition for SAES_KEYR1 register ******************/
#define SAES_KEYR1_Pos (0U)
#define SAES_KEYR1_Msk (0xFFFFFFFFUL << SAES_KEYR1_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR1 SAES_KEYR1_Msk /*!< SAES cryptographic key, bits [63:32] */
/******************* Bits definition for SAES_KEYR2 register ******************/
#define SAES_KEYR2_Pos (0U)
#define SAES_KEYR2_Msk (0xFFFFFFFFUL << SAES_KEYR2_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR2 SAES_KEYR2_Msk /*!< SAES cryptographic key, bits [95:64] */
/******************* Bits definition for SAES_KEYR3 register ******************/
#define SAES_KEYR3_Pos (0U)
#define SAES_KEYR3_Msk (0xFFFFFFFFUL << SAES_KEYR3_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR3 SAES_KEYR3_Msk /*!< SAES cryptographic key, bits [127:96] */
/******************* Bits definition for SAES_KEYR4 register ******************/
#define SAES_KEYR4_Pos (0U)
#define SAES_KEYR4_Msk (0xFFFFFFFFUL << SAES_KEYR4_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR4 SAES_KEYR4_Msk /*!< SAES cryptographic key, bits [127:96] */
/******************* Bits definition for SAES_KEYR5 register ******************/
#define SAES_KEYR5_Pos (0U)
#define SAES_KEYR5_Msk (0xFFFFFFFFUL << SAES_KEYR5_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR5 SAES_KEYR5_Msk /*!< SAES cryptographic key, bits [127:96] */
/******************* Bits definition for SAES_KEYR6 register ******************/
#define SAES_KEYR6_Pos (0U)
#define SAES_KEYR6_Msk (0xFFFFFFFFUL << SAES_KEYR6_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR6 SAES_KEYR6_Msk /*!< SAES cryptographic key, bits [127:96] */
/******************* Bits definition for SAES_KEYR7 register ******************/
#define SAES_KEYR7_Pos (0U)
#define SAES_KEYR7_Msk (0xFFFFFFFFUL << SAES_KEYR7_Pos) /*!< 0xFFFFFFFF */
#define SAES_KEYR7 SAES_KEYR7_Msk /*!< SAES cryptographic key, bits [127:96] */
/******************* Bits definition for SAES_IVR0 register ******************/
#define SAES_IVR0_Pos (0U)
#define SAES_IVR0_Msk (0xFFFFFFFFUL << SAES_IVR0_Pos) /*!< 0xFFFFFFFF */
#define SAES_IVR0 SAES_IVR0_Msk /*!< SAES initialization vector input, bits [31:0] */
/******************* Bits definition for SAES_IVR1 register ******************/
#define SAES_IVR1_Pos (0U)
#define SAES_IVR1_Msk (0xFFFFFFFFUL << SAES_IVR1_Pos) /*!< 0xFFFFFFFF */
#define SAES_IVR1 SAES_IVR1_Msk /*!< SAES initialization vector input, bits [63:32] */
/******************* Bits definition for SAES_IVR2 register ******************/
#define SAES_IVR2_Pos (0U)
#define SAES_IVR2_Msk (0xFFFFFFFFUL << SAES_IVR2_Pos) /*!< 0xFFFFFFFF */
#define SAES_IVR2 SAES_IVR2_Msk /*!< SAES initialization vector input, bits [95:64] */
/******************* Bits definition for SAES_IVR3 register ******************/
#define SAES_IVR3_Pos (0U)
#define SAES_IVR3_Msk (0xFFFFFFFFUL << SAES_IVR3_Pos) /*!< 0xFFFFFFFF */
#define SAES_IVR3 SAES_IVR3_Msk /*!< SAES initialization vector input, bits [127:96] */
/******************* Bits definition for SAES_DPACFGR register ******************/
#define SAES_DPACFGR_REDCFG_Pos (0U)
#define SAES_DPACFGR_REDCFG_Msk (0x3UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000003 */
#define SAES_DPACFGR_REDCFG SAES_DPACFGR_REDCFG_Msk /*!< Redundancy configuration*/
#define SAES_DPACFGR_REDCFG_0 (0x1UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000001 */
#define SAES_DPACFGR_REDCFG_1 (0x2UL << SAES_DPACFGR_REDCFG_Pos) /*!< 0x00000002 */
#define SAES_DPACFGR_RESEED_Pos (2U)
#define SAES_DPACFGR_RESEED_Msk (0x1UL << SAES_DPACFGR_RESEED_Pos) /*!< 0x00000004 */
#define SAES_DPACFGR_RESEED SAES_DPACFGR_RESEED_Msk /*!< Automatic reseed enable */
#define SAES_DPACFGR_TRIMCFG_Pos (3U)
#define SAES_DPACFGR_TRIMCFG_Msk (0x3UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000018 */
#define SAES_DPACFGR_TRIMCFG SAES_DPACFGR_TRIMCFG_Msk /*!< Clock trimming */
#define SAES_DPACFGR_TRIMCFG_0 (0x1UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000008 */
#define SAES_DPACFGR_TRIMCFG_1 (0x2UL << SAES_DPACFGR_TRIMCFG_Pos) /*!< 0x00000010 */
#define SAES_DPACFGR_CONFIGLOCK_Pos (31U)
#define SAES_DPACFGR_CONFIGLOCK_Msk (0x1UL << SAES_DPACFGR_CONFIGLOCK_Pos) /*!< 0x80000000 */
#define SAES_DPACFGR_CONFIGLOCK SAES_DPACFGR_CONFIGLOCK_Msk /*!< DPA configuration lock */
/******************* Bits definition for SAES_IER register ******************/
#define SAES_IER_CCFIE_Pos (0U)
#define SAES_IER_CCFIE_Msk (0x1UL << SAES_IER_CCFIE_Pos) /*!< 0x00000001 */
#define SAES_IER_CCFIE SAES_IER_CCFIE_Msk /*!< Computation complete flag interrupt enable */
#define SAES_IER_RWEIE_Pos (1U)
#define SAES_IER_RWEIE_Msk (0x1UL << SAES_IER_RWEIE_Pos) /*!< 0x00000002 */
#define SAES_IER_RWEIE SAES_IER_RWEIE_Msk /*!< Read or write error Interrupt Enable */
#define SAES_IER_KEIE_Pos (2U)
#define SAES_IER_KEIE_Msk (0x1UL << SAES_IER_KEIE_Pos) /*!< 0x00000004 */
#define SAES_IER_KEIE SAES_IER_KEIE_Msk /*!< Key error interrupt enable */
#define SAES_IER_RNGEIE_Pos (3U)
#define SAES_IER_RNGEIE_Msk (0x1UL << SAES_IER_RNGEIE_Pos) /*!< 0x00000008 */
#define SAES_IER_RNGEIE SAES_IER_RNGEIE_Msk /*!< RNG error interrupt enable */
/******************* Bits definition for SAES_ISR register ******************/
#define SAES_ISR_CCF_Pos (0U)
#define SAES_ISR_CCF_Msk (0x1UL << SAES_ISR_CCF_Pos) /*!< 0x00000001 */
#define SAES_ISR_CCF SAES_ISR_CCF_Msk /*!< Computation complete flag */
#define SAES_ISR_RWEIF_Pos (1U)
#define SAES_ISR_RWEIF_Msk (0x1UL << SAES_ISR_RWEIF_Pos) /*!< 0x00000002 */
#define SAES_ISR_RWEIF SAES_ISR_RWEIF_Msk /*!< Read or write error Interrupt flag */
#define SAES_ISR_KEIF_Pos (2U)
#define SAES_ISR_KEIF_Msk (0x1UL << SAES_ISR_KEIF_Pos) /*!< 0x00000004 */
#define SAES_ISR_KEIF SAES_ISR_KEIF_Msk /*!< Key error interrupt flag */
#define SAES_ISR_RNGEIF_Pos (3U)
#define SAES_ISR_RNGEIF_Msk (0x1UL << SAES_ISR_RNGEIF_Pos) /*!< 0x00000008 */
#define SAES_ISR_RNGEIF SAES_ISR_RNGEIF_Msk /*!< RNG error interrupt flag */
/******************* Bits definition for SAES_ICR register ******************/
#define SAES_ICR_CCF_Pos (0U)
#define SAES_ICR_CCF_Msk (0x1UL << SAES_ICR_CCF_Pos) /*!< 0x00000001 */
#define SAES_ICR_CCF SAES_ICR_CCF_Msk /*!< Computation complete flag clear */
#define SAES_ICR_RWEIF_Pos (1U)
#define SAES_ICR_RWEIF_Msk (0x1UL << SAES_ICR_RWEIF_Pos) /*!< 0x00000002 */
#define SAES_ICR_RWEIF SAES_ICR_RWEIF_Msk /*!< Read or write error Interrupt flag clear */
#define SAES_ICR_KEIF_Pos (2U)
#define SAES_ICR_KEIF_Msk (0x1UL << SAES_ICR_KEIF_Pos) /*!< 0x00000004 */
#define SAES_ICR_KEIF SAES_ICR_KEIF_Msk /*!< Key error interrupt flag clear */
#define SAES_ICR_RNGEIF_Pos (3U)
#define SAES_ICR_RNGEIF_Msk (0x1UL << SAES_ICR_RNGEIF_Pos) /*!< 0x00000008 */
#define SAES_ICR_RNGEIF SAES_ICR_RNGEIF_Msk /*!< RNG error interrupt flag clear */
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000UL) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000UL) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000UL) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000UL) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000UL) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000UL) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* SDMMC Interface */
/* */
/******************************************************************************/
/****************** Bit definition for SDMMC_POWER register ******************/
#define SDMMC_POWER_PWRCTRL_Pos (0U)
#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
#define SDMMC_POWER_VSWITCH_Pos (2U)
#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
#define SDMMC_POWER_VSWITCHEN_Pos (3U)
#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
#define SDMMC_POWER_DIRPOL_Pos (4U)
#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
/****************** Bit definition for SDMMC_CLKCR register ******************/
#define SDMMC_CLKCR_CLKDIV_Pos (0U)
#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
#define SDMMC_CLKCR_PWRSAV_Pos (12U)
#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
#define SDMMC_CLKCR_WIDBUS_Pos (14U)
#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
#define SDMMC_CLKCR_DDR_Pos (18U)
#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
/******************* Bit definition for SDMMC_ARG register *******************/
#define SDMMC_ARG_CMDARG_Pos (0U)
#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
/******************* Bit definition for SDMMC_CMD register *******************/
#define SDMMC_CMD_CMDINDEX_Pos (0U)
#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
#define SDMMC_CMD_CMDTRANS_Pos (6U)
#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
#define SDMMC_CMD_CMDSTOP_Pos (7U)
#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
#define SDMMC_CMD_WAITRESP_Pos (8U)
#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
#define SDMMC_CMD_WAITINT_Pos (10U)
#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
#define SDMMC_CMD_WAITPEND_Pos (11U)
#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
#define SDMMC_CMD_CPSMEN_Pos (12U)
#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
#define SDMMC_CMD_DTHOLD_Pos (13U)
#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
#define SDMMC_CMD_BOOTMODE_Pos (14U)
#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
#define SDMMC_CMD_BOOTEN_Pos (15U)
#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
/***************** Bit definition for SDMMC_RESPCMD register *****************/
#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
/****************** Bit definition for SDMMC_RESP1 register ******************/
#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP2 register ******************/
#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP3 register ******************/
#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_RESP4 register ******************/
#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
/****************** Bit definition for SDMMC_DTIMER register *****************/
#define SDMMC_DTIMER_DATATIME_Pos (0U)
#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
/****************** Bit definition for SDMMC_DLEN register *******************/
#define SDMMC_DLEN_DATALENGTH_Pos (0U)
#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
/****************** Bit definition for SDMMC_DCTRL register ******************/
#define SDMMC_DCTRL_DTEN_Pos (0U)
#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
#define SDMMC_DCTRL_DTDIR_Pos (1U)
#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
#define SDMMC_DCTRL_DTMODE_Pos (2U)
#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
#define SDMMC_DCTRL_RWSTART_Pos (8U)
#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
#define SDMMC_DCTRL_RWSTOP_Pos (9U)
#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
#define SDMMC_DCTRL_RWMOD_Pos (10U)
#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
#define SDMMC_DCTRL_SDIOEN_Pos (11U)
#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
#define SDMMC_DCTRL_FIFORST_Pos (13U)
#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
/****************** Bit definition for SDMMC_DCOUNT register *****************/
#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
/****************** Bit definition for SDMMC_STA register ********************/
#define SDMMC_STA_CCRCFAIL_Pos (0U)
#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
#define SDMMC_STA_DCRCFAIL_Pos (1U)
#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
#define SDMMC_STA_CTIMEOUT_Pos (2U)
#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
#define SDMMC_STA_DTIMEOUT_Pos (3U)
#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
#define SDMMC_STA_TXUNDERR_Pos (4U)
#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
#define SDMMC_STA_RXOVERR_Pos (5U)
#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
#define SDMMC_STA_CMDREND_Pos (6U)
#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
#define SDMMC_STA_CMDSENT_Pos (7U)
#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
#define SDMMC_STA_DATAEND_Pos (8U)
#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
#define SDMMC_STA_DHOLD_Pos (9U)
#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
#define SDMMC_STA_DBCKEND_Pos (10U)
#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
#define SDMMC_STA_DABORT_Pos (11U)
#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
#define SDMMC_STA_DPSMACT_Pos (12U)
#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
#define SDMMC_STA_CPSMACT_Pos (13U)
#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
#define SDMMC_STA_TXFIFOHE_Pos (14U)
#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
#define SDMMC_STA_RXFIFOHF_Pos (15U)
#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
#define SDMMC_STA_TXFIFOF_Pos (16U)
#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
#define SDMMC_STA_RXFIFOF_Pos (17U)
#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
#define SDMMC_STA_TXFIFOE_Pos (18U)
#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
#define SDMMC_STA_RXFIFOE_Pos (19U)
#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
#define SDMMC_STA_BUSYD0_Pos (20U)
#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
#define SDMMC_STA_BUSYD0END_Pos (21U)
#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
#define SDMMC_STA_SDIOIT_Pos (22U)
#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
#define SDMMC_STA_ACKFAIL_Pos (23U)
#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
#define SDMMC_STA_VSWEND_Pos (25U)
#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
#define SDMMC_STA_CKSTOP_Pos (26U)
#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
#define SDMMC_STA_IDMATE_Pos (27U)
#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
#define SDMMC_STA_IDMABTC_Pos (28U)
#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
/******************* Bit definition for SDMMC_ICR register *******************/
#define SDMMC_ICR_CCRCFAILC_Pos (0U)
#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
#define SDMMC_ICR_DCRCFAILC_Pos (1U)
#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
#define SDMMC_ICR_TXUNDERRC_Pos (4U)
#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
#define SDMMC_ICR_RXOVERRC_Pos (5U)
#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
#define SDMMC_ICR_CMDRENDC_Pos (6U)
#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
#define SDMMC_ICR_CMDSENTC_Pos (7U)
#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
#define SDMMC_ICR_DATAENDC_Pos (8U)
#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
#define SDMMC_ICR_DHOLDC_Pos (9U)
#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
#define SDMMC_ICR_DBCKENDC_Pos (10U)
#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
#define SDMMC_ICR_DABORTC_Pos (11U)
#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
#define SDMMC_ICR_SDIOITC_Pos (22U)
#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
#define SDMMC_ICR_ACKFAILC_Pos (23U)
#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
#define SDMMC_ICR_VSWENDC_Pos (25U)
#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
#define SDMMC_ICR_CKSTOPC_Pos (26U)
#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
#define SDMMC_ICR_IDMATEC_Pos (27U)
#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
#define SDMMC_ICR_IDMABTCC_Pos (28U)
#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
/****************** Bit definition for SDMMC_MASK register *******************/
#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
#define SDMMC_MASK_RXOVERRIE_Pos (5U)
#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
#define SDMMC_MASK_CMDRENDIE_Pos (6U)
#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
#define SDMMC_MASK_CMDSENTIE_Pos (7U)
#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
#define SDMMC_MASK_DATAENDIE_Pos (8U)
#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
#define SDMMC_MASK_DHOLDIE_Pos (9U)
#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
#define SDMMC_MASK_DBCKENDIE_Pos (10U)
#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
#define SDMMC_MASK_DABORTIE_Pos (11U)
#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
#define SDMMC_MASK_SDIOITIE_Pos (22U)
#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
#define SDMMC_MASK_ACKFAILIE_Pos (23U)
#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
#define SDMMC_MASK_VSWENDIE_Pos (25U)
#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
#define SDMMC_MASK_CKSTOPIE_Pos (26U)
#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
#define SDMMC_MASK_IDMABTCIE_Pos (28U)
#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
/***************** Bit definition for SDMMC_ACKTIME register *****************/
#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
/****************** Bit definition for SDMMC_FIFOTHR register *******************/
#define SDMMC_FIFOTHR_THR_Pos (0U)
#define SDMMC_FIFOTHR_THR_Msk (0xFUL << SDMMC_FIFOTHR_THR_Pos) /*!< 0x0000000F */
#define SDMMC_FIFOTHR_THR SDMMC_FIFOTHR_THR_Msk /*!<FIFO threshold */
/****************** Bit definition for SDMMC_FIFO register *******************/
#define SDMMC_FIFO_FIFODATA_Pos (0U)
#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
/****************** Bit definition for SDMMC_IDMACTRL register ****************/
#define SDMMC_IDMA_IDMAEN_Pos (0U)
#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
#define SDMMC_IDMA_IDMABMODE_Pos (1U)
#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable Linked List mode for IDMA */
/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
#define SDMMC_IDMABSIZE_IDMABNDT_Pos (6U)
#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0x7FFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x0001FFC0 */
#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
/***************** Bit definition for SDMMC_IDMABASER register ***************/
#define SDMMC_IDMABASER_IDMABASER ((uint32_t)0xFFFFFFFF) /*!< Memory base address register */
/***************** Bit definition for SDMMC_IDMALAR) register ***************/
#define SDMMC_IDMALAR_IDMALA_Pos (0U)
#define SDMMC_IDMALAR_IDMALA_Msk (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos) /*!< 0x00003FFF */
#define SDMMC_IDMALAR_IDMALA SDMMC_IDMALAR_IDMALA_Msk /*!< Linked list item address offset */
#define SDMMC_IDMALAR_ABR_Pos (29U)
#define SDMMC_IDMALAR_ABR_Msk (0x1UL << SDMMC_IDMALAR_ABR_Pos) /*!< 0x20000000 */
#define SDMMC_IDMALAR_ABR SDMMC_IDMALAR_ABR_Msk /*!< Acknowledge linked list buffer ready */
#define SDMMC_IDMALAR_ULS_Pos (30U)
#define SDMMC_IDMALAR_ULS_Msk (0x1UL << SDMMC_IDMALAR_ULS_Pos) /*!< 0x40000000 */
#define SDMMC_IDMALAR_ULS SDMMC_IDMALAR_ULS_Msk /*!< Update Size from linked list */
#define SDMMC_IDMALAR_ULA_Pos (31U)
#define SDMMC_IDMALAR_ULA_Msk (0x1UL << SDMMC_IDMALAR_ULA_Pos) /*!< 0x80000000 */
#define SDMMC_IDMALAR_ULA SDMMC_IDMALAR_ULA_Msk /*!< Update Address from linked list */
/***************** Bit definition for SDMMC_IDMABAR) register ***************/
#define SDMMC_IDMABAR_IDMABAR ((uint32_t)0xFFFFFFFF) /*!< linked list memory base register */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_SPE_Pos (0U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
#define SPI_CR1_MASRX_Pos (8U)
#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
#define SPI_CR1_CSTART_Pos (9U)
#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
#define SPI_CR1_CSUSP_Pos (10U)
#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
#define SPI_CR1_HDDIR_Pos (11U)
#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
#define SPI_CR1_SSI_Pos (12U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
#define SPI_CR1_CRC33_17_Pos (13U)
#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
#define SPI_CR1_RCRCINI_Pos (14U)
#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
#define SPI_CR1_TCRCINI_Pos (15U)
#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
#define SPI_CR1_IOLOCK_Pos (16U)
#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_TSIZE_Pos (0U)
#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
/******************* Bit definition for SPI_CFG1 register *******************/
#define SPI_CFG1_DSIZE_Pos (0U)
#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
#define SPI_CFG1_FTHLV_Pos (5U)
#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
#define SPI_CFG1_UDRCFG_Pos (9U)
#define SPI_CFG1_UDRCFG_Msk (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<Behavior of Slave transmitter at underrun */
#define SPI_CFG1_RXDMAEN_Pos (14U)
#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
#define SPI_CFG1_TXDMAEN_Pos (15U)
#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
#define SPI_CFG1_CRCSIZE_Pos (16U)
#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame */
#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
#define SPI_CFG1_CRCEN_Pos (22U)
#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
#define SPI_CFG1_MBR_Pos (28U)
#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
#define SPI_CFG1_BPASS_Pos (31U)
#define SPI_CFG1_BPASS_Msk (0x1UL << SPI_CFG1_BPASS_Pos) /*!< 0x80000000 */
#define SPI_CFG1_BPASS SPI_CFG1_BPASS_Msk /*!<Bypass of the prescaler */
/******************* Bit definition for SPI_CFG2 register *******************/
#define SPI_CFG2_MSSI_Pos (0U)
#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
#define SPI_CFG2_MIDI_Pos (4U)
#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
#define SPI_CFG2_RDIOM_Pos (13U)
#define SPI_CFG2_RDIOM_Msk (0x1UL << SPI_CFG2_RDIOM_Pos) /*!< 0x00002000 */
#define SPI_CFG2_RDIOM SPI_CFG2_RDIOM_Msk /*!<RDY signal input/output management */
#define SPI_CFG2_RDIOP_Pos (14U)
#define SPI_CFG2_RDIOP_Msk (0x1UL << SPI_CFG2_RDIOP_Pos) /*!< 0x00004000 */
#define SPI_CFG2_RDIOP SPI_CFG2_RDIOP_Msk /*!<RDY signal input/output polarity */
#define SPI_CFG2_IOSWP_Pos (15U)
#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
#define SPI_CFG2_COMM_Pos (17U)
#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
#define SPI_CFG2_SP_Pos (19U)
#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
#define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
#define SPI_CFG2_MASTER_Pos (22U)
#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
#define SPI_CFG2_LSBFRST_Pos (23U)
#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
#define SPI_CFG2_CPHA_Pos (24U)
#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
#define SPI_CFG2_CPOL_Pos (25U)
#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
#define SPI_CFG2_SSM_Pos (26U)
#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
#define SPI_CFG2_SSIOP_Pos (28U)
#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
#define SPI_CFG2_SSOE_Pos (29U)
#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
#define SPI_CFG2_SSOM_Pos (30U)
#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
#define SPI_CFG2_AFCNTR_Pos (31U)
#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
/******************* Bit definition for SPI_IER register ********************/
#define SPI_IER_RXPIE_Pos (0U)
#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
#define SPI_IER_TXPIE_Pos (1U)
#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
#define SPI_IER_DXPIE_Pos (2U)
#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
#define SPI_IER_EOTIE_Pos (3U)
#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
#define SPI_IER_TXTFIE_Pos (4U)
#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
#define SPI_IER_UDRIE_Pos (5U)
#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
#define SPI_IER_OVRIE_Pos (6U)
#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
#define SPI_IER_CRCEIE_Pos (7U)
#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
#define SPI_IER_TIFREIE_Pos (8U)
#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
#define SPI_IER_MODFIE_Pos (9U)
#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
/******************* Bit definition for SPI_SR register *********************/
#define SPI_SR_RXP_Pos (0U)
#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
#define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
#define SPI_SR_TXP_Pos (1U)
#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
#define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
#define SPI_SR_DXP_Pos (2U)
#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
#define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
#define SPI_SR_EOT_Pos (3U)
#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
#define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
#define SPI_SR_TXTF_Pos (4U)
#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
#define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
#define SPI_SR_UDR_Pos (5U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
#define SPI_SR_CRCE_Pos (7U)
#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
#define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
#define SPI_SR_TIFRE_Pos (8U)
#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
#define SPI_SR_MODF_Pos (9U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
#define SPI_SR_SUSP_Pos (11U)
#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
#define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
#define SPI_SR_TXC_Pos (12U)
#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
#define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
#define SPI_SR_RXPLVL_Pos (13U)
#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
#define SPI_SR_RXWNE_Pos (15U)
#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
#define SPI_SR_CTSIZE_Pos (16U)
#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
/******************* Bit definition for SPI_IFCR register *******************/
#define SPI_IFCR_EOTC_Pos (3U)
#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
#define SPI_IFCR_TXTFC_Pos (4U)
#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
#define SPI_IFCR_UDRC_Pos (5U)
#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
#define SPI_IFCR_OVRC_Pos (6U)
#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
#define SPI_IFCR_CRCEC_Pos (7U)
#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
#define SPI_IFCR_TIFREC_Pos (8U)
#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
#define SPI_IFCR_MODFC_Pos (9U)
#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
#define SPI_IFCR_SUSPC_Pos (11U)
#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
/******************* Bit definition for SPI_TXDR register *******************/
#define SPI_TXDR_TXDR_Pos (0U)
#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
/******************* Bit definition for SPI_RXDR register *******************/
#define SPI_RXDR_RXDR_Pos (0U)
#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
/******************* Bit definition for SPI_CRCPOLY register ****************/
#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
/******************* Bit definition for SPI_TXCRC register ******************/
#define SPI_TXCRC_TXCRC_Pos (0U)
#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
/******************* Bit definition for SPI_RXCRC register ******************/
#define SPI_RXCRC_RXCRC_Pos (0U)
#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
/******************* Bit definition for SPI_UDRDR register ******************/
#define SPI_UDRDR_UDRDR_Pos (0U)
#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
/******************* Bits definition for SPI_I2SCFGR register ***************/
#define SPI_I2SCFGR_I2SMOD_Pos (0U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_I2SCFG_Pos (1U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFGR[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_DATLEN_Pos (8U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_CHLEN_Pos (10U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_CKPOL_Pos (11U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Serial audio clock polarity */
#define SPI_I2SCFGR_FIXCH_Pos (12U)
#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
#define SPI_I2SCFGR_WSINV_Pos (13U)
#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
#define SPI_I2SCFGR_DATFMT_Pos (14U)
#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00003000 */
#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
#define SPI_I2SCFGR_I2SDIV_Pos (16U)
#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SCFGR_ODD_Pos (24U)
#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SCFGR_MCKOE_Pos (25U)
#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SPDIF-RX Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SPDIF_CR register ******************/
#define SPDIFRX_CR_SPDIFRXEN_Pos (0U)
#define SPDIFRX_CR_SPDIFRXEN_Msk (0x3UL << SPDIFRX_CR_SPDIFRXEN_Pos) /*!< 0x00000003 */
#define SPDIFRX_CR_SPDIFRXEN SPDIFRX_CR_SPDIFRXEN_Msk /*!<Peripheral Block Enable */
#define SPDIFRX_CR_SPDIFRXEN_0 (0x01UL << SPDIFRX_CR_SPDIFRXEN_Pos) /*!< 0x00000001 */
#define SPDIFRX_CR_SPDIFRXEN_1 (0x02UL << SPDIFRX_CR_SPDIFRXEN_Pos) /*!< 0x00000002 */
#define SPDIFRX_CR_RXDMAEN_Pos (2U)
#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
#define SPDIFRX_CR_RXSTEO_Pos (3U)
#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
#define SPDIFRX_CR_DRFMT_Pos (4U)
#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
#define SPDIFRX_CR_PMSK_Pos (6U)
#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
#define SPDIFRX_CR_VMSK_Pos (7U)
#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
#define SPDIFRX_CR_CUMSK_Pos (8U)
#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
#define SPDIFRX_CR_PTMSK_Pos (9U)
#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
#define SPDIFRX_CR_CBDMAEN_Pos (10U)
#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
#define SPDIFRX_CR_CHSEL_Pos (11U)
#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
#define SPDIFRX_CR_NBTR_Pos (12U)
#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
#define SPDIFRX_CR_WFA_Pos (14U)
#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
#define SPDIFRX_CR_INSEL_Pos (16U)
#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
#define SPDIFRX_CR_CKSEN_Pos (20U)
#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
/******************* Bit definition for SPDIFRX_IMR register *******************/
#define SPDIFRX_IMR_RXNEIE_Pos (0U)
#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
#define SPDIFRX_IMR_PERRIE_Pos (2U)
#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
#define SPDIFRX_IMR_OVRIE_Pos (3U)
#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
#define SPDIFRX_IMR_SBLKIE_Pos (4U)
#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
#define SPDIFRX_IMR_IFEIE_Pos (6U)
#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
/******************* Bit definition for SPDIFRX_SR register *******************/
#define SPDIFRX_SR_RXNE_Pos (0U)
#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
#define SPDIFRX_SR_CSRNE_Pos (1U)
#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
#define SPDIFRX_SR_PERR_Pos (2U)
#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
#define SPDIFRX_SR_OVR_Pos (3U)
#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
#define SPDIFRX_SR_SBD_Pos (4U)
#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
#define SPDIFRX_SR_SYNCD_Pos (5U)
#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
#define SPDIFRX_SR_FERR_Pos (6U)
#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
#define SPDIFRX_SR_SERR_Pos (7U)
#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
#define SPDIFRX_SR_TERR_Pos (8U)
#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
#define SPDIFRX_SR_WIDTH5_Pos (16U)
#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
/******************* Bit definition for SPDIFRX_IFCR register *******************/
#define SPDIFRX_IFCR_PERRCF_Pos (2U)
#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
#define SPDIFRX_IFCR_OVRCF_Pos (3U)
#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
#define SPDIFRX_IFCR_SBDCF_Pos (4U)
#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
#define SPDIFRX_DR0_DR_Pos (0U)
#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
#define SPDIFRX_DR0_PE_Pos (24U)
#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
#define SPDIFRX_DR0_V_Pos (25U)
#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
#define SPDIFRX_DR0_U_Pos (26U)
#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
#define SPDIFRX_DR0_C_Pos (27U)
#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
#define SPDIFRX_DR0_PT_Pos (28U)
#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
#define SPDIFRX_DR1_DR_Pos (8U)
#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
#define SPDIFRX_DR1_PT_Pos (4U)
#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
#define SPDIFRX_DR1_C_Pos (3U)
#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
#define SPDIFRX_DR1_U_Pos (2U)
#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
#define SPDIFRX_DR1_V_Pos (1U)
#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
#define SPDIFRX_DR1_PE_Pos (0U)
#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
#define SPDIFRX_DR1_DRNL1_Pos (16U)
#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
#define SPDIFRX_DR1_DRNL2_Pos (0U)
#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
/******************* Bit definition for SPDIFRX_CSR register *******************/
#define SPDIFRX_CSR_USR_Pos (0U)
#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
#define SPDIFRX_CSR_CS_Pos (16U)
#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
#define SPDIFRX_CSR_SOB_Pos (24U)
#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
/******************* Bit definition for SPDIFRX_DIR register *******************/
#define SPDIFRX_DIR_THI_Pos (0U)
#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
#define SPDIFRX_DIR_TLO_Pos (16U)
#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_BOOTCR register ****************/
#define SYSCFG_BOOTCR_BOOT0_PD_Pos (0U)
#define SYSCFG_BOOTCR_BOOT0_PD_Msk (0x1UL << SYSCFG_BOOTCR_BOOT0_PD_Pos) /*!< 0x00000001 */
#define SYSCFG_BOOTCR_BOOT0_PD SYSCFG_BOOTCR_BOOT0_PD_Msk /*!< BOOT0 pin pull-down disable */
#define SYSCFG_BOOTCR_BOOT1_PD_Pos (1U)
#define SYSCFG_BOOTCR_BOOT1_PD_Msk (0x1UL << SYSCFG_BOOTCR_BOOT1_PD_Pos) /*!< 0x00000002 */
#define SYSCFG_BOOTCR_BOOT1_PD SYSCFG_BOOTCR_BOOT1_PD_Msk /*!< BOOT1 pin pull-down disable */
/****************** Bit definition for SYSCFG_CM55CR register ****************/
#define SYSCFG_CM55CR_FPU_IT_EN_Pos (0U)
#define SYSCFG_CM55CR_FPU_IT_EN_Msk (0x3FUL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x0000003F */
#define SYSCFG_CM55CR_FPU_IT_EN SYSCFG_CM55CR_FPU_IT_EN_Msk /*!< Enable FPU exception */
#define SYSCFG_CM55CR_FPU_IT_EN_0 (0x1UL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_CM55CR_FPU_IT_EN_1 (0x2UL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x00000002 */
#define SYSCFG_CM55CR_FPU_IT_EN_2 (0x4UL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x00000004 */
#define SYSCFG_CM55CR_FPU_IT_EN_3 (0x8UL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x00000008 */
#define SYSCFG_CM55CR_FPU_IT_EN_4 (0x10UL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x00000010 */
#define SYSCFG_CM55CR_FPU_IT_EN_5 (0x20UL << SYSCFG_CM55CR_FPU_IT_EN_Pos) /*!< 0x00000020 */
#define SYSCFG_CM55CR_LOCKSVTAIRCR_Pos (16U)
#define SYSCFG_CM55CR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CM55CR_LOCKSVTAIRCR_Pos) /*!< 0x00010000 */
#define SYSCFG_CM55CR_LOCKSVTAIRCR SYSCFG_CM55CR_LOCKSVTAIRCR_Msk
#define SYSCFG_CM55CR_LOCKNSVTOR_Pos (17U)
#define SYSCFG_CM55CR_LOCKNSVTOR_Msk (0x1UL << SYSCFG_CM55CR_LOCKNSVTOR_Pos) /*!< 0x00020000 */
#define SYSCFG_CM55CR_LOCKNSVTOR SYSCFG_CM55CR_LOCKNSVTOR_Msk /*!< Prevent changes to the non-secure vector table base address */
#define SYSCFG_CM55CR_LOCKSMPU_Pos (18U)
#define SYSCFG_CM55CR_LOCKSMPU_Msk (0x1UL << SYSCFG_CM55CR_LOCKSMPU_Pos) /*!< 0x00040000 */
#define SYSCFG_CM55CR_LOCKSMPU SYSCFG_CM55CR_LOCKSMPU_Msk /*!< Prevent changes to programmed secure MPU memory regions */
#define SYSCFG_CM55CR_LOCKNSMPU_Pos (19U)
#define SYSCFG_CM55CR_LOCKNSMPU_Msk (0x1UL << SYSCFG_CM55CR_LOCKNSMPU_Pos) /*!< 0x00080000 */
#define SYSCFG_CM55CR_LOCKNSMPU SYSCFG_CM55CR_LOCKNSMPU_Msk /*!< Prevent changes to programmed non-secure MPU memory regions */
#define SYSCFG_CM55CR_LOCKSAU_Pos (20U)
#define SYSCFG_CM55CR_LOCKSAU_Msk (0x1UL << SYSCFG_CM55CR_LOCKSAU_Pos) /*!< 0x00100000 */
#define SYSCFG_CM55CR_LOCKSAU SYSCFG_CM55CR_LOCKSAU_Msk /*!< Prevent changes to secure SAU memory regions already programmed */
#define SYSCFG_CM55CR_LOCKDCAIC_Pos (21U)
#define SYSCFG_CM55CR_LOCKDCAIC_Msk (0x1UL << SYSCFG_CM55CR_LOCKDCAIC_Pos) /*!< 0x00200000 */
#define SYSCFG_CM55CR_LOCKDCAIC SYSCFG_CM55CR_LOCKDCAIC_Msk
/****************** Bit definition for SYSCFG_CM55TCMCR register ***************/
#define SYSCFG_CM55TCMCR_CFGITCMSZ_Pos (0U)
#define SYSCFG_CM55TCMCR_CFGITCMSZ_Msk (0xFUL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos) /*!< 0x0000000F */
#define SYSCFG_CM55TCMCR_CFGITCMSZ SYSCFG_CM55TCMCR_CFGITCMSZ_Msk /*!< Select ITCM memory size */
#define SYSCFG_CM55TCMCR_CFGITCMSZ_0 (0x1UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos) /*!< 0x00000001 */
#define SYSCFG_CM55TCMCR_CFGITCMSZ_1 (0x2UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos) /*!< 0x00000002 */
#define SYSCFG_CM55TCMCR_CFGITCMSZ_2 (0x4UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos) /*!< 0x00000004 */
#define SYSCFG_CM55TCMCR_CFGITCMSZ_3 (0x8UL << SYSCFG_CM55TCMCR_CFGITCMSZ_Pos) /*!< 0x00000008 */
#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos (4U)
#define SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk (0xFUL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos) /*!< 0x000000F0 */
#define SYSCFG_CM55TCMCR_CFGDTCMSZ SYSCFG_CM55TCMCR_CFGDTCMSZ_Msk /*!< Select DTCM memory size */
#define SYSCFG_CM55TCMCR_CFGDTCMSZ_0 (0x1UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos) /*!< 0x00000010 */
#define SYSCFG_CM55TCMCR_CFGDTCMSZ_1 (0x2UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos) /*!< 0x00000020 */
#define SYSCFG_CM55TCMCR_CFGDTCMSZ_2 (0x4UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos) /*!< 0x00000040 */
#define SYSCFG_CM55TCMCR_CFGDTCMSZ_3 (0x8UL << SYSCFG_CM55TCMCR_CFGDTCMSZ_Pos) /*!< 0x00000080 */
#define SYSCFG_CM55TCMCR_LOCKTCM_Pos (16U)
#define SYSCFG_CM55TCMCR_LOCKTCM_Msk (0x1UL << SYSCFG_CM55TCMCR_LOCKTCM_Pos) /*!< 0x00010000 */
#define SYSCFG_CM55TCMCR_LOCKTCM SYSCFG_CM55TCMCR_LOCKTCM_Msk /*!< Disable writes to registers associated with the TCM region */
#define SYSCFG_CM55TCMCR_LOCKITGU_Pos (17U)
#define SYSCFG_CM55TCMCR_LOCKITGU_Msk (0x1UL << SYSCFG_CM55TCMCR_LOCKITGU_Pos) /*!< 0x00020000 */
#define SYSCFG_CM55TCMCR_LOCKITGU SYSCFG_CM55TCMCR_LOCKITGU_Msk /*!< Disable writes to registers associated with the ITCM interface security/gating */
#define SYSCFG_CM55TCMCR_LOCKDTGU_Pos (18U)
#define SYSCFG_CM55TCMCR_LOCKDTGU_Msk (0x1UL << SYSCFG_CM55TCMCR_LOCKDTGU_Pos) /*!< 0x00040000 */
#define SYSCFG_CM55TCMCR_LOCKDTGU SYSCFG_CM55TCMCR_LOCKDTGU_Msk /*!< Disable writes to registers associated with the DTCM interface security/gating. */
#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos (23U)
#define SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk (0x1UL << SYSCFG_CM55TCMCR_ITCMWSDISABLE_Pos) /*!< 0x00800000 */
#define SYSCFG_CM55TCMCR_ITCMWSDISABLE SYSCFG_CM55TCMCR_ITCMWSDISABLE_Msk /*!< Disable wait-state applied by default on extended ITCM memory */
#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos (24U)
#define SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk (0x1UL << SYSCFG_CM55TCMCR_DTCMWSDISABLE_Pos) /*!< 0x01000000 */
#define SYSCFG_CM55TCMCR_DTCMWSDISABLE SYSCFG_CM55TCMCR_DTCMWSDISABLE_Msk /*!< Disable wait-state applied by default on extended DTCM memory */
/****************** Bit definition for SYSCFG_CM55RWMCR register **************/
#define SYSCFG_CM55RWMCR_RME_TCM_Pos (0U)
#define SYSCFG_CM55RWMCR_RME_TCM_Msk (0x1UL << SYSCFG_CM55RWMCR_RME_TCM_Pos) /*!< 0x00000001 */
#define SYSCFG_CM55RWMCR_RME_TCM SYSCFG_CM55RWMCR_RME_TCM_Msk /*!< RW margin enable input for TCM memories */
#define SYSCFG_CM55RWMCR_RM_TCM_Pos (1U)
#define SYSCFG_CM55RWMCR_RM_TCM_Msk (0xFUL << SYSCFG_CM55RWMCR_RM_TCM_Pos) /*!< 0x0000001E */
#define SYSCFG_CM55RWMCR_RM_TCM SYSCFG_CM55RWMCR_RM_TCM_Msk /*!< External RW margin inputs for TCM memories */
#define SYSCFG_CM55RWMCR_BC1_TCM_Pos (5U)
#define SYSCFG_CM55RWMCR_BC1_TCM_Msk (0x1UL << SYSCFG_CM55RWMCR_BC1_TCM_Pos) /*!< 0x00000020 */
#define SYSCFG_CM55RWMCR_BC1_TCM SYSCFG_CM55RWMCR_BC1_TCM_Msk /*!< Biasing level adjust input recommended for Vnom */
#define SYSCFG_CM55RWMCR_BC2_TCM_Pos (6U)
#define SYSCFG_CM55RWMCR_BC2_TCM_Msk (0x1UL << SYSCFG_CM55RWMCR_BC2_TCM_Pos) /*!< 0x00000040 */
#define SYSCFG_CM55RWMCR_BC2_TCM SYSCFG_CM55RWMCR_BC2_TCM_Msk /*!< Biasing level adjust input recommended for Vnom + 10% */
#define SYSCFG_CM55RWMCR_RME_CACHE_Pos (7U)
#define SYSCFG_CM55RWMCR_RME_CACHE_Msk (0x1UL << SYSCFG_CM55RWMCR_RME_CACHE_Pos) /*!< 0x00000080 */
#define SYSCFG_CM55RWMCR_RME_CACHE SYSCFG_CM55RWMCR_RME_CACHE_Msk /*!< RW margin enable input for caches memories */
#define SYSCFG_CM55RWMCR_RM_CACHE_Pos (8U)
#define SYSCFG_CM55RWMCR_RM_CACHE_Msk (0xFUL << SYSCFG_CM55RWMCR_RM_CACHE_Pos) /*!< 0x00000F00 */
#define SYSCFG_CM55RWMCR_RM_CACHE SYSCFG_CM55RWMCR_RM_CACHE_Msk /*!< External read/write (RW) margin inputs for caches memories */
#define SYSCFG_CM55RWMCR_BC1_CACHE_Pos (12U)
#define SYSCFG_CM55RWMCR_BC1_CACHE_Msk (0x1UL << SYSCFG_CM55RWMCR_BC1_CACHE_Pos) /*!< 0x0001000 */
#define SYSCFG_CM55RWMCR_BC1_CACHE SYSCFG_CM55RWMCR_BC1_CACHE_Msk /*!< Biasing level adjust input recommended for Vnom */
#define SYSCFG_CM55RWMCR_BC2_CACHE_Pos (13U)
#define SYSCFG_CM55RWMCR_BC2_CACHE_Msk (0x1UL << SYSCFG_CM55RWMCR_BC2_CACHE_Pos) /*!< 0x00002000 */
#define SYSCFG_CM55RWMCR_BC2_CACHE SYSCFG_CM55RWMCR_BC2_CACHE_Msk /*!< Biasing level adjust input recommended for Vnom + 10% */
/****************** Bit definition for SYSCFG_INITSVTORCR register **************/
#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos (7U)
#define SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk (0x1FFFFFFUL << SYSCFG_INITSVTORCR_SVTOR_ADDR_Pos) /*!< 0xFFFFFF80 */
#define SYSCFG_INITSVTORCR_SVTOR_ADDR SYSCFG_INITSVTORCR_SVTOR_ADDR_Msk /*!< Secure vector table base address */
/****************** Bit definition for SYSCFG_INITNSVTORCR register **************/
#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos (7U)
#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk (0x1FFFFFFUL << SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Pos) /*!< 0xFFFFFF80 */
#define SYSCFG_INITNSVTORCR_NSVTOR_ADDR SYSCFG_INITNSVTORCR_NSVTOR_ADDR_Msk /*!< Non-Secure vector table base address */
/****************** Bit definition for SYSCFG_CM55RSTCR register **************/
#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos (0U)
#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk (0x1UL << SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Pos) /*!< 0x00000001 */
#define SYSCFG_CM55RSTCR_CORE_RESET_TYPE SYSCFG_CM55RSTCR_CORE_RESET_TYPE_Msk /*!< Select reset to apply on core upon SYSRESETREQ */
#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos (1U)
#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Pos) /*!< 0x00000002 */
#define SYSCFG_CM55RSTCR_LOCKUP_RST_EN SYSCFG_CM55RSTCR_LOCKUP_RST_EN_Msk /*!< Select action to perform on a lockup state on the core */
#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos (2U)
#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk (0x1UL << SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Pos) /*!< 0x00000004 */
#define SYSCFG_CM55RSTCR_LOCKUP_NMI_EN SYSCFG_CM55RSTCR_LOCKUP_NMI_EN_Msk /*!< Select action to perform on a lockup state on the core */
/****************** Bit definition for SYSCFG_CM55PAHBWPR register **************/
#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos (0U)
#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk (0x1UL << SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Pos) /*!< 0x00000001 */
#define SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK SYSCFG_CM55PAHBWPR_PAHB_ERROR_ACK_Msk /*!< Error capture in write posting buffer */
/****************** Bit definition for SYSCFG_VENCRAMCR register **************/
#define SYSCFG_VENCRAMCR_VENCRAM_EN_Pos (0U)
#define SYSCFG_VENCRAMCR_VENCRAM_EN_Msk (0x1UL << SYSCFG_VENCRAMCR_VENCRAM_EN_Pos) /*!< 0x00000001 */
#define SYSCFG_VENCRAMCR_VENCRAM_EN SYSCFG_VENCRAMCR_VENCRAM_EN_Msk /*!< VENCRAM allocation VENC if active, or to system (if VENC inactive) */
/****************** Bit definition for SYSCFG_POTTAMPRSTCR register **************/
#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos (0U)
#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk (0x1UL << SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Pos) /*!< 0x00000001 */
#define SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK SYSCFG_POTTAMPRSTCR_POTTAMPERSETMASK_Msk /*!< mask PKA, SAES, CRYP1/2, and HASH reset, in case of potential tamper */
/****************** Bit definition for SYSCFG_NPUNICQOSCR register **************/
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos (0U)
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x0000000F */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Msk /*!< NPUNIC read QoS information for NPU1 master port */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_0 (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000001 */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_1 (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000002 */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_2 (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000004 */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_3 (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSR_Pos) /*!< 0x00000008 */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos (4U)
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk (0xFUL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x0000000F */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Msk /*!< NPUNIC write QoS information for NPU1 master port */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_0 (0x1UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000001 */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_1 (0x2UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000002 */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_2 (0x4UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000004 */
#define SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_3 (0x8UL << SYSCFG_NPUNICQOSCR_NPU1_ARQOSW_Pos) /*!< 0x00000008 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos (8U)
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x0000000F */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Msk /*!< NPUNIC read QoS information for NPU2 master port */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_0 (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000001 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_1 (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000002 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_2 (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000004 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_3 (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSR_Pos) /*!< 0x00000008 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos (12U)
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk (0xFUL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x0000000F */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Msk /*!< NPUNIC write QoS information for NPU2 master port */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_0 (0x1UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000001 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_1 (0x2UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000002 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_2 (0x4UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000004 */
#define SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_3 (0x8UL << SYSCFG_NPUNICQOSCR_NPU2_ARQOSW_Pos) /*!< 0x00000008 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos (16U)
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x0000000F */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Msk /*!< NPUNIC read QoS information for master port from CPUSS */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_0 (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000001 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_1 (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000002 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_2 (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000004 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_3 (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSR_Pos) /*!< 0x00000008 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos (20U)
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk (0xFUL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x0000000F */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Msk /*!< NPUNIC write QoS information for master port from CPUSS */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_0 (0x1UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000001 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_1 (0x2UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000002 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_2 (0x4UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000004 */
#define SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_3 (0x8UL << SYSCFG_NPUNICQOSCR_CPUSS_ARQOSW_Pos) /*!< 0x00000008 */
/****************** Bit definition for SYSCFG_ICNEWRCR register **************/
#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos (0U)
#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk (0x1UL << SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000001 */
#define SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE SYSCFG_ICNEWRCR_SDMMC1_EARLY_WR_RSP_ENABLE_Msk /*!< SDMMC1 early-write response */
#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos (1U)
#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk (0x1UL << SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000002 */
#define SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE SYSCFG_ICNEWRCR_SDMMC2_EARLY_WR_RSP_ENABLE_Msk /*!< SDMMC2 early-write response */
#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos (2U)
#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk (0x1UL << SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000004 */
#define SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE SYSCFG_ICNEWRCR_USB1_EARLY_WR_RSP_ENABLE_Msk /*!< USB1 early-write response */
#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos (3U)
#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk (0x1UL << SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Pos) /*!< 0x00000008 */
#define SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE SYSCFG_ICNEWRCR_USB2_EARLY_WR_RSP_ENABLE_Msk /*!< USB2 early-write response */
/****************** Bit definition for SYSCFG_ICNCGCR register **************/
#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos (0U)
#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk (0x1UL << SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Pos) /*!< 0x00000001 */
#define SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE SYSCFG_ICNCGCR_NPU_NIC_CG_DISABLE_Msk /*!< NPU_NIC clock gating disable */
#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos (1U)
#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk (0x1UL << SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Pos) /*!< 0x00000002 */
#define SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE SYSCFG_ICNCGCR_CPU_NIC_CG_DISABLE_Msk /*!< CPU_NIC clock gating disable */
#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos (2U)
#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk (0x1UL << SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Pos) /*!< 0x00000004 */
#define SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE SYSCFG_ICNCGCR_CPU_NOC_CG_DISABLE_Msk /*!< CPU_NOC clock gating disable */
/****************** Bit definition for SYSCFG_IOCR register **************/
#define SYSCFG_IOCR_IOCR_Pos (0U)
#define SYSCFG_IOCR_IOCR_Msk (0xFFFFFFFFUL << SYSCFG_IOCR_IOCR_Pos) /*!< 0xFFFFFFFF */
#define SYSCFG_IOCR_IOCR SYSCFG_IOCR_IOCR_Msk /*!< Digital or analog pins */
/****************** Bit definition for SYSCFG_VDDIO2CCCR register **************/
#define SYSCFG_VDDIO2CCCR_RANSRC_Pos (0U)
#define SYSCFG_VDDIO2CCCR_RANSRC_Msk (0xFUL << SYSCFG_VDDIO2CCCR_RANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO2CCCR_RANSRC SYSCFG_VDDIO2CCCR_RANSRC_Msk /*!< I/O compensation code for NMOS transistors */
#define SYSCFG_VDDIO2CCCR_RANSRC_0 (0x1UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO2CCCR_RANSRC_1 (0x2UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO2CCCR_RANSRC_2 (0x4UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO2CCCR_RANSRC_3 (0x8UL << SYSCFG_VDDIO2CCCR_RANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO2CCCR_RAPSRC_Pos (4U)
#define SYSCFG_VDDIO2CCCR_RAPSRC_Msk (0xFUL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO2CCCR_RAPSRC SYSCFG_VDDIO2CCCR_RAPSRC_Msk /*!< I/O compensation code for PMOS transistors */
#define SYSCFG_VDDIO2CCCR_RAPSRC_0 (0x1UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO2CCCR_RAPSRC_1 (0x2UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO2CCCR_RAPSRC_2 (0x4UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO2CCCR_RAPSRC_3 (0x8UL << SYSCFG_VDDIO2CCCR_RAPSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO2CCCR_EN_Pos (8U)
#define SYSCFG_VDDIO2CCCR_EN_Msk (0x1UL << SYSCFG_VDDIO2CCCR_EN_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO2CCCR_EN SYSCFG_VDDIO2CCCR_EN_Msk /*!< Enables the compensation cell of I/Os supplied by VDDIO2 */
#define SYSCFG_VDDIO2CCCR_CS_Pos (9U)
#define SYSCFG_VDDIO2CCCR_CS_Msk (0x1UL << SYSCFG_VDDIO2CCCR_CS_Pos) /*!< 0x00000200 */
#define SYSCFG_VDDIO2CCCR_CS SYSCFG_VDDIO2CCCR_CS_Msk /*!< Code selection for the compensation cell of I/Os supplied by VDDIO2 */
/****************** Bit definition for SYSCFG_VDDIO2CCSR register **************/
#define SYSCFG_VDDIO2CCSR_ANSRC_Pos (0U)
#define SYSCFG_VDDIO2CCSR_ANSRC_Msk (0xFUL << SYSCFG_VDDIO2CCSR_ANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO2CCSR_ANSRC SYSCFG_VDDIO2CCSR_ANSRC_Msk
#define SYSCFG_VDDIO2CCSR_ANSRC_0 (0x1UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO2CCSR_ANSRC_1 (0x2UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO2CCSR_ANSRC_2 (0x4UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO2CCSR_ANSRC_3 (0x8UL << SYSCFG_VDDIO2CCSR_ANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO2CCSR_APSRC_Pos (4U)
#define SYSCFG_VDDIO2CCSR_APSRC_Msk (0xFUL << SYSCFG_VDDIO2CCSR_APSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO2CCSR_APSRC SYSCFG_VDDIO2CCSR_APSRC_Msk
#define SYSCFG_VDDIO2CCSR_APSRC_0 (0x1UL << SYSCFG_VDDIO2CCSR_APSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO2CCSR_APSRC_1 (0x2UL << SYSCFG_VDDIO2CCSR_APSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO2CCSR_APSRC_2 (0x4UL << SYSCFG_VDDIO2CCSR_APSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO2CCSR_APSRC_3 (0x8UL << SYSCFG_VDDIO2CCSR_APSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO2CCSR_READY_Pos (8U)
#define SYSCFG_VDDIO2CCSR_READY_Msk (0x1UL << SYSCFG_VDDIO2CCSR_READY_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO2CCSR_READY SYSCFG_VDDIO2CCSR_READY_Msk /*!< Provides the compensation cell status of I/Os supplied by VDDIO2 */
/****************** Bit definition for SYSCFG_VDDIO3CCCR register **************/
#define SYSCFG_VDDIO3CCCR_RANSRC_Pos (0U)
#define SYSCFG_VDDIO3CCCR_RANSRC_Msk (0xFUL << SYSCFG_VDDIO3CCCR_RANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO3CCCR_RANSRC SYSCFG_VDDIO3CCCR_RANSRC_Msk /*!< I/O compensation code for NMOS transistors */
#define SYSCFG_VDDIO3CCCR_RANSRC_0 (0x1UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO3CCCR_RANSRC_1 (0x2UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO3CCCR_RANSRC_2 (0x4UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO3CCCR_RANSRC_3 (0x8UL << SYSCFG_VDDIO3CCCR_RANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO3CCCR_RAPSRC_Pos (4U)
#define SYSCFG_VDDIO3CCCR_RAPSRC_Msk (0xFUL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO3CCCR_RAPSRC SYSCFG_VDDIO3CCCR_RAPSRC_Msk /*!< I/O compensation code for PMOS transistors */
#define SYSCFG_VDDIO3CCCR_RAPSRC_0 (0x1UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO3CCCR_RAPSRC_1 (0x2UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO3CCCR_RAPSRC_2 (0x4UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO3CCCR_RAPSRC_3 (0x8UL << SYSCFG_VDDIO3CCCR_RAPSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO3CCCR_EN_Pos (8U)
#define SYSCFG_VDDIO3CCCR_EN_Msk (0x1UL << SYSCFG_VDDIO3CCCR_EN_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO3CCCR_EN SYSCFG_VDDIO3CCCR_EN_Msk /*!< Enables the compensation cell of I/Os supplied by VDDIO3 */
#define SYSCFG_VDDIO3CCCR_CS_Pos (9U)
#define SYSCFG_VDDIO3CCCR_CS_Msk (0x1UL << SYSCFG_VDDIO3CCCR_CS_Pos) /*!< 0x00000200 */
#define SYSCFG_VDDIO3CCCR_CS SYSCFG_VDDIO3CCCR_CS_Msk /*!< Code selection for the compensation cell of I/Os supplied by VDDIO3 */
/****************** Bit definition for SYSCFG_VDDIO3CCSR register **************/
#define SYSCFG_VDDIO3CCSR_ANSRC_Pos (0U)
#define SYSCFG_VDDIO3CCSR_ANSRC_Msk (0xFUL << SYSCFG_VDDIO3CCSR_ANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO3CCSR_ANSRC SYSCFG_VDDIO3CCSR_ANSRC_Msk
#define SYSCFG_VDDIO3CCSR_ANSRC_0 (0x1UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO3CCSR_ANSRC_1 (0x2UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO3CCSR_ANSRC_2 (0x4UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO3CCSR_ANSRC_3 (0x8UL << SYSCFG_VDDIO3CCSR_ANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO3CCSR_APSRC_Pos (4U)
#define SYSCFG_VDDIO3CCSR_APSRC_Msk (0xFUL << SYSCFG_VDDIO3CCSR_APSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO3CCSR_APSRC SYSCFG_VDDIO3CCSR_APSRC_Msk
#define SYSCFG_VDDIO3CCSR_APSRC_0 (0x1UL << SYSCFG_VDDIO3CCSR_APSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO3CCSR_APSRC_1 (0x2UL << SYSCFG_VDDIO3CCSR_APSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO3CCSR_APSRC_2 (0x4UL << SYSCFG_VDDIO3CCSR_APSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO3CCSR_APSRC_3 (0x8UL << SYSCFG_VDDIO3CCSR_APSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO3CCSR_READY_Pos (8U)
#define SYSCFG_VDDIO3CCSR_READY_Msk (0x1UL << SYSCFG_VDDIO3CCSR_READY_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO3CCSR_READY SYSCFG_VDDIO3CCSR_READY_Msk /*!< Provides the compensation cell status of I/Os supplied by VDDIO3 */
/****************** Bit definition for SYSCFG_VDDIO4CCCR register **************/
#define SYSCFG_VDDIO4CCCR_RANSRC_Pos (0U)
#define SYSCFG_VDDIO4CCCR_RANSRC_Msk (0xFUL << SYSCFG_VDDIO4CCCR_RANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO4CCCR_RANSRC SYSCFG_VDDIO4CCCR_RANSRC_Msk /*!< I/O compensation code for NMOS transistors */
#define SYSCFG_VDDIO4CCCR_RANSRC_0 (0x1UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO4CCCR_RANSRC_1 (0x2UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO4CCCR_RANSRC_2 (0x4UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO4CCCR_RANSRC_3 (0x8UL << SYSCFG_VDDIO4CCCR_RANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO4CCCR_RAPSRC_Pos (4U)
#define SYSCFG_VDDIO4CCCR_RAPSRC_Msk (0xFUL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO4CCCR_RAPSRC SYSCFG_VDDIO4CCCR_RAPSRC_Msk /*!< I/O compensation code for PMOS transistors */
#define SYSCFG_VDDIO4CCCR_RAPSRC_0 (0x1UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO4CCCR_RAPSRC_1 (0x2UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO4CCCR_RAPSRC_2 (0x4UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO4CCCR_RAPSRC_3 (0x8UL << SYSCFG_VDDIO4CCCR_RAPSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO4CCCR_EN_Pos (8U)
#define SYSCFG_VDDIO4CCCR_EN_Msk (0x1UL << SYSCFG_VDDIO4CCCR_EN_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO4CCCR_EN SYSCFG_VDDIO4CCCR_EN_Msk /*!< Enables the compensation cell of I/Os supplied by VDDIO4 */
#define SYSCFG_VDDIO4CCCR_CS_Pos (9U)
#define SYSCFG_VDDIO4CCCR_CS_Msk (0x1UL << SYSCFG_VDDIO4CCCR_CS_Pos) /*!< 0x00000200 */
#define SYSCFG_VDDIO4CCCR_CS SYSCFG_VDDIO4CCCR_CS_Msk /*!< Code selection for the compensation cell of I/Os supplied by VDDIO4 */
/****************** Bit definition for SYSCFG_VDDIO4CCSR register **************/
#define SYSCFG_VDDIO4CCSR_ANSRC_Pos (0U)
#define SYSCFG_VDDIO4CCSR_ANSRC_Msk (0xFUL << SYSCFG_VDDIO4CCSR_ANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO4CCSR_ANSRC SYSCFG_VDDIO4CCSR_ANSRC_Msk
#define SYSCFG_VDDIO4CCSR_ANSRC_0 (0x1UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO4CCSR_ANSRC_1 (0x2UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO4CCSR_ANSRC_2 (0x4UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO4CCSR_ANSRC_3 (0x8UL << SYSCFG_VDDIO4CCSR_ANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO4CCSR_APSRC_Pos (4U)
#define SYSCFG_VDDIO4CCSR_APSRC_Msk (0xFUL << SYSCFG_VDDIO4CCSR_APSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO4CCSR_APSRC SYSCFG_VDDIO4CCSR_APSRC_Msk
#define SYSCFG_VDDIO4CCSR_APSRC_0 (0x1UL << SYSCFG_VDDIO4CCSR_APSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO4CCSR_APSRC_1 (0x2UL << SYSCFG_VDDIO4CCSR_APSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO4CCSR_APSRC_2 (0x4UL << SYSCFG_VDDIO4CCSR_APSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO4CCSR_APSRC_3 (0x8UL << SYSCFG_VDDIO4CCSR_APSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO4CCSR_READY_Pos (8U)
#define SYSCFG_VDDIO4CCSR_READY_Msk (0x1UL << SYSCFG_VDDIO4CCSR_READY_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO4CCSR_READY SYSCFG_VDDIO4CCSR_READY_Msk /*!< Provides the compensation cell status of I/Os supplied by VDDIO4 */
/****************** Bit definition for SYSCFG_VDDIO5CCCR register **************/
#define SYSCFG_VDDIO5CCCR_RANSRC_Pos (0U)
#define SYSCFG_VDDIO5CCCR_RANSRC_Msk (0xFUL << SYSCFG_VDDIO5CCCR_RANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO5CCCR_RANSRC SYSCFG_VDDIO5CCCR_RANSRC_Msk /*!< I/O compensation code for NMOS transistors */
#define SYSCFG_VDDIO5CCCR_RANSRC_0 (0x1UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO5CCCR_RANSRC_1 (0x2UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO5CCCR_RANSRC_2 (0x4UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO5CCCR_RANSRC_3 (0x8UL << SYSCFG_VDDIO5CCCR_RANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO5CCCR_RAPSRC_Pos (4U)
#define SYSCFG_VDDIO5CCCR_RAPSRC_Msk (0xFUL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO5CCCR_RAPSRC SYSCFG_VDDIO5CCCR_RAPSRC_Msk /*!< I/O compensation code for PMOS transistors */
#define SYSCFG_VDDIO5CCCR_RAPSRC_0 (0x1UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO5CCCR_RAPSRC_1 (0x2UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO5CCCR_RAPSRC_2 (0x4UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO5CCCR_RAPSRC_3 (0x8UL << SYSCFG_VDDIO5CCCR_RAPSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO5CCCR_EN_Pos (8U)
#define SYSCFG_VDDIO5CCCR_EN_Msk (0x1UL << SYSCFG_VDDIO5CCCR_EN_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO5CCCR_EN SYSCFG_VDDIO5CCCR_EN_Msk /*!< Enables the compensation cell of I/Os supplied by VDDIO5 */
#define SYSCFG_VDDIO5CCCR_CS_Pos (9U)
#define SYSCFG_VDDIO5CCCR_CS_Msk (0x1UL << SYSCFG_VDDIO5CCCR_CS_Pos) /*!< 0x00000200 */
#define SYSCFG_VDDIO5CCCR_CS SYSCFG_VDDIO5CCCR_CS_Msk /*!< Code selection for the compensation cell of I/Os supplied by VDDIO5 */
/****************** Bit definition for SYSCFG_VDDIO5CCSR register **************/
#define SYSCFG_VDDIO5CCSR_ANSRC_Pos (0U)
#define SYSCFG_VDDIO5CCSR_ANSRC_Msk (0xFUL << SYSCFG_VDDIO5CCSR_ANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDIO5CCSR_ANSRC SYSCFG_VDDIO5CCSR_ANSRC_Msk
#define SYSCFG_VDDIO5CCSR_ANSRC_0 (0x1UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDIO5CCSR_ANSRC_1 (0x2UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDIO5CCSR_ANSRC_2 (0x4UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDIO5CCSR_ANSRC_3 (0x8UL << SYSCFG_VDDIO5CCSR_ANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDIO5CCSR_APSRC_Pos (4U)
#define SYSCFG_VDDIO5CCSR_APSRC_Msk (0xFUL << SYSCFG_VDDIO5CCSR_APSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDIO5CCSR_APSRC SYSCFG_VDDIO5CCSR_APSRC_Msk
#define SYSCFG_VDDIO5CCSR_APSRC_0 (0x1UL << SYSCFG_VDDIO5CCSR_APSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDIO5CCSR_APSRC_1 (0x2UL << SYSCFG_VDDIO5CCSR_APSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDIO5CCSR_APSRC_2 (0x4UL << SYSCFG_VDDIO5CCSR_APSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDIO5CCSR_APSRC_3 (0x8UL << SYSCFG_VDDIO5CCSR_APSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDIO5CCSR_READY_Pos (8U)
#define SYSCFG_VDDIO5CCSR_READY_Msk (0x1UL << SYSCFG_VDDIO5CCSR_READY_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDIO5CCSR_READY SYSCFG_VDDIO5CCSR_READY_Msk /*!< Provides the compensation cell status of I/Os supplied by VDDIO5 */
/****************** Bit definition for SYSCFG_VDDCCCR register **************/
#define SYSCFG_VDDCCCR_RANSRC_Pos (0U)
#define SYSCFG_VDDCCCR_RANSRC_Msk (0xFUL << SYSCFG_VDDCCCR_RANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDCCCR_RANSRC SYSCFG_VDDCCCR_RANSRC_Msk /*!< I/O compensation code for NMOS transistors */
#define SYSCFG_VDDCCCR_RANSRC_0 (0x1UL << SYSCFG_VDDCCCR_RANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDCCCR_RANSRC_1 (0x2UL << SYSCFG_VDDCCCR_RANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDCCCR_RANSRC_2 (0x4UL << SYSCFG_VDDCCCR_RANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDCCCR_RANSRC_3 (0x8UL << SYSCFG_VDDCCCR_RANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDCCCR_RAPSRC_Pos (4U)
#define SYSCFG_VDDCCCR_RAPSRC_Msk (0xFUL << SYSCFG_VDDCCCR_RAPSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDCCCR_RAPSRC SYSCFG_VDDCCCR_RAPSRC_Msk /*!< I/O compensation code for PMOS transistors */
#define SYSCFG_VDDCCCR_RAPSRC_0 (0x1UL << SYSCFG_VDDCCCR_RAPSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDCCCR_RAPSRC_1 (0x2UL << SYSCFG_VDDCCCR_RAPSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDCCCR_RAPSRC_2 (0x4UL << SYSCFG_VDDCCCR_RAPSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDCCCR_RAPSRC_3 (0x8UL << SYSCFG_VDDCCCR_RAPSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDCCCR_EN_Pos (8U)
#define SYSCFG_VDDCCCR_EN_Msk (0x1UL << SYSCFG_VDDCCCR_EN_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDCCCR_EN SYSCFG_VDDCCCR_EN_Msk /*!< Enables the compensation cell of I/Os supplied by VDD */
#define SYSCFG_VDDCCCR_CS_Pos (9U)
#define SYSCFG_VDDCCCR_CS_Msk (0x1UL << SYSCFG_VDDCCCR_CS_Pos) /*!< 0x00000200 */
#define SYSCFG_VDDCCCR_CS SYSCFG_VDDCCCR_CS_Msk /*!< Code selection for the compensation cell of I/Os supplied by VDD */
/****************** Bit definition for SYSCFG_VDDCCSR register **************/
#define SYSCFG_VDDCCSR_ANSRC_Pos (0U)
#define SYSCFG_VDDCCSR_ANSRC_Msk (0xFUL << SYSCFG_VDDCCSR_ANSRC_Pos) /*!< 0x0000000F */
#define SYSCFG_VDDCCSR_ANSRC SYSCFG_VDDCCSR_ANSRC_Msk
#define SYSCFG_VDDCCSR_ANSRC_0 (0x1UL << SYSCFG_VDDCCSR_ANSRC_Pos) /*!< 0x00000001 */
#define SYSCFG_VDDCCSR_ANSRC_1 (0x2UL << SYSCFG_VDDCCSR_ANSRC_Pos) /*!< 0x00000002 */
#define SYSCFG_VDDCCSR_ANSRC_2 (0x4UL << SYSCFG_VDDCCSR_ANSRC_Pos) /*!< 0x00000004 */
#define SYSCFG_VDDCCSR_ANSRC_3 (0x8UL << SYSCFG_VDDCCSR_ANSRC_Pos) /*!< 0x00000008 */
#define SYSCFG_VDDCCSR_APSRC_Pos (4U)
#define SYSCFG_VDDCCSR_APSRC_Msk (0xFUL << SYSCFG_VDDCCSR_APSRC_Pos) /*!< 0x000000F0 */
#define SYSCFG_VDDCCSR_APSRC SYSCFG_VDDCCSR_APSRC_Msk
#define SYSCFG_VDDCCSR_APSRC_0 (0x1UL << SYSCFG_VDDCCSR_APSRC_Pos) /*!< 0x00000010 */
#define SYSCFG_VDDCCSR_APSRC_1 (0x2UL << SYSCFG_VDDCCSR_APSRC_Pos) /*!< 0x00000020 */
#define SYSCFG_VDDCCSR_APSRC_2 (0x4UL << SYSCFG_VDDCCSR_APSRC_Pos) /*!< 0x00000040 */
#define SYSCFG_VDDCCSR_APSRC_3 (0x8UL << SYSCFG_VDDCCSR_APSRC_Pos) /*!< 0x00000080 */
#define SYSCFG_VDDCCSR_READY_Pos (8U)
#define SYSCFG_VDDCCSR_READY_Msk (0x1UL << SYSCFG_VDDCCSR_READY_Pos) /*!< 0x00000100 */
#define SYSCFG_VDDCCSR_READY SYSCFG_VDDCCSR_READY_Msk /*!< Provides the compensation cell status of I/Os supplied by VDD */
/****************** Bit definition for SYSCFG_CBR register **************/
#define SYSCFG_CBR_CM55L_Pos (0U)
#define SYSCFG_CBR_CM55L_Msk (0x1UL << SYSCFG_CBR_CM55L_Pos) /*!< 0x00000001 */
#define SYSCFG_CBR_CM55L SYSCFG_CBR_CM55L_Msk /*!< CM55 lockup lock enable */
#define SYSCFG_CBR_PVDL_LOCK_Pos (2U)
#define SYSCFG_CBR_PVDL_LOCK_Msk (0x1UL << SYSCFG_CBR_PVDL_LOCK_Pos) /*!< 0x00000004 */
#define SYSCFG_CBR_PVDL_LOCK SYSCFG_CBR_PVDL_LOCK_Msk /*!< PVD lock enable */
#define SYSCFG_CBR_BKPRAML_Pos (8U)
#define SYSCFG_CBR_BKPRAML_Msk (0x1UL << SYSCFG_CBR_BKPRAML_Pos) /*!< 0x00000100 */
#define SYSCFG_CBR_BKPRAML SYSCFG_CBR_BKPRAML_Msk /*!< Backup SRAM double ECC error lock */
#define SYSCFG_CBR_CM55CACHEL_Pos (9U)
#define SYSCFG_CBR_CM55CACHEL_Msk (0x1UL << SYSCFG_CBR_CM55CACHEL_Pos) /*!< 0x00000200 */
#define SYSCFG_CBR_CM55CACHEL SYSCFG_CBR_CM55CACHEL_Msk /*!< CM55 cache double ECC error lock */
#define SYSCFG_CBR_CM55TCML_Pos (10U)
#define SYSCFG_CBR_CM55TCML_Msk (0x1UL << SYSCFG_CBR_CM55TCML_Pos) /*!< 0x00000400 */
#define SYSCFG_CBR_CM55TCML SYSCFG_CBR_CM55TCML_Msk /*!< CM55 TCM double ECC error lock */
/****************** Bit definition for SYSCFG_SEC_AIDCR register **************/
#define SYSCFG_SEC_AIDCR_DMACID_SEC_Pos (0U)
#define SYSCFG_SEC_AIDCR_DMACID_SEC_Msk (0x7UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos) /*!< 0x0000000F */
#define SYSCFG_SEC_AIDCR_DMACID_SEC SYSCFG_SEC_AIDCR_DMACID_SEC_Msk /* Secure OS allocates specific CID to DMA channel through these bits */
#define SYSCFG_SEC_AIDCR_DMACID_SEC_0 (0x1UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos) /*!< 0x00000001 */
#define SYSCFG_SEC_AIDCR_DMACID_SEC_1 (0x2UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos) /*!< 0x00000002 */
#define SYSCFG_SEC_AIDCR_DMACID_SEC_2 (0x4UL << SYSCFG_SEC_AIDCR_DMACID_SEC_Pos) /*!< 0x00000004 */
/****************** Bit definition for SYSCFG_FMC_RETIMECR register **************/
#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos (0U)
#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Pos) /*!< 0x00000001 */
#define SYSCFG_FMC_RETIMECR_CFG_RETIME_RX SYSCFG_FMC_RETIMECR_CFG_RETIME_RX_Msk /*!< Retiming on Rx path */
#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos (1U)
#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk (0x1UL << SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Pos) /*!< 0x00000002 */
#define SYSCFG_FMC_RETIMECR_CFG_RETIME_TX SYSCFG_FMC_RETIMECR_CFG_RETIME_TX_Msk /*!< Retiming on Tx path */
#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos (2U)
#define SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk (0x1UL << SYSCFG_FMC_RETIMECR_SDFBCLK_180_Pos) /*!< 0x00000004 */
#define SYSCFG_FMC_RETIMECR_SDFBCLK_180 SYSCFG_FMC_RETIMECR_SDFBCLK_180_Msk /*!< Delay on feedback clock */
/****************** Bit definition for SYSCFG_NPU_ICNCR register **************/
#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos (0U)
#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk (0x1UL << SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Pos) /*!< 0x00000001 */
#define SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE SYSCFG_NPU_ICNCR_INTERLEAVING_ACTIVE_Msk /*!< Control interleaving on NPU RAMs */
/****************** Bit definition for SYSCFG_BOOTSR register **************/
#define SYSCFG_BOOTSR_BOOT0_Pos (0U)
#define SYSCFG_BOOTSR_BOOT0_Msk (0x1UL << SYSCFG_BOOTSR_BOOT0_Pos) /*!< 0x00000001 */
#define SYSCFG_BOOTSR_BOOT0 SYSCFG_BOOTSR_BOOT0_Msk /*!< BOOT0 pin value */
#define SYSCFG_BOOTSR_BOOT1_Pos (1U)
#define SYSCFG_BOOTSR_BOOT1_Msk (0x1UL << SYSCFG_BOOTSR_BOOT1_Pos) /*!< 0x00000002 */
#define SYSCFG_BOOTSR_BOOT1 SYSCFG_BOOTSR_BOOT1_Msk /*!< BOOT1 pin value */
/****************** Bit definition for SYSCFG_AHBWP_ERROR_SR register **************/
#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos (0U)
#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk (0xFFFFFFFFUL << SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Pos) /*!< 0xFFFFFFFF */
#define SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR SYSCFG_AHBWP_ERROR_SR_PAHB_ERROR_ADDR_Msk /*!< Reports address of the first error in P-AHB write-posting buffer */
/****************** Bit definition for SYSCFG_SECPRIV_AIDCR register **************/
#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos (0U)
#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk (0x7UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos) /*!< 0x0000000F */
#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Msk /* Non-Secure OS allocates specific CID to DMA channel through these bits */
#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_0 (0x1UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos) /*!< 0x00000001 */
#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_1 (0x2UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos) /*!< 0x00000002 */
#define SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_2 (0x4UL << SYSCFG_SECPRIV_AIDCR_DMACID_NONSEC_Pos) /*!< 0x00000004 */
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_TAMP4E_Pos (3U)
#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */
#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk
#define TAMP_CR1_TAMP5E_Pos (4U)
#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */
#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk
#define TAMP_CR1_TAMP6E_Pos (5U)
#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */
#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk
#define TAMP_CR1_TAMP7E_Pos (6U)
#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */
#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk
#define TAMP_CR1_ITAMP1E_Pos (16U)
#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */
#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk
#define TAMP_CR1_ITAMP2E_Pos (17U)
#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */
#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
#define TAMP_CR1_ITAMP7E_Pos (22U)
#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */
#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk
#define TAMP_CR1_ITAMP8E_Pos (23U)
#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */
#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk
#define TAMP_CR1_ITAMP9E_Pos (24U)
#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */
#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk
#define TAMP_CR1_ITAMP11E_Pos (26U)
#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */
#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1POM_Pos (0U)
#define TAMP_CR2_TAMP1POM_Msk (0x1UL << TAMP_CR2_TAMP1POM_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1POM TAMP_CR2_TAMP1POM_Msk
#define TAMP_CR2_TAMP2POM_Pos (1U)
#define TAMP_CR2_TAMP2POM_Msk (0x1UL << TAMP_CR2_TAMP2POM_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2POM TAMP_CR2_TAMP2POM_Msk
#define TAMP_CR2_TAMP3POM_Pos (2U)
#define TAMP_CR2_TAMP3POM_Msk (0x1UL << TAMP_CR2_TAMP3POM_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3POM TAMP_CR2_TAMP3POM_Msk
#define TAMP_CR2_TAMP4POM_Pos (3U)
#define TAMP_CR2_TAMP4POM_Msk (0x1UL << TAMP_CR2_TAMP4POM_Pos) /*!< 0x00000008 */
#define TAMP_CR2_TAMP4POM TAMP_CR2_TAMP4POM_Msk
#define TAMP_CR2_TAMP5POM_Pos (4U)
#define TAMP_CR2_TAMP5POM_Msk (0x1UL << TAMP_CR2_TAMP5POM_Pos) /*!< 0x00000010 */
#define TAMP_CR2_TAMP5POM TAMP_CR2_TAMP5POM_Msk
#define TAMP_CR2_TAMP6POM_Pos (5U)
#define TAMP_CR2_TAMP6POM_Msk (0x1UL << TAMP_CR2_TAMP6POM_Pos) /*!< 0x00000020 */
#define TAMP_CR2_TAMP6POM TAMP_CR2_TAMP6POM_Msk
#define TAMP_CR2_TAMP7POM_Pos (6U)
#define TAMP_CR2_TAMP7POM_Msk (0x1UL << TAMP_CR2_TAMP7POM_Pos) /*!< 0x00000040 */
#define TAMP_CR2_TAMP7POM TAMP_CR2_TAMP7POM_Msk
#define TAMP_CR2_TAMP1MSK_Pos (16U)
#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
#define TAMP_CR2_TAMP2MSK_Pos (17U)
#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
#define TAMP_CR2_TAMP3MSK_Pos (18U)
#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
#define TAMP_CR2_BKBLOCK_Pos (22U)
#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */
#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk
#define TAMP_CR2_BKERASE_Pos (23U)
#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */
#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
#define TAMP_CR2_TAMP4TRG_Pos (27U)
#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk
#define TAMP_CR2_TAMP5TRG_Pos (28U)
#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk
#define TAMP_CR2_TAMP6TRG_Pos (29U)
#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk
#define TAMP_CR2_TAMP7TRG_Pos (30U)
#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk
/******************** Bits definition for TAMP_CR3 register *****************/
#define TAMP_CR3_ITAMP1POM_Pos (0U)
#define TAMP_CR3_ITAMP1POM_Msk (0x1UL << TAMP_CR3_ITAMP1POM_Pos) /*!< 0x00000001 */
#define TAMP_CR3_ITAMP1POM TAMP_CR3_ITAMP1POM_Msk
#define TAMP_CR3_ITAMP2POM_Pos (1U)
#define TAMP_CR3_ITAMP2POM_Msk (0x1UL << TAMP_CR3_ITAMP2POM_Pos) /*!< 0x00000002 */
#define TAMP_CR3_ITAMP2POM TAMP_CR3_ITAMP2POM_Msk
#define TAMP_CR3_ITAMP3POM_Pos (2U)
#define TAMP_CR3_ITAMP3POM_Msk (0x1UL << TAMP_CR3_ITAMP3POM_Pos) /*!< 0x00000004 */
#define TAMP_CR3_ITAMP3POM TAMP_CR3_ITAMP3POM_Msk
#define TAMP_CR3_ITAMP4POM_Pos (3U)
#define TAMP_CR3_ITAMP4POM_Msk (0x1UL << TAMP_CR3_ITAMP4POM_Pos) /*!< 0x00000008 */
#define TAMP_CR3_ITAMP4POM TAMP_CR3_ITAMP4POM_Msk
#define TAMP_CR3_ITAMP5POM_Pos (4U)
#define TAMP_CR3_ITAMP5POM_Msk (0x1UL << TAMP_CR3_ITAMP5POM_Pos) /*!< 0x00000010 */
#define TAMP_CR3_ITAMP5POM TAMP_CR3_ITAMP5POM_Msk
#define TAMP_CR3_ITAMP6POM_Pos (5U)
#define TAMP_CR3_ITAMP6POM_Msk (0x1UL << TAMP_CR3_ITAMP6POM_Pos) /*!< 0x00000020 */
#define TAMP_CR3_ITAMP6POM TAMP_CR3_ITAMP6POM_Msk
#define TAMP_CR3_ITAMP7POM_Pos (6U)
#define TAMP_CR3_ITAMP7POM_Msk (0x1UL << TAMP_CR3_ITAMP7POM_Pos) /*!< 0x00000040 */
#define TAMP_CR3_ITAMP7POM TAMP_CR3_ITAMP7POM_Msk
#define TAMP_CR3_ITAMP8POM_Pos (7U)
#define TAMP_CR3_ITAMP8POM_Msk (0x1UL << TAMP_CR3_ITAMP8POM_Pos) /*!< 0x00000080 */
#define TAMP_CR3_ITAMP8POM TAMP_CR3_ITAMP8POM_Msk
#define TAMP_CR3_ITAMP9POM_Pos (8U)
#define TAMP_CR3_ITAMP9POM_Msk (0x1UL << TAMP_CR3_ITAMP9POM_Pos) /*!< 0x00000100 */
#define TAMP_CR3_ITAMP9POM TAMP_CR3_ITAMP9POM_Msk
#define TAMP_CR3_ITAMP11POM_Pos (10U)
#define TAMP_CR3_ITAMP11POM_Msk (0x1UL << TAMP_CR3_ITAMP11POM_Pos) /*!< 0x00000400 */
#define TAMP_CR3_ITAMP11POM TAMP_CR3_ITAMP11POM_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */
#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */
#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */
#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */
#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_ATCR1 register ***************/
#define TAMP_ATCR1_TAMP1AM_Pos (0U)
#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
#define TAMP_ATCR1_TAMP2AM_Pos (1U)
#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
#define TAMP_ATCR1_TAMP3AM_Pos (2U)
#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
#define TAMP_ATCR1_TAMP4AM_Pos (3U)
#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */
#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk
#define TAMP_ATCR1_TAMP5AM_Pos (4U)
#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */
#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk
#define TAMP_ATCR1_TAMP6AM_Pos (5U)
#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */
#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk
#define TAMP_ATCR1_TAMP7AM_Pos (6U)
#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */
#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk
#define TAMP_ATCR1_ATOSEL1_Pos (8U)
#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
#define TAMP_ATCR1_ATOSEL2_Pos (10U)
#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
#define TAMP_ATCR1_ATOSEL3_Pos (12U)
#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
#define TAMP_ATCR1_ATOSEL4_Pos (14U)
#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
#define TAMP_ATCR1_ATCKSEL_Pos (16U)
#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */
#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */
#define TAMP_ATCR1_ATPER_Pos (24U)
#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */
#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */
#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */
#define TAMP_ATCR1_ATOSHARE_Pos (30U)
#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
#define TAMP_ATCR1_FLTEN_Pos (31U)
#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
/******************** Bits definition for TAMP_ATSEEDR register ******************/
#define TAMP_ATSEEDR_SEED_Pos (0U)
#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
/******************** Bits definition for TAMP_ATOR register ******************/
#define TAMP_ATOR_PRNG_Pos (0U)
#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */
#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk
#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */
#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */
#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */
#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */
#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */
#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */
#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */
#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */
#define TAMP_ATOR_SEEDF_Pos (14U)
#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */
#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk
#define TAMP_ATOR_INITS_Pos (15U)
#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */
#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
/******************** Bits definition for TAMP_ATCR2 register ***************/
#define TAMP_ATCR2_ATOSEL1_Pos (8U)
#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */
#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk
#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */
#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */
#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */
#define TAMP_ATCR2_ATOSEL2_Pos (11U)
#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */
#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk
#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */
#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */
#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */
#define TAMP_ATCR2_ATOSEL3_Pos (14U)
#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */
#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk
#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */
#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */
#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */
#define TAMP_ATCR2_ATOSEL4_Pos (17U)
#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */
#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk
#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */
#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */
#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */
#define TAMP_ATCR2_ATOSEL5_Pos (20U)
#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */
#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk
#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */
#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */
#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */
#define TAMP_ATCR2_ATOSEL6_Pos (23U)
#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */
#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk
#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */
#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */
#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */
#define TAMP_ATCR2_ATOSEL7_Pos (26U)
#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */
#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk
#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */
#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */
#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */
/******************** Bits definition for TAMP_SECCFGR register *************/
#define TAMP_SECCFGR_BKPRWSEC_Pos (0U)
#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */
#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk
#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */
#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */
#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */
#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */
#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */
#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */
#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */
#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */
#define TAMP_SECCFGR_CNT1SEC_Pos (15U)
#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */
#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk
#define TAMP_SECCFGR_BKPWSEC_Pos (16U)
#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */
#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk
#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */
#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */
#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */
#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */
#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */
#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */
#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */
#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */
#define TAMP_SECCFGR_BHKLOCK_Pos (30U)
#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */
#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk
#define TAMP_SECCFGR_TAMPSEC_Pos (31U)
#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */
#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk
/******************** Bits definition for TAMP_PRIVCFGR register ************/
#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U)
#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */
#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk
#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U)
#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */
#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk
#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U)
#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */
#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk
#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U)
#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */
#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_TAMP4IE_Pos (3U)
#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */
#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk
#define TAMP_IER_TAMP5IE_Pos (4U)
#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */
#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk
#define TAMP_IER_TAMP6IE_Pos (5U)
#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */
#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk
#define TAMP_IER_TAMP7IE_Pos (6U)
#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */
#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk
#define TAMP_IER_ITAMP1IE_Pos (16U)
#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */
#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk
#define TAMP_IER_ITAMP2IE_Pos (17U)
#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */
#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
#define TAMP_IER_ITAMP7IE_Pos (22U)
#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */
#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk
#define TAMP_IER_ITAMP8IE_Pos (23U)
#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */
#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk
#define TAMP_IER_ITAMP9IE_Pos (24U)
#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */
#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk
#define TAMP_IER_ITAMP11IE_Pos (26U)
#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */
#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk
/******************** Bits definition for TAMP_SR register *****************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_TAMP4F_Pos (3U)
#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */
#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk
#define TAMP_SR_TAMP5F_Pos (4U)
#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */
#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk
#define TAMP_SR_TAMP6F_Pos (5U)
#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */
#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk
#define TAMP_SR_TAMP7F_Pos (6U)
#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */
#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk
#define TAMP_SR_ITAMP1F_Pos (16U)
#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */
#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk
#define TAMP_SR_ITAMP2F_Pos (17U)
#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */
#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
#define TAMP_SR_ITAMP7F_Pos (22U)
#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */
#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk
#define TAMP_SR_ITAMP8F_Pos (23U)
#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */
#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk
#define TAMP_SR_ITAMP9F_Pos (24U)
#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */
#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk
#define TAMP_SR_ITAMP11F_Pos (26U)
#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */
#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_TAMP4MF_Pos (3U)
#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */
#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk
#define TAMP_MISR_TAMP5MF_Pos (4U)
#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */
#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk
#define TAMP_MISR_TAMP6MF_Pos (5U)
#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */
#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk
#define TAMP_MISR_TAMP7MF_Pos (6U)
#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */
#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk
#define TAMP_MISR_ITAMP1MF_Pos (16U)
#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk
#define TAMP_MISR_ITAMP2MF_Pos (17U)
#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
#define TAMP_MISR_ITAMP7MF_Pos (22U)
#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */
#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk
#define TAMP_MISR_ITAMP8MF_Pos (23U)
#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */
#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk
#define TAMP_MISR_ITAMP9MF_Pos (24U)
#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */
#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk
#define TAMP_MISR_ITAMP11MF_Pos (26U)
#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */
#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk
/******************** Bits definition for TAMP_SMISR register ************ *****/
#define TAMP_SMISR_TAMP1MF_Pos (0U)
#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk
#define TAMP_SMISR_TAMP2MF_Pos (1U)
#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk
#define TAMP_SMISR_TAMP3MF_Pos (2U)
#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk
#define TAMP_SMISR_TAMP4MF_Pos (3U)
#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */
#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk
#define TAMP_SMISR_TAMP5MF_Pos (4U)
#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */
#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk
#define TAMP_SMISR_TAMP6MF_Pos (5U)
#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */
#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk
#define TAMP_SMISR_TAMP7MF_Pos (6U)
#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */
#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk
#define TAMP_SMISR_ITAMP1MF_Pos (16U)
#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk
#define TAMP_SMISR_ITAMP2MF_Pos (17U)
#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk
#define TAMP_SMISR_ITAMP3MF_Pos (18U)
#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk
#define TAMP_SMISR_ITAMP4MF_Pos (19U)
#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk
#define TAMP_SMISR_ITAMP5MF_Pos (20U)
#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk
#define TAMP_SMISR_ITAMP6MF_Pos (21U)
#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk
#define TAMP_SMISR_ITAMP7MF_Pos (22U)
#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */
#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk
#define TAMP_SMISR_ITAMP8MF_Pos (23U)
#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */
#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk
#define TAMP_SMISR_ITAMP9MF_Pos (24U)
#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */
#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk
#define TAMP_SMISR_ITAMP11MF_Pos (26U)
#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */
#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CTAMP4F_Pos (3U)
#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */
#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk
#define TAMP_SCR_CTAMP5F_Pos (4U)
#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */
#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk
#define TAMP_SCR_CTAMP6F_Pos (5U)
#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */
#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk
#define TAMP_SCR_CTAMP7F_Pos (6U)
#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */
#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk
#define TAMP_SCR_CTAMP8F_Pos (7U)
#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */
#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk
#define TAMP_SCR_CITAMP1F_Pos (16U)
#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */
#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk
#define TAMP_SCR_CITAMP2F_Pos (17U)
#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */
#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
#define TAMP_SCR_CITAMP7F_Pos (22U)
#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */
#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk
#define TAMP_SCR_CITAMP8F_Pos (23U)
#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */
#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
#define TAMP_SCR_CITAMP9F_Pos (24U)
#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk
#define TAMP_SCR_CITAMP11F_Pos (26U)
#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */
#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk
/******************** Bits definition for TAMP_COUNT1R register ***************/
#define TAMP_COUNT1R_COUNT_Pos (0U)
#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */
#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk
/******************** Bits definition for TAMP_OR register ***************/
#define TAMP_OR_VCOREMEN_Pos (0U)
#define TAMP_OR_VCOREMEN_Msk (0x1UL << TAMP_OR_VCOREMEN_Pos) /*!< 0x00000001 */
#define TAMP_OR_VCOREMEN TAMP_OR_VCOREMEN_Msk
/******************** Bits definition for TAMP_RPCFGR register ***************/
#define TAMP_RPCFGR_RPCFG0_Pos (0U)
#define TAMP_RPCFGR_RPCFG0_Msk (0x1UL << TAMP_RPCFGR_RPCFG0_Pos) /*!< 0x00000001 */
#define TAMP_RPCFGR_RPCFG0 TAMP_RPCFGR_RPCFG0_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ****************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ****************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ****************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ****************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ****************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ****************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ****************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ****************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ****************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************** Bits definition for TAMP_BKP16R register ***************/
#define TAMP_BKP16R_Pos (0U)
#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP16R TAMP_BKP16R_Msk
/******************** Bits definition for TAMP_BKP17R register ***************/
#define TAMP_BKP17R_Pos (0U)
#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP17R TAMP_BKP17R_Msk
/******************** Bits definition for TAMP_BKP18R register ***************/
#define TAMP_BKP18R_Pos (0U)
#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP18R TAMP_BKP18R_Msk
/******************** Bits definition for TAMP_BKP19R register ***************/
#define TAMP_BKP19R_Pos (0U)
#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP19R TAMP_BKP19R_Msk
/******************** Bits definition for TAMP_BKP20R register ***************/
#define TAMP_BKP20R_Pos (0U)
#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP20R TAMP_BKP20R_Msk
/******************** Bits definition for TAMP_BKP21R register ***************/
#define TAMP_BKP21R_Pos (0U)
#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP21R TAMP_BKP21R_Msk
/******************** Bits definition for TAMP_BKP22R register ***************/
#define TAMP_BKP22R_Pos (0U)
#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP22R TAMP_BKP22R_Msk
/******************** Bits definition for TAMP_BKP23R register ***************/
#define TAMP_BKP23R_Pos (0U)
#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP23R TAMP_BKP23R_Msk
/******************** Bits definition for TAMP_BKP24R register ***************/
#define TAMP_BKP24R_Pos (0U)
#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP24R TAMP_BKP24R_Msk
/******************** Bits definition for TAMP_BKP25R register ***************/
#define TAMP_BKP25R_Pos (0U)
#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP25R TAMP_BKP25R_Msk
/******************** Bits definition for TAMP_BKP26R register ***************/
#define TAMP_BKP26R_Pos (0U)
#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP26R TAMP_BKP26R_Msk
/******************** Bits definition for TAMP_BKP27R register ***************/
#define TAMP_BKP27R_Pos (0U)
#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP27R TAMP_BKP27R_Msk
/******************** Bits definition for TAMP_BKP28R register ***************/
#define TAMP_BKP28R_Pos (0U)
#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP28R TAMP_BKP28R_Msk
/******************** Bits definition for TAMP_BKP29R register ***************/
#define TAMP_BKP29R_Pos (0U)
#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP29R TAMP_BKP29R_Msk
/******************** Bits definition for TAMP_BKP30R register ***************/
#define TAMP_BKP30R_Pos (0U)
#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP30R TAMP_BKP30R_Msk
/******************** Bits definition for TAMP_BKP31R register ***************/
#define TAMP_BKP31R_Pos (0U)
#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP31R TAMP_BKP31R_Msk
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 ( 0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 ( 0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 ( 0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
#define TIM_CR2_ADSYNC_Pos (28U)
#define TIM_CR2_ADSYNC_Msk (0x1UL << TIM_CR2_ADSYNC_Pos) /*!< 0x10000000 */
#define TIM_CR2_ADSYNC TIM_CR2_ADSYNC_Msk /*!<ADC synchronization */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0x000FFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x000FFFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime preload enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_IBLK_Pos (3U)
#define TIM_ECR_IBLK_Msk (0x3UL << TIM_ECR_IBLK_Pos) /*!< 0x00000018 */
#define TIM_ECR_IBLK TIM_ECR_IBLK_Msk /*!<IBLK[1:0] bits (Index blanking)*/
#define TIM_ECR_IBLK_0 (0x01UL << TIM_ECR_IBLK_Pos) /*!< 0x00000008 */
#define TIM_ECR_IBLK_1 (0x02UL << TIM_ECR_IBLK_Pos) /*!< 0x00000010 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000040 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000080 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits */
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits */
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits */
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits */
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_AF1 register ********************/
#define TIM_AF1_BKINE_Pos (0U)
#define TIM_AF1_BKINE_Msk (0x1UL << TIM_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM_AF1_BKINE TIM_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM_AF1_BKCMP1E_Pos (1U)
#define TIM_AF1_BKCMP1E_Msk (0x1UL << TIM_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM_AF1_BKCMP1E TIM_AF1_BKCMP1E_Msk /*!<BRK CMP1 enable */
#define TIM_AF1_BKCMP2E_Pos (2U)
#define TIM_AF1_BKCMP2E_Msk (0x1UL << TIM_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM_AF1_BKCMP2E TIM_AF1_BKCMP2E_Msk /*!<BRK CMP2 enable */
#define TIM_AF1_BKCMP3E_Pos (3U)
#define TIM_AF1_BKCMP3E_Msk (0x1UL << TIM_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM_AF1_BKCMP3E TIM_AF1_BKCMP3E_Msk /*!<BRK CMP3 enable */
#define TIM_AF1_BKCMP4E_Pos (4U)
#define TIM_AF1_BKCMP4E_Msk (0x1UL << TIM_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM_AF1_BKCMP4E TIM_AF1_BKCMP4E_Msk /*!<BRK CMP4 enable */
#define TIM_AF1_BKCMP5E_Pos (5U)
#define TIM_AF1_BKCMP5E_Msk (0x1UL << TIM_AF1_BKCMP5E_Pos) /*!< 0x00000020 */
#define TIM_AF1_BKCMP5E TIM_AF1_BKCMP5E_Msk /*!<BRK CMP5 enable */
#define TIM_AF1_BKCMP6E_Pos (6U)
#define TIM_AF1_BKCMP6E_Msk (0x1UL << TIM_AF1_BKCMP6E_Pos) /*!< 0x00000040 */
#define TIM_AF1_BKCMP6E TIM_AF1_BKCMP6E_Msk /*!<BRK CMP6 enable */
#define TIM_AF1_BKCMP7E_Pos (7U)
#define TIM_AF1_BKCMP7E_Msk (0x1UL << TIM_AF1_BKCMP7E_Pos) /*!< 0x00000080 */
#define TIM_AF1_BKCMP7E TIM_AF1_BKCMP7E_Msk /*!<BRK CMP7 enable */
#define TIM_AF1_BKCMP8E_Pos (8U)
#define TIM_AF1_BKCMP8E_Msk (0x1UL << TIM_AF1_BKCMP8E_Pos) /*!< 0x00000100 */
#define TIM_AF1_BKCMP8E TIM_AF1_BKCMP8E_Msk /*!<BRK CMP8 enable */
#define TIM_AF1_BKINP_Pos (9U)
#define TIM_AF1_BKINP_Msk (0x1UL << TIM_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM_AF1_BKINP TIM_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM_AF1_BKCMP1P_Pos (10U)
#define TIM_AF1_BKCMP1P_Msk (0x1UL << TIM_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM_AF1_BKCMP1P TIM_AF1_BKCMP1P_Msk /*!<BRK CMP1 input polarity */
#define TIM_AF1_BKCMP2P_Pos (11U)
#define TIM_AF1_BKCMP2P_Msk (0x1UL << TIM_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM_AF1_BKCMP2P TIM_AF1_BKCMP2P_Msk /*!<BRK CMP1 input polarity */
#define TIM_AF1_BKCMP3P_Pos (12U)
#define TIM_AF1_BKCMP3P_Msk (0x1UL << TIM_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM_AF1_BKCMP3P TIM_AF1_BKCMP3P_Msk /*!<BRK CMP1 input polarity */
#define TIM_AF1_BKCMP4P_Pos (13U)
#define TIM_AF1_BKCMP4P_Msk (0x1UL << TIM_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM_AF1_BKCMP4P TIM_AF1_BKCMP4P_Msk /*!<BRK CMP1 input polarity */
#define TIM_AF1_ETRSEL_Pos (14U)
#define TIM_AF1_ETRSEL_Msk (0xFUL << TIM_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM_AF1_ETRSEL TIM_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM_AF1_ETRSEL_0 (0x1UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM_AF1_ETRSEL_1 (0x2UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM_AF1_ETRSEL_2 (0x4UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM_AF1_ETRSEL_3 (0x8UL << TIM_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM_AF2 register ********************/
#define TIM_AF2_BK2INE_Pos (0U)
#define TIM_AF2_BK2INE_Msk (0x1UL << TIM_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM_AF2_BK2INE TIM_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM_AF2_BK2CMP8E_Pos (8U)
#define TIM_AF2_BK2CMP8E_Msk (0x1UL << TIM_AF2_BK2CMP8E_Pos) /*!< 0x00000100 */
#define TIM_AF2_BK2CMP8E TIM_AF2_BK2CMP8E_Msk /*!<BRK2 CMP8 enable */
#define TIM_AF2_BK2INP_Pos (9U)
#define TIM_AF2_BK2INP_Msk (0x1UL << TIM_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM_AF2_BK2INP TIM_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
#define TIM_DCR_DBSS_Pos (16U)
#define TIM_DCR_DBSS_Msk (0xFUL << TIM_DCR_DBSS_Pos) /*!< 0x000F0000 */
#define TIM_DCR_DBSS TIM_DCR_DBSS_Msk /*!<DBSS[19:16] bits (DMA Burst Source Selection) */
#define TIM_DCR_DBSS_0 (0x01UL << TIM_DCR_DBSS_Pos) /*!< 0x00010000 */
#define TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) /*!< 0x00020000 */
#define TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) /*!< 0x00040000 */
#define TIM_DCR_DBSS_3 (0x08UL << TIM_DCR_DBSS_Pos) /*!< 0x00080000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/*********************************************************************************/
/* */
/* UCPD */
/* */
/*********************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
#define UCPD_CFG2_RXAFILTEN_Pos (8U)
#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */
#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */
/******************** Bits definition for UCPD_CR register *********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_USEEXTPHY_Pos (12U)
#define UCPD_CR_USEEXTPHY_Msk (0x1UL << UCPD_CR_USEEXTPHY_Pos) /*!< 0x00001000 */
#define UCPD_CR_USEEXTPHY UCPD_CR_USEEXTPHY_Msk /*!< Controls enable of USB Power Delivery transmitter */
#define UCPD_CR_CC2VCONNEN_Pos (13U)
#define UCPD_CR_CC2VCONNEN_Msk (0x1UL << UCPD_CR_CC2VCONNEN_Pos) /*!< 0x00002000 */
#define UCPD_CR_CC2VCONNEN UCPD_CR_CC2VCONNEN_Msk /*!< VCONN enable for CC2 */
#define UCPD_CR_CC1VCONNEN_Pos (14U)
#define UCPD_CR_CC1VCONNEN_Msk (0x1UL << UCPD_CR_CC1VCONNEN_Pos) /*!< 0x00004000 */
#define UCPD_CR_CC1VCONNEN UCPD_CR_CC1VCONNEN_Msk /*!< VCONN enable for CC1 */
#define UCPD_CR_DBATEN_Pos (15U)
#define UCPD_CR_DBATEN_Msk (0x1UL << UCPD_CR_DBATEN_Pos) /*!< 0x00008000 */
#define UCPD_CR_DBATEN UCPD_CR_DBATEN_Msk /*!< Enable dead battery behavior (Active High) */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_RPUSBABSENT_Pos (19U)
#define UCPD_CR_RPUSBABSENT_Msk (0x1UL << UCPD_CR_RPUSBABSENT_Pos) /*!< 0x00080000 */
#define UCPD_CR_RPUSBABSENT UCPD_CR_RPUSBABSENT_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register ********************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
/******************** Bits definition for UCPD_SR register *********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
/******************** Bits definition for UCPD_ICR register ********************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
/******************** Bits definition for UCPD_TXORDSET register ***************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register ***************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match Interrupt Enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out Interrupt Enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block Interrupt Enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TX FIFO Empty Interrupt Enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RX FIFO Full Interrupt Enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TX FIFO Threshold Interrupt Enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RX FIFO Threshold Configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RX FIFO Threshold Interrupt Enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TX FIFO Threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART ((uint32_t)0x000FFFFF) /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Timeout Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit Data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise Error detection Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt Flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS Flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Timeout */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun error Flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from low power mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TX FIFO Empty Flag */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RX FIFO Full Flag */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RX FIFO Threshold Flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TX FIFO Threshold Flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TX FIFO Empty Clear Flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* USB_OTG */
/* */
/******************************************************************************/
/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
/******************** Bit definition for USB_OTG_HCFG register ********************/
#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
#define USB_OTG_HCFG_FSLSS_Pos (2U)
#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
/******************** Bit definition for USB_OTG_DCFG register ********************/
#define USB_OTG_DCFG_DSPD_Pos (0U)
#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
#define USB_OTG_DCFG_DAD_Pos (4U)
#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
#define USB_OTG_DCFG_PFIVL_Pos (11U)
#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
#define USB_OTG_DCFG_ERRATIM_Pos (15U)
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
/******************** Bit definition for USB_OTG_PCGCR register ********************/
#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
/******************** Bit definition for USB_OTG_GOTGINT register ********************/
#define USB_OTG_GOTGINT_SEDET_Pos (2U)
#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
/******************** Bit definition for USB_OTG_DCTL register ********************/
#define USB_OTG_DCTL_RWUSIG_Pos (0U)
#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
#define USB_OTG_DCTL_SDIS_Pos (1U)
#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
#define USB_OTG_DCTL_GINSTS_Pos (2U)
#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
#define USB_OTG_DCTL_GONSTS_Pos (3U)
#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
#define USB_OTG_DCTL_TCTL_Pos (4U)
#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
#define USB_OTG_DCTL_SGINAK_Pos (7U)
#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
#define USB_OTG_DCTL_CGINAK_Pos (8U)
#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
#define USB_OTG_DCTL_SGONAK_Pos (9U)
#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
#define USB_OTG_DCTL_CGONAK_Pos (10U)
#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
/******************** Bit definition for USB_OTG_HFIR register ********************/
#define USB_OTG_HFIR_FRIVL_Pos (0U)
#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
/******************** Bit definition for USB_OTG_HFNUM register ********************/
#define USB_OTG_HFNUM_FRNUM_Pos (0U)
#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
#define USB_OTG_HFNUM_FTREM_Pos (16U)
#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
/******************** Bit definition for USB_OTG_DSTS register ********************/
#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
#define USB_OTG_DSTS_EERR_Pos (3U)
#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
#define USB_OTG_DSTS_FNSOF_Pos (8U)
#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
#define USB_OTG_GAHBCFG_GINT_Pos (0U)
#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
#define USB_OTG_GRSTCTL_CSRSTDONE_Pos (29U)
#define USB_OTG_GRSTCTL_CSRSTDONE_Msk (0x1UL << USB_OTG_GRSTCTL_CSRSTDONE_Pos) /*!< 0x20000000 */
#define USB_OTG_GRSTCTL_CSRSTDONE USB_OTG_GRSTCTL_CSRSTDONE_Msk /*!< Core soft reset done */
#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPMSK_TOM_Pos (3U)
#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
#define USB_OTG_DIEPMSK_BIM_Pos (9U)
#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
/******************** Bit definition for USB_OTG_HAINT register ********************/
#define USB_OTG_HAINT_HAINT_Pos (0U)
#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
/******************** Bit definition for USB_OTG_GINTSTS register ********************/
#define USB_OTG_GINTSTS_CMOD_Pos (0U)
#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
#define USB_OTG_GINTSTS_MMIS_Pos (1U)
#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
#define USB_OTG_GINTSTS_SOF_Pos (3U)
#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
#define USB_OTG_GINTSTS_USBRST_Pos (12U)
#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
#define USB_OTG_GINTSTS_EOPF_Pos (15U)
#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
#define USB_OTG_GINTSTS_HCINT_Pos (25U)
#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
/******************** Bit definition for USB_OTG_GINTMSK register ********************/
#define USB_OTG_GINTMSK_MMISM_Pos (1U)
#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
#define USB_OTG_GINTMSK_SOFM_Pos (3U)
#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
#define USB_OTG_GINTMSK_USBRST_Pos (12U)
#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
#define USB_OTG_GINTMSK_HCIM_Pos (25U)
#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
#define USB_OTG_GINTMSK_WUIM_Pos (31U)
#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
/******************** Bit definition for USB_OTG_DAINT register ********************/
#define USB_OTG_DAINT_IEPINT_Pos (0U)
#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
#define USB_OTG_DAINT_OEPINT_Pos (16U)
#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_DPID_Pos (15U)
#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_CHNUM_Pos (0U)
#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos (4U)
#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
#define USB_OTG_DPID_Pos (15U)
#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_PKTSTS_Pos (17U)
#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
#define USB_OTG_EPNUM_Pos (0U)
#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
#define USB_OTG_FRMNUM_Pos (21U)
#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
/******************** Bit definition for OTG register ********************/
#define USB_OTG_NPTXFSA_Pos (0U)
#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
#define USB_OTG_NPTXFD_Pos (16U)
#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
#define USB_OTG_TX0FSA_Pos (0U)
#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
#define USB_OTG_TX0FD_Pos (16U)
#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
/******************** Bit definition for USB_OTG_DEACHINT register ********************/
#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
/******************** Bit definition for USB_OTG_HS_GCCFG register ********************/
#define USB_OTG_GCCFG_CHGDET_Pos (0U)
#define USB_OTG_GCCFG_CHGDET_Msk (0x1U << USB_OTG_GCCFG_CHGDET_Pos) /*!< 0x00000001 */
#define USB_OTG_GCCFG_CHGDET USB_OTG_GCCFG_CHGDET_Msk /*!< Battery Charger Detection */
#define USB_OTG_GCCFG_FSVPLUS_Pos (1U)
#define USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) /*!< 0x00000002 */
#define USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk /*!< Single-Ended DP2 indicator DP voltage level */
#define USB_OTG_GCCFG_FSVMINUS_Pos (2U)
#define USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) /*!< 0x00000004 */
#define USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk /*!< Single-Ended DM2 indicator DM voltage level */
#define USB_OTG_GCCFG_SESSVLD_Pos (3U)
#define USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) /*!< 0x00000008 */
#define USB_OTG_GCCFG_SESSVLD USB_OTG_GCCFG_SESSVLD_Msk /*!< VBUS session valid indicator: Vbus is above VBUS session threshold. */
#define USB_OTG_GCCFG_VBUSVLD_Pos (4U)
#define USB_OTG_GCCFG_VBUSVLD_Msk (0x1U << USB_OTG_GCCFG_VBUSVLD_Pos) /*!< 0x00000010 */
#define USB_OTG_GCCFG_VBUSVLD USB_OTG_GCCFG_VBUSVLD_Msk /*!< VBUS session valid indicator: VBUS is above VBUS valid threshold. */
#define USB_OTG_GCCFG_H_CDPEN_Pos (16U)
#define USB_OTG_GCCFG_H_CDPEN_Msk (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos) /*!< 0x00010000 */
#define USB_OTG_GCCFG_H_CDPEN USB_OTG_GCCFG_H_CDPEN_Msk /*!< VBUS session valid indicator Vbus voltage level */
#define USB_OTG_GCCFG_H_CDPDETEN_Pos (17U)
#define USB_OTG_GCCFG_H_CDPDETEN_Msk (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos) /*!< 0x00020000 */
#define USB_OTG_GCCFG_H_CDPDETEN USB_OTG_GCCFG_H_CDPDETEN_Msk /*!< Enable of voltage detector on DP for CDP port */
#define USB_OTG_GCCFG_H_VDMSRCEN_Pos (18U)
#define USB_OTG_GCCFG_H_VDMSRCEN_Msk (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos) /*!< 0x00040000 */
#define USB_OTG_GCCFG_H_VDMSRCEN USB_OTG_GCCFG_H_VDMSRCEN_Msk /*!< Enable Voltage source on DM for CDP port */
#define USB_OTG_GCCFG_DCDETEN_Pos (19U)
#define USB_OTG_GCCFG_DCDETEN_Msk (0x1U << USB_OTG_GCCFG_DCDETEN_Pos) /*!< 0x00080000 */
#define USB_OTG_GCCFG_DCDETEN USB_OTG_GCCFG_DCDETEN_Msk /*!< Data contact detection (DCD) mode enable */
#define USB_OTG_GCCFG_PDETEN_Pos (20U)
#define USB_OTG_GCCFG_PDETEN_Msk (0x1U << USB_OTG_GCCFG_PDETEN_Pos) /*!< 0x00080000 */
#define USB_OTG_GCCFG_PDETEN USB_OTG_GCCFG_PDETEN_Msk /*!< Primary detection (PD) mode enable */
#define USB_OTG_GCCFG_SDETEN_Pos (22U)
#define USB_OTG_GCCFG_SDETEN_Msk (0x1U << USB_OTG_GCCFG_SDETEN_Pos) /*!< 0x00400000 */
#define USB_OTG_GCCFG_SDETEN USB_OTG_GCCFG_SDETEN_Msk /*!< Secondary detection (PD) mode enable */
#define USB_OTG_GCCFG_VBVALOVAL_Pos (23U)
#define USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) /*!< 0x00800000 */
#define USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk /*!< Value of VBUSVLDEXT0 femtoPHY input */
#define USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U)
#define USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) /*!< 0x01000000 */
#define USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk /*!< Enables of VBUSVLDEXT0 femtoPHY input override */
#define USB_OTG_GCCFG_PULLDOWNEN_Pos (25U)
#define USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) /*!< 0x02000000 */
#define USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk /*!< Enables Host pulldown resistors, used when ID PAD is disabled */
#define USB_OTG_GCCFG_FORCEBCMODE_Pos (26U)
#define USB_OTG_GCCFG_FORCEBCMODE_Msk (0x1U << USB_OTG_GCCFG_FORCEBCMODE_Pos) /*!< 0x04000000 */
#define USB_OTG_GCCFG_FORCEBCMODE USB_OTG_GCCFG_FORCEBCMODE_Msk /*!< Force Battery charging (BC) mode */
#define USB_OTG_GCCFG_IDPULLUP_DIS_Pos (28U)
#define USB_OTG_GCCFG_IDPULLUP_DIS_Msk (0x1U << USB_OTG_GCCFG_IDPULLUP_DIS_Pos) /*!< 0x10000000 */
#define USB_OTG_GCCFG_IDPULLUP_DIS USB_OTG_GCCFG_IDPULLUP_DIS_Msk /*!< Analog ID Input Sample Disable: disable sampling on the analog ID line */
/******************** Bit definition for USB_OTG_GPWRDN) register ********************/
#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
/******************** Bit definition for USB_OTG_CID register ********************/
#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
#define USB_OTG_GLPMCFG_BESL_Pos (2U)
#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
/******************** Bit definition for USB_OTG_HPRT register ********************/
#define USB_OTG_HPRT_PCSTS_Pos (0U)
#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
#define USB_OTG_HPRT_PCDET_Pos (1U)
#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
#define USB_OTG_HPRT_PENA_Pos (2U)
#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
#define USB_OTG_HPRT_PENCHNG_Pos (3U)
#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
#define USB_OTG_HPRT_POCA_Pos (4U)
#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
#define USB_OTG_HPRT_POCCHNG_Pos (5U)
#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
#define USB_OTG_HPRT_PRES_Pos (6U)
#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
#define USB_OTG_HPRT_PSUSP_Pos (7U)
#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
#define USB_OTG_HPRT_PRST_Pos (8U)
#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
#define USB_OTG_HPRT_PLSTS_Pos (10U)
#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
#define USB_OTG_HPRT_PPWR_Pos (12U)
#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
#define USB_OTG_HPRT_PTCTL_Pos (13U)
#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
#define USB_OTG_HPRT_PSPD_Pos (17U)
#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_DIEPCTL_STALL_Pos (21U)
#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
/******************** Bit definition for USB_OTG_HCCHAR register ********************/
#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_HCCHAR_MC_Pos (20U)
#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
#define USB_OTG_HCCHAR_DAD_Pos (22U)
#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
#define USB_OTG_HCCHAR_CHENA_Pos (31U)
#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
/******************** Bit definition for USB_OTG_HCSPLT register ********************/
#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
/******************** Bit definition for USB_OTG_HCINT register ********************/
#define USB_OTG_HCINT_XFRC_Pos (0U)
#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
#define USB_OTG_HCINT_CHH_Pos (1U)
#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
#define USB_OTG_HCINT_AHBERR_Pos (2U)
#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
#define USB_OTG_HCINT_STALL_Pos (3U)
#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
#define USB_OTG_HCINT_NAK_Pos (4U)
#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
#define USB_OTG_HCINT_ACK_Pos (5U)
#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
#define USB_OTG_HCINT_NYET_Pos (6U)
#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
#define USB_OTG_HCINT_TXERR_Pos (7U)
#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
#define USB_OTG_HCINT_BBERR_Pos (8U)
#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
#define USB_OTG_HCINT_FRMOR_Pos (9U)
#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
#define USB_OTG_HCINT_DTERR_Pos (10U)
#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
/******************** Bit definition for USB_OTG_DIEPINT register ********************/
#define USB_OTG_DIEPINT_XFRC_Pos (0U)
#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
#define USB_OTG_DIEPINT_TOC_Pos (3U)
#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
#define USB_OTG_DIEPINT_TXFE_Pos (7U)
#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
#define USB_OTG_DIEPINT_BNA_Pos (9U)
#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
#define USB_OTG_DIEPINT_BERR_Pos (12U)
#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
#define USB_OTG_DIEPINT_NAK_Pos (13U)
#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
#define USB_OTG_HCINTMSK_NYET_Pos (6U)
#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
#define USB_OTG_HCTSIZ_DPID_Pos (29U)
#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
/******************** Bit definition for USB_OTG_HCDMA register ********************/
#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
#define USB_OTG_DOEPCTL_STALL_Pos (21U)
#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
/******************** Bit definition for USB_OTG_DOEPINT register ********************/
#define USB_OTG_DOEPINT_XFRC_Pos (0U)
#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
#define USB_OTG_DOEPINT_STUP_Pos (3U)
#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
#define USB_OTG_DOEPINT_BERR_Pos (12U)
#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
#define USB_OTG_DOEPINT_NAK_Pos (13U)
#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
#define USB_OTG_DOEPINT_NYET_Pos (14U)
#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
/******************** Bit definition for USB_OTG_PCGCCTL register ********************/
#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
/******************** Bit definition for USB_OTG_PCGCCTL1 register ********************/
#define USB_OTG_PCGCCTL1_GATEEN_Pos (0U)
#define USB_OTG_PCGCCTL1_GATEEN_Msk (0x1UL << USB_OTG_PCGCCTL1_GATEEN_Pos) /*!< 0x00000001 */
#define USB_OTG_PCGCCTL1_GATEEN USB_OTG_PCGCCTL1_GATEEN_Msk /*!< Enable Active Clock Gating */
#define USB_OTG_PCGCCTL1_COUNTER_Pos (1U)
#define USB_OTG_PCGCCTL1_COUNTER_Msk (0x3UL << USB_OTG_PCGCCTL1_COUNTER_Pos) /*!< 0x00000002 */
#define USB_OTG_PCGCCTL1_COUNTER USB_OTG_PCGCCTL1_COUNTER_Msk /*!< Count to Gate Clock */
#define USB_OTG_PCGCCTL1_RAMGATEEN_Pos (3U)
#define USB_OTG_PCGCCTL1_RAMGATEEN_Msk (0x1UL << USB_OTG_PCGCCTL1_RAMGATEEN_Pos) /*!< 0x00000010 */
#define USB_OTG_PCGCCTL1_RAMGATEEN USB_OTG_PCGCCTL1_RAMGATEEN_Msk /*!< RAM Clock Gating Enable */
/*!< USB registers base address */
#define USB_OTG_GLOBAL_BASE (0x000UL)
#define USB_OTG_DEVICE_BASE (0x800UL)
#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
#define USB_OTG_EP_REG_SIZE (0x20UL)
#define USB_OTG_HOST_BASE (0x400UL)
#define USB_OTG_HOST_PORT_BASE (0x440UL)
#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
#define USB_OTG_PCGCCTL_BASE (0xE00UL)
#define USB_OTG_FIFO_BASE (0x1000UL)
#define USB_OTG_FIFO_SIZE (0x1000UL)
#define USB_OTG_HS_EP_NBR (9UL) /*!< Number of USB HS Device endpoints */
#define USB_OTG_HS_CH_NBR (16UL) /*!< Number of USB HS Host channels */
/******************** Bit definition for USB_USBPHYC_CR register ********************/
#define USB_USBPHYC_CR_RETENABLEN1_Pos (0U)
#define USB_USBPHYC_CR_RETENABLEN1_Msk (0x1UL << USB_USBPHYC_CR_RETENABLEN1_Pos) /*!< 0x00000001 */
#define USB_USBPHYC_CR_RETENABLEN1 USB_USBPHYC_CR_RETENABLEN1_Msk /*!< Retention mode enable */
#define USB_USBPHYC_CR_AUTORSMENB1_Pos (1U)
#define USB_USBPHYC_CR_AUTORSMENB1_Msk (0x1UL << USB_USBPHYC_CR_AUTORSMENB1_Pos) /*!< 0x00000002 */
#define USB_USBPHYC_CR_AUTORSMENB1 USB_USBPHYC_CR_AUTORSMENB1_Msk /*!< Auto-resume mode enable */
#define USB_USBPHYC_CR_CMN_Pos (2U)
#define USB_USBPHYC_CR_CMN_Msk (0x1UL << USB_USBPHYC_CR_CMN_Pos) /*!< 0x00000004 */
#define USB_USBPHYC_CR_CMN USB_USBPHYC_CR_CMN_Msk /*!< Controls the power down of analog blocks during Suspend and Sleep */
#define USB_USBPHYC_CR_FSEL_Pos (4U)
#define USB_USBPHYC_CR_FSEL_Msk (0x7UL << USB_USBPHYC_CR_FSEL_Pos) /*!< 0x00000070 */
#define USB_USBPHYC_CR_FSEL USB_USBPHYC_CR_FSEL_Msk /*!< Frequency selection */
#define USB_USBPHYC_CR_FSEL_0 (0x1UL << USB_USBPHYC_CR_FSEL_Pos) /*!< 0x00000010 */
#define USB_USBPHYC_CR_FSEL_1 (0x2UL << USB_USBPHYC_CR_FSEL_Pos) /*!< 0x00000020 */
#define USB_USBPHYC_CR_FSEL_2 (0x3UL << USB_USBPHYC_CR_FSEL_Pos) /*!< 0x00000040 */
#define USB_USBPHYC_CR_OTGDISABLE0_Pos (16U)
#define USB_USBPHYC_CR_OTGDISABLE0_Msk (0x1UL << USB_USBPHYC_CR_OTGDISABLE0_Pos) /*!< 0x00010000 */
#define USB_USBPHYC_CR_OTGDISABLE0 USB_USBPHYC_CR_OTGDISABLE0_Msk /*!< OTG disable 0 */
#define USB_USBPHYC_CR_DRVVBUS0_Pos (17U)
#define USB_USBPHYC_CR_DRVVBUS0_Msk (0x1UL << USB_USBPHYC_CR_DRVVBUS0_Pos) /*!< 0x00020000 */
#define USB_USBPHYC_CR_DRVVBUS0 USB_USBPHYC_CR_DRVVBUS0_Msk /*!< Drive VBUS 0 */
#define USB_USBPHYC_CR_SELOTGDBG_Pos (31U)
#define USB_USBPHYC_CR_SELOTGDBG_Msk (0x1UL << USB_USBPHYC_CR_SELOTGDBG_Pos) /*!< 0x80000000 */
#define USB_USBPHYC_CR_SELOTGDBG USB_USBPHYC_CR_SELOTGDBG_Msk /*!< Select HS PHY debug port */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
#define VREFBUF_CSR_VRS_0 (0x01UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x000O0010 */
#define VREFBUF_CSR_VRS_1 (0x02UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
#define VREFBUF_CSR_VRS_2 (0x04UL<< VREFBUF_CSR_VRS_Pos) /*!< 0x00000040 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/******************************************************************************/
/* */
/* Extended-SPI Interface (XSPI) */
/* */
/******************************************************************************/
/***************** Bit definition for XSPI_CR register *******************/
#define XSPI_CR_EN_Pos (0U)
#define XSPI_CR_EN_Msk (0x1UL << XSPI_CR_EN_Pos) /*!< 0x00000001 */
#define XSPI_CR_EN XSPI_CR_EN_Msk /*!< Enable */
#define XSPI_CR_ABORT_Pos (1U)
#define XSPI_CR_ABORT_Msk (0x1UL << XSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define XSPI_CR_ABORT XSPI_CR_ABORT_Msk /*!< Abort request */
#define XSPI_CR_DMAEN_Pos (2U)
#define XSPI_CR_DMAEN_Msk (0x1UL << XSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define XSPI_CR_DMAEN XSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define XSPI_CR_TCEN_Pos (3U)
#define XSPI_CR_TCEN_Msk (0x1UL << XSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define XSPI_CR_TCEN XSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define XSPI_CR_DMM_Pos (6U)
#define XSPI_CR_DMM_Msk (0x1UL << XSPI_CR_DMM_Pos) /*!< 0x00000040 */
#define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual Memory Mode */
#define XSPI_CR_FSEL_Pos (7U)
#define XSPI_CR_FSEL_Msk (0x1UL << XSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define XSPI_CR_FSEL XSPI_CR_FSEL_Msk /*!< Flash Select */
#define XSPI_CR_FTHRES_Pos (8U)
#define XSPI_CR_FTHRES_Msk (0x3FUL << XSPI_CR_FTHRES_Pos) /*!< 0x00003F00 */
#define XSPI_CR_FTHRES XSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
#define XSPI_CR_TEIE_Pos (16U)
#define XSPI_CR_TEIE_Msk (0x1UL << XSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define XSPI_CR_TEIE XSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define XSPI_CR_TCIE_Pos (17U)
#define XSPI_CR_TCIE_Msk (0x1UL << XSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define XSPI_CR_TCIE XSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define XSPI_CR_FTIE_Pos (18U)
#define XSPI_CR_FTIE_Msk (0x1UL << XSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define XSPI_CR_FTIE XSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define XSPI_CR_SMIE_Pos (19U)
#define XSPI_CR_SMIE_Msk (0x1UL << XSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define XSPI_CR_SMIE XSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define XSPI_CR_TOIE_Pos (20U)
#define XSPI_CR_TOIE_Msk (0x1UL << XSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define XSPI_CR_TOIE XSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define XSPI_CR_APMS_Pos (22U)
#define XSPI_CR_APMS_Msk (0x1UL << XSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define XSPI_CR_APMS XSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
#define XSPI_CR_PMM_Pos (23U)
#define XSPI_CR_PMM_Msk (0x1UL << XSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define XSPI_CR_PMM XSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define XSPI_CR_CSSEL_Pos (24U)
#define XSPI_CR_CSSEL_Msk (0x1UL << XSPI_CR_CSSEL_Pos) /*!< 0x01000000 */
#define XSPI_CR_CSSEL XSPI_CR_CSSEL_Msk /*!< Chip Select Selection */
#define XSPI_CR_NOPREF_Pos (25U)
#define XSPI_CR_NOPREF_Msk (0x1UL << XSPI_CR_NOPREF_Pos) /*!< 0x02000000 */
#define XSPI_CR_NOPREF XSPI_CR_NOPREF_Msk /*!< No Prefetch Data */
#define XSPI_CR_NOPREF_AXI_Pos (26U)
#define XSPI_CR_NOPREF_AXI_Msk (0x1UL << XSPI_CR_NOPREF_AXI_Pos) /*!< 0x04000000 */
#define XSPI_CR_NOPREF_AXI XSPI_CR_NOPREF_AXI_Msk /*!< No Prefetch For Signaled AXI Transactions */
#define XSPI_CR_FMODE_Pos (28U)
#define XSPI_CR_FMODE_Msk (0x3UL << XSPI_CR_FMODE_Pos) /*!< 0x30000000 */
#define XSPI_CR_FMODE XSPI_CR_FMODE_Msk /*!< Functional Mode */
#define XSPI_CR_FMODE_0 (0x1UL << XSPI_CR_FMODE_Pos) /*!< 0x10000000 */
#define XSPI_CR_FMODE_1 (0x2UL << XSPI_CR_FMODE_Pos) /*!< 0x20000000 */
#define XSPI_CR_MSEL_Pos (30U)
#define XSPI_CR_MSEL_Msk (0x3UL << XSPI_CR_MSEL_Pos) /*!< 0xC0000000 */
#define XSPI_CR_MSEL XSPI_CR_MSEL_Msk /*!< Memory Select */
#define XSPI_CR_MSEL_0 (0x1UL << XSPI_CR_MSEL_Pos) /*!< 0x40000000 */
#define XSPI_CR_MSEL_1 (0x2UL << XSPI_CR_MSEL_Pos) /*!< 0x80000000 */
/**************** Bit definition for XSPI_DCR1 register ******************/
#define XSPI_DCR1_CKMODE_Pos (0U)
#define XSPI_DCR1_CKMODE_Msk (0x1UL << XSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
#define XSPI_DCR1_CKMODE XSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define XSPI_DCR1_FRCK_Pos (1U)
#define XSPI_DCR1_FRCK_Msk (0x1UL << XSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
#define XSPI_DCR1_FRCK XSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
#define XSPI_DCR1_CSHT_Pos (8U)
#define XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) /*!< 0x00003F00 */
#define XSPI_DCR1_CSHT XSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
#define XSPI_DCR1_DEVSIZE_Pos (16U)
#define XSPI_DCR1_DEVSIZE_Msk (0x1FUL << XSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
#define XSPI_DCR1_DEVSIZE XSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
#define XSPI_DCR1_EXTENDMEM_Pos (21U)
#define XSPI_DCR1_EXTENDMEM_Msk (0x1UL << XSPI_DCR1_EXTENDMEM_Pos) /*!< 0x00200000 */
#define XSPI_DCR1_EXTENDMEM XSPI_DCR1_EXTENDMEM_Msk /*!< Extended Memory Support */
#define XSPI_DCR1_MTYP_Pos (24U)
#define XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
#define XSPI_DCR1_MTYP XSPI_DCR1_MTYP_Msk /*!< Memory Type */
#define XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
#define XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
#define XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
/**************** Bit definition for XSPI_DCR2 register ******************/
#define XSPI_DCR2_PRESCALER_Pos (0U)
#define XSPI_DCR2_PRESCALER_Msk (0xFFUL << XSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
#define XSPI_DCR2_PRESCALER XSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
#define XSPI_DCR2_WRAPSIZE_Pos (16U)
#define XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
#define XSPI_DCR2_WRAPSIZE XSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
#define XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
#define XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
#define XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
/**************** Bit definition for XSPI_DCR3 register ******************/
#define XSPI_DCR3_MAXTRAN_Pos (0U)
#define XSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */
#define XSPI_DCR3_MAXTRAN XSPI_DCR3_MAXTRAN_Msk /*!< Maximum transfer */
#define XSPI_DCR3_CSBOUND_Pos (16U)
#define XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
#define XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk /*!< Maximum transfer */
/**************** Bit definition for XSPI_DCR4 register ******************/
#define XSPI_DCR4_REFRESH_Pos (0U)
#define XSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
#define XSPI_DCR4_REFRESH XSPI_DCR4_REFRESH_Msk /*!< Refresh rate */
/***************** Bit definition for XSPI_SR register *******************/
#define XSPI_SR_TEF_Pos (0U)
#define XSPI_SR_TEF_Msk (0x1UL << XSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define XSPI_SR_TEF XSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define XSPI_SR_TCF_Pos (1U)
#define XSPI_SR_TCF_Msk (0x1UL << XSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define XSPI_SR_TCF XSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define XSPI_SR_FTF_Pos (2U)
#define XSPI_SR_FTF_Msk (0x1UL << XSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define XSPI_SR_FTF XSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
#define XSPI_SR_SMF_Pos (3U)
#define XSPI_SR_SMF_Msk (0x1UL << XSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define XSPI_SR_SMF XSPI_SR_SMF_Msk /*!< Status Match Flag */
#define XSPI_SR_TOF_Pos (4U)
#define XSPI_SR_TOF_Msk (0x1UL << XSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define XSPI_SR_TOF XSPI_SR_TOF_Msk /*!< Timeout Flag */
#define XSPI_SR_BUSY_Pos (5U)
#define XSPI_SR_BUSY_Msk (0x1UL << XSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define XSPI_SR_BUSY XSPI_SR_BUSY_Msk /*!< Busy */
#define XSPI_SR_FLEVEL_Pos (8U)
#define XSPI_SR_FLEVEL_Msk (0x7FUL << XSPI_SR_FLEVEL_Pos) /*!< 0x00007F00 */
#define XSPI_SR_FLEVEL XSPI_SR_FLEVEL_Msk /*!< FIFO Level */
/**************** Bit definition for XSPI_FCR register *******************/
#define XSPI_FCR_CTEF_Pos (0U)
#define XSPI_FCR_CTEF_Msk (0x1UL << XSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define XSPI_FCR_CTEF XSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define XSPI_FCR_CTCF_Pos (1U)
#define XSPI_FCR_CTCF_Msk (0x1UL << XSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define XSPI_FCR_CTCF XSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define XSPI_FCR_CSMF_Pos (3U)
#define XSPI_FCR_CSMF_Msk (0x1UL << XSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define XSPI_FCR_CSMF XSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define XSPI_FCR_CTOF_Pos (4U)
#define XSPI_FCR_CTOF_Msk (0x1UL << XSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define XSPI_FCR_CTOF XSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/**************** Bit definition for XSPI_DLR register *******************/
#define XSPI_DLR_DL_Pos (0U)
#define XSPI_DLR_DL_Msk (0xFFFFFFFFUL << XSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define XSPI_DLR_DL XSPI_DLR_DL_Msk /*!< Data Length */
/***************** Bit definition for XSPI_AR register *******************/
#define XSPI_AR_ADDRESS_Pos (0U)
#define XSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
#define XSPI_AR_ADDRESS XSPI_AR_ADDRESS_Msk /*!< Address */
/***************** Bit definition for XSPI_DR register *******************/
#define XSPI_DR_DATA_Pos (0U)
#define XSPI_DR_DATA_Msk (0xFFFFFFFFUL << XSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define XSPI_DR_DATA XSPI_DR_DATA_Msk /*!< Data */
/*************** Bit definition for XSPI_PSMKR register ******************/
#define XSPI_PSMKR_MASK_Pos (0U)
#define XSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
#define XSPI_PSMKR_MASK XSPI_PSMKR_MASK_Msk /*!< Status mask */
/*************** Bit definition for XSPI_PSMAR register ******************/
#define XSPI_PSMAR_MATCH_Pos (0U)
#define XSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
#define XSPI_PSMAR_MATCH XSPI_PSMAR_MATCH_Msk /*!< Status match */
/**************** Bit definition for XSPI_PIR register *******************/
#define XSPI_PIR_INTERVAL_Pos (0U)
#define XSPI_PIR_INTERVAL_Msk (0xFFFFUL << XSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define XSPI_PIR_INTERVAL XSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
/**************** Bit definition for XSPI_CCR register *******************/
#define XSPI_CCR_IMODE_Pos (0U)
#define XSPI_CCR_IMODE_Msk (0x7UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
#define XSPI_CCR_IMODE XSPI_CCR_IMODE_Msk /*!< Instruction Mode */
#define XSPI_CCR_IMODE_0 (0x1UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
#define XSPI_CCR_IMODE_1 (0x2UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
#define XSPI_CCR_IMODE_2 (0x4UL << XSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
#define XSPI_CCR_IDTR_Pos (3U)
#define XSPI_CCR_IDTR_Msk (0x1UL << XSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
#define XSPI_CCR_IDTR XSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
#define XSPI_CCR_ISIZE_Pos (4U)
#define XSPI_CCR_ISIZE_Msk (0x3UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
#define XSPI_CCR_ISIZE XSPI_CCR_ISIZE_Msk /*!< Instruction Size */
#define XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
#define XSPI_CCR_ISIZE_1 (0x2UL << XSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
#define XSPI_CCR_ADMODE_Pos (8U)
#define XSPI_CCR_ADMODE_Msk (0x7UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
#define XSPI_CCR_ADMODE XSPI_CCR_ADMODE_Msk /*!< Address Mode */
#define XSPI_CCR_ADMODE_0 (0x1UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
#define XSPI_CCR_ADMODE_1 (0x2UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
#define XSPI_CCR_ADMODE_2 (0x4UL << XSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define XSPI_CCR_ADDTR_Pos (11U)
#define XSPI_CCR_ADDTR_Msk (0x1UL << XSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
#define XSPI_CCR_ADDTR XSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
#define XSPI_CCR_ADSIZE_Pos (12U)
#define XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define XSPI_CCR_ADSIZE XSPI_CCR_ADSIZE_Msk /*!< Address Size */
#define XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define XSPI_CCR_ABMODE_Pos (16U)
#define XSPI_CCR_ABMODE_Msk (0x7UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
#define XSPI_CCR_ABMODE XSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
#define XSPI_CCR_ABMODE_0 (0x1UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
#define XSPI_CCR_ABMODE_1 (0x2UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
#define XSPI_CCR_ABMODE_2 (0x4UL << XSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
#define XSPI_CCR_ABDTR_Pos (19U)
#define XSPI_CCR_ABDTR_Msk (0x1UL << XSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
#define XSPI_CCR_ABDTR XSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_CCR_ABSIZE_Pos (20U)
#define XSPI_CCR_ABSIZE_Msk (0x3UL << XSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
#define XSPI_CCR_ABSIZE XSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
#define XSPI_CCR_ABSIZE_0 (0x1UL << XSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
#define XSPI_CCR_ABSIZE_1 (0x2UL << XSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
#define XSPI_CCR_DMODE_Pos (24U)
#define XSPI_CCR_DMODE_Msk (0x7UL << XSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
#define XSPI_CCR_DMODE XSPI_CCR_DMODE_Msk /*!< Data Mode */
#define XSPI_CCR_DMODE_0 (0x1UL << XSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define XSPI_CCR_DMODE_1 (0x2UL << XSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define XSPI_CCR_DMODE_2 (0x4UL << XSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
#define XSPI_CCR_DDTR_Pos (27U)
#define XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
#define XSPI_CCR_DDTR XSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
#define XSPI_CCR_DQSE_Pos (29U)
#define XSPI_CCR_DQSE_Msk (0x1UL << XSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
#define XSPI_CCR_DQSE XSPI_CCR_DQSE_Msk /*!< DQS Enable */
/**************** Bit definition for XSPI_TCR register *******************/
#define XSPI_TCR_DCYC_Pos (0U)
#define XSPI_TCR_DCYC_Msk (0x1FUL << XSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
#define XSPI_TCR_DCYC XSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
#define XSPI_TCR_DHQC_Pos (28U)
#define XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
#define XSPI_TCR_DHQC XSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
#define XSPI_TCR_SSHIFT_Pos (30U)
#define XSPI_TCR_SSHIFT_Msk (0x1UL << XSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
#define XSPI_TCR_SSHIFT XSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
/***************** Bit definition for XSPI_IR register *******************/
#define XSPI_IR_INSTRUCTION_Pos (0U)
#define XSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
#define XSPI_IR_INSTRUCTION XSPI_IR_INSTRUCTION_Msk /*!< Instruction */
/**************** Bit definition for XSPI_ABR register *******************/
#define XSPI_ABR_ALTERNATE_Pos (0U)
#define XSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define XSPI_ABR_ALTERNATE XSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
/**************** Bit definition for XSPI_LPTR register ******************/
#define XSPI_LPTR_TIMEOUT_Pos (0U)
#define XSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define XSPI_LPTR_TIMEOUT XSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
/**************** Bit definition for XSPI_WPCCR register *******************/
#define XSPI_WPCCR_IMODE_Pos (0U)
#define XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
#define XSPI_WPCCR_IMODE XSPI_WPCCR_IMODE_Msk /*!< Instruction Mode */
#define XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
#define XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
#define XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
#define XSPI_WPCCR_IDTR_Pos (3U)
#define XSPI_WPCCR_IDTR_Msk (0x1UL << XSPI_WPCCR_IDTR_Pos) /*!< 0x00000008 */
#define XSPI_WPCCR_IDTR XSPI_WPCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
#define XSPI_WPCCR_ISIZE_Pos (4U)
#define XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
#define XSPI_WPCCR_ISIZE XSPI_WPCCR_ISIZE_Msk /*!< Instruction Size */
#define XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
#define XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
#define XSPI_WPCCR_ADMODE_Pos (8U)
#define XSPI_WPCCR_ADMODE_Msk (0x7UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000700 */
#define XSPI_WPCCR_ADMODE XSPI_WPCCR_ADMODE_Msk /*!< Address Mode */
#define XSPI_WPCCR_ADMODE_0 (0x1UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000100 */
#define XSPI_WPCCR_ADMODE_1 (0x2UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000200 */
#define XSPI_WPCCR_ADMODE_2 (0x4UL << XSPI_WPCCR_ADMODE_Pos) /*!< 0x00000400 */
#define XSPI_WPCCR_ADDTR_Pos (11U)
#define XSPI_WPCCR_ADDTR_Msk (0x1UL << XSPI_WPCCR_ADDTR_Pos) /*!< 0x00000800 */
#define XSPI_WPCCR_ADDTR XSPI_WPCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
#define XSPI_WPCCR_ADSIZE_Pos (12U)
#define XSPI_WPCCR_ADSIZE_Msk (0x3UL << XSPI_WPCCR_ADSIZE_Pos) /*!< 0x00003000 */
#define XSPI_WPCCR_ADSIZE XSPI_WPCCR_ADSIZE_Msk /*!< Address Size */
#define XSPI_WPCCR_ADSIZE_0 (0x1UL << XSPI_WPCCR_ADSIZE_Pos) /*!< 0x00001000 */
#define XSPI_WPCCR_ADSIZE_1 (0x2UL << XSPI_WPCCR_ADSIZE_Pos) /*!< 0x00002000 */
#define XSPI_WPCCR_ABMODE_Pos (16U)
#define XSPI_WPCCR_ABMODE_Msk (0x7UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00070000 */
#define XSPI_WPCCR_ABMODE XSPI_WPCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
#define XSPI_WPCCR_ABMODE_0 (0x1UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00010000 */
#define XSPI_WPCCR_ABMODE_1 (0x2UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00020000 */
#define XSPI_WPCCR_ABMODE_2 (0x4UL << XSPI_WPCCR_ABMODE_Pos) /*!< 0x00040000 */
#define XSPI_WPCCR_ABDTR_Pos (19U)
#define XSPI_WPCCR_ABDTR_Msk (0x1UL << XSPI_WPCCR_ABDTR_Pos) /*!< 0x00080000 */
#define XSPI_WPCCR_ABDTR XSPI_WPCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_WPCCR_ABSIZE_Pos (20U)
#define XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
#define XSPI_WPCCR_ABSIZE XSPI_WPCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
#define XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
#define XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
#define XSPI_WPCCR_DMODE_Pos (24U)
#define XSPI_WPCCR_DMODE_Msk (0x7UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x07000000 */
#define XSPI_WPCCR_DMODE XSPI_WPCCR_DMODE_Msk /*!< Data Mode */
#define XSPI_WPCCR_DMODE_0 (0x1UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x01000000 */
#define XSPI_WPCCR_DMODE_1 (0x2UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x02000000 */
#define XSPI_WPCCR_DMODE_2 (0x4UL << XSPI_WPCCR_DMODE_Pos) /*!< 0x04000000 */
#define XSPI_WPCCR_DDTR_Pos (27U)
#define XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
#define XSPI_WPCCR_DDTR XSPI_WPCCR_DDTR_Msk /*!< Data Double Transfer Rate */
#define XSPI_WPCCR_DQSE_Pos (29U)
#define XSPI_WPCCR_DQSE_Msk (0x1UL << XSPI_WPCCR_DQSE_Pos) /*!< 0x20000000 */
#define XSPI_WPCCR_DQSE XSPI_WPCCR_DQSE_Msk /*!< DQS Enable */
/**************** Bit definition for XSPI_WPTCR register *******************/
#define XSPI_WPTCR_DCYC_Pos (0U)
#define XSPI_WPTCR_DCYC_Msk (0x1FUL << XSPI_WPTCR_DCYC_Pos) /*!< 0x0000001F */
#define XSPI_WPTCR_DCYC XSPI_WPTCR_DCYC_Msk /*!< Number of Dummy Cycles */
#define XSPI_WPTCR_DHQC_Pos (28U)
#define XSPI_WPTCR_DHQC_Msk (0x1UL << XSPI_WPTCR_DHQC_Pos) /*!< 0x10000000 */
#define XSPI_WPTCR_DHQC XSPI_WPTCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
#define XSPI_WPTCR_SSHIFT_Pos (30U)
#define XSPI_WPTCR_SSHIFT_Msk (0x1UL << XSPI_WPTCR_SSHIFT_Pos) /*!< 0x40000000 */
#define XSPI_WPTCR_SSHIFT XSPI_WPTCR_SSHIFT_Msk /*!< Sample Shift */
/***************** Bit definition for XSPI_WPIR register *******************/
#define XSPI_WPIR_INSTRUCTION_Pos (0U)
#define XSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WPIR_INSTRUCTION XSPI_WPIR_INSTRUCTION_Msk /*!< Instruction */
/**************** Bit definition for XSPI_WPABR register *******************/
#define XSPI_WPABR_ALTERNATE_Pos (0U)
#define XSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WPABR_ALTERNATE XSPI_WPABR_ALTERNATE_Msk /*!< Alternate Bytes */
/**************** Bit definition for XSPI_WCCR register ******************/
#define XSPI_WCCR_IMODE_Pos (0U)
#define XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
#define XSPI_WCCR_IMODE XSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
#define XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
#define XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
#define XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
#define XSPI_WCCR_IDTR_Pos (3U)
#define XSPI_WCCR_IDTR_Msk (0x1UL << XSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
#define XSPI_WCCR_IDTR XSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
#define XSPI_WCCR_ISIZE_Pos (4U)
#define XSPI_WCCR_ISIZE_Msk (0x3UL << XSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
#define XSPI_WCCR_ISIZE XSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
#define XSPI_WCCR_ISIZE_0 (0x1UL << XSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
#define XSPI_WCCR_ISIZE_1 (0x2UL << XSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
#define XSPI_WCCR_ADMODE_Pos (8U)
#define XSPI_WCCR_ADMODE_Msk (0x7UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
#define XSPI_WCCR_ADMODE XSPI_WCCR_ADMODE_Msk /*!< Address Mode */
#define XSPI_WCCR_ADMODE_0 (0x1UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
#define XSPI_WCCR_ADMODE_1 (0x2UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
#define XSPI_WCCR_ADMODE_2 (0x4UL << XSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
#define XSPI_WCCR_ADDTR_Pos (11U)
#define XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
#define XSPI_WCCR_ADDTR XSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
#define XSPI_WCCR_ADSIZE_Pos (12U)
#define XSPI_WCCR_ADSIZE_Msk (0x3UL << XSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
#define XSPI_WCCR_ADSIZE XSPI_WCCR_ADSIZE_Msk /*!< Address Size */
#define XSPI_WCCR_ADSIZE_0 (0x1UL << XSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
#define XSPI_WCCR_ADSIZE_1 (0x2UL << XSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
#define XSPI_WCCR_ABMODE_Pos (16U)
#define XSPI_WCCR_ABMODE_Msk (0x7UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
#define XSPI_WCCR_ABMODE XSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
#define XSPI_WCCR_ABMODE_0 (0x1UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
#define XSPI_WCCR_ABMODE_1 (0x2UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
#define XSPI_WCCR_ABMODE_2 (0x4UL << XSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
#define XSPI_WCCR_ABDTR_Pos (19U)
#define XSPI_WCCR_ABDTR_Msk (0x1UL << XSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
#define XSPI_WCCR_ABDTR XSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
#define XSPI_WCCR_ABSIZE_Pos (20U)
#define XSPI_WCCR_ABSIZE_Msk (0x3UL << XSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
#define XSPI_WCCR_ABSIZE XSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
#define XSPI_WCCR_ABSIZE_0 (0x1UL << XSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
#define XSPI_WCCR_ABSIZE_1 (0x2UL << XSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
#define XSPI_WCCR_DMODE_Pos (24U)
#define XSPI_WCCR_DMODE_Msk (0x7UL << XSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
#define XSPI_WCCR_DMODE XSPI_WCCR_DMODE_Msk /*!< Data Mode */
#define XSPI_WCCR_DMODE_0 (0x1UL << XSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
#define XSPI_WCCR_DMODE_1 (0x2UL << XSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
#define XSPI_WCCR_DMODE_2 (0x4UL << XSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
#define XSPI_WCCR_DDTR_Pos (27U)
#define XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
#define XSPI_WCCR_DDTR XSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
#define XSPI_WCCR_DQSE_Pos (29U)
#define XSPI_WCCR_DQSE_Msk (0x1UL << XSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
#define XSPI_WCCR_DQSE XSPI_WCCR_DQSE_Msk /*!< DQS Enable */
/**************** Bit definition for XSPI_WTCR register ******************/
#define XSPI_WTCR_DCYC_Pos (0U)
#define XSPI_WTCR_DCYC_Msk (0x1FUL << XSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
#define XSPI_WTCR_DCYC XSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
/**************** Bit definition for XSPI_WIR register *******************/
#define XSPI_WIR_INSTRUCTION_Pos (0U)
#define XSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WIR_INSTRUCTION XSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
/**************** Bit definition for XSPI_WABR register ******************/
#define XSPI_WABR_ALTERNATE_Pos (0U)
#define XSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
#define XSPI_WABR_ALTERNATE XSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
/**************** Bit definition for XSPI_HLCR register ******************/
#define XSPI_HLCR_LM_Pos (0U)
#define XSPI_HLCR_LM_Msk (0x1UL << XSPI_HLCR_LM_Pos) /*!< 0x00000001 */
#define XSPI_HLCR_LM XSPI_HLCR_LM_Msk /*!< Latency Mode */
#define XSPI_HLCR_WZL_Pos (1U)
#define XSPI_HLCR_WZL_Msk (0x1UL << XSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
#define XSPI_HLCR_WZL XSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
#define XSPI_HLCR_TACC_Pos (8U)
#define XSPI_HLCR_TACC_Msk (0xFFUL << XSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
#define XSPI_HLCR_TACC XSPI_HLCR_TACC_Msk /*!< Access Time */
#define XSPI_HLCR_TRWR_Pos (16U)
#define XSPI_HLCR_TRWR_Msk (0xFFUL << XSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
#define XSPI_HLCR_TRWR XSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
/**************** Bit definition for XSPI_CALFCR register ****************/
#define XSPI_CALFCR_FINE_Pos (0U)
#define XSPI_CALFCR_FINE_Msk (0x7FUL << XSPI_CALFCR_FINE_Pos) /*!< 0x0000007F */
#define XSPI_CALFCR_FINE XSPI_CALFCR_FINE_Msk /*!< Fine Calibration */
#define XSPI_CALFCR_COARSE_Pos (16U)
#define XSPI_CALFCR_COARSE_Msk (0x1FUL << XSPI_CALFCR_COARSE_Pos) /*!< 0x001F0000 */
#define XSPI_CALFCR_COARSE XSPI_CALFCR_COARSE_Msk /*!< Coarse Calibration */
#define XSPI_CALFCR_CALMAX_Pos (31U)
#define XSPI_CALFCR_CALMAX_Msk (0x1UL << XSPI_CALFCR_CALMAX_Pos) /*!< 0x80000000 */
#define XSPI_CALFCR_CALMAX XSPI_CALFCR_CALMAX_Msk /*!< Max Value */
/**************** Bit definition for XSPI_CALMR register *****************/
#define XSPI_CALMR_FINE_Pos (0U)
#define XSPI_CALMR_FINE_Msk (0x7FUL << XSPI_CALMR_FINE_Pos) /*!< 0x0000007F */
#define XSPI_CALMR_FINE XSPI_CALMR_FINE_Msk /*!< Fine Calibration */
#define XSPI_CALMR_COARSE_Pos (16U)
#define XSPI_CALMR_COARSE_Msk (0x1FUL << XSPI_CALMR_COARSE_Pos) /*!< 0x001F0000 */
#define XSPI_CALMR_COARSE XSPI_CALMR_COARSE_Msk /*!< Coarse Calibration */
/**************** Bit definition for XSPI_CALSOR register ****************/
#define XSPI_CALSOR_FINE_Pos (0U)
#define XSPI_CALSOR_FINE_Msk (0x7FUL << XSPI_CALSOR_FINE_Pos) /*!< 0x0000007F */
#define XSPI_CALSOR_FINE XSPI_CALSOR_FINE_Msk /*!< Fine Calibration */
#define XSPI_CALSOR_COARSE_Pos (16U)
#define XSPI_CALSOR_COARSE_Msk (0x1FUL << XSPI_CALSOR_COARSE_Pos) /*!< 0x001F0000 */
#define XSPI_CALSOR_COARSE XSPI_CALSOR_COARSE_Msk /*!< Coarse Calibration */
/**************** Bit definition for XSPI_CALSIR register ****************/
#define XSPI_CALSIR_FINE_Pos (0U)
#define XSPI_CALSIR_FINE_Msk (0x7FUL << XSPI_CALSIR_FINE_Pos) /*!< 0x0000007F */
#define XSPI_CALSIR_FINE XSPI_CALSIR_FINE_Msk /*!< Fine Calibration */
#define XSPI_CALSIR_COARSE_Pos (16U)
#define XSPI_CALSIR_COARSE_Msk (0x1FUL << XSPI_CALSIR_COARSE_Pos) /*!< 0x001F0000 */
#define XSPI_CALSIR_COARSE XSPI_CALSIR_COARSE_Msk /*!< Coarse Calibration */
/******************************************************************************/
/* */
/* XSPIM */
/* */
/******************************************************************************/
/*************** Bit definition for XSPIM_CR register ********************/
#define XSPIM_CR_MUXEN_Pos (0U)
#define XSPIM_CR_MUXEN_Msk (0x1UL << XSPIM_CR_MUXEN_Pos) /*!< 0x00000001 */
#define XSPIM_CR_MUXEN XSPIM_CR_MUXEN_Msk /*!< Multiplexed Mode Enable */
#define XSPIM_CR_MODE_Pos (1U)
#define XSPIM_CR_MODE_Msk (0x1UL << XSPIM_CR_MODE_Pos) /*!< 0x00000002 */
#define XSPIM_CR_MODE XSPIM_CR_MODE_Msk /*!< Multiplexing Mode */
#define XSPIM_CR_CSSEL_OVR_EN_Pos (4U)
#define XSPIM_CR_CSSEL_OVR_EN_Msk (0x1UL << XSPIM_CR_CSSEL_OVR_EN_Pos) /*!< 0x00000010 */
#define XSPIM_CR_CSSEL_OVR_EN XSPIM_CR_CSSEL_OVR_EN_Msk /*!< Chip Select Selector Override Enable */
#define XSPIM_CR_CSSEL_OVR_O1_Pos (5U)
#define XSPIM_CR_CSSEL_OVR_O1_Msk (0x1UL << XSPIM_CR_CSSEL_OVR_O1_Pos) /*!< 0x00000020 */
#define XSPIM_CR_CSSEL_OVR_O1 XSPIM_CR_CSSEL_OVR_O1_Msk /*!< Chip Select Selector Override Setting For XSPI1 */
#define XSPIM_CR_CSSEL_OVR_O2_Pos (6U)
#define XSPIM_CR_CSSEL_OVR_O2_Msk (0x1UL << XSPIM_CR_CSSEL_OVR_O2_Pos) /*!< 0x00000040 */
#define XSPIM_CR_CSSEL_OVR_O2 XSPIM_CR_CSSEL_OVR_O2_Msk /*!< Chip Select Selector Override Setting For XSPI2 */
#define XSPIM_CR_REQ2ACK_TIME_Pos (16U)
#define XSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */
#define XSPIM_CR_REQ2ACK_TIME XSPIM_CR_REQ2ACK_TIME_Msk /*!< REQ to ACK Time */
/** @} */ /* End of group STM32N6xx_Peripheral_declaration */
/** @addtogroup STM32N6xx_Peripheral_Exported_macros
* @{
*/
#if defined (CPU_IN_SECURE_STATE)
/* Instances allowed from Secure state */
/******************************* ADC Instances *******************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS) || \
((INSTANCE) == ADC2_S) || ((INSTANCE) == ADC2_NS))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_S) || ((INSTANCE) == ADC1_NS))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_S) || ((INSTANCE) == ADC12_COMMON_NS))
/****************************** BSEC Instances *******************************/
#define IS_BSEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == BSEC_S)
/******************************* CACHEAXI Instances ***************************/
#define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CACHEAXI_S) || ((INSTANCE) == CACHEAXI_NS))
/******************************* CRC Instances *******************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_S) || ((INSTANCE) == CRC_NS))
/******************************* DCMI Instances ******************************/
#define IS_DCMI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMI_S) || ((INSTANCE) == DCMI_NS))
/******************************* DCMIPP Instances ****************************/
#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCMIPP_S) || ((INSTANCE) == DCMIPP_NS))
/********************************* DLYB Instances ****************************/
#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_S) || ((INSTANCE) == DLYB_SDMMC1_NS) || \
((INSTANCE) == DLYB_SDMMC2_S) || ((INSTANCE) == DLYB_SDMMC2_NS))
/******************************** DMA Instances ******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
((INSTANCE) == GPDMA1_Channel2_S) || ((INSTANCE) == GPDMA1_Channel2_NS) || \
((INSTANCE) == GPDMA1_Channel3_S) || ((INSTANCE) == GPDMA1_Channel3_NS) || \
((INSTANCE) == GPDMA1_Channel4_S) || ((INSTANCE) == GPDMA1_Channel4_NS) || \
((INSTANCE) == GPDMA1_Channel5_S) || ((INSTANCE) == GPDMA1_Channel5_NS) || \
((INSTANCE) == GPDMA1_Channel6_S) || ((INSTANCE) == GPDMA1_Channel6_NS) || \
((INSTANCE) == GPDMA1_Channel7_S) || ((INSTANCE) == GPDMA1_Channel7_NS) || \
((INSTANCE) == GPDMA1_Channel8_S) || ((INSTANCE) == GPDMA1_Channel8_NS) || \
((INSTANCE) == GPDMA1_Channel9_S) || ((INSTANCE) == GPDMA1_Channel9_NS) || \
((INSTANCE) == GPDMA1_Channel10_S) || ((INSTANCE) == GPDMA1_Channel10_NS) || \
((INSTANCE) == GPDMA1_Channel11_S) || ((INSTANCE) == GPDMA1_Channel11_NS) || \
((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS))
#define IS_HPDMA_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
((INSTANCE) == HPDMA1_Channel2_S) || ((INSTANCE) == HPDMA1_Channel2_NS) || \
((INSTANCE) == HPDMA1_Channel3_S) || ((INSTANCE) == HPDMA1_Channel3_NS) || \
((INSTANCE) == HPDMA1_Channel4_S) || ((INSTANCE) == HPDMA1_Channel4_NS) || \
((INSTANCE) == HPDMA1_Channel5_S) || ((INSTANCE) == HPDMA1_Channel5_NS) || \
((INSTANCE) == HPDMA1_Channel6_S) || ((INSTANCE) == HPDMA1_Channel6_NS) || \
((INSTANCE) == HPDMA1_Channel7_S) || ((INSTANCE) == HPDMA1_Channel7_NS) || \
((INSTANCE) == HPDMA1_Channel8_S) || ((INSTANCE) == HPDMA1_Channel8_NS) || \
((INSTANCE) == HPDMA1_Channel9_S) || ((INSTANCE) == HPDMA1_Channel9_NS) || \
((INSTANCE) == HPDMA1_Channel10_S) || ((INSTANCE) == HPDMA1_Channel10_NS) || \
((INSTANCE) == HPDMA1_Channel11_S) || ((INSTANCE) == HPDMA1_Channel11_NS) || \
((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_S) || ((INSTANCE) == GPDMA1_Channel12_NS) || \
((INSTANCE) == GPDMA1_Channel13_S) || ((INSTANCE) == GPDMA1_Channel13_NS) || \
((INSTANCE) == GPDMA1_Channel14_S) || ((INSTANCE) == GPDMA1_Channel14_NS) || \
((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_S) || ((INSTANCE) == HPDMA1_Channel12_NS) || \
((INSTANCE) == HPDMA1_Channel13_S) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_S) || ((INSTANCE) == HPDMA1_Channel14_NS) || \
((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_S) || ((INSTANCE) == GPDMA1_Channel0_NS) || \
((INSTANCE) == GPDMA1_Channel1_S) || ((INSTANCE) == GPDMA1_Channel1_NS) || \
((INSTANCE) == GPDMA1_Channel15_S) || ((INSTANCE) == GPDMA1_Channel15_NS) || \
((INSTANCE) == HPDMA1_Channel0_S) || ((INSTANCE) == HPDMA1_Channel0_NS) || \
((INSTANCE) == HPDMA1_Channel1_S) || ((INSTANCE) == HPDMA1_Channel1_NS) || \
((INSTANCE) == HPDMA1_Channel15_S) || ((INSTANCE) == HPDMA1_Channel15_NS))
/******************************* DMA2D Instances *****************************/
#define IS_DMA2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA2D_S) || ((INSTANCE) == DMA2D_NS))
/******************************* DTS Instances *****************************/
#define IS_DTS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DTS_S) || ((INSTANCE) == DTS_NS))
/******************************* ETH Instances *******************************/
#define IS_ETH_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ETH1_S) || ((INSTANCE) == ETH1_NS))
/******************************* FDCAN Instances *****************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_S) || ((INSTANCE) == FDCAN1_NS) || \
((INSTANCE) == FDCAN2_S) || ((INSTANCE) == FDCAN2_NS) || \
((INSTANCE) == FDCAN3_S) || ((INSTANCE) == FDCAN3_NS))
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN_CONFIG_S) || ((INSTANCE) == FDCAN_CONFIG_NS))
#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_S)
/******************************* GFXMMU Instance *****************************/
#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_S) || ((INSTANCE) == GFXMMU_NS))
/******************************* GFXTIM Instance *****************************/
#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXTIM_S) || ((INSTANCE) == GFXTIM_NS))
/********************************* GPIO Instances ****************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_S) || ((INSTANCE) == GPIOA_NS) || \
((INSTANCE) == GPIOB_S) || ((INSTANCE) == GPIOB_NS) || \
((INSTANCE) == GPIOC_S) || ((INSTANCE) == GPIOC_NS) || \
((INSTANCE) == GPIOD_S) || ((INSTANCE) == GPIOD_NS) || \
((INSTANCE) == GPIOE_S) || ((INSTANCE) == GPIOE_NS) || \
((INSTANCE) == GPIOF_S) || ((INSTANCE) == GPIOF_NS) || \
((INSTANCE) == GPIOG_S) || ((INSTANCE) == GPIOG_NS) || \
((INSTANCE) == GPIOH_S) || ((INSTANCE) == GPIOH_NS) || \
((INSTANCE) == GPION_S) || ((INSTANCE) == GPION_NS) || \
((INSTANCE) == GPIOO_S) || ((INSTANCE) == GPIOO_NS) || \
((INSTANCE) == GPIOP_S) || ((INSTANCE) == GPIOP_NS) || \
((INSTANCE) == GPIOQ_S) || ((INSTANCE) == GPIOQ_NS))
/******************************* GPIO AF Instances ***************************/
/* All GPIO Banks support AF */
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances ****************************/
/* All GPIO Banks support the Lock mechanism */
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************* GPU2D Instances *****************************/
#define IS_GPU2D_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPU2D_BASE_S) || ((INSTANCE) == GPU2D_BASE_NS))
/******************************** I2C Instances ******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
/****************** I2C Instances : wakeup capability from stop modes ********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/******************************** I3C Instances *******************************/
#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_S) || ((INSTANCE) == I3C1_NS) || \
((INSTANCE) == I3C2_S) || ((INSTANCE) == I3C2_NS))
/****************************** IWDG Instances *******************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_S) || ((INSTANCE) == IWDG_NS))
/******************************* JPEG Instances ******************************/
#define IS_JPEG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == JPEG_S) || ((INSTANCE) == JPEG_NS))
/****************************** LTDC Instances *******************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LTDC_S) || ((INSTANCE) == LTDC_NS))
/******************************* MCE Instances *******************************/
#define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_S) || ((INSTANCE) == MCE1_NS) || \
((INSTANCE) == MCE2_S) || ((INSTANCE) == MCE2_NS) || \
((INSTANCE) == MCE3_S) || ((INSTANCE) == MCE3_NS) || \
((INSTANCE) == MCE4_S) || ((INSTANCE) == MCE4_NS))
/******************************* MDF/ADF Instances ***************************/
#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_S) || ((INSTANCE) == MDF1_Filter0_NS) || \
((INSTANCE) == MDF1_Filter1_S) || ((INSTANCE) == MDF1_Filter1_NS) || \
((INSTANCE) == MDF1_Filter2_S) || ((INSTANCE) == MDF1_Filter2_NS) || \
((INSTANCE) == MDF1_Filter3_S) || ((INSTANCE) == MDF1_Filter3_NS) || \
((INSTANCE) == MDF1_Filter4_S) || ((INSTANCE) == MDF1_Filter4_NS) || \
((INSTANCE) == MDF1_Filter5_S) || ((INSTANCE) == MDF1_Filter5_NS) || \
((INSTANCE) == ADF1_Filter0_S) || ((INSTANCE) == ADF1_Filter0_NS))
/****************************** MDIOS Instances ******************************/
#define IS_MDIOS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDIOS_S) || ((INSTANCE) == MDIOS_NS))
/******************************* PKA Instances *******************************/
#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_S) || ((INSTANCE) == PKA_NS))
/******************************* PSSI Instances ******************************/
#define IS_PSSI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PSSI_S) || ((INSTANCE) == PSSI_NS))
/****************************** RAMCFG Instances ********************************/
#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_S) || ((INSTANCE) == RAMCFG_SRAM1_AHB_NS) || \
((INSTANCE) == RAMCFG_SRAM2_AHB_S) || ((INSTANCE) == RAMCFG_SRAM2_AHB_NS) || \
((INSTANCE) == RAMCFG_SRAM1_AXI_S) || ((INSTANCE) == RAMCFG_SRAM1_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM2_AXI_S) || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM3_AXI_S) || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM4_AXI_S) || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM5_AXI_S) || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM6_AXI_S) || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS) || \
((INSTANCE) == RAMCFG_BKPSRAM_S) || ((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
((INSTANCE) == RAMCFG_FLEXRAM_S) || ((INSTANCE) == RAMCFG_FLEXRAM_NS) || \
((INSTANCE) == RAMCFG_VENC_RAM_S) || ((INSTANCE) == RAMCFG_VENC_RAM_NS))
/***************************** RAMCFG ECC Instances *****************************/
#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_S) || ((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
((INSTANCE) == RAMCFG_FLEXRAM_S) || ((INSTANCE) == RAMCFG_FLEXRAM_NS))
/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_S) || ((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM3_AXI_S) || ((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM4_AXI_S) || ((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM5_AXI_S) || ((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM6_AXI_S) || ((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
/******************************* RNG Instances *******************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_S) || ((INSTANCE) == RNG_NS))
/******************************* RTC Instances *******************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_S) || ((INSTANCE) == RTC_NS))
/******************************** SAI Instances ******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_S) || ((INSTANCE) == SAI1_Block_A_NS) || \
((INSTANCE) == SAI1_Block_B_S) || ((INSTANCE) == SAI1_Block_B_NS) || \
((INSTANCE) == SAI2_Block_A_S) || ((INSTANCE) == SAI2_Block_A_NS) || \
((INSTANCE) == SAI2_Block_B_S) || ((INSTANCE) == SAI2_Block_B_NS))
/******************************* SDMMC Instances *****************************/
#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_S) || ((INSTANCE) == SDMMC1_NS) || \
((INSTANCE) == SDMMC2_S) || ((INSTANCE) == SDMMC2_NS))
/******************************** SMBUS Instances ****************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_S) || ((INSTANCE) == I2C1_NS) || \
((INSTANCE) == I2C2_S) || ((INSTANCE) == I2C2_NS) || \
((INSTANCE) == I2C3_S) || ((INSTANCE) == I2C3_NS) || \
((INSTANCE) == I2C4_S) || ((INSTANCE) == I2C4_NS))
/****************************** SPDIFRX Instances ****************************/
#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPDIFRX_S) || ((INSTANCE) == SPDIFRX_NS))
/******************************** SPI Instances ******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS) || \
((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_S) || ((INSTANCE) == SPI4_NS) || \
((INSTANCE) == SPI5_S) || ((INSTANCE) == SPI5_NS))
/******************************** I2S Instances ******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_S) || ((INSTANCE) == SPI1_NS) || \
((INSTANCE) == SPI2_S) || ((INSTANCE) == SPI2_NS) || \
((INSTANCE) == SPI3_S) || ((INSTANCE) == SPI3_NS) || \
((INSTANCE) == SPI6_S) || ((INSTANCE) == SPI6_NS))
/****************************** UCPD Instances *******************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_S) || ((INSTANCE) == UCPD1_NS))
/******************************* OTG HS HCD Instances *************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
/******************************* OTG HS PCD Instances *************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS_S) || ((INSTANCE) == USB1_OTG_HS_NS) || \
((INSTANCE) == USB2_OTG_HS_S) || ((INSTANCE) == USB2_OTG_HS_NS))
/******************************* USB HS PHY Instances *************************/
#define IS_USBPHYC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_HS_PHYC_S) || ((INSTANCE) == USB1_HS_PHYC_NS) || \
((INSTANCE) == USB2_HS_PHYC_S) || ((INSTANCE) == USB2_HS_PHYC_NS))
/******************** USART Instances : Synchronous mode *********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
/******************** UART Instances : Asynchronous mode *********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
/*********************** UART Instances : FIFO mode **************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
/****************** UART Instances : Driver Enable ***************************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
/****************** UART Instances : Hardware Flow control *******************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
/******************** UART Instances : LIN mode ******************************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_S) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_S) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_S) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_S) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_S) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_S) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_S) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_S) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_S))
/******************** UART Instances : Wake-up from Stop mode ****************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
/*********************** UART Instances : IRDA mode **************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_S) || ((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_S) || ((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_S) || ((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_S) || ((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_S) || ((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
/********************* USART Instances : Smard card mode *********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_S) || ((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_S) || ((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_S) || ((INSTANCE) == USART3_NS) || \
((INSTANCE) == USART6_S) || ((INSTANCE) == USART6_NS) || \
((INSTANCE) == USART10_S) || ((INSTANCE) == USART10_NS))
/******************** LPUART Instance ****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_S) || ((INSTANCE) == LPUART1_NS))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
/****************** LPTIM Instances : DMA supported instances *****************/
#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
/************* LPTIM Instances : at least 1 capture/compare channel ***********/
#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS) || \
((INSTANCE) == LPTIM4_S) || ((INSTANCE) == LPTIM4_NS) || \
((INSTANCE) == LPTIM5_S) || ((INSTANCE) == LPTIM5_NS))
/************* LPTIM Instances : at least 2 capture/compare channel ***********/
#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
/****************** LPTIM Instances : supporting Input Capture **************/
#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_S) || ((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_S) || ((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_S) || ((INSTANCE) == LPTIM3_NS))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM6_S) || ((INSTANCE) == TIM6_NS) || \
((INSTANCE) == TIM7_S) || ((INSTANCE) == TIM7_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS) || \
((INSTANCE) == TIM18_S) || ((INSTANCE) == TIM18_NS))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM6_S) || ((INSTANCE) == TIM6_NS) || \
((INSTANCE) == TIM7_S) || ((INSTANCE) == TIM7_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
(((((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
((((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
((((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
((((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
((((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
((((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
((((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
((((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
((((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
((((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
((((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
((((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM15_S) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
((((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
((((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
(((((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
((((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS)) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
((((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS)) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
((((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS)) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
((((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS)) && \
((CHANNEL) == TIM_CHANNEL_1)))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM6_S) || ((INSTANCE) == TIM6_NS) || \
((INSTANCE) == TIM7_S) || ((INSTANCE) == TIM7_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_S) || ((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_S) || ((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_S) || ((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM5_S) || ((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM9_S) || ((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM10_S) || ((INSTANCE) == TIM10_NS) || \
((INSTANCE) == TIM11_S) || ((INSTANCE) == TIM11_NS) || \
((INSTANCE) == TIM12_S) || ((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM13_S) || ((INSTANCE) == TIM13_NS) || \
((INSTANCE) == TIM14_S) || ((INSTANCE) == TIM14_NS) || \
((INSTANCE) == TIM15_S) || ((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_S) || ((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_S) || ((INSTANCE) == TIM17_NS))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_S) || ((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_S) || ((INSTANCE) == TIM8_NS))
/****************************** WWDG Instances *******************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_S) || ((INSTANCE) == WWDG_NS))
/******************************** XSPI Instances *****************************/
#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_S) || ((INSTANCE) == XSPI1_NS) || \
((INSTANCE) == XSPI2_S) || ((INSTANCE) == XSPI2_NS) || \
((INSTANCE) == XSPI3_S) || ((INSTANCE) == XSPI3_NS))
/****************************** XSPIM Instances ***************************/
#define IS_XSPIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPIM_S) || ((INSTANCE) == XSPIM_NS))
#else
/* Instances allowed from Non-Secure state - only alias Non-Secure */
/******************************* ADC Instances *******************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \
((INSTANCE) == ADC2_NS))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_NS)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON_NS)
/******************************* CACHEAXI Instances ***************************/
#define IS_CACHEAXI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CACHEAXI_NS)
/******************************* CRC Instances *******************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC_NS)
/******************************* DCMI Instances ******************************/
#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI_NS)
/******************************* DCMIPP Instances ****************************/
#define IS_DCMIPP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMIPP_NS)
/******************************* DLYB Instances ****************************/
#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \
((INSTANCE) == DLYB_SDMMC2_NS))
/******************************** DMA Instances ******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
((INSTANCE) == GPDMA1_Channel1_NS) || \
((INSTANCE) == GPDMA1_Channel2_NS) || \
((INSTANCE) == GPDMA1_Channel3_NS) || \
((INSTANCE) == GPDMA1_Channel4_NS) || \
((INSTANCE) == GPDMA1_Channel5_NS) || \
((INSTANCE) == GPDMA1_Channel6_NS) || \
((INSTANCE) == GPDMA1_Channel7_NS) || \
((INSTANCE) == GPDMA1_Channel8_NS) || \
((INSTANCE) == GPDMA1_Channel9_NS) || \
((INSTANCE) == GPDMA1_Channel10_NS) || \
((INSTANCE) == GPDMA1_Channel11_NS) || \
((INSTANCE) == GPDMA1_Channel12_NS) || \
((INSTANCE) == GPDMA1_Channel13_NS) || \
((INSTANCE) == GPDMA1_Channel14_NS) || \
((INSTANCE) == GPDMA1_Channel15_NS) || \
((INSTANCE) == HPDMA1_Channel0_NS) || \
((INSTANCE) == HPDMA1_Channel1_NS) || \
((INSTANCE) == HPDMA1_Channel2_NS) || \
((INSTANCE) == HPDMA1_Channel3_NS) || \
((INSTANCE) == HPDMA1_Channel4_NS) || \
((INSTANCE) == HPDMA1_Channel5_NS) || \
((INSTANCE) == HPDMA1_Channel6_NS) || \
((INSTANCE) == HPDMA1_Channel7_NS) || \
((INSTANCE) == HPDMA1_Channel8_NS) || \
((INSTANCE) == HPDMA1_Channel9_NS) || \
((INSTANCE) == HPDMA1_Channel10_NS) || \
((INSTANCE) == HPDMA1_Channel11_NS) || \
((INSTANCE) == HPDMA1_Channel12_NS) || \
((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_NS) || \
((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
((INSTANCE) == GPDMA1_Channel1_NS) || \
((INSTANCE) == GPDMA1_Channel2_NS) || \
((INSTANCE) == GPDMA1_Channel3_NS) || \
((INSTANCE) == GPDMA1_Channel4_NS) || \
((INSTANCE) == GPDMA1_Channel5_NS) || \
((INSTANCE) == GPDMA1_Channel6_NS) || \
((INSTANCE) == GPDMA1_Channel7_NS) || \
((INSTANCE) == GPDMA1_Channel8_NS) || \
((INSTANCE) == GPDMA1_Channel9_NS) || \
((INSTANCE) == GPDMA1_Channel10_NS) || \
((INSTANCE) == GPDMA1_Channel11_NS) || \
((INSTANCE) == GPDMA1_Channel12_NS) || \
((INSTANCE) == GPDMA1_Channel13_NS) || \
((INSTANCE) == GPDMA1_Channel14_NS) || \
((INSTANCE) == GPDMA1_Channel15_NS))
#define IS_HPDMA_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel0_NS) || \
((INSTANCE) == HPDMA1_Channel1_NS) || \
((INSTANCE) == HPDMA1_Channel2_NS) || \
((INSTANCE) == HPDMA1_Channel3_NS) || \
((INSTANCE) == HPDMA1_Channel4_NS) || \
((INSTANCE) == HPDMA1_Channel5_NS) || \
((INSTANCE) == HPDMA1_Channel6_NS) || \
((INSTANCE) == HPDMA1_Channel7_NS) || \
((INSTANCE) == HPDMA1_Channel8_NS) || \
((INSTANCE) == HPDMA1_Channel9_NS) || \
((INSTANCE) == HPDMA1_Channel10_NS) || \
((INSTANCE) == HPDMA1_Channel11_NS) || \
((INSTANCE) == HPDMA1_Channel12_NS) || \
((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_NS) || \
((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || \
((INSTANCE) == GPDMA1_Channel13_NS) || \
((INSTANCE) == GPDMA1_Channel14_NS) || \
((INSTANCE) == GPDMA1_Channel15_NS) || \
((INSTANCE) == HPDMA1_Channel12_NS) || \
((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_NS) || \
((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_DMA_LIMIT_INSTANCE(INSTANCE) (((INSTANCE) == HPDMA1_Channel12_NS) || ((INSTANCE) == HPDMA1_Channel13_NS) || \
((INSTANCE) == HPDMA1_Channel14_NS) || ((INSTANCE) == HPDMA1_Channel15_NS))
#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || \
((INSTANCE) == GPDMA1_Channel1_NS) || \
((INSTANCE) == GPDMA1_Channel15_NS) || \
((INSTANCE) == HPDMA1_Channel0_NS) || \
((INSTANCE) == HPDMA1_Channel1_NS) || \
((INSTANCE) == HPDMA1_Channel15_NS))
/******************************* DMA2D Instances *****************************/
#define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D_NS)
/******************************* DTS Instances *****************************/
#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS_NS)
/******************************* ETH Instances *******************************/
#define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH1_NS)
/******************************* FDCAN Instances *****************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || \
((INSTANCE) == FDCAN2_NS) || \
((INSTANCE) == FDCAN3_NS))
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_NS)
/******************************* GFXMMU Instance *****************************/
#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU_NS)
/******************************* GFXTIM Instance *****************************/
#define IS_GFXTIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXTIM_NS)
/********************************* GPIO Instances ****************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || \
((INSTANCE) == GPIOB_NS) || \
((INSTANCE) == GPIOC_NS) || \
((INSTANCE) == GPIOD_NS) || \
((INSTANCE) == GPIOE_NS) || \
((INSTANCE) == GPIOF_NS) || \
((INSTANCE) == GPIOG_NS) || \
((INSTANCE) == GPIOH_NS) || \
((INSTANCE) == GPION_NS) || \
((INSTANCE) == GPIOO_NS) || \
((INSTANCE) == GPIOP_NS) || \
((INSTANCE) == GPIOQ_NS))
/******************************* GPIO AF Instances ***************************/
/* All GPIO Banks support AF */
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances ****************************/
/* All GPIO Banks support the Lock mechanism */
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************* GPU2D Instances *****************************/
#define IS_GPU2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GPU2D_BASE_NS)
/******************************** I2C Instances ******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
((INSTANCE) == I2C2_NS) || \
((INSTANCE) == I2C3_NS) || \
((INSTANCE) == I2C4_NS))
/****************** I2C Instances : wakeup capability from stop modes ********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/******************************** I3C Instances *******************************/
#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || \
((INSTANCE) == I3C2_NS))
/****************************** IWDG Instances *******************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG_NS)
/******************************* JPEG Instances ******************************/
#define IS_JPEG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == JPEG_NS)
/****************************** LTDC Instances *******************************/
#define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC_NS)
/******************************* MCE Instances *******************************/
#define IS_MCE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MCE1_NS) || \
((INSTANCE) == MCE2_NS) || \
((INSTANCE) == MCE3_NS) || \
((INSTANCE) == MCE4_NS))
/******************************* MDF/ADF Instances ***************************/
#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || \
((INSTANCE) == MDF1_Filter1_NS) || \
((INSTANCE) == MDF1_Filter2_NS) || \
((INSTANCE) == MDF1_Filter3_NS) || \
((INSTANCE) == MDF1_Filter4_NS) || \
((INSTANCE) == MDF1_Filter5_NS) || \
((INSTANCE) == ADF1_Filter0_NS))
/****************************** MDIOS Instances ******************************/
#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS_NS)
/******************************* PKA Instances *******************************/
#define IS_PKA_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PKA_NS)
/******************************* PSSI Instances ******************************/
#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI_NS)
/****************************** RAMCFG Instances ********************************/
#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_AHB_NS) || \
((INSTANCE) == RAMCFG_SRAM2_AHB_NS) || \
((INSTANCE) == RAMCFG_SRAM1_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM6_AXI_NS) || \
((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
((INSTANCE) == RAMCFG_FLEXRAM_NS) || \
((INSTANCE) == RAMCFG_VENC_RAM_NS))
/***************************** RAMCFG ECC Instances *****************************/
#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_BKPSRAM_NS) || \
((INSTANCE) == RAMCFG_FLEXRAM_NS))
/***************************** RAMCFG AXISRAM POWERDOWN Instances ***************/
#define IS_RAMCFG_AXISRAM_POWERDOWN_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM3_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM4_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM5_AXI_NS) || \
((INSTANCE) == RAMCFG_SRAM6_AXI_NS))
/******************************* RNG Instances *******************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG_NS)
/******************************* RTC Instances *******************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC_NS)
/******************************** SAI Instances ******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || \
((INSTANCE) == SAI1_Block_B_NS) || \
((INSTANCE) == SAI2_Block_A_NS) || \
((INSTANCE) == SAI2_Block_B_NS))
/******************************* SDMMC Instances *****************************/
#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || \
((INSTANCE) == SDMMC2_NS))
/******************************** SMBUS Instances ****************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || \
((INSTANCE) == I2C2_NS) || \
((INSTANCE) == I2C3_NS) || \
((INSTANCE) == I2C4_NS))
/****************************** SPDIFRX Instances ****************************/
#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX_NS)
/******************************** SPI Instances ******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
((INSTANCE) == SPI2_NS) || \
((INSTANCE) == SPI3_NS) || \
((INSTANCE) == SPI4_NS) || \
((INSTANCE) == SPI5_NS) || \
((INSTANCE) == SPI6_NS))
#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
((INSTANCE) == SPI2_NS) || \
((INSTANCE) == SPI3_NS) || \
((INSTANCE) == SPI6_NS))
#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || \
((INSTANCE) == SPI5_NS))
/******************************** I2S Instances ******************************/
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || \
((INSTANCE) == SPI2_NS) || \
((INSTANCE) == SPI3_NS) || \
((INSTANCE) == SPI6_NS))
/****************************** UCPD Instances *******************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1_NS)
/******************** USART Instances : Synchronous mode *********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == USART10_NS))
/******************** UART Instances : Asynchronous mode *********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS))
/*********************** UART Instances : FIFO mode **************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_NS))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == USART10_NS))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS))
/****************** UART Instances : Driver Enable ***************************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_NS))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_NS))
/****************** UART Instances : Hardware Flow control *******************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_NS))
/******************** UART Instances : LIN mode ******************************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS))
/******************** UART Instances : Wake-up from Stop mode ****************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS) || \
((INSTANCE) == LPUART1_NS))
/*********************** UART Instances : IRDA mode **************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == UART4_NS) || \
((INSTANCE) == UART5_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == UART7_NS) || \
((INSTANCE) == UART8_NS) || \
((INSTANCE) == UART9_NS) || \
((INSTANCE) == USART10_NS))
/********************* USART Instances : Smard card mode *********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || \
((INSTANCE) == USART2_NS) || \
((INSTANCE) == USART3_NS) || \
((INSTANCE) == USART6_NS) || \
((INSTANCE) == USART10_NS))
/******************** LPUART Instance ****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1_NS)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_NS) || \
((INSTANCE) == LPTIM4_NS) || \
((INSTANCE) == LPTIM5_NS))
/****************** LPTIM Instances : DMA supported instances *****************/
#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_NS))
/************* LPTIM Instances : at least 1 capture/compare channel ***********/
#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_NS) || \
((INSTANCE) == LPTIM4_NS) || \
((INSTANCE) == LPTIM5_NS))
/************* LPTIM Instances : at least 2 capture/compare channel ***********/
#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_NS))
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_NS))
/****************** LPTIM Instances : supporting Input Capture **************/
#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || \
((INSTANCE) == LPTIM2_NS) || \
((INSTANCE) == LPTIM3_NS))
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM6_NS) || \
((INSTANCE) == TIM7_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM10_NS) || \
((INSTANCE) == TIM11_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM13_NS) || \
((INSTANCE) == TIM14_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS) || \
((INSTANCE) == TIM18_NS))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM10_NS) || \
((INSTANCE) == TIM11_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM13_NS) || \
((INSTANCE) == TIM14_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM6_NS) || \
((INSTANCE) == TIM7_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS) || \
((INSTANCE) == TIM18_NS))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM5_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM9_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM10_NS) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM11_NS) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM12_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM13_NS) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM14_NS) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM15_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16_NS) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17_NS) && \
(((CHANNEL) == TIM_CHANNEL_1))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8_NS) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15_NS) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16_NS) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17_NS) && \
((CHANNEL) == TIM_CHANNEL_1)))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM6_NS) || \
((INSTANCE) == TIM7_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM4_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM8_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM15_NS))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || \
((INSTANCE) == TIM3_NS) || \
((INSTANCE) == TIM5_NS) || \
((INSTANCE) == TIM9_NS) || \
((INSTANCE) == TIM10_NS) || \
((INSTANCE) == TIM11_NS) || \
((INSTANCE) == TIM12_NS) || \
((INSTANCE) == TIM13_NS) || \
((INSTANCE) == TIM14_NS) || \
((INSTANCE) == TIM15_NS) || \
((INSTANCE) == TIM16_NS) || \
((INSTANCE) == TIM17_NS))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || \
((INSTANCE) == TIM8_NS))
/****************************** WWDG Instances *******************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG_NS)
/******************************** XSPI Instances *****************************/
#define IS_XSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == XSPI1_NS) || \
((INSTANCE) == XSPI2_NS) || \
((INSTANCE) == XSPI3_NS))
/****************************** XSPIM Instances ***************************/
#define IS_XSPIM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == XSPIM_NS)
#endif
/** @} */ /* End of group STM32N6xx_Peripheral_Exported_macros */
/** @} */ /* End of group STM32N657xx */
/** @} */ /* End of group ST */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32N657xx_H */