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96 lines
2.9 KiB
C
96 lines
2.9 KiB
C
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file DPHY_Private.h
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* @author Prasanna Ravi
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* @email prasanna.ravi@alifsemi.com
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* @version V1.0.0
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* @date 24-Feb-2022
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* @brief Driver Specific Header file for DPHY Driver.
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******************************************************************************/
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#ifndef DPHY_PRIVATE_H_
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#define DPHY_PRIVATE_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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/*Helper macro*/
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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/**
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* enum DPHY_STOPSTATE
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* DPHY physical lanes stop state status
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*/
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typedef enum _DPHY_STOPSTATE {
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DPHY_STOPSTATE_LANE0 = (1U << 0), /**< DPHY lane 0 stopstate status */
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DPHY_STOPSTATE_LANE1 = (1U << 1), /**< DPHY lane 1 stopstate status */
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DPHY_STOPSTATE_CLOCK = (1U << 2), /**< DPHY lane clock stopstate status */
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} DPHY_STOPSTATE;
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/**
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* enum DPHY_PLL_STATUS
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* DPHY PLL lock status
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*/
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typedef enum _DPHY_PLL_STATUS {
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DPHY_PLL_STATUS_NO_PLL_LOCK, /**< DPHY status locked */
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DPHY_PLL_STATUS_PLL_LOCK, /**< DPHY status not locked */
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} DPHY_PLL_STATUS;
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/**
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* enum DPHY_INIT_STATUS
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* DPHY initialization status
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*/
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typedef enum _DPHY_INIT_STATUS {
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DPHY_INIT_STATUS_UNINITIALIZED, /**< DPHY driver uinitialized */
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DPHY_INIT_STATUS_INITIALIZED, /**< DPHY driver initialized */
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}DPHY_INIT_STATUS;
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/**
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* enum DPHY_MODE_CFG
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* DPHY mode(CIS2/DSI)
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*/
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typedef enum _DPHY_MODE_CFG {
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DPHY_MODE_CFG_DSI, /**< DPHY mode DSI */
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DPHY_MODE_CFG_CSI2, /**< DPHY mode CSI2 */
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}DPHY_MODE_CFG;
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/** \brief hsfreqrange and osc_freq_target range */
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typedef struct _DPHY_FREQ_RANGE {
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uint16_t bitrate_in_mbps; /**< DPHY data rate in mbps */
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uint8_t hsfreqrange; /**< DPHY HS frequency range */
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uint16_t osc_freq_target; /**< DPHY oscillator frequency target */
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}DPHY_FREQ_RANGE;
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/** \brief PLL vco_cntrl range */
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typedef struct _DPHY_PLL_VCO_CTRL {
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float frequency_mhz; /**< DPHY frequency in MHZ */
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int8_t vco_ctrl; /**< DPHY VCO control */
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}DPHY_PLL_VCO_CTRL;
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/**
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\brief PLL Output division factor range
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*/
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typedef struct _DPHY_PLL_OUTPUT_DIVISION_FACTOR {
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float frequency_mhz; /**< DPHY frequency in MHZ */
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int8_t p; /**< DPHY output division factor*/
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}DPHY_PLL_OUTPUT_DIVISION_FACTOR;
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#ifdef __cplusplus
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}
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#endif
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#endif /* DPHY_PRIVATE_H_ */
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