mirror of
https://github.com/openmv/openmv.git
synced 2025-11-04 14:49:50 +08:00
581 lines
16 KiB
C
581 lines
16 KiB
C
#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include "stm32f4xx_hal.h"
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#include "sccb.h"
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#include "ov2640.h"
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#include "systick.h"
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#include "ov2640_regs.h"
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#define SVGA_HSIZE (800)
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#define SVGA_VSIZE (600)
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#define UXGA_HSIZE (1600)
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#define UXGA_VSIZE (1200)
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static const uint8_t default_regs[][2] = {
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{ BANK_SEL, BANK_SEL_DSP },
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{ 0x2c, 0xff },
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{ 0x2e, 0xdf },
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{ BANK_SEL, BANK_SEL_SENSOR },
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{ 0x3c, 0x32 },
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{ CLKRC, 0x80 }, /* Set PCLK divider */
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{ COM2, COM2_OUT_DRIVE_3x }, /* Output drive x2 */
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{ REG04, REG04_SET(REG04_HREF_EN)}, /* Mirror/VFLIP/AEC[1:0] */
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{ COM8, COM8_SET(COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN) },
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{ COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
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{ 0x2c, 0x0c },
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{ 0x33, 0x78 },
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{ 0x3a, 0x33 },
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{ 0x3b, 0xfb },
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{ 0x3e, 0x00 },
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{ 0x43, 0x11 },
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{ 0x16, 0x10 },
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{ 0x39, 0x02 },
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{ 0x35, 0x88 },
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{ 0x22, 0x0a },
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{ 0x37, 0x40 },
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{ 0x23, 0x00 },
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{ ARCOM2, 0xa0 },
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{ 0x06, 0x02 },
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{ 0x06, 0x88 },
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{ 0x07, 0xc0 },
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{ 0x0d, 0xb7 },
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{ 0x0e, 0x01 },
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{ 0x4c, 0x00 },
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{ 0x4a, 0x81 },
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{ 0x21, 0x99 },
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{ AEW, 0x40 },
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{ AEB, 0x38 },
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/* AGC/AEC fast mode operating region */
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{ VV, VV_AGC_TH_SET(0x08, 0x02) },
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{ COM19, 0x00 }, /* Zoom control 2 MSBs */
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{ ZOOMS, 0x00 }, /* Zoom control 8 MSBs */
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{ 0x5c, 0x00 },
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{ 0x63, 0x00 },
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{ FLL, 0x00 },
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{ FLH, 0x00 },
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/* Set banding filter */
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{ COM3, COM3_BAND_SET(COM3_BAND_AUTO) },
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{ REG5D, 0x55 },
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{ REG5E, 0x7d },
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{ REG5F, 0x7d },
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{ REG60, 0x55 },
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{ HISTO_LOW, 0x70 },
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{ HISTO_HIGH, 0x80 },
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{ 0x7c, 0x05 },
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{ 0x20, 0x80 },
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{ 0x28, 0x30 },
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{ 0x6c, 0x00 },
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{ 0x6d, 0x80 },
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{ 0x6e, 0x00 },
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{ 0x70, 0x02 },
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{ 0x71, 0x94 },
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{ 0x73, 0xc1 },
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{ 0x3d, 0x34 },
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//{ COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
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{ 0x5a, 0x57 },
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{ BD50, 0xbb },
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{ BD60, 0x9c },
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{ BANK_SEL, BANK_SEL_DSP },
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{ 0xe5, 0x7f },
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{ MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
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{ 0x41, 0x24 },
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{ RESET, RESET_JPEG | RESET_DVP },
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{ 0x76, 0xff },
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{ 0x33, 0xa0 },
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{ 0x42, 0x20 },
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{ 0x43, 0x18 },
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{ 0x4c, 0x00 },
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{ CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
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{ 0x88, 0x3f },
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{ 0xd7, 0x03 },
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{ 0xd9, 0x10 },
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{ R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 },
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{ 0xc8, 0x08 },
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{ 0xc9, 0x80 },
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{ BPADDR, 0x00 },
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{ BPDATA, 0x00 },
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{ BPADDR, 0x03 },
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{ BPDATA, 0x48 },
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{ BPDATA, 0x48 },
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{ BPADDR, 0x08 },
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{ BPDATA, 0x20 },
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{ BPDATA, 0x10 },
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{ BPDATA, 0x0e },
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{ 0x90, 0x00 },
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{ 0x91, 0x0e },
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{ 0x91, 0x1a },
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{ 0x91, 0x31 },
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{ 0x91, 0x5a },
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{ 0x91, 0x69 },
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{ 0x91, 0x75 },
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{ 0x91, 0x7e },
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{ 0x91, 0x88 },
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{ 0x91, 0x8f },
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{ 0x91, 0x96 },
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{ 0x91, 0xa3 },
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{ 0x91, 0xaf },
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{ 0x91, 0xc4 },
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{ 0x91, 0xd7 },
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{ 0x91, 0xe8 },
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{ 0x91, 0x20 },
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{ 0x92, 0x00 },
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{ 0x93, 0x06 },
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{ 0x93, 0xe3 },
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{ 0x93, 0x03 },
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{ 0x93, 0x03 },
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{ 0x93, 0x00 },
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{ 0x93, 0x02 },
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{ 0x93, 0x00 },
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{ 0x93, 0x00 },
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{ 0x93, 0x00 },
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{ 0x93, 0x00 },
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{ 0x93, 0x00 },
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{ 0x93, 0x00 },
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{ 0x93, 0x00 },
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{ 0x96, 0x00 },
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{ 0x97, 0x08 },
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{ 0x97, 0x19 },
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{ 0x97, 0x02 },
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{ 0x97, 0x0c },
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{ 0x97, 0x24 },
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{ 0x97, 0x30 },
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{ 0x97, 0x28 },
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{ 0x97, 0x26 },
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{ 0x97, 0x02 },
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{ 0x97, 0x98 },
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{ 0x97, 0x80 },
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{ 0x97, 0x00 },
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{ 0x97, 0x00 },
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{ 0xa4, 0x00 },
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{ 0xa8, 0x00 },
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{ 0xc5, 0x11 },
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{ 0xc6, 0x51 },
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{ 0xbf, 0x80 },
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{ 0xc7, 0x10 },
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{ 0xb6, 0x66 },
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{ 0xb8, 0xA5 },
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{ 0xb7, 0x64 },
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{ 0xb9, 0x7C },
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{ 0xb3, 0xaf },
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{ 0xb4, 0x97 },
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{ 0xb5, 0xFF },
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{ 0xb0, 0xC5 },
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{ 0xb1, 0x94 },
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{ 0xb2, 0x0f },
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{ 0xc4, 0x5c },
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{ 0xa6, 0x00 },
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{ 0xa7, 0x20 },
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{ 0xa7, 0xd8 },
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{ 0xa7, 0x1b },
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{ 0xa7, 0x31 },
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{ 0xa7, 0x00 },
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{ 0xa7, 0x18 },
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{ 0xa7, 0x20 },
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{ 0xa7, 0xd8 },
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{ 0xa7, 0x19 },
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{ 0xa7, 0x31 },
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{ 0xa7, 0x00 },
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{ 0xa7, 0x18 },
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{ 0xa7, 0x20 },
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{ 0xa7, 0xd8 },
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{ 0xa7, 0x19 },
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{ 0xa7, 0x31 },
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{ 0xa7, 0x00 },
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{ 0xa7, 0x18 },
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{ 0x7f, 0x00 },
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{ 0xe5, 0x1f },
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{ 0xe1, 0x77 },
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{ 0xdd, 0x7f },
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{ CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
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{ 0x00, 0x00 }
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};
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static const uint8_t cif_regs[][2] = {
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};
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static const uint8_t svga_regs[][2] = {
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{ BANK_SEL, BANK_SEL_SENSOR },
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/* DSP input image resoultion and window size control */
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{ COM7, COM7_RES_SVGA},
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{ COM1, 0x0A }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
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{ REG32, 0x09 }, /* UXGA=0x36, SVGA/CIF=0x09 */
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{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIS=0x11 */
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{ HSTOP, 0x43 }, /* UXGA=0x75, SVGA/CIF=0x43 */
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{ VSTART, 0x00 }, /* UXGA=0x01, SVGA/CIF=0x00 */
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{ VSTOP, 0x4b }, /* UXGA=0x97, SVGA/CIS=0x4b */
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{ 0x3d, 0x38 }, /* UXGA=0x34, SVGA/CIF=0x38 */
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{ 0x35, 0xda },
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{ 0x22, 0x1a },
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{ 0x37, 0xc3 },
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{ 0x34, 0xc0 },
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{ 0x06, 0x88 },
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{ 0x0d, 0x87 },
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{ 0x0e, 0x41 },
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{ 0x42, 0x03 },
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/* Set DSP input image size and offset.
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The sensor output image can be scaled with OUTW/OUTH */
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{ BANK_SEL, BANK_SEL_DSP },
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{ R_BYPASS, R_BYPASS_DSP_BYPAS },
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{ RESET, RESET_DVP },
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{ HSIZE8, (SVGA_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
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{ VSIZE8, (SVGA_VSIZE>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
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/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
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{ SIZEL, ((SVGA_HSIZE>>6)&0x40) | ((SVGA_HSIZE&0x7)<<3) | (SVGA_VSIZE&0x7)},
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{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
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{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
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{ HSIZE, ((SVGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0]= HSIZE/4 */
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{ VSIZE, ((SVGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0]= VSIZE/4 */
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/* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
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{ VHYX, ((SVGA_VSIZE>>3)&0x80) | ((SVGA_HSIZE>>7)&0x08) },
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{ TEST, (SVGA_HSIZE>>4)&0x80}, /* H_SIZE[9] */
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{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
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CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
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/* H_DIVIDER/V_DIVIDER */
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{ CTRLI, CTRLI_LP_DP | 0x00},
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/* DVP prescalar */
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{ R_DVP_SP, R_DVP_SP_AUTO_MODE},
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{ R_BYPASS, R_BYPASS_DSP_EN },
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{ RESET, 0x00 },
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{0, 0},
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};
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static const uint8_t uxga_regs[][2] = {
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{ BANK_SEL, BANK_SEL_SENSOR },
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/* DSP input image resoultion and window size control */
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{ COM7, COM7_RES_UXGA},
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{ COM1, 0x0F }, /* UXGA=0x0F, SVGA=0x0A, CIF=0x06 */
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{ REG32, 0x36 }, /* UXGA=0x36, SVGA/CIF=0x09 */
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{ HSTART, 0x11 }, /* UXGA=0x11, SVGA/CIS=0x11 */
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{ HSTOP, 0x75 }, /* UXGA=0x75, SVGA/CIF=0x43 */
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{ VSTART, 0x01 }, /* UXGA=0x01, SVGA/CIF=0x00 */
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{ VSTOP, 0x97 }, /* UXGA=0x97, SVGA/CIS=0x4b */
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{ 0x3d, 0x34 }, /* UXGA=0x34, SVGA/CIF=0x38 */
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{ 0x35, 0x88 },
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{ 0x22, 0x0a },
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{ 0x37, 0x40 },
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{ 0x34, 0xa0 },
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{ 0x06, 0x02 },
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{ 0x0d, 0xb7 },
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{ 0x0e, 0x01 },
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{ 0x42, 0x83 },
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/* Set DSP input image size and offset.
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The sensor output image can be scaled with OUTW/OUTH */
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{ BANK_SEL, BANK_SEL_DSP },
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{ R_BYPASS, R_BYPASS_DSP_BYPAS },
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{ RESET, RESET_DVP },
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{ HSIZE8, (UXGA_HSIZE>>3)}, /* Image Horizontal Size HSIZE[10:3] */
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{ VSIZE8, (UXGA_VSIZE>>3)}, /* Image Vertiacl Size VSIZE[10:3] */
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/* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
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{ SIZEL, ((SVGA_HSIZE>>6)&0x40) | ((UXGA_HSIZE&0x7)<<3) | (UXGA_VSIZE&0x7)},
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{ XOFFL, 0x00 }, /* OFFSET_X[7:0] */
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{ YOFFL, 0x00 }, /* OFFSET_Y[7:0] */
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{ HSIZE, ((UXGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
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{ VSIZE, ((UXGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
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/* V_SIZE[8]/OFFSET_Y[10:8]/H_SIZE[8]/OFFSET_X[10:8] */
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{ VHYX, ((UXGA_VSIZE>>3)&0x80) | ((UXGA_HSIZE>>7)&0x08) },
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{ TEST, (UXGA_HSIZE>>4)&0x80}, /* H_SIZE[9] */
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{ CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
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CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
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/* H_DIVIDER/V_DIVIDER */
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{ CTRLI, CTRLI_LP_DP | 0x00},
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/* DVP prescalar */
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{ R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x04},
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{ R_BYPASS, R_BYPASS_DSP_EN },
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{ RESET, 0x00 },
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{0, 0},
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};
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static const uint8_t yuv422_regs[][2] = {
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{ BANK_SEL, BANK_SEL_DSP },
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{ RESET, RESET_DVP},
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{ IMAGE_MODE, IMAGE_MODE_YUV422 },
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{ 0xD7, 0x01 },
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{ 0xE1, 0x67 },
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{ RESET, 0x00 },
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{0, 0},
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};
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static const uint8_t rgb565_regs[][2] = {
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{ BANK_SEL, BANK_SEL_DSP },
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{ RESET, RESET_DVP},
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{ IMAGE_MODE, IMAGE_MODE_RGB565 },
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{ 0xD7, 0x03 },
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{ 0xE1, 0x77 },
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{ RESET, 0x00 },
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{0, 0},
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};
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static const uint8_t jpeg_regs[][2] = {
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{ BANK_SEL, BANK_SEL_DSP },
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{ RESET, RESET_DVP},
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{ IMAGE_MODE, IMAGE_MODE_JPEG_EN|IMAGE_MODE_RGB565 },
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{ 0xD7, 0x03 },
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{ 0xE1, 0x77 },
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{ QS, 0x0C },
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{ RESET, 0x00 },
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{0, 0},
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};
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#define NUM_BRIGHTNESS_LEVELS (5)
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static const uint8_t brightness_regs[NUM_BRIGHTNESS_LEVELS + 1][5] = {
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{ BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
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{ 0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
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{ 0x00, 0x04, 0x09, 0x10, 0x00 }, /* -1 */
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{ 0x00, 0x04, 0x09, 0x20, 0x00 }, /* 0 */
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{ 0x00, 0x04, 0x09, 0x30, 0x00 }, /* +1 */
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{ 0x00, 0x04, 0x09, 0x40, 0x00 }, /* +2 */
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};
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#define NUM_CONTRAST_LEVELS (5)
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static const uint8_t contrast_regs[NUM_CONTRAST_LEVELS + 1][7] = {
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{ BPADDR, BPDATA, BPADDR, BPDATA, BPDATA, BPDATA, BPDATA },
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{ 0x00, 0x04, 0x07, 0x20, 0x18, 0x34, 0x06 }, /* -2 */
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{ 0x00, 0x04, 0x07, 0x20, 0x1c, 0x2a, 0x06 }, /* -1 */
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{ 0x00, 0x04, 0x07, 0x20, 0x20, 0x20, 0x06 }, /* 0 */
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{ 0x00, 0x04, 0x07, 0x20, 0x24, 0x16, 0x06 }, /* +1 */
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{ 0x00, 0x04, 0x07, 0x20, 0x28, 0x0c, 0x06 }, /* +2 */
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};
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#define NUM_SATURATION_LEVELS (5)
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static const uint8_t saturation_regs[NUM_SATURATION_LEVELS + 1][5] = {
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{ BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
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{ 0x00, 0x02, 0x03, 0x28, 0x28 }, /* -2 */
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{ 0x00, 0x02, 0x03, 0x38, 0x38 }, /* -1 */
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{ 0x00, 0x02, 0x03, 0x48, 0x48 }, /* 0 */
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{ 0x00, 0x02, 0x03, 0x58, 0x58 }, /* +1 */
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{ 0x00, 0x02, 0x03, 0x58, 0x58 }, /* +2 */
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};
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static int reset()
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{
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int i=0;
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const uint8_t (*regs)[2];
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/* Reset all registers */
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SCCB_Write(BANK_SEL, BANK_SEL_SENSOR);
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SCCB_Write(COM7, COM7_SRST);
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/* delay n ms */
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systick_sleep(10);
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i = 0;
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regs = default_regs;
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/* Write initial regsiters */
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while (regs[i][0]) {
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SCCB_Write(regs[i][0], regs[i][1]);
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i++;
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}
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i = 0;
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regs = svga_regs;
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/* Write DSP input regsiters */
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while (regs[i][0]) {
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SCCB_Write(regs[i][0], regs[i][1]);
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i++;
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}
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return 0;
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}
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static int set_pixformat(enum sensor_pixformat pixformat)
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{
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int i=0;
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const uint8_t (*regs)[2]=NULL;
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/* read pixel format reg */
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switch (pixformat) {
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case PIXFORMAT_RGB565:
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regs = rgb565_regs;
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break;
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case PIXFORMAT_YUV422:
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case PIXFORMAT_GRAYSCALE:
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regs = yuv422_regs;
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break;
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case PIXFORMAT_JPEG:
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regs = jpeg_regs;
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break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
/* Write initial regsiters */
|
|
while (regs[i][0]) {
|
|
SCCB_Write(regs[i][0], regs[i][1]);
|
|
i++;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int set_framesize(enum sensor_framesize framesize)
|
|
{
|
|
int ret=0;
|
|
uint8_t clkrc = 0x80;
|
|
uint16_t w=res_width[framesize];
|
|
uint16_t h=res_height[framesize];
|
|
|
|
if (framesize > FRAMESIZE_QVGA) {
|
|
clkrc =0x81;
|
|
}
|
|
|
|
/* Disable DSP */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
|
|
ret |= SCCB_Write(R_BYPASS, R_BYPASS_DSP_BYPAS);
|
|
|
|
/* Write output width */
|
|
ret |= SCCB_Write(ZMOW, (w>>2)&0xFF); /* OUTW[7:0] (real/4) */
|
|
ret |= SCCB_Write(ZMOH, (h>>2)&0xFF); /* OUTH[7:0] (real/4) */
|
|
ret |= SCCB_Write(ZMHH, ((h>>8)&0x04)|((w>>10)&0x03)); /* OUTH[8]/OUTW[9:8] */
|
|
|
|
/* Set CLKRC */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_SENSOR);
|
|
ret |= SCCB_Write(CLKRC, clkrc);
|
|
|
|
/* Enable DSP */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
|
|
ret |= SCCB_Write(R_BYPASS, R_BYPASS_DSP_EN);
|
|
return ret;
|
|
}
|
|
|
|
static int set_framerate(enum sensor_framerate framerate)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int set_contrast(int level)
|
|
{
|
|
int ret=0;
|
|
|
|
level += (NUM_CONTRAST_LEVELS / 2 + 1);
|
|
if (level < 0 || level > NUM_CONTRAST_LEVELS) {
|
|
return -1;
|
|
}
|
|
|
|
/* Switch to DSP register bank */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
|
|
|
|
/* Write contrast registers */
|
|
for (int i=0; i<sizeof(contrast_regs[0])/sizeof(contrast_regs[0][0]); i++) {
|
|
ret |= SCCB_Write(contrast_regs[0][i], contrast_regs[level][i]);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int set_brightness(int level)
|
|
{
|
|
int ret=0;
|
|
|
|
level += (NUM_BRIGHTNESS_LEVELS / 2 + 1);
|
|
if (level < 0 || level > NUM_BRIGHTNESS_LEVELS) {
|
|
return -1;
|
|
}
|
|
|
|
/* Switch to DSP register bank */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
|
|
|
|
/* Write brightness registers */
|
|
for (int i=0; i<sizeof(brightness_regs[0])/sizeof(brightness_regs[0][0]); i++) {
|
|
ret |= SCCB_Write(brightness_regs[0][i], brightness_regs[level][i]);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int set_saturation(int level)
|
|
{
|
|
int ret=0;
|
|
|
|
level += (NUM_SATURATION_LEVELS / 2 + 1);
|
|
if (level < 0 || level > NUM_SATURATION_LEVELS) {
|
|
return -1;
|
|
}
|
|
|
|
/* Switch to DSP register bank */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
|
|
|
|
/* Write contrast registers */
|
|
for (int i=0; i<sizeof(saturation_regs[0])/sizeof(saturation_regs[0][0]); i++) {
|
|
ret |= SCCB_Write(saturation_regs[0][i], saturation_regs[level][i]);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int set_exposure(int exposure)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int set_gainceiling(enum sensor_gainceiling gainceiling)
|
|
{
|
|
int ret =0;
|
|
|
|
/* Switch to SENSOR register bank */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_SENSOR);
|
|
|
|
/* Write gain ceiling register */
|
|
ret |= SCCB_Write(COM9, COM9_AGC_SET(gainceiling));
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int set_quality(int qs)
|
|
{
|
|
int ret=0;
|
|
|
|
/* Switch to DSP register bank */
|
|
ret |= SCCB_Write(BANK_SEL, BANK_SEL_DSP);
|
|
|
|
/* Write QS register */
|
|
ret |= SCCB_Write(QS, qs);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int ov2640_init(struct sensor_dev *sensor)
|
|
{
|
|
/* set HSYNC/VSYNC/PCLK polarity */
|
|
sensor->vsync_pol = DCMI_VSPOLARITY_LOW;
|
|
sensor->hsync_pol = DCMI_HSPOLARITY_LOW;
|
|
sensor->pixck_pol = DCMI_PCKPOLARITY_RISING;
|
|
|
|
/* set function pointers */
|
|
sensor->reset = reset;
|
|
sensor->set_pixformat = set_pixformat;
|
|
sensor->set_framesize = set_framesize;
|
|
sensor->set_framerate = set_framerate;
|
|
sensor->set_contrast = set_contrast;
|
|
sensor->set_brightness= set_brightness;
|
|
sensor->set_saturation= set_saturation;
|
|
sensor->set_exposure = set_exposure;
|
|
sensor->set_gainceiling = set_gainceiling;
|
|
sensor->set_quality = set_quality;
|
|
return 0;
|
|
}
|