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75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
#include <stdint.h>
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#include <stm32f4xx.h>
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#include <stm32f4xx_rcc.h>
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#include "rcc_ctrl.h"
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void rcc_ctrl_set_frequency(enum sysclk_freq freq)
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{
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int freqs[] = {42, 84, 168, 200, 240};
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/* USB freqs: 42MHz, 42Mhz, 48MHz, 50MHz, 48MHz */
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int pll_div[] = {2, 4, 7, 8, 10};
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/* PLL_VCO = (HSE_VALUE / PLL_M) * PLL_N */
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/* SYSCLK = PLL_VCO / PLL_P */
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/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
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uint32_t PLL_P = 2;
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uint32_t PLL_N = freqs[freq] * 2;
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uint32_t PLL_M = (HSE_VALUE/1000000);
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uint32_t PLL_Q = pll_div[freq];
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RCC_DeInit();
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/* Enable HSE osscilator */
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RCC_HSEConfig(RCC_HSE_ON);
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if (RCC_WaitForHSEStartUp() == ERROR) {
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return;
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}
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/* Configure PLL clock M, N, P, and Q dividers */
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RCC_PLLConfig(RCC_PLLSource_HSE, PLL_M, PLL_N, PLL_P, PLL_Q);
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/* Enable PLL clock */
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RCC_PLLCmd(ENABLE);
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/* Wait until PLL clock is stable */
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while ((RCC->CR & RCC_CR_PLLRDY) == 0);
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/* Set PLL_CLK as system clock source SYSCLK */
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RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
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/* Set AHB clock divider */
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RCC_HCLKConfig(RCC_SYSCLK_Div1);
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/* Set APBx clock dividers */
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switch (freq) {
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/* Max freq APB1: 42MHz APB2: 84MHz */
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case SYSCLK_42_MHZ:
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RCC_PCLK1Config(RCC_HCLK_Div1); /* 42MHz */
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RCC_PCLK2Config(RCC_HCLK_Div1); /* 42MHz */
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break;
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case SYSCLK_84_MHZ:
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RCC_PCLK1Config(RCC_HCLK_Div2); /* 42MHz */
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RCC_PCLK2Config(RCC_HCLK_Div1); /* 84MHz */
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break;
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case SYSCLK_168_MHZ:
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RCC_PCLK1Config(RCC_HCLK_Div4); /* 42MHz */
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RCC_PCLK2Config(RCC_HCLK_Div2); /* 84MHz */
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break;
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case SYSCLK_200_MHZ:
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RCC_PCLK1Config(RCC_HCLK_Div4); /* 50MHz */
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RCC_PCLK2Config(RCC_HCLK_Div2); /* 100MHz */
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break;
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case SYSCLK_240_MHZ:
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RCC_PCLK1Config(RCC_HCLK_Div4); /* 60MHz */
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RCC_PCLK2Config(RCC_HCLK_Div2); /* 120MHz */
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break;
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}
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/* Update SystemCoreClock variable */
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SystemCoreClockUpdate();
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}
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