openmv/tools/st/cubeprog/Data_Base/STM32_Prog_DB_0x435.xml
iabdalkader f9ee15bf46 tools/st: Add cubeprog.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
2025-02-11 17:22:20 +01:00

655 lines
23 KiB
XML

<?xml version="1.0" encoding="UTF-8"?>
<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
<Device>
<DeviceID>0x435</DeviceID>
<Vendor>STMicroelectronics</Vendor>
<Type>MCU</Type>
<CPU>Cortex-M4</CPU>
<Name>STM32L43xxx/STM32L44xxx</Name>
<Series>STM32L4</Series>
<Description>ARM 32-bit Cortex-M4 based device</Description>
<Configurations>
<!-- JTAG_SWD Interface -->
<Interface name="JTAG_SWD"/>
<!-- Bootloader Interface -->
<Interface name="Bootloader"/>
</Configurations>
<!-- Peripherals -->
<Peripherals>
<!-- Embedded SRAM -->
<Peripheral>
<Name>Embedded SRAM</Name>
<Type>Storage</Type>
<Description/>
<ErasedValue>0x00</ErasedValue>
<Access>RWE</Access>
<!-- 128 KB -->
<Configuration>
<Parameters address="0x20000000" name="SRAM" size="0xC000"/>
<Description/>
<Organization>Single</Organization>
<Bank name="Bank 1">
<Field>
<Parameters address="0x20000000" name="SRAM" occurrence="0x1" size="0xC000"/>
</Field>
</Bank>
</Configuration>
</Peripheral>
<!-- Embedded Flash -->
<Peripheral>
<Name>Embedded Flash</Name>
<Type>Storage</Type>
<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
<ErasedValue>0xFF</ErasedValue>
<Access>RWE</Access>
<FlashSize address="0x1FFF75E0" default="0x80000"/>
<BootloaderVersion address="0x1FFF6FFE"/>
<!-- 512KB single Bank -->
<Configuration>
<Parameters address="0x08000000" name=" 512 Kbytes Embedded Flash" size="0x80000"/>
<Description/>
<Organization>Single</Organization>
<Alignment>0x8</Alignment>
<Bank name="Bank 1">
<Field>
<Parameters address="0x08000000" name="sector0" occurrence="0x100" size="0x800"/>
</Field>
</Bank>
</Configuration>
</Peripheral>
<!-- OTP -->
<Peripheral>
<Name>OTP</Name>
<Type>Storage</Type>
<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
<ErasedValue>0xFF</ErasedValue>
<Access>RW</Access>
<!-- 1 KBytes single bank -->
<Configuration>
<Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
<Description/>
<Organization>Single</Organization>
<Alignment>0x4</Alignment>
<Bank name="OTP">
<Field>
<Parameters address="0x1FFF7000" name="OTP" occurrence="0x1" size="0x400"/>
</Field>
</Bank>
</Configuration>
</Peripheral>
<!-- Mirror Option Bytes -->
<Peripheral>
<Name>MirrorOptionBytes</Name>
<Type>Storage</Type>
<Description>Mirror Option Bytes contains the extra area.</Description>
<ErasedValue>0xFF</ErasedValue>
<Access>RW</Access>
<!-- 36 Bytes single bank -->
<Configuration>
<Parameters address="0x1FFF7800" name=" 36 Bytes Data MirrorOptionBytes" size="0x24"/>
<Description/>
<Organization>Single</Organization>
<Alignment>0x4</Alignment>
<Bank name="MirrorOptionBytes">
<Field>
<Parameters address="0x1FFF7800" name="MirrorOptionBytes" occurrence="0x1" size="0x24"/>
</Field>
</Bank>
</Configuration>
</Peripheral>
<!-- Option Bytes -->
<Peripheral>
<Name>Option Bytes</Name>
<Type>Configuration</Type>
<Description/>
<Access>RW</Access>
<Bank interface="JTAG_SWD">
<Parameters address="0x40022020" name="Bank 1" size="0x14"/>
<Category>
<Name>Read Out Protection</Name>
<Field>
<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>RDP</Name>
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0xAA">Level 0, no protection</Val>
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
<Val value="0xCC">Level 2, chip protection</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>BOR Level</Name>
<Field>
<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>BOR_LEV</Name>
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
<BitOffset>0x8</BitOffset>
<BitWidth>0x3</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>User Configuration</Name>
<Field>
<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>nRST_STOP</Name>
<Description/>
<BitOffset>0xC</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Stop mode</Val>
<Val value="0x1">No reset generated when entering Stop mode</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_STDBY</Name>
<Description/>
<BitOffset>0xD</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Standby mode</Val>
<Val value="0x1">No reset generated when entering Standby mode</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_SHDW</Name>
<Description/>
<BitOffset>0xE</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_SW</Name>
<Description/>
<BitOffset>0x10</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware independent watchdog</Val>
<Val value="0x1">Software independent watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_STOP</Name>
<Description/>
<BitOffset>0x11</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
<Val value="0x1">IWDG counter active in stop mode</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_STDBY</Name>
<Description/>
<BitOffset>0x12</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
<Val value="0x1">IWDG counter active in standby mode</Val>
</Values>
</Bit>
<Bit>
<Name>WWDG_SW</Name>
<Description/>
<BitOffset>0x13</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware window watchdog</Val>
<Val value="0x1">Software window watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT1</Name>
<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
<BitOffset>0x17</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
<Val value="0x1">Boot from system memory when BOOT0=1</Val>
</Values>
</Bit>
<Bit>
<Name>SRAM2_PE</Name>
<Description/>
<BitOffset>0x18</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">SRAM2 parity check enable</Val>
<Val value="0x1">SRAM2 parity check disable</Val>
</Values>
</Bit>
<Bit>
<Name>SRAM2_RST</Name>
<Description/>
<BitOffset>0x19</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
</Values>
</Bit>
<Bit>
<Name>nSWBOOT0</Name>
<Description/>
<BitOffset>0x1A</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT0</Name>
<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
<BitOffset>0x1B</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>PCROP Protection</Name>
<Field>
<Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1_STRT</Name>
<Description>Flash Bank 1 PCROP start address</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x10</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x8" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1_END</Name>
<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x10</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x8" offset="0x08000000"/>
</Bit>
<Bit>
<Name>PCROP_RDP</Name>
<Description/>
<BitOffset>0x1F</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>Write Protection</Name>
<Field>
<Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1A_STRT</Name>
<Description>The address of the first page of the Bank 1 WRP first area</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1A_END</Name>
<Description>The address of the last page of the Bank 1 WRP first area</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1B_STRT</Name>
<Description>The address of the first page of the Bank 1 WRP second area</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1B_END</Name>
<Description>The address of the last page of the Bank 1 WRP second area</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
</Category>
</Bank>
<Bank interface="Bootloader">
<Parameters address="0x1FFF7800" name="Bank 1" size="0x24"/>
<Category>
<Name>Read Out Protection</Name>
<Field>
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>RDP</Name>
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0xAA">Level 0, no protection</Val>
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
<Val value="0xCC">Level 2, chip protection</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>BOR Level</Name>
<Field>
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>BOR_LEV</Name>
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
<BitOffset>0x8</BitOffset>
<BitWidth>0x3</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>User Configuration</Name>
<Field>
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>IWDG_STOP</Name>
<Description/>
<BitOffset>0x11</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
<Val value="0x1">IWDG counter active in stop mode</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_STDBY</Name>
<Description/>
<BitOffset>0x12</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
<Val value="0x1">IWDG counter active in standby mode</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WWDG_SW</Name>
<Description/>
<BitOffset>0x13</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware window watchdog</Val>
<Val value="0x1">Software window watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>IWDG_SW</Name>
<Description/>
<BitOffset>0x10</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Hardware independent watchdog</Val>
<Val value="0x1">Software independent watchdog</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_STOP</Name>
<Description/>
<BitOffset>0xC</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Stop mode</Val>
<Val value="0x1">No reset generated</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_STDBY</Name>
<Description/>
<BitOffset>0xD</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering Standby mode</Val>
<Val value="0x1">No reset generated</Val>
</Values>
</Bit>
<Bit>
<Name>nRST_SHDW</Name>
<Description/>
<BitOffset>0xE</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT1</Name>
<Description>This bit selects the boot mode only when BOOT0=1. If BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory. </Description>
<BitOffset>0x17</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">Boot from embedded SRAM1 when BOOT0=1</Val>
<Val value="0x1">Boot from system memory when BOOT0=1</Val>
</Values>
</Bit>
<Bit>
<Name>SRAM2_PE</Name>
<Description/>
<BitOffset>0x18</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">SRAM2 parity check enable</Val>
<Val value="0x1">SRAM2 parity check disable</Val>
</Values>
</Bit>
<Bit>
<Name>SRAM2_RST</Name>
<Description/>
<BitOffset>0x19</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">SRAM2 erased when a system reset occurs</Val>
<Val value="0x1">SRAM2 is not erased when a system reset occurs</Val>
</Values>
</Bit>
<Bit>
<Name>nSWBOOT0</Name>
<Description/>
<BitOffset>0x1A</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
<Val value="0x1">BOOT0 taken from PH3/BOOT0 pin</Val>
</Values>
</Bit>
<Bit>
<Name>nBOOT0</Name>
<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
<BitOffset>0x1B</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">BOOT0 = 1, boot memory depends on nBOOT1 value</Val>
<Val value="0x1">BOOT0 = 0, boot from system memory when nSWBOOT0=1 and main flash is empty,otherwise, boot from main flash memory</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>PCROP Protection</Name>
<Field>
<Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1_STRT</Name>
<Description>Flash Bank 1 PCROP start address</Description>
<Description/>
<BitOffset>0x0</BitOffset>
<BitWidth>0x10</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x8" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
<AssignedBits>
<Bit>
<Name>PCROP1_END</Name>
<Description>Flash Bank 1 PCROP End address. Deactivation of PCROP can be done by enabling PCROP_RDP and changing RDP from level 1 to level 0</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x10</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x8" offset="0x08000000"/>
</Bit>
<Bit>
<Name>PCROP_RDP</Name>
<Description/>
<BitOffset>0x1F</BitOffset>
<BitWidth>0x1</BitWidth>
<Access>RW</Access>
<Values>
<Val value="0x0">PCROP zone is kept when RDP is decreased</Val>
<Val value="0x1">PCROP zone is erased when RDP is decreased</Val>
</Values>
</Bit>
</AssignedBits>
</Field>
</Category>
<Category>
<Name>Write Protection</Name>
<Field>
<Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1A_STRT</Name>
<Description>The address of the first page of the Bank 1 WRP first area</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1A_END</Name>
<Description>The address of the last page of the Bank 1 WRP first area</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
<Field>
<Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
<AssignedBits>
<Bit>
<Name>WRP1B_STRT</Name>
<Description>The address of the first page of the Bank 1 WRP second area</Description>
<BitOffset>0x0</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
<Bit>
<Name>WRP1B_END</Name>
<Description>The address of the last page of the Bank 1 WRP second area</Description>
<BitOffset>0x10</BitOffset>
<BitWidth>0x8</BitWidth>
<Access>RW</Access>
<Equation multiplier="0x800" offset="0x08000000"/>
</Bit>
</AssignedBits>
</Field>
</Category>
</Bank>
</Peripheral>
</Peripherals>
</Device>
</Root>