mirror of
https://github.com/openmv/openmv.git
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1331 lines
50 KiB
XML
1331 lines
50 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
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<Device>
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<DeviceID>0x469</DeviceID>
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<Vendor>STMicroelectronics</Vendor>
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<Type>MCU</Type>
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<CPU>Cortex-M4</CPU>
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<Name>STM32G47x/G48x/G414</Name>
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<Series>STM32G4</Series>
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<Description>Category 3 devices, ARM 32-bit Cortex-M4 based device</Description>
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<Configurations>
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<!-- JTAG_SWD Interface -->
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<Interface name="JTAG_SWD">
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<Configuration number="0x0"> <!-- 512KB single Bank-->
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<DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
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<FLASHSIZE reference="0x0"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x200"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x1"> <!-- 512KB Dual Bank-->
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<DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x200"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x3"> <!-- 256KB single Bank-->
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<DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x100"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x4"> <!-- 256KB Dual Bank-->
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<DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x100"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x5"> <!-- 128KB single Bank-->
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<DBANK reference="0x0"> <ReadRegister address="0x40022020" mask="0x400000" value="0x0"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x80"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x6"> <!-- 128KB Dual Bank-->
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<DBANK reference="0x1"> <ReadRegister address="0x40022020" mask="0x400000" value="0x400000"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x80"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x2">
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<dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
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</Configuration>
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</Interface>
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<!-- Bootloader Interface -->
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<Interface name="Bootloader">
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<Configuration number="0x0"> <!-- 512KB single Bank-->
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<DBANK reference="0x0"> <ReadRegister address="0x1FFF7800" mask="0x400000" value="0x0"/> </DBANK>
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<FLASHSIZE reference="0x0"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x200"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x1"> <!-- 512KB Dual Bank-->
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<DBANK reference="0x1"> <ReadRegister address="0x1FFF7800" mask="0x400000" value="0x400000"/> </DBANK>
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<FLASHSIZE reference="0x0"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x200"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x3"> <!-- 256KB single Bank-->
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<DBANK reference="0x0"> <ReadRegister address="0x1FFF7800" mask="0x400000" value="0x0"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x100"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x4"> <!-- 256KB Dual Bank-->
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<DBANK reference="0x1"> <ReadRegister address="0x1FFF7800" mask="0x400000" value="0x400000"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x100"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x5"> <!-- 128KB single Bank-->
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<DBANK reference="0x0"> <ReadRegister address="0x1FFF7800" mask="0x400000" value="0x0"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x80"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x6"> <!-- 128KB Dual Bank-->
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<DBANK reference="0x1"> <ReadRegister address="0x1FFF7800" mask="0x400000" value="0x400000"/> </DBANK>
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<FLASHSIZE reference="0x1"> <ReadRegister address="0x1FFF75E0" mask="0x000FFF" value="0x80"/> </FLASHSIZE>
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</Configuration>
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<Configuration number="0x2">
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<dummy> <ReadRegister address="0x20000000" mask="0" value="0"/> </dummy>
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</Configuration>
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</Interface>
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</Configurations>
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<!-- Peripherals -->
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<Peripherals>
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<!-- Embedded SRAM -->
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<Peripheral>
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<Name>Embedded SRAM</Name>
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<Type>Storage</Type>
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<Description/>
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<ErasedValue>0x00</ErasedValue>
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<Access>RWE</Access>
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<!-- 96 KB -->
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<Configuration>
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<Parameters address="0x20000000" name="SRAM" size="0x18000"/>
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<Description/>
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<Organization>Single</Organization>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x20000000" name="SRAM" occurrence="0x1" size="0x18000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Embedded Flash -->
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<Peripheral>
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<Name>Embedded Flash</Name>
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<Type>Storage</Type>
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<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RWE</Access>
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<FlashSize address="0x1FFF75E0" default="0x80000"/>
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<BootloaderVersion address="0x1FFF6FFE"/>
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<DBGMCU_CR address="0xE0042004" mask="0x06"/>
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<DBGMCU_APB1_FZ address="0xE0042008" mask="0x1800"/>
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<RCC_APB1ENR address="0x40021058" mask="0x00000800"/>
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<!-- 512KB single Bank -->
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<Configuration config="0">
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<Parameters address="0x08000000" name=" 512 Kbyte Embedded Flash" size="0x80000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x80" size="0x1000"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 512KB dual Bank -->
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<Configuration config="1,2">
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<Parameters address="0x08000000" name=" 512 Kbyte Embedded Flash" size="0x80000"/>
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x80" size="0x800"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x08040000" name="sector65280" occurrence="0x80" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 265KB single Bank -->
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<Configuration config="3">
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<Parameters address="0x08000000" name=" 256 Kbyte Embedded Flash" size="0x40000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x40" size="0x1000"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 265KB dual Bank -->
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<Configuration config="4">
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<Parameters address="0x08000000" name=" 256 Kbyte Embedded Flash" size="0x40000"/> <!-- size="0x80000" to avoid the download Issue in bank2 -->
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x40" size="0x800"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x08020000" name="sector65280" occurrence="0x40" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 128KB single Bank -->
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<Configuration config="5">
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<Parameters address="0x08000000" name=" 128 Kbyte Embedded Flash" size="0x20000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x20" size="0x1000"/>
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</Field>
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</Bank>
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</Configuration>
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<!-- 128KB dual Bank -->
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<Configuration config="6">
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<Parameters address="0x08000000" name=" 128 Kbyte Embedded Flash" size="0x20000"/> <!-- size="0x80000" to avoid the download Issue in bank2 -->
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<Description/>
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<Organization>Dual</Organization>
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<Alignment>0x8</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x20" size="0x800"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x08010000" name="sector65280" occurrence="0x20" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- OTP -->
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<Peripheral>
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<Name>OTP</Name>
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<Type>Storage</Type>
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<Description>The Data OTP memory block. It contains the one time programmable bits.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 1 KBytes single bank -->
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<Configuration>
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<Parameters address="0x1FFF7000" name=" 1 KBytes Data OTP" size="0x400"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="OTP">
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<Field>
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<Parameters address="0x1FFF7000" name="OTP" occurrence="0x1" size="0x400"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Mirror Option Bytes -->
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<Peripheral>
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<Name>MirrorOptionBytes</Name>
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<Type>Storage</Type>
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<Description>Mirror Option Bytes contains the extra area.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 64 Bytes single bank -->
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<Configuration>
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<Parameters address="0x1FFF7800" name=" 64 Bytes Data MirrorOptionBytes" size="0x40"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x1FFF7800" name="Bank1" occurrence="0x1" size="0x30"/>
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</Field>
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</Bank>
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<Bank name="Bank 2">
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<Field>
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<Parameters address="0x1FFFF800" name="Bank2" occurrence="0x1" size="0x30"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Option Bytes -->
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<Peripheral>
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<Name>Option Bytes</Name>
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<Type>Configuration</Type>
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<Description/>
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<Access>RW</Access>
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<Bank interface="JTAG_SWD">
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<Parameters address="0x40022020" name="Bank 1" size="0x14"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, no debug</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x3</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
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<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
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<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
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<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
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<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x40022020" name="FLASH_OPTR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>nRST_STOP</Name>
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<Description/>
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<BitOffset>0xC</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Stop mode</Val>
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<Val value="0x1">No reset generated when entering Stop mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STDBY</Name>
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<Description/>
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<BitOffset>0xD</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Standby mode</Val>
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<Val value="0x1">No reset generated when entering Standby mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_SHDW</Name>
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<Description/>
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<BitOffset>0xE</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
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<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_SW</Name>
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<Description/>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware independent watchdog</Val>
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<Val value="0x1">Software independent watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_STOP</Name>
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<Description/>
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<BitOffset>0x11</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in stop mode</Val>
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<Val value="0x1">IWDG counter active in stop mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>IWDG_STDBY</Name>
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<Description/>
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<BitOffset>0x12</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Freeze IWDG counter in standby mode</Val>
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<Val value="0x1">IWDG counter active in standby mode</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>WWDG_SW</Name>
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<Description/>
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<BitOffset>0x13</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Hardware window watchdog</Val>
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<Val value="0x1">Software window watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>BFB2</Name>
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<Description/>
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<BitOffset>0x14</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Dual-bank boot disable</Val>
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<Val value="0x1">Dual-bank boot enable</Val>
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</Values>
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</Bit>
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<Bit reference="DualBank">
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<Name>DBANK</Name>
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<Description/>
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<BitOffset>0x16</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Single bank mode with 128 bits data read width</Val>
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<Val value="0x1">Dual bank mode with 64 bits data</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nBOOT1</Name>
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<Description/>
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<BitOffset>0x17</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
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<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>SRAM_PE</Name>
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<Description>SRAM1 and CCM SRAM parity check enable</Description>
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<BitOffset>0x18</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0x0">SRAM1 and CCM SRAM parity check enable</Val>
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<Val value="0x1">SRAM1 and CCM SRAM parity check disable</Val>
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</Values>
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</Bit>
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<Bit>
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|
<Name>CCMSRAM_RST</Name>
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|
<Description>CCM SRAM Erase when system reset</Description>
|
|
<BitOffset>0x19</BitOffset>
|
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<BitWidth>0x1</BitWidth>
|
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<Access>RW</Access>
|
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<Values>
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<Val value="0x0">CCM SRAM erased when a system reset occurs</Val>
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<Val value="0x1">CCM SRAM is not erased when a system reset occurs</Val>
|
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</Values>
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</Bit>
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<Bit>
|
|
<Name>nSWBOOT0</Name>
|
|
<Description>Software BOOT0</Description>
|
|
<BitOffset>0x1A</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
|
|
<Val value="0x1">BOOT0 taken from PB8/BOOT0 pin</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nBOOT0</Name>
|
|
<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
|
|
<BitOffset>0x1B</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">nBOOT0 = 0</Val>
|
|
<Val value="0x1">nBOOT0 = 1</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NRST_MODE</Name>
|
|
<Description/>
|
|
<BitOffset>0x1C</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reserved</Val>
|
|
<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
|
|
<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
|
|
<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IRHEN</Name>
|
|
<Description>Internal reset holder enable bit</Description>
|
|
<BitOffset>0x1E</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
|
|
<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>PCROP Protection (Bank 1)</Name>
|
|
<Field>
|
|
<Parameters address="0x40022024" name="FLASH_PCROP1SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP1_STRT</Name>
|
|
<Description>Flash Bank 1 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP1_STRT</Name>
|
|
<Description>Flash Bank 1 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022028" name="FLASH_PCROP1ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP1_END</Name>
|
|
<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08000008"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP1_END</Name>
|
|
<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000008"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>PCROP_RDP</Name>
|
|
<Description/>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0</Val>
|
|
<Val value="0x1">PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection (Bank 1)</Name>
|
|
<Field>
|
|
<Parameters address="0x4002202C" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1A_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1A_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022030" name="FLASH_WRP1BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1B_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1B_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x40022044" name="Bank 2" size="0x10"/>
|
|
<Category>
|
|
<Name>PCROP Protection (Bank 2)</Name>
|
|
<Field>
|
|
<Parameters address="0x40022044" name="FLASH_PCROP2SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP2_STRT</Name>
|
|
<Description>Flash Bank 2 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP2_STRT</Name>
|
|
<Description>Flash Bank 2 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08040000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022048" name="FLASH_PCROP2ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP2_END</Name>
|
|
<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08000008"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP2_END</Name>
|
|
<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08040008"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection (Bank 2)</Name>
|
|
<Field>
|
|
<Parameters address="0x4002204C" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2A_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2A_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08040000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2A_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2A_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08040000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x40022050" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2B_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2B_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08040000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2B_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2B_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08040000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="JTAG_SWD">
|
|
<Parameters address="0x40022070" name="Bank 3" size="0x8"/>
|
|
<Category>
|
|
<Name>Secure Protection (Bank 1)</Name>
|
|
<Field>
|
|
<Parameters address="0x40022070" name="FLASH_SECR1" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SEC_SIZE1</Name>
|
|
<Description>sets the number of pages used in the bank 1 securable area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>BOOT_LOCK</Name>
|
|
<Description>Unique boot entry point</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Boot based on the pad/option bit configuration</Val>
|
|
<Val value="0x1">Boot will be done from user flash only, whatever the RDP level</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Secure Protection (Bank 2)</Name>
|
|
<Field>
|
|
<Parameters address="0x40022074" name="FLASH_SECR2" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SEC_SIZE2</Name>
|
|
<Description>sets the number of pages used in the bank 2 securable area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x1FFF7800" name="Bank 1" size="0x24"/>
|
|
<Category>
|
|
<Name>Read Out Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>RDP</Name>
|
|
<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0xAA">Level 0, no protection</Val>
|
|
<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
|
|
<Val value="0xCC">Level 2, no debug</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>BOR Level</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOR_LEV</Name>
|
|
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x3</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR Level 0, reset level threshold is around 1.7 V</Val>
|
|
<Val value="0x1">BOR Level 1, reset level threshold is around 2.0 V</Val>
|
|
<Val value="0x2">BOR Level 2, reset level threshold is around 2.2 V</Val>
|
|
<Val value="0x3">BOR Level 3, reset level threshold is around 2.5 V</Val>
|
|
<Val value="0x4">BOR Level 4, reset level threshold is around 2.8 V</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>User Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_STOP</Name>
|
|
<Description/>
|
|
<BitOffset>0x11</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Freeze IWDG counter in stop mode</Val>
|
|
<Val value="0x1">IWDG counter active in stop mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IWDG_STDBY</Name>
|
|
<Description/>
|
|
<BitOffset>0x12</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Freeze IWDG counter in standby mode</Val>
|
|
<Val value="0x1">IWDG counter active in standby mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7800" name="FLASH_OPTR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WWDG_SW</Name>
|
|
<Description/>
|
|
<BitOffset>0x13</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Hardware window watchdog</Val>
|
|
<Val value="0x1">Software window watchdog</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description/>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Hardware independent watchdog</Val>
|
|
<Val value="0x1">Software independent watchdog</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_STOP</Name>
|
|
<Description/>
|
|
<BitOffset>0xC</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
|
<Val value="0x1">No reset generated</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_STDBY</Name>
|
|
<Description/>
|
|
<BitOffset>0xD</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
|
<Val value="0x1">No reset generated</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_SHDW</Name>
|
|
<Description/>
|
|
<BitOffset>0xE</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering the Shutdown mode</Val>
|
|
<Val value="0x1">No reset generated when entering the Shutdown mode</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>BFB2</Name>
|
|
<Description/>
|
|
<BitOffset>0x14</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Dual-bank boot disable</Val>
|
|
<Val value="0x1">Dual-bank boot enable</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit reference="DualBank">
|
|
<Name>DBANK</Name>
|
|
<Description/>
|
|
<BitOffset>0x16</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Single bank mode with 128 bits data read width</Val>
|
|
<Val value="0x1">Dual bank mode with 64 bits data</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nBOOT1</Name>
|
|
<Description/>
|
|
<BitOffset>0x17</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
|
|
<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>SRAM_PE</Name>
|
|
<Description>SRAM1 and CCM SRAM parity check enable</Description>
|
|
<BitOffset>0x18</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">SRAM1 and CCM SRAM parity check enable</Val>
|
|
<Val value="0x1">SRAM1 and CCM SRAM parity check disable</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>CCMSRAM_RST</Name>
|
|
<Description>CCM SRAM Erase when system reset</Description>
|
|
<BitOffset>0x19</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">CCM SRAM erased when a system reset occurs</Val>
|
|
<Val value="0x1">CCM SRAM is not erased when a system reset occurs</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nSWBOOT0</Name>
|
|
<Description>Software BOOT0</Description>
|
|
<BitOffset>0x1A</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">BOOT0 taken from the option bit nBOOT0</Val>
|
|
<Val value="0x1">BOOT0 taken from PB8/BOOT0 pin</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nBOOT0</Name>
|
|
<Description>This option bit sets the BOOT0 value only when nSWBOOT0=0</Description>
|
|
<BitOffset>0x1B</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">nBOOT0 = 0</Val>
|
|
<Val value="0x1">nBOOT0 = 1</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>NRST_MODE</Name>
|
|
<Description/>
|
|
<BitOffset>0x1C</BitOffset>
|
|
<BitWidth>0x2</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reserved</Val>
|
|
<Val value="0x1">Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin</Val>
|
|
<Val value="0x2">GPIO: standard GPIO pad functionality, only internal RESET possible</Val>
|
|
<Val value="0x3">Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>IRHEN</Name>
|
|
<Description>Internal reset holder enable bit</Description>
|
|
<BitOffset>0x1E</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Internal resets are propagated as simple pulse on NRST pin</Val>
|
|
<Val value="0x1">Internal resets drives NRST pin low until it is seen as low level</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>PCROP Protection (Bank 1)</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7808" name="FLASH_PCROP1SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP1_STRT</Name>
|
|
<Description>Flash Bank 1 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP1_STRT</Name>
|
|
<Description>Flash Bank 1 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7810" name="FLASH_PCROP1ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP1_END</Name>
|
|
<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08000008"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP1_END</Name>
|
|
<Description>Flash Bank 1 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08000008"/>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>PCROP_RDP</Name>
|
|
<Description/>
|
|
<BitOffset>0x1F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0</Val>
|
|
<Val value="0x1">PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase)</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection (Bank 1)</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7818" name="FLASH_WRP1AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1A_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1A_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1A_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFF7820" name="FLASH_WRP1BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP1B_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1B_STRT</Name>
|
|
<Description>The address of the first page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP1B_END</Name>
|
|
<Description>The address of the last page of the Bank 1 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08000000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x1FFFF808" name="Bank 2" size="0x24"/>
|
|
<Category>
|
|
<Name>PCROP Protection (Bank 2)</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFFF808" name="FLASH_PCROP2SR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP2_STRT</Name>
|
|
<Description>Flash Bank 2 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08080000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP2_STRT</Name>
|
|
<Description>Flash Bank 2 PCROP start address</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08080000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFFF810" name="FLASH_PCROP2ER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>PCROP2_END</Name>
|
|
<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x10" offset="0x08080008"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>PCROP2_END</Name>
|
|
<Description>Flash Bank 2 PCROP End address(excluded). Deactivation of PCROP can be done by enbaling PCROP_RDP and changing RDP from level 1 to level 0</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0xF</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x8" offset="0x08080008"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection (Bank 2)</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFFF818" name="FLASH_WRP2AR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2A_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08080000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2A_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08080000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2A_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08080000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2A_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP first area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08080000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
<Field>
|
|
<Parameters address="0x1FFFF820" name="FLASH_WRP2BR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2B_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08080000"/>
|
|
</Bit>
|
|
<Bit config="0,3,5">
|
|
<Name>WRP2B_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08080000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2B_STRT</Name>
|
|
<Description>The address of first page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x1000" offset="0x08080000"/>
|
|
</Bit>
|
|
<Bit config="1,2,4,6">
|
|
<Name>WRP2B_END</Name>
|
|
<Description>The address of last page of the Bank 2 WRP second area</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x7</BitWidth>
|
|
<Access>RW</Access>
|
|
<Equation multiplier="0x800" offset="0x08080000"/>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x1FFF7828" name="Bank 3" size="0x4"/>
|
|
<Category>
|
|
<Name>Secure Protection (Bank 1)</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFF7828" name="FLASH_SECR1" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SEC_SIZE1</Name>
|
|
<Description>sets the number of pages used in the bank 1 securable area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>BOOT_LOCK</Name>
|
|
<Description>Unique boot entry point</Description>
|
|
<BitOffset>0x10</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Boot based on the pad/option bit configuration</Val>
|
|
<Val value="0x1">Boot will be done from user flash only, whatever the RDP level</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
<Bank interface="Bootloader">
|
|
<Parameters address="0x1FFFF828" name="Bank 4" size="0x8"/>
|
|
<Category>
|
|
<Name>Secure Protection (Bank 2)</Name>
|
|
<Field>
|
|
<Parameters address="0x1FFFF828" name="FLASH_SECR2" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>SEC_SIZE2</Name>
|
|
<Description>sets the number of pages used in the bank 2 securable area</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x8</BitWidth>
|
|
<Access>RW</Access>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
</Peripheral>
|
|
</Peripherals>
|
|
</Device>
|
|
</Root> |