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469 lines
18 KiB
C
469 lines
18 KiB
C
/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2021 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2021 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_ARCH_STR "OMV4 H7 1024" // 33 chars max
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#define OMV_BOARD_TYPE "H7"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800
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#define OMV_UNIQUE_ID_SIZE 3 // 3 words
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// Needed by the SWD JTAG testrig - located at the bottom of the frame buffer stack.
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#define OMV_SELF_TEST_SWD_ADDR MAIN_FB()->pixfmt
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// Flash sectors for the bootloader.
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// Flash FS sector, main FW sector, max sector.
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#define OMV_FLASH_LAYOUT {1, 2, 15}
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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// Sensor external clock source.
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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// Sensor external clock timer frequency.
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#define OMV_XCLK_FREQUENCY (12000000)
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// Sensor PLL register value.
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#define OMV_OV7725_PLL_CONFIG (0x41) // x4
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// Sensor Banding Filter Value
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#define OMV_OV7725_BANDING (0x7F)
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// Bootloader LED GPIO port/pin
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#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_1)
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#define OMV_BOOTLDR_LED_PORT (GPIOC)
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// RAW buffer size
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#define OMV_RAW_BUF_SIZE (409600)
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// Enable hardware JPEG
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#define OMV_HARDWARE_JPEG (1)
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// Enable MDMA sensor offload.
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#define OMV_ENABLE_SENSOR_MDMA (1)
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// Enable sensor drivers
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#define OMV_ENABLE_OV2640 (1)
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#define OMV_ENABLE_OV5640 (1)
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#define OMV_ENABLE_OV7670 (0)
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#define OMV_ENABLE_OV7690 (1)
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#define OMV_ENABLE_OV7725 (1)
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#define OMV_ENABLE_OV9650 (1)
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#define OMV_ENABLE_MT9M114 (1)
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#define OMV_ENABLE_MT9V034 (1)
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#define OMV_ENABLE_LEPTON (1)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_PAJ6100 (1)
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#define OMV_ENABLE_FROGEYE2020 (1)
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// Set which OV767x sensor is used
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#define OMV_OV7670_VERSION (70)
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// OV7670 clock divider
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#define OMV_OV7670_CLKRC (0)
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// Enable sensor features
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#define OMV_ENABLE_OV5640_AF (0)
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// Enable WiFi debug
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#define OMV_ENABLE_WIFIDBG (1)
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// Enable self-tests on first boot
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#define OMV_ENABLE_SELFTEST (1)
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// If buffer size is bigger than this threshold, the quality is reduced.
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// This is only used for JPEG images sent to the IDE not normal compression.
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#define JPEG_QUALITY_THRESH (320*240*2)
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// Low and high JPEG QS.
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 16
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.3"
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_FS_IRQn)
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//PLL1 480MHz/48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (3)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (3)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_LDO_SUPPLY)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_FFS_MEMORY DTCM // Flash filesystem cache memory
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap memory
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#define OMV_STACK_MEMORY ITCM // stack memory
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#define OMV_DMA_MEMORY SRAM2 // DMA buffers memory.
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#define OMV_FB_MEMORY AXI_SRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY SRAM3 // JPEG buffer memory.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
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#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (100K) // minimum fb alloc size
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#define OMV_STACK_SIZE (64K)
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#define OMV_HEAP_SIZE (236K)
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#define OMV_LINE_BUF_SIZE (3 * 1024) // Image line buffer round(640 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
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#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
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#define OMV_JPEG_BUF_SIZE (32 * 1024) // IDE JPEG buffer (header + data).
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#define OMV_BOOT_ORIGIN 0x08000000
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#define OMV_BOOT_LENGTH 128K
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#define OMV_TEXT_ORIGIN 0x08040000
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#define OMV_TEXT_LENGTH 1792K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_ITCM_ORIGIN 0x00000000
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#define OMV_ITCM_LENGTH 64K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 248K
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#define OMV_SRAM2_ORIGIN 0x3003E000 // 8KB of SRAM1
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#define OMV_SRAM2_LENGTH 8K
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#define OMV_SRAM3_ORIGIN 0x30040000
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#define OMV_SRAM3_LENGTH 32K
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#define OMV_SRAM4_ORIGIN 0x38000000
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#define OMV_SRAM4_LENGTH 64K
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#define OMV_AXI_SRAM_ORIGIN 0x24000000
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#define OMV_AXI_SRAM_LENGTH 512K
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// Domain 1 DMA buffers region.
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#define OMV_DMA_MEMORY_D1 AXI_SRAM
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#define OMV_DMA_MEMORY_D1_SIZE (8*1024) // Reserved memory for DMA buffers
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#define OMV_DMA_REGION_D1_BASE (OMV_AXI_SRAM_ORIGIN+(500*1024))
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#define OMV_DMA_REGION_D1_SIZE MPU_REGION_SIZE_8KB
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// Domain 2 DMA buffers region.
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#define OMV_DMA_MEMORY_D2 SRAM2
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#define OMV_DMA_MEMORY_D2_SIZE (1*1024) // Reserved memory for DMA buffers
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#define OMV_DMA_REGION_D2_BASE (OMV_SRAM2_ORIGIN+(0*1024))
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#define OMV_DMA_REGION_D2_SIZE MPU_REGION_SIZE_8KB
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// Domain 3 DMA buffers region.
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//#define OMV_DMA_MEMORY_D3 SRAM4
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//#define OMV_DMA_REGION_D3_BASE (OMV_SRAM4_ORIGIN+(0*1024))
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//#define OMV_DMA_REGION_D3_SIZE MPU_REGION_SIZE_64KB
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// AXI QoS - Low-High (0:15) - default 0
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#define OMV_AXI_QOS_MDMA_R_PRI 15 // Max pri to move data.
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// Image sensor I2C
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#define ISC_I2C (I2C1)
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#define ISC_I2C_ID (1)
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#define ISC_I2C_AF (GPIO_AF4_I2C1)
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#define ISC_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define ISC_I2C_SCL_PORT (GPIOB)
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#define ISC_I2C_SCL_PIN (GPIO_PIN_8)
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#define ISC_I2C_SDA_PORT (GPIOB)
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#define ISC_I2C_SDA_PIN (GPIO_PIN_9)
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#define ISC_I2C_SPEED (CAMBUS_SPEED_STANDARD)
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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/* FIR I2C */
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#define FIR_I2C (I2C2)
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#define FIR_I2C_ID (2)
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#define FIR_I2C_AF (GPIO_AF4_I2C2)
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#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define FIR_I2C_SCL_PORT (GPIOB)
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#define FIR_I2C_SCL_PIN (GPIO_PIN_10)
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#define FIR_I2C_SDA_PORT (GPIOB)
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#define FIR_I2C_SDA_PIN (GPIO_PIN_11)
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#define FIR_I2C_SPEED (CAMBUS_SPEED_FULL)
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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/* DCMI */
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#define DCMI_TIM (TIM1)
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#define DCMI_TIM_PIN (GPIO_PIN_8)
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#define DCMI_TIM_PORT (GPIOA)
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#define DCMI_TIM_AF (GPIO_AF1_TIM1)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define DCMI_RESET_PIN (GPIO_PIN_10)
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#define DCMI_RESET_PORT (GPIOA)
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#define DCMI_PWDN_PIN (GPIO_PIN_7)
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#define DCMI_PWDN_PORT (GPIOD)
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#define DCMI_FSYNC_PIN (GPIO_PIN_4)
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#define DCMI_FSYNC_PORT (GPIOB)
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#define DCMI_D0_PIN (GPIO_PIN_6)
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#define DCMI_D1_PIN (GPIO_PIN_7)
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#define DCMI_D2_PIN (GPIO_PIN_0)
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#define DCMI_D3_PIN (GPIO_PIN_1)
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#define DCMI_D4_PIN (GPIO_PIN_4)
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#define DCMI_D5_PIN (GPIO_PIN_6)
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#define DCMI_D6_PIN (GPIO_PIN_5)
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#define DCMI_D7_PIN (GPIO_PIN_6)
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#define DCMI_D0_PORT (GPIOC)
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#define DCMI_D1_PORT (GPIOC)
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#define DCMI_D2_PORT (GPIOE)
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#define DCMI_D3_PORT (GPIOE)
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#define DCMI_D4_PORT (GPIOE)
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#define DCMI_D5_PORT (GPIOB)
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#define DCMI_D6_PORT (GPIOE)
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#define DCMI_D7_PORT (GPIOE)
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#define DCMI_HSYNC_PIN (GPIO_PIN_4)
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#define DCMI_VSYNC_PIN (GPIO_PIN_7)
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#define DCMI_PXCLK_PIN (GPIO_PIN_6)
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#define DCMI_HSYNC_PORT (GPIOA)
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#define DCMI_VSYNC_PORT (GPIOB)
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#define DCMI_PXCLK_PORT (GPIOA)
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#define DCMI_RESET_LOW() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_RESET)
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#define DCMI_RESET_HIGH() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_SET)
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#define DCMI_PWDN_LOW() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_RESET)
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#define DCMI_PWDN_HIGH() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_SET)
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#define DCMI_FSYNC_LOW() HAL_GPIO_WritePin(DCMI_FSYNC_PORT, DCMI_FSYNC_PIN, GPIO_PIN_RESET)
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#define DCMI_FSYNC_HIGH() HAL_GPIO_WritePin(DCMI_FSYNC_PORT, DCMI_FSYNC_PIN, GPIO_PIN_SET)
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#define DCMI_VSYNC_IRQN EXTI9_5_IRQn
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#define DCMI_VSYNC_IRQ_LINE (7)
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#define WINC_SPI (SPI2)
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#define WINC_SPI_AF (GPIO_AF5_SPI2)
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#define WINC_SPI_TIMEOUT (1000)
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// SPI1/2/3 clock source is PLL2 (160MHz/4 == 40MHz).
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#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4)
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#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI2_CLK_ENABLE()
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#define WINC_SPI_SCLK_PIN (GPIO_PIN_13)
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#define WINC_SPI_MISO_PIN (GPIO_PIN_14)
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#define WINC_SPI_MOSI_PIN (GPIO_PIN_15)
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#define WINC_SPI_SCLK_PORT (GPIOB)
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#define WINC_SPI_MISO_PORT (GPIOB)
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#define WINC_SPI_MOSI_PORT (GPIOB)
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#define WINC_EN_PIN (GPIO_PIN_5)
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#define WINC_CS_PIN (GPIO_PIN_12)
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#define WINC_RST_PIN (GPIO_PIN_12)
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#define WINC_IRQ_PIN (pin_D13)
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#define WINC_EN_PORT (GPIOA)
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#define WINC_CS_PORT (GPIOB)
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#define WINC_RST_PORT (GPIOD)
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#define WINC_CS_LOW() HAL_GPIO_WritePin(WINC_CS_PORT, WINC_CS_PIN, GPIO_PIN_RESET)
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#define WINC_CS_HIGH() HAL_GPIO_WritePin(WINC_CS_PORT, WINC_CS_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_PORT GPIOB
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#define SOFT_I2C_SIOC_PIN GPIO_PIN_10
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#define SOFT_I2C_SIOD_PIN GPIO_PIN_11
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#define SOFT_I2C_SIOC_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_SIOC_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_RESET)
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#define SOFT_I2C_SIOD_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_SIOD_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_RESET)
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#define SOFT_I2C_SIOD_READ() HAL_GPIO_ReadPin (SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN)
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#define SOFT_I2C_SIOD_WRITE(bit) HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, bit);
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#define SOFT_I2C_SPIN_DELAY 64
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#define ISC_SPI (SPI3)
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// SPI1/2/3 clock source is PLL3 (160MHz/8 == 20MHz) - Minimum (164*240*8*27 = 8,501,760Hz)
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#define ISC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_8)
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#define ISC_SPI_IRQn (SPI3_IRQn)
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#define ISC_SPI_IRQHandler (SPI3_IRQHandler)
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#define ISC_SPI_DMA_IRQn (DMA1_Stream0_IRQn)
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#define ISC_SPI_DMA_STREAM (DMA1_Stream0)
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#define ISC_SPI_DMA_REQUEST (DMA_REQUEST_SPI3_RX)
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#define ISC_SPI_DMA_IRQHandler (DMA1_Stream0_IRQHandler)
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#define ISC_SPI_RESET() __HAL_RCC_SPI3_FORCE_RESET()
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#define ISC_SPI_RELEASE() __HAL_RCC_SPI3_RELEASE_RESET()
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#define ISC_SPI_CLK_ENABLE() __HAL_RCC_SPI3_CLK_ENABLE()
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#define ISC_SPI_CLK_DISABLE() __HAL_RCC_SPI3_CLK_DISABLE()
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#define ISC_SPI_SCLK_AF (GPIO_AF6_SPI3)
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#define ISC_SPI_MISO_AF (GPIO_AF6_SPI3)
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#define ISC_SPI_MOSI_AF (GPIO_AF7_SPI3)
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#define ISC_SPI_SSEL_AF (GPIO_AF6_SPI3)
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#define ISC_SPI_SCLK_PIN (GPIO_PIN_3)
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#define ISC_SPI_MISO_PIN (GPIO_PIN_4)
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#define ISC_SPI_MOSI_PIN (GPIO_PIN_5)
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#define ISC_SPI_SSEL_PIN (GPIO_PIN_15)
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#define ISC_SPI_SCLK_PORT (GPIOB)
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#define ISC_SPI_MISO_PORT (GPIOB)
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#define ISC_SPI_MOSI_PORT (GPIOB)
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#define ISC_SPI_SSEL_PORT (GPIOA)
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// The IMU sensor is on the same SPI bus pins as the camera module interface
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// SPI bus. While the buses overlap both devices will never be in-use at once.
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#define IMU_SPI (SPI1)
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#define IMU_SPI_AF (GPIO_AF5_SPI1)
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// SPI1/2/3 clock source is PLL2 (160MHz/16 == 10MHz).
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#define IMU_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16)
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#define IMU_SPI_RESET() __HAL_RCC_SPI1_FORCE_RESET()
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#define IMU_SPI_RELEASE() __HAL_RCC_SPI1_RELEASE_RESET()
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#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI1_CLK_ENABLE()
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#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI1_CLK_DISABLE()
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#define IMU_SPI_SCLK_PIN (GPIO_PIN_3)
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#define IMU_SPI_MISO_PIN (GPIO_PIN_4)
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#define IMU_SPI_MOSI_PIN (GPIO_PIN_5)
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#define IMU_SPI_SSEL_PIN (GPIO_PIN_15)
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#define IMU_SPI_SCLK_PORT (GPIOB)
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#define IMU_SPI_MISO_PORT (GPIOB)
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#define IMU_SPI_MOSI_PORT (GPIOB)
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#define IMU_SPI_SSEL_PORT (GPIOA)
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
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#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
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#define OMV_SPI_LCD_MOSI_PIN (GPIO_PIN_15)
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#define OMV_SPI_LCD_MOSI_PORT (GPIOB)
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#define OMV_SPI_LCD_MOSI_ALT (GPIO_AF5_SPI2)
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#define OMV_SPI_LCD_MISO_PIN (GPIO_PIN_14)
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#define OMV_SPI_LCD_MISO_PORT (GPIOB)
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#define OMV_SPI_LCD_MISO_ALT (GPIO_AF5_SPI2)
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#define OMV_SPI_LCD_SCLK_PIN (GPIO_PIN_13)
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#define OMV_SPI_LCD_SCLK_PORT (GPIOB)
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#define OMV_SPI_LCD_SCLK_ALT (GPIO_AF5_SPI2)
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#define OMV_SPI_LCD_RST_PIN (GPIO_PIN_12)
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#define OMV_SPI_LCD_RST_PORT (GPIOD)
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#define OMV_SPI_LCD_RST_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_RST_PORT, OMV_SPI_LCD_RST_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_RST_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_RST_PORT, OMV_SPI_LCD_RST_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_RS_PIN (GPIO_PIN_13)
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#define OMV_SPI_LCD_RS_PORT (GPIOD)
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#define OMV_SPI_LCD_RS_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_RS_PORT, OMV_SPI_LCD_RS_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_RS_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_RS_PORT, OMV_SPI_LCD_RS_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_CS_PIN (GPIO_PIN_12)
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#define OMV_SPI_LCD_CS_PORT (GPIOB)
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#define OMV_SPI_LCD_CS_HIGH() HAL_GPIO_WritePin(OMV_SPI_LCD_CS_PORT, OMV_SPI_LCD_CS_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_CS_LOW() HAL_GPIO_WritePin(OMV_SPI_LCD_CS_PORT, OMV_SPI_LCD_CS_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_BL_PIN (GPIO_PIN_5)
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#define OMV_SPI_LCD_BL_PORT (GPIOA)
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#define OMV_SPI_LCD_BL_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_BL_PORT, OMV_SPI_LCD_BL_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_BL_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_BL_PORT, OMV_SPI_LCD_BL_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_BL_DAC (DAC1)
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#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
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#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
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#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
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#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
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#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
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// FIR Module
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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#define OMV_ENABLE_FIR_MLX90641 (1)
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#define OMV_ENABLE_FIR_AMG8833 (1)
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#define OMV_ENABLE_FIR_LEPTON (1)
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
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#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
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#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[1])
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#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI2)
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#define OMV_FIR_LEPTON_MOSI_PIN (GPIO_PIN_15)
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#define OMV_FIR_LEPTON_MOSI_PORT (GPIOB)
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#define OMV_FIR_LEPTON_MOSI_ALT (GPIO_AF5_SPI2)
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#define OMV_FIR_LEPTON_MISO_PIN (GPIO_PIN_14)
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#define OMV_FIR_LEPTON_MISO_PORT (GPIOB)
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#define OMV_FIR_LEPTON_MISO_ALT (GPIO_AF5_SPI2)
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#define OMV_FIR_LEPTON_SCLK_PIN (GPIO_PIN_13)
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#define OMV_FIR_LEPTON_SCLK_PORT (GPIOB)
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#define OMV_FIR_LEPTON_SCLK_ALT (GPIO_AF5_SPI2)
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#define OMV_FIR_LEPTON_CS_PIN (GPIO_PIN_12)
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#define OMV_FIR_LEPTON_CS_PORT (GPIOB)
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#define OMV_FIR_LEPTON_CS_HIGH() HAL_GPIO_WritePin(OMV_FIR_LEPTON_CS_PORT, OMV_FIR_LEPTON_CS_PIN, GPIO_PIN_SET)
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#define OMV_FIR_LEPTON_CS_LOW() HAL_GPIO_WritePin(OMV_FIR_LEPTON_CS_PORT, OMV_FIR_LEPTON_CS_PIN, GPIO_PIN_RESET)
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#endif //__OMV_BOARDCONFIG_H__
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