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https://github.com/openmv/openmv.git
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944 lines
38 KiB
C
944 lines
38 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file spi.h
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* @author Girish BN, Manoj A Murudi
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* @email girish.bn@alifsemi.com, manoj.murudi@alifsemi.com
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* @version V1.0.0
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* @date 20-04-2023
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* @brief Low Level Header file for SPI.
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* @bug None.
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* @Note None
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******************************************************************************/
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#ifndef SPI_H_
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#define SPI_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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/**
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* @brief LPSPI (LPSPI)
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*/
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typedef struct {
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volatile uint32_t SPI_CTRLR0; /*!< (@ 0x00000000) Control Register 0 */
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volatile uint32_t SPI_CTRLR1; /*!< (@ 0x00000004) Control Register 1 */
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volatile uint32_t SPI_ENR; /*!< (@ 0x00000008) SPI Enable Register */
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volatile uint32_t SPI_MWCR; /*!< (@ 0x0000000C) Microwire Control Register */
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volatile uint32_t SPI_SER; /*!< (@ 0x00000010) Slave Enable Register */
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volatile uint32_t SPI_BAUDR; /*!< (@ 0x00000014) Baud Rate Select Register */
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volatile uint32_t SPI_TXFTLR; /*!< (@ 0x00000018) Transmit FIFO Threshold Level Register */
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volatile uint32_t SPI_RXFTLR; /*!< (@ 0x0000001C) Receive FIFO Threshold Level Register */
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volatile const uint32_t SPI_TXFLR; /*!< (@ 0x00000020) Transmit FIFO Level Register */
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volatile const uint32_t SPI_RXFLR; /*!< (@ 0x00000024) Receive FIFO Level Register */
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volatile const uint32_t SPI_SR; /*!< (@ 0x00000028) Status Register */
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volatile uint32_t SPI_IMR; /*!< (@ 0x0000002C) Interrupt Mask Register */
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volatile const uint32_t SPI_ISR; /*!< (@ 0x00000030) Interrupt Status Register */
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volatile const uint32_t SPI_RISR; /*!< (@ 0x00000034) Raw Interrupt Status Register */
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volatile const uint32_t SPI_TXOICR; /*!< (@ 0x00000038) Transmit FIFO Overflow Interrupt Clear Register */
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volatile const uint32_t SPI_RXOICR; /*!< (@ 0x0000003C) Receive FIFO Overflow Interrupt Clear Register */
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volatile const uint32_t SPI_RXUICR; /*!< (@ 0x00000040) Receive FIFO Underflow Interrupt Clear Register */
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volatile const uint32_t SPI_MSTICR; /*!< (@ 0x00000044) Multi-Master Interrupt Clear Register */
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volatile const uint32_t SPI_ICR; /*!< (@ 0x00000048) Interrupt Clear Register */
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volatile uint32_t SPI_DMACR; /*!< (@ 0x0000004C) DMA Control Register */
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volatile uint32_t SPI_DMATDLR; /*!< (@ 0x00000050) DMA Transmit Data Level Register */
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volatile uint32_t SPI_DMARDLR; /*!< (@ 0x00000054) DMA Receive Data Level Register */
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volatile const uint32_t SPI_IDR; /*!< (@ 0x00000058) Reserved */
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volatile const uint32_t SPI_VERSION_ID; /*!< (@ 0x0000005C) Reserved */
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volatile uint32_t SPI_DR[36]; /*!< (@ 0x00000060) SPI Data Register (n) */
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volatile uint32_t SPI_RX_SAMPLE_DELAY; /*!< (@ 0x000000F0) RX Sample Delay Register */
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} SPI_Type; /*!< Size = 244 (0xf4) */
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#define SPI_TX_FIFO_DEPTH 16U
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#define SPI_RX_FIFO_DEPTH 16U
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#define SPI_MAX_SLAVE_SELECT_PINS 4U
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#define SPI_SLAVE_SELECT_PIN_MASK 0xFFFFFFF0U
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#define SPI_DATA_FRAME_SIZE_MIN 4U
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#define SPI_DATA_FRAME_SIZE_MAX 32U
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#define SPI_ENABLE 1U
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#define SPI_DISABLE 0U
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/* SPI Control Register 0 (CTRLR0) bit Definition, Macros, Offsets and Masks
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* these include DFS, FRF, SCPH, SCPOL, TMOD, etc
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*/
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/* Data Frame DFS bit[4:0]*/
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#define SPI_CTRLR0_DFS 0U
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#define SPI_CTRLR0_DFS_MASK (0x1FU << SPI_CTRLR0_DFS)
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/* Frame Format FRF bit[7:6] */
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#define SPI_CTRLR0_FRF 6U
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#define SPI_CTRLR0_FRF_MASK (0x3UL << SPI_CTRLR0_FRF)
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#define SPI_CTRLR0_FRF_MOTOROLA 0x00U /* 0x0 Motorola SPI Frame Format */
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#define SPI_CTRLR0_FRF_TI 0x40U /* 0x1 Texas Instruments SSP Frame Format */
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#define SPI_CTRLR0_FRF_MICROWIRE 0x80U /* 0X2 National Semiconductors Microwire Frame Format */
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/* Serial Clock Polarity SCPOL | Serial Clock Phase SCPH bit[9:8] */
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#define SPI_CTRLR0_SC 8U
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#define SPI_CTRLR0_SC_MASK (0x3UL << SPI_CTRLR0_SC)
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#define SPI_CTRLR0_SCPH_HIGH 0x100U /* 0x1 SPI SCPH high */
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#define SPI_CTRLR0_SCPH_LOW 0x000U /* 0x0 SPI SCPH low */
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#define SPI_CTRLR0_SCPOL_HIGH 0x200U /* 0x2 SPI SCPOL high */
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#define SPI_CTRLR0_SCPOL_LOW 0x000U /* 0x0 SPI SCPOL low */
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/* Transfer Mode TMOD bit[11:10] */
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#define SPI_CTRLR0_TMOD 10U
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#define SPI_CTRLR0_TMOD_MASK (0x3UL << SPI_CTRLR0_TMOD)
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#define SPI_CTRLR0_TMOD_TRANSFER 0x000U /* 0x0 SPI transfer mode */
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#define SPI_CTRLR0_TMOD_SEND_ONLY 0x400U /* 0x1 SPI send only mode */
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#define SPI_CTRLR0_TMOD_RECEIVE_ONLY 0x800U /* 0x2 SPI receive only mode */
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#define SPI_CTRLR0_TMOD_EEPROM_READ_ONLY 0xC00U /* 0x3 SPI EEPROM read only mode */
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/* Useful when SPI Controller acting as a Slave
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* When configured as a serial master, this
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* bit-field has no functionality.
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*/
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/*Slave Output Enable SLV_OE bit[12] */
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#define SPI_CTRLR0_SLV_OE 12U
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#define SPI_CTRLR0_SLV_OE_MASK (0x1UL << SPI_CTRLR0_SLV_OE)
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#define SPI_CTRLR0_SLV_OE_ENABLE 0x1000U /* 0x1 SPI slave output enable */
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#define SPI_CTRLR0_SLV_OE_DISABLE 0x0000U /* 0x0 SPI slave output disable */
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/* Slave Select toggle Enable bit[14]
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* While operating in SPI mode with clock phase (SCPH) set to
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* 0, this register controls the behavior of the slave select line
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* between data frames.
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*/
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/* Slave Select toggle Enable SSTE bit[14] */
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#define SPI_CTRLR0_SSTE 14U
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#define SPI_CTRLR0_SSTE_MASK (1<< SPI_CTRLR0_SSTE)
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#define SPI_CTRLR0_SSTE_ENABLE 0x4000U /* 0x1 SPI slave select toggle enable */
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#define SPI_CTRLR0_SSTE_DISABLE 0x0000U /* 0x0 SPI slave select toggle disable */
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/* Control Frame Size for the Microwire frame format CFS bit[19:16]*/
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#define SPI_CTRLR0_CFS 16U
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#define SPI_CTRLR0_CFS_MASK (0xF << SPI_CTRLR0_CFS)
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/* SPI Frame Format SPI_FRF bit[23:22]*/
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#define SPI_CTRLR0_SPI_FRF 22U
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#define SPI_CTRLR0_SPI_FRF_MASK (0xCU << SPI_CTRLR0_SPI_FRF)
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#define SPI_CTRLR0_SPI_FRF_STANDRAD 0x000000 /* 0x0 Standard SPI Format */
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#define SPI_CTRLR0_SPI_FRF_DUAL 0x400000 /* 0x1 Dual SPI Format */
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#define SPI_CTRLR0_SPI_FRF_QUAD 0x800000 /* 0X2 Quad SPI Format */
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#define SPI_CTRLR0_SPI_FRF_OCTAL 0xC00000 /* 0X2 Octal SPI Format */
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/* SPI Hyperbus Frame format enable SPI_HYPERBUS_EN bit[24] */
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#define SPI_CTRLR0_SPI_HYPERBUS_EN 24U
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#define SPI_CTRLR0_SPI_HYPERBUS_EN_SSTE_MASK (1 << SPI_CTRLR0_SPI_HYPERBUS_EN)
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#define SPI_CTRLR0_SPI_HYPERBUS_ENABLE 0x4000U /* 0x1 SPI Hyperbus Frame format enable */
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#define SPI_CTRLR0_SPI_HYPERBUS_DISABLE 0x0000U /* 0x0 SPI Hyperbus Frame format disable */
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/* SPI is working in Master or Slave SSI_IS_MST bit[31] */
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#define SPI_CTRLR0_SSI_IS_MST 31U
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#define SPI_CTRLR0_SSI_IS_MST_MASK (0x1UL << SPI_CTRLR0_SSI_IS_MST)
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#define SPI_CTRLR0_SSI_IS_MST_MASTER 0x80000000U /* 0x1 SPI master */
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#define SPI_CTRLR0_SSI_IS_MST_SLAVE 0x00000000U /* 0x0 SPI slave */
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/* Quad SPI MODE Macros */
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#define SPI_CTRLR0_SPI_QUAD_ENABLE (0x2UL << SPI_CTRLR0_SPI_FRF)
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#define SPI_CTRLR0_SPI_QUAD_TX_MODE SPI_TMOD_SEND_ONLY
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#define SPI_CTRLR0_SPI_QUAD_RX_MODE SPI_TMOD_RECEIVE_ONLY
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/* Octal SPI MODE Macros */
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#define SPI_CTRLR0_SPI_OCTAL_ENABLE (0x3UL << SPI_CTRLR0_SPI_FRF)
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#define SPI_CTRLR0_SPI_OCTAL_TX_RX_MODE SPI_TMOD_TRANSFER
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#define SPI_CTRLR0_SPI_OCTAL_TX_MODE SPI_TMOD_SEND_ONLY
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#define SPI_CTRLR0_SPI_OCTAL_RX_MODE SPI_TMOD_RECEIVE_ONLY
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/* LPSPI Control Register 0 (CTRLR0) bit Definition, Macros, Offsets and Masks */
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/* Data Frame DFS bit[3:0] */
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#define LPSPI_CTRLR0_DFS 0U
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#define LPSPI_CTRLR0_DFS_MASK (0xFU << LPSPI_CTRLR0_DFS)
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/* Frame Format FRF bit [5:4] */
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#define LPSPI_CTRLR0_FRF 4U
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#define LPSPI_CTRLR0_FRF_MASK (0x3UL << LPSPI_CTRLR0_FRF)
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#define LPSPI_CTRLR0_FRF_MOTOROLA 0x00U /* 0x0 Motorola SPI Frame Format */
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#define LPSPI_CTRLR0_FRF_TI 0x10U /* 0x1 Texas Instruments SSP Frame Format */
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#define LPSPI_CTRLR0_FRF_MICROWIRE 0x20U /* 0X2 National Semiconductors Microwire Frame Format */
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/* Serial Clock Polarity SCPOL | Serial Clock Phase SCPH bit [7:6] */
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#define LPSPI_CTRLR0_SC 6U
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#define LPSPI_CTRLR0_SC_MASK (0x3UL << LPSPI_CTRLR0_SC)
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#define LPSPI_CTRLR0_SCPH_HIGH 0x40U /* 0x1 SPI SCPH high */
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#define LPSPI_CTRLR0_SCPH_LOW 0x00U /* 0x0 SPI SCPH low */
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#define LPSPI_CTRLR0_SCPOL_HIGH 0x80U /* 0x2 SPI SCPOL high */
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#define LPSPI_CTRLR0_SCPOL_LOW 0x00U /* 0x0 SPI SCPOL low */
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/* Transfer Mode TMOD bit[9:8] */
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#define LPSPI_CTRLR0_TMOD 8U
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#define LPSPI_CTRLR0_TMOD_MASK (0x3UL << LPSPI_CTRLR0_TMOD)
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#define LPSPI_CTRLR0_TMOD_TRANSFER 0x000U /* 0x0 SPI transfer mode */
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#define LPSPI_CTRLR0_TMOD_SEND_ONLY 0x100U /* 0x1 SPI send only mode */
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#define LPSPI_CTRLR0_TMOD_RECEIVE_ONLY 0x200U /* 0x2 SPI receive only mode */
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#define LPSPI_CTRLR0_TMOD_EEPROM_READ_ONLY 0x300U /* 0x3 SPI EEPROM read only mode */
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/* Control Frame Size for the Microwire frame format CFS bit[15:12]*/
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#define LPSPI_CTRLR0_CFS 12U
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#define LPSPI_CTRLR0_CFS_MASK (0xF << LPSPI_CTRLR0_CFS)
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/* Data Frame DFS 32 bit [20:16] */
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#define LPSPI_CTRLR0_DFS_32 16U
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#define LPSPI_CTRLR0_DFS32_MASK (0x1FU << LPSPI_CTRLR0_DFS_32)
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/* Slave Select toggle Enable SSTE bit[24] */
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#define LPSPI_CTRLR0_SSTE 24U
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#define LPSPI_CTRLR0_SSTE_MASK (1 << LPSPI_CTRLR0_SSTE)
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#define LPSPI_CTRLR0_SSTE_ENABLE 0x1000000U /* 0x1 SPI slave select toggle enable */
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#define LPSPI_CTRLR0_SSTE_DISABLE 0x0000000U /* 0x0 SPI slave select toggle disable */
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/* Microwire Control Register (MWCR) bit Definition, Macros */
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/* Microwire Transfer Mode bit[0] */
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#define SPI_MWCR_MWMOD_SEQUENTIAL_MODE 0x1U
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#define SPI_MWCR_MWMOD_NON_SEQUENTIAL_MODE 0x0U
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/* Microwire Direction control bit[1] */
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#define SPI_MWCR_MDD_TRANSMIT 0x2U
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#define SPI_MWCR_MDD_RECEIVE 0x0U
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/* Microwire Handshake Interface bit[2] */
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#define SPI_MWCR_MHS_ENABLE 0x4U
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#define SPI_MWCR_MHS_DISABLE 0x0U
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#define SPI_TXFTLR_TFT_SHIFT 0U
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#define SPI_TXFTLR_TFT_MASK (0xFFFFU << SPI_TXFTLR_TFT_SHIFT)
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#define SPI_TXFTLR_TXFTHR_SHIFT 16U
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#define SPI_TXFTLR_TXFTHR_MASK (0xFFFFU << SPI_TXFTLR_TXFTHR_SHIFT)
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#define SPI_IMR_TX_FIFO_EMPTY_INTERRUPT_MASK 0x00000001U /* Transmit fifo empty interrupt mask*/
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#define SPI_IMR_TX_FIFO_OVER_FLOW_INTERRUPT_MASK 0x00000002U /* Transmit fifo overflow interrupt mask*/
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#define SPI_IMR_RX_FIFO_UNDER_FLOW_INTERRUPT_MASK 0x00000004U /* Receive fifo underflow interrupt mask*/
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#define SPI_IMR_RX_FIFO_OVER_FLOW_INTERRUPT_MASK 0x00000008U /* Receive fifo Overflow interrupt mask*/
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#define SPI_IMR_RX_FIFO_FULL_INTERRUPT_MASK 0x00000010U /* Receive fifo full interrupt mask*/
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#define SPI_IMR_MULTI_MASTER_CONTENTION_INTERRUPT_MASK 0x00000020U /* Multi-Master contention interrupt mask.*/
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#define SPI_DMACR_RX_DMA_ENABLE (0x1U)
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#define SPI_DMACR_TX_DMA_ENABLE (0x2U)
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#define SPI_SR_TFNF (0x2U)
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#define SPI_SR_RFNE (0x8U)
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#define SPI_SR_TX_FIFO_EMPTY (0x4U)
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#define SPI_SR_BUSY (0x1U)
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/****** SPI events *****/
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#define SPI_TX_FIFO_EMPTY_EVENT (0x01) /* Transmit fifo empty interrupt mask*/
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#define SPI_TX_FIFO_OVER_FLOW_EVENT (0x02) /* Transmit fifo overflow interrupt mask*/
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#define SPI_RX_FIFO_UNDER_FLOW_EVENT (0x04) /* Receive fifo underflow interrupt mask*/
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#define SPI_RX_FIFO_OVER_FLOW_EVENT (0x08) /* Receive fifo Overflow interrupt mask*/
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#define SPI_RX_FIFO_FULL_EVENT (0x10) /* Receive fifo full interrupt mask*/
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#define SPI_MULTI_MASTER_CONTENTION_EVENT (0x20) /* Multi-Master contention interrupt mask.*/
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/**
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* enum SPI_MODE.
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* SPI modes with CPOL and CPHA.
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*/
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typedef enum _SPI_MODE
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{
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SPI_MODE_0, /**< SPI Mode - 0 : CPHA = 0, CPOL = 0 */
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SPI_MODE_1, /**< SPI Mode - 1 : CPHA = 1, CPOL = 0 */
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SPI_MODE_2, /**< SPI Mode - 2 : CPHA = 0, CPOL = 1 */
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SPI_MODE_3 /**< SPI Mode - 3 : CPHA = 1, CPOL = 1 */
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} SPI_MODE;
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/**
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* enum SPI_PROTO.
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* Serial protocols.
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*/
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typedef enum _SPI_PROTO
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{
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SPI_PROTO_SPI, /**< Motorola SPI */
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SPI_PROTO_SSP, /**< Texas Instruments SSP */
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SPI_PROTO_MICROWIRE /**< National Semiconductors Microwire */
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} SPI_PROTO;
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/**
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* enum SPI_TMOD.
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* SPI transfer modes.
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*/
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typedef enum _SPI_TMOD
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{
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SPI_TMOD_TX_AND_RX = 0x00, /**< Transmit and Receive */
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SPI_TMOD_TX = 0x01, /*/mit only */
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SPI_TMOD_RX = 0x02, /**< Receive only */
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SPI_TMOD_EEPROM_READ = 0x03 /**< EEPROM read */
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} SPI_TMOD;
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/**
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* enum SPI_SS_STATE.
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* SPI Slave Select States.
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*/
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typedef enum _SPI_SS_STATE
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{
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SPI_SS_STATE_DISABLE, /**< Slave select disabled */
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SPI_SS_STATE_ENABLE, /**< Slave select Enabled */
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} SPI_SS_STATE;
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/**
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* enum SPI_TRANSFER_STATUS.
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* Status of an ongoing SPI transfer.
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*/
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typedef enum _SPI_TRANSFER_STATUS
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{
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SPI_TRANSFER_STATUS_NONE, /**< Transfer status none */
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SPI_TRANSFER_STATUS_COMPLETE, /**< Transfer status complete */
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SPI_TRANSFER_STATUS_OVERFLOW, /**< Transfer status Tx/Rx overflow */
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SPI_TRANSFER_STATUS_MASTER_CONTENTION, /**< Transfer status master contention */
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SPI_TRANSFER_STATUS_RX_UNDERFLOW, /**< Transfer status Rx underflow */
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} SPI_TRANSFER_STATUS;
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typedef struct _spi_transfer_t {
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volatile uint32_t tx_current_cnt; /**< Current Tx Transfer count */
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volatile uint32_t rx_current_cnt; /**< Current Rx Transfer count */
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uint32_t tx_total_cnt; /**< Total count to Tx transfer */
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uint32_t rx_total_cnt; /**< Total count to Rx transfer */
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const uint8_t *tx_buff; /**< Pointer to TX buffer */
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void *rx_buff; /**< Pointer to Rx buffer */
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uint32_t tx_default_val; /**< Default value to Transfer */
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bool tx_default_enable; /**< Enable Tx default value transfer */
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bool is_master; /**< SPI is master/slave */
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SPI_TMOD mode; /**< SPI transfer mode */
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uint8_t frame_size; /**< SPI Data frame size */
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volatile SPI_TRANSFER_STATUS status; /**< transfer status */
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} spi_transfer_t;
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/**
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\fn static inline void spi_disable(SPI_Type *spi)
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\brief Disable the SPI instance
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\param[in] spi Pointer to the SPI register map
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\return none
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*/
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static inline void spi_disable(SPI_Type *spi)
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{
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spi->SPI_ENR = SPI_DISABLE;
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}
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/**
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\fn static inline void spi_enable(SPI_Type *spi)
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\brief Enable the SPI instance
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\param[in] spi Pointer to the SPI register map
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\return none
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*/
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static inline void spi_enable(SPI_Type *spi)
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{
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spi->SPI_ENR = SPI_ENABLE;
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}
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/**
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\fn static inline void spi_mode_master(SPI_Type *spi)
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\brief Enable master mode in the SPI instance.
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\param[in] spi Pointer to the SPI register map
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\return none
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*/
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static inline void spi_mode_master(SPI_Type *spi)
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{
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spi_disable(spi);
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spi->SPI_CTRLR0 |= SPI_CTRLR0_SSI_IS_MST_MASTER;
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spi_enable(spi);
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}
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/**
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\fn static inline void spi_mode_slave(SPI_Type *spi)
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\brief Enable slave mode in the SPI instance.
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\param[in] spi Pointer to the SPI register map
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\return none
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*/
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static inline void spi_mode_slave(SPI_Type *spi)
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{
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spi_disable(spi);
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spi->SPI_CTRLR0 &= ~SPI_CTRLR0_SSI_IS_MST_MASTER;
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spi_enable(spi);
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}
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/**
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\fn static inline void spi_set_bus_speed(SPI_Type *spi, uint32_t speed, uint32_t clk)
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\brief Set the bus speed for the SPI instance.
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\param[in] spi Pointer to the SPI register map
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\param[in] speed The bus speed to be set
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\param[in] clk SPI input clk
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\return none
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*/
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static inline void spi_set_bus_speed(SPI_Type *spi, uint32_t speed, uint32_t clk)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_BAUDR = (clk / speed);
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline uint32_t spi_get_bus_speed(SPI_Type *spi, uint32_t clk)
|
|
\brief Get the current bus speed of the SPI instance.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] clk SPI input clk
|
|
\return Current bus speed
|
|
*/
|
|
static inline uint32_t spi_get_bus_speed(SPI_Type *spi, uint32_t clk)
|
|
{
|
|
return clk / spi->SPI_BAUDR;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_mask_interrupts(SPI_Type *spi)
|
|
\brief Mask all the interrupts for the SPI instance
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_mask_interrupts(SPI_Type *spi)
|
|
{
|
|
spi->SPI_IMR = 0;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_enable_rx_dma(SPI_Type *spi)
|
|
\brief Enable SPI RX DMA Block
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_enable_rx_dma(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_DMACR |= SPI_DMACR_RX_DMA_ENABLE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_disable_rx_dma(SPI_Type *spi)
|
|
\brief Enable SPI RX DMA Block
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_disable_rx_dma(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_DMACR &= ~SPI_DMACR_RX_DMA_ENABLE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_enable_tx_dma(SPI_Type *spi)
|
|
\brief Enable SPI TX DMA Block
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_enable_tx_dma(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_DMACR |= SPI_DMACR_TX_DMA_ENABLE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_disable_tx_dma(SPI_Type *spi)
|
|
\brief Enable SPI TX DMA Block
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_disable_tx_dma(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_DMACR &= ~SPI_DMACR_TX_DMA_ENABLE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_set_dma_rx_level(SPI_Type *spi, uint8_t data_level)
|
|
\brief Enable SPI RX DMA Block
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_set_dma_rx_level(SPI_Type *spi, uint8_t data_level)
|
|
{
|
|
spi->SPI_DMARDLR = data_level;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_set_dma_tx_level(SPI_Type *spi, uint8_t data_level)
|
|
\brief Enable SPI TX DMA Block
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_set_dma_tx_level(SPI_Type *spi, uint8_t data_level)
|
|
{
|
|
spi->SPI_DMATDLR = data_level;
|
|
}
|
|
|
|
/**
|
|
\fn volatile uint32_t* spi_get_data_addr(SPI_Type *spi)
|
|
\brief Return the Data reg Address
|
|
\param[in] spi Pointer to SPI register map
|
|
\return \ref Return the address
|
|
*/
|
|
static inline volatile uint32_t* spi_get_data_addr(SPI_Type *spi)
|
|
{
|
|
return &spi->SPI_DR[0];
|
|
}
|
|
|
|
/**
|
|
\fn bool spi_busy(SPI_Type *spi)
|
|
\brief return spi busy status
|
|
\param[in] spi Pointer to SPI register map
|
|
\return \ref spi busy status
|
|
*/
|
|
static inline bool spi_busy(SPI_Type *spi)
|
|
{
|
|
return (spi->SPI_SR & 1);
|
|
}
|
|
|
|
/**
|
|
\fn void spi_set_rx_sample_delay(SPI_Type *spi, uint8_t rx_sample_delay)
|
|
\brief Set Receive sample delay for the SPI instance
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] rx_sample_delay rx sample delay
|
|
\return none
|
|
*/
|
|
static inline void spi_set_rx_sample_delay(SPI_Type *spi, uint8_t rx_sample_delay)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_RX_SAMPLE_DELAY = rx_sample_delay;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_mw_enable_handshake(SPI_Type *spi)
|
|
\brief Enable microwire handshake feature
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_mw_enable_handshake(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_MWCR |= SPI_MWCR_MHS_ENABLE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_mw_disable_handshake(SPI_Type *spi)
|
|
\brief Disable microwire handshake feature
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_mw_disable_handshake(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_MWCR |= SPI_MWCR_MHS_DISABLE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_mw_set_sequential_mode(SPI_Type *spi)
|
|
\brief config microwire Sequential transfer mode
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_mw_set_sequential_mode(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_MWCR |= SPI_MWCR_MWMOD_SEQUENTIAL_MODE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_mw_set_non_sequential_mode(SPI_Type *spi)
|
|
\brief config microwire non-sequential transfer mode
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
static inline void spi_mw_set_non_sequential_mode(SPI_Type *spi)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_MWCR |= SPI_MWCR_MWMOD_NON_SEQUENTIAL_MODE;
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void lpspi_mw_set_cfs(SPI_Type *lpspi, uint8_t cfs)
|
|
\brief set microwire control frame size for lpspi
|
|
\param[in] lpspi Pointer to the SPI register map
|
|
\param[in] cfs control frame size
|
|
\return none
|
|
*/
|
|
static inline void lpspi_mw_set_cfs(SPI_Type *lpspi, uint8_t cfs)
|
|
{
|
|
spi_disable(lpspi);
|
|
lpspi->SPI_CTRLR0 |= ((cfs - 1) << LPSPI_CTRLR0_CFS);
|
|
spi_enable(lpspi);
|
|
}
|
|
|
|
/**
|
|
\fn static inline void spi_mw_set_cfs(SPI_Type *spi, uint8_t cfs)
|
|
\brief set microwire control frame size for spi
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] cfs control frame size
|
|
\return none
|
|
*/
|
|
static inline void spi_mw_set_cfs(SPI_Type *spi, uint8_t cfs)
|
|
{
|
|
spi_disable(spi);
|
|
spi->SPI_CTRLR0 |= ((cfs - 1) << SPI_CTRLR0_CFS);
|
|
spi_enable(spi);
|
|
}
|
|
|
|
/**
|
|
\fn void spi_set_mode(SPI_Type *spi, SPI_MODE mode)
|
|
\brief Set the SPI mode for the SPI instance.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] mode The mode to be set.
|
|
\return none
|
|
*/
|
|
void spi_set_mode(SPI_Type *spi, SPI_MODE mode);
|
|
|
|
/**
|
|
\fn void spi_set_protocol(SPI_Type *spi, SPI_PROTO format)
|
|
\brief Set the protocol format for the SPI instance.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] format The protocol to be set
|
|
\return none
|
|
*/
|
|
void spi_set_protocol(SPI_Type *spi, SPI_PROTO format);
|
|
|
|
/**
|
|
\fn void spi_set_dfs(SPI_Type *spi, uint8_t dfs)
|
|
\brief Set the data frame size for the SPI instance.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] dfs The data frame size
|
|
\return none
|
|
*/
|
|
void spi_set_dfs(SPI_Type *spi, uint8_t dfs);
|
|
|
|
/**
|
|
\fn void spi_set_tmode(SPI_Type *spi, SPI_TMOD tmod)
|
|
\brief Set the transfer mode for the SPI instance.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] tmod Transfer mode
|
|
\return none
|
|
*/
|
|
void spi_set_tmod(SPI_Type *spi, SPI_TMOD tmod);
|
|
|
|
/**
|
|
\fn SPI_TMOD spi_get_tmod(SPI_Type *spi)
|
|
\brief Get the transfer mode of the SPI instance.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return The current transfer mode
|
|
*/
|
|
SPI_TMOD spi_get_tmod(SPI_Type *spi);
|
|
|
|
/**
|
|
\fn void spi_set_sste(SPI_Type *spi, bool enable)
|
|
\brief Enable/Disable Slave Select Toggle for the SPI instance
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] enable Enable/Disable control
|
|
\return none
|
|
*/
|
|
void spi_set_sste(SPI_Type *spi, bool enable);
|
|
|
|
/**
|
|
\fn void spi_set_tx_threshold(SPI_Type *spi, uint8_t threshold)
|
|
\brief Set Transmit FIFO interrupt threshold for the SPI instance
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] threshold Transmit FIFO threshold
|
|
\return none
|
|
*/
|
|
void spi_set_tx_threshold(SPI_Type *spi, uint8_t threshold);
|
|
|
|
/**
|
|
\fn void spi_set_rx_threshold(SPI_Type *spi, uint8_t threshold)
|
|
\brief Set Receive FIFO interrupt threshold for the SPI instance
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] threshold Receive FIFO threshold
|
|
\return none
|
|
*/
|
|
void spi_set_rx_threshold(SPI_Type *spi, uint8_t threshold);
|
|
|
|
/**
|
|
\fn void spi_set_tx_fifo_start_level(SPI_Type *spi, uint16_t level)
|
|
\brief Set Transmit FIFO start level
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] level Transmit FIFO start level
|
|
\return none
|
|
*/
|
|
void spi_set_tx_fifo_start_level(SPI_Type *spi, uint16_t level);
|
|
|
|
/**
|
|
\fn void spi_control_ss(SPI_Type *spi, uint8_t slave, SPI_SS_STATE state)
|
|
\brief Control the slave select line
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] slave The slave to be selected
|
|
\param[in] state The state of the slave select line
|
|
\return none
|
|
*/
|
|
void spi_control_ss(SPI_Type *spi, uint8_t slave, SPI_SS_STATE state);
|
|
|
|
/**
|
|
\fn void spi_send(SPI_Type *spi)
|
|
\brief Prepare the SPI instance for transmission
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
void spi_send(SPI_Type *spi);
|
|
|
|
/**
|
|
\fn void spi_receive(SPI_Type *spi, spi_transfer_t *transfer)
|
|
\brief Prepare the SPI instance for reception
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] transfer Pointer to transfer structure
|
|
\return none
|
|
*/
|
|
void spi_receive(SPI_Type *spi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn void spi_transfer(SPI_Type *spi)
|
|
\brief Prepare the SPI instance for transfer
|
|
\param[in] spi Pointer to the SPI register map
|
|
\return none
|
|
*/
|
|
void spi_transfer(SPI_Type *spi);
|
|
|
|
/**
|
|
\fn void spi_send_blocking(SPI_Type *spi, spi_transfer_t *transfer)
|
|
\brief Execute a blocking SPI send described by the transfer structure.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] transfer Pointer to the SPI transfer structure
|
|
\return none
|
|
*/
|
|
void spi_send_blocking(SPI_Type *spi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn void spi_receive_blocking(SPI_Type *spi, spi_transfer_t *transfer)
|
|
\brief Execute a blocking SPI receive described by the transfer structure.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] transfer Pointer to the SPI transfer structure
|
|
\return none
|
|
*/
|
|
void spi_receive_blocking(SPI_Type *spi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn void spi_transfer_blocking(SPI_Type *spi, spi_transfer_t *transfer)
|
|
\brief Execute a blocking SPI transfer described by the transfer structure.
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] transfer Pointer to the SPI transfer structure
|
|
\return none
|
|
*/
|
|
void spi_transfer_blocking(SPI_Type *spi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn void lpspi_send_blocking(SPI_Type *lpspi, spi_transfer_t *transfer)
|
|
\brief Execute a blocking SPI receive described by the transfer structure.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] transfer Pointer to transfer structure
|
|
\return none
|
|
*/
|
|
void lpspi_send_blocking(SPI_Type *lpspi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn void lpspi_receive_blocking(SPI_Type *lpspi, spi_transfer_t *transfer)
|
|
\brief Execute a blocking SPI send described by the transfer structure.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] transfer Pointer to transfer structure
|
|
\return none
|
|
*/
|
|
void lpspi_receive_blocking(SPI_Type *lpspi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn void lpspi_transfer_blocking(SPI_Type *lpspi, spi_transfer_t *transfer)
|
|
\brief Execute a blocking SPI transfer described by the transfer structure.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] transfer Pointer to transfer structure
|
|
\return none
|
|
*/
|
|
void lpspi_transfer_blocking(SPI_Type *lpspi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn void lpspi_set_mode(SPI_Type *spi, SPI_MODE mode)
|
|
\brief Set the mode for the LPSPI instance.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] mode The mode to be set.
|
|
\return none
|
|
*/
|
|
void lpspi_set_mode(SPI_Type *lpspi, SPI_MODE mode);
|
|
|
|
/**
|
|
\fn void lpspi_set_protocol(SPI_Type *lpspi, SPI_PROTO format)
|
|
\brief Set the protocol format for the LPSPI instance.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] format The protocol to be set
|
|
\return none
|
|
*/
|
|
void lpspi_set_protocol(SPI_Type *lpspi, SPI_PROTO format);
|
|
|
|
/**
|
|
\fn void lpspi_set_dfs(SPI_Type *lpspi, uint8_t dfs)
|
|
\brief Set the data frame size for the LPSPI instance.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] dfs The data frame size
|
|
\return none
|
|
*/
|
|
void lpspi_set_dfs(SPI_Type *lpspi, uint8_t dfs);
|
|
|
|
/**
|
|
\fn void lpspi_set_tmod(SPI_Type *lpspi, SPI_TMOD tmod)
|
|
\brief Set the transfer mode for the LPSPI instance.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] tmod Transfer mode
|
|
\return none
|
|
*/
|
|
void lpspi_set_tmod(SPI_Type *lpspi, SPI_TMOD tmod);
|
|
|
|
/**
|
|
\fn SPI_TMOD lpspi_get_tmod(SPI_Type *lpspi)
|
|
\brief Get the transfer mode of the LPSPI instance.
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\return The current transfer mode
|
|
*/
|
|
SPI_TMOD lpspi_get_tmod(SPI_Type *lpspi);
|
|
|
|
/**
|
|
\fn void lpspi_send(SPI_Type *spi)
|
|
\brief Prepare the SPI instance for transmission
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\return none
|
|
*/
|
|
void lpspi_send(SPI_Type *lpspi);
|
|
|
|
/**
|
|
\fn void lpspi_receive(SPI_Type *lpspi, uint32_t total_cnt)
|
|
\brief Prepare the LPSPI instance for reception
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\param[in] total_cnt total number of data count
|
|
\return none
|
|
*/
|
|
void lpspi_receive(SPI_Type *lpspi, uint32_t total_cnt);
|
|
|
|
/**
|
|
\fn void lpspi_transfer(SPI_Type *lpspi)
|
|
\brief Prepare the LPSPI instance for transfer
|
|
\param[in] lpspi Pointer to the LPSPI register map
|
|
\return none
|
|
*/
|
|
void lpspi_transfer(SPI_Type *lpspi);
|
|
|
|
/**
|
|
\fn void lpspi_set_sste(SPI_Type *lpspi, bool enable)
|
|
\brief Enable/Disable Slave Select Toggle for the LPSPI instance
|
|
\param[in] lpspi Pointer to the SPI register map
|
|
\param[in] enable Enable/Disable control
|
|
\return none
|
|
*/
|
|
void lpspi_set_sste(SPI_Type *lpspi, bool enable);
|
|
|
|
/**
|
|
\fn void spi_mw_transmit(SPI_Type *spi, bool is_slave)
|
|
\brief config microwire in transmit mode
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] is_slave whether config as master/slave
|
|
\return none
|
|
*/
|
|
void spi_mw_transmit(SPI_Type *spi, bool is_slave);
|
|
|
|
/**
|
|
\fn void spi_mw_receive(SPI_Type *spi, spi_transfer_t *transfer)
|
|
\brief config microwire in receive mode
|
|
\param[in] spi Pointer to the SPI register map
|
|
\param[in] transfer pointer to transfer structure
|
|
\return none
|
|
*/
|
|
void spi_mw_receive(SPI_Type *spi, spi_transfer_t *transfer);
|
|
|
|
/**
|
|
\fn uint32_t spi_dma_calc_rx_level(uint32_t total_cnt, uint8_t fifo_threshold)
|
|
\brief Calculate SPI DMA receive data level
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\param[in] fifo_threshold receive fifo threshold value
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\param[in] total_cnt total number of data count
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\return final value after calculation
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*/
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uint32_t spi_dma_calc_rx_level(uint32_t total_cnt, uint8_t fifo_threshold);
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/**
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\fn void spi_dma_send(SPI_Type *spi)
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\brief Prepare the SPI instance for DMA send
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\param[in] spi Pointer to the SPI register map
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\return none
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*/
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void spi_dma_send(SPI_Type *spi);
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/**
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\fn void spi_dma_receive(SPI_Type *spi, spi_transfer_t *transfer)
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\brief Prepare the SPI instance for DMA reception
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\param[in] spi Pointer to the SPI register map
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\param[in] transfer Pointer to transfer structure
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\return none
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*/
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void spi_dma_receive(SPI_Type *spi, spi_transfer_t *transfer);
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/**
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\fn void spi_dma_transfer(SPI_Type *spi)
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\brief Prepare the SPI instance for DMA transfer
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\param[in] spi Pointer to the SPI register map
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\return none
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*/
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void spi_dma_transfer(SPI_Type *spi);
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/**
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\fn void lpspi_dma_send(SPI_Type *spi)
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\brief Prepare the SPI instance for DMA transmission
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\param[in] lpspi Pointer to the LPSPI register map
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\return none
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*/
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void lpspi_dma_send(SPI_Type *lpspi);
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/**
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\fn void lpspi_dma_receive(SPI_Type *lpspi, uint32_t total_cnt)
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\brief Prepare the LPSPI instance for DMA reception
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\param[in] lpspi Pointer to the LPSPI register map
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\param[in] total_cnt total number of data count
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\return none
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*/
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void lpspi_dma_receive(SPI_Type *lpspi, uint32_t total_cnt);
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/**
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\fn void lpspi_dma_transfer(SPI_Type *lpspi)
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\brief Prepare the LPSPI instance for DMA transfer
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\param[in] lpspi Pointer to the LPSPI register map
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\return none
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*/
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void lpspi_dma_transfer(SPI_Type *lpspi);
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/**
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\fn void spi_irq_handler(SPI_Type *spi, spi_master_transfer_t *transfer)
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\brief Handle interrupts for the SPI instance.
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\param[in] spi Pointer to the SPI register map
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\param[in] transfer The transfer structure for the SPI instance
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\return none
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*/
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void spi_irq_handler(SPI_Type *spi, spi_transfer_t *transfer);
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/**
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\fn void spi_mw_irq_handler(SPI_Type *spi, spi_master_transfer_t *transfer)
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\brief Handle interrupts for the MW frame format.
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\param[in] spi Pointer to the SPI register map
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\param[in] transfer The transfer structure for the SPI instance
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\return none
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*/
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void spi_mw_irq_handler(SPI_Type *spi, spi_transfer_t *transfer);
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#ifdef __cplusplus
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}
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#endif
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#endif /* SPI_H_ */
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