mirror of
https://github.com/openmv/openmv.git
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324 lines
8.4 KiB
C
324 lines
8.4 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2023-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* STM32 DMA helper functions.
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*/
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#include <stdbool.h>
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#include STM32_HAL_H
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#include "py/mphal.h"
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#include "omv_boardconfig.h"
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#include "omv_common.h"
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#include "dma_utils.h"
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#if defined(GPDMA1)
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static DMA_HandleTypeDef *dma_handle[32];
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#else
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// Defined in micropython/ports/stm32/dma.c or in uvc/src/main.c
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extern DMA_HandleTypeDef *dma_handle[16];
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#endif
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uint8_t dma_utils_channel_to_irqn(void *dma_channel) {
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if (0) {
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#if defined(DMA1_Stream0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA1_BASE) {
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return ((DMA_Stream_TypeDef *) dma_channel - DMA1_Stream0) + DMA1_Stream0_IRQn;
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#endif
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#if defined(DMA2_Stream0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA2_BASE) {
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return ((DMA_Stream_TypeDef *) dma_channel - DMA2_Stream0) + DMA2_Stream0_IRQn;
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#endif
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#if defined(GPDMA1_Channel0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFF000) == GPDMA1_BASE) {
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return ((DMA_Channel_TypeDef *) dma_channel - GPDMA1_Channel0) + GPDMA1_Channel0_IRQn;
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#endif
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#if defined(HPDMA1_Channel0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFF000) == HPDMA1_BASE) {
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return ((DMA_Channel_TypeDef *) dma_channel - HPDMA1_Channel0) + HPDMA1_Channel0_IRQn;
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#endif
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}
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return 0;
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}
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// This returns a DMA ID that can be used to index into the dma_handle
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// array defined in micropython. Setting a DMA handle in that array allows
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// DMA IRQ handlers (which are all defined in micropython) to use it.
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uint8_t dma_utils_channel_to_id(void *dma_channel) {
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if (0) {
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#if defined(DMA1_Stream0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA1_BASE) {
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return ((DMA_Stream_TypeDef *) dma_channel - DMA1_Stream0);
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#endif
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#if defined(DMA2_Stream0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFFF00) == DMA2_BASE) {
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return ((DMA_Stream_TypeDef *) dma_channel - DMA2_Stream0) + 8;
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#endif
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#if defined(GPDMA1_Channel0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFF000) == GPDMA1_BASE) {
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return ((DMA_Channel_TypeDef *) dma_channel - GPDMA1_Channel0);
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#endif
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#if defined(HPDMA1_Channel0)
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} else if ((((uint32_t) dma_channel) & 0xFFFFF000) == HPDMA1_BASE) {
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return ((DMA_Channel_TypeDef *) dma_channel - HPDMA1_Channel0) + 16;
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#endif
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}
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return -1;
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}
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int dma_utils_set_irq_descr(void *dma_channel, DMA_HandleTypeDef *dma_descr) {
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uint8_t dma_id = dma_utils_channel_to_id(dma_channel);
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if (dma_id != -1) {
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dma_handle[dma_id] = dma_descr;
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return 0;
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}
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return -1;
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}
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uint8_t dma_utils_mpu_region_size(uint32_t size) {
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#if (__ARM_ARCH <= 7)
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switch (size) {
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case 0x00000020U: {
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return MPU_REGION_SIZE_32B;
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}
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case 0x00000040U: {
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return MPU_REGION_SIZE_64B;
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}
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case 0x00000080U: {
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return MPU_REGION_SIZE_128B;
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}
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case 0x00000100U: {
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return MPU_REGION_SIZE_256B;
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}
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case 0x00000200U: {
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return MPU_REGION_SIZE_512B;
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}
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case 0x00000400U: {
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return MPU_REGION_SIZE_1KB;
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}
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case 0x00000800U: {
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return MPU_REGION_SIZE_2KB;
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}
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case 0x00001000U: {
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return MPU_REGION_SIZE_4KB;
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}
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case 0x00002000U: {
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return MPU_REGION_SIZE_8KB;
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}
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case 0x00004000U: {
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return MPU_REGION_SIZE_16KB;
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}
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case 0x00008000U: {
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return MPU_REGION_SIZE_32KB;
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}
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case 0x00010000U: {
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return MPU_REGION_SIZE_64KB;
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}
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case 0x00020000U: {
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return MPU_REGION_SIZE_128KB;
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}
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case 0x00040000U: {
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return MPU_REGION_SIZE_256KB;
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}
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case 0x00080000U: {
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return MPU_REGION_SIZE_512KB;
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}
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case 0x00100000U: {
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return MPU_REGION_SIZE_1MB;
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}
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case 0x00200000U: {
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return MPU_REGION_SIZE_2MB;
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}
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case 0x00400000U: {
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return MPU_REGION_SIZE_4MB;
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}
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case 0x00800000U: {
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return MPU_REGION_SIZE_8MB;
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}
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case 0x01000000U: {
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return MPU_REGION_SIZE_16MB;
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}
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case 0x02000000U: {
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return MPU_REGION_SIZE_32MB;
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}
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case 0x04000000U: {
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return MPU_REGION_SIZE_64MB;
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}
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case 0x08000000U: {
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return MPU_REGION_SIZE_128MB;
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}
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case 0x10000000U: {
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return MPU_REGION_SIZE_256MB;
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}
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case 0x20000000U: {
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return MPU_REGION_SIZE_512MB;
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}
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case 0x40000000U: {
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return MPU_REGION_SIZE_1GB;
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}
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case 0x80000000U: {
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return MPU_REGION_SIZE_2GB;
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}
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default: {
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return MPU_REGION_SIZE_4GB;
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}
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}
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#endif
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return -1;
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}
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#if defined(GPDMA1)
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static inline void dma_utils_irq_handler(size_t irqn) {
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if (dma_handle[irqn] != NULL) {
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HAL_DMA_IRQHandler(dma_handle[irqn]);
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}
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}
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void GPDMA1_Channel0_IRQHandler(void) {
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dma_utils_irq_handler(0);
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}
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void GPDMA1_Channel1_IRQHandler(void) {
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dma_utils_irq_handler(1);
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}
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void GPDMA1_Channel2_IRQHandler(void) {
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dma_utils_irq_handler(2);
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}
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void GPDMA1_Channel3_IRQHandler(void) {
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dma_utils_irq_handler(3);
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}
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void GPDMA1_Channel4_IRQHandler(void) {
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dma_utils_irq_handler(4);
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}
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void GPDMA1_Channel5_IRQHandler(void) {
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dma_utils_irq_handler(5);
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}
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void GPDMA1_Channel6_IRQHandler(void) {
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dma_utils_irq_handler(6);
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}
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void GPDMA1_Channel7_IRQHandler(void) {
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dma_utils_irq_handler(7);
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}
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void GPDMA1_Channel8_IRQHandler(void) {
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dma_utils_irq_handler(8);
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}
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void GPDMA1_Channel9_IRQHandler(void) {
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dma_utils_irq_handler(9);
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}
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void GPDMA1_Channel10_IRQHandler(void) {
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dma_utils_irq_handler(10);
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}
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void GPDMA1_Channel11_IRQHandler(void) {
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dma_utils_irq_handler(11);
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}
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void GPDMA1_Channel12_IRQHandler(void) {
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dma_utils_irq_handler(12);
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}
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void GPDMA1_Channel13_IRQHandler(void) {
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dma_utils_irq_handler(13);
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}
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void GPDMA1_Channel14_IRQHandler(void) {
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dma_utils_irq_handler(14);
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}
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void GPDMA1_Channel15_IRQHandler(void) {
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dma_utils_irq_handler(15);
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}
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void HPDMA1_Channel0_IRQHandler(void) {
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dma_utils_irq_handler(16);
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}
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void HPDMA1_Channel1_IRQHandler(void) {
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dma_utils_irq_handler(17);
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}
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void HPDMA1_Channel2_IRQHandler(void) {
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dma_utils_irq_handler(18);
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}
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void HPDMA1_Channel3_IRQHandler(void) {
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dma_utils_irq_handler(19);
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}
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void HPDMA1_Channel4_IRQHandler(void) {
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dma_utils_irq_handler(20);
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}
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void HPDMA1_Channel5_IRQHandler(void) {
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dma_utils_irq_handler(21);
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}
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void HPDMA1_Channel6_IRQHandler(void) {
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dma_utils_irq_handler(22);
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}
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void HPDMA1_Channel7_IRQHandler(void) {
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dma_utils_irq_handler(23);
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}
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void HPDMA1_Channel8_IRQHandler(void) {
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dma_utils_irq_handler(24);
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}
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void HPDMA1_Channel9_IRQHandler(void) {
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dma_utils_irq_handler(25);
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}
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void HPDMA1_Channel10_IRQHandler(void) {
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dma_utils_irq_handler(26);
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}
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void HPDMA1_Channel11_IRQHandler(void) {
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dma_utils_irq_handler(27);
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}
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void HPDMA1_Channel12_IRQHandler(void) {
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dma_utils_irq_handler(28);
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}
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void HPDMA1_Channel13_IRQHandler(void) {
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dma_utils_irq_handler(29);
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}
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void HPDMA1_Channel14_IRQHandler(void) {
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dma_utils_irq_handler(30);
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}
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void HPDMA1_Channel15_IRQHandler(void) {
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dma_utils_irq_handler(31);
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}
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#endif
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