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349 lines
14 KiB
C
349 lines
14 KiB
C
/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2021 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2021 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_ARCH_STR "NICLAV H7 1024" // 33 chars max
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#define OMV_BOARD_TYPE "NICLAV"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800 // Unique ID address.
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#define OMV_UNIQUE_ID_SIZE 3 // Unique ID size in words.
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#define OMV_UNIQUE_ID_OFFSET 4 // Bytes offset for multi-word UIDs.
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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#define OMV_XCLK_OSC (2U)
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// Sensor external clock source
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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// Sensor external clock timer frequency
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#define OMV_XCLK_FREQUENCY (12000000)
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// GC4145 Sensor Settings
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#define OMV_GC2145_ROTATE (1)
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// Enable hardware JPEG
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#define OMV_HARDWARE_JPEG (1)
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// Enable MDMA sensor offload
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#define OMV_ENABLE_SENSOR_MDMA (1)
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// Enable additional GPIO banks
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#define OMV_ENABLE_GPIO_BANK_F (1)
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#define OMV_ENABLE_GPIO_BANK_G (1)
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#define OMV_ENABLE_GPIO_BANK_H (1)
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#define OMV_ENABLE_GPIO_BANK_I (1)
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#define OMV_ENABLE_GPIO_BANK_J (1)
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#define OMV_ENABLE_GPIO_BANK_K (1)
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// Configure image sensor drivers
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#define OMV_ENABLE_OV2640 (0)
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#define OMV_ENABLE_OV5640 (0)
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#define OMV_ENABLE_OV7690 (1)
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#define OMV_ENABLE_OV7725 (0)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9V0XX (0)
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#define OMV_ENABLE_MT9M114 (1)
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#define OMV_ENABLE_LEPTON (0)
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#define OMV_ENABLE_HM01B0 (0)
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#define OMV_ENABLE_GC2145 (1)
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// Configure FIR sensors drivers
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#define OMV_ENABLE_FIR_MLX90621 (1)
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#define OMV_ENABLE_FIR_MLX90640 (1)
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#define OMV_ENABLE_FIR_MLX90641 (1)
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#define OMV_ENABLE_FIR_AMG8833 (1)
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#define OMV_ENABLE_FIR_LEPTON (1)
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// Enable WiFi debug
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#define OMV_ENABLE_WIFIDBG (0)
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// Enable self-tests on first boot
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#define OMV_ENABLE_SELFTEST (0)
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// If buffer size is bigger than this threshold, the quality is reduced.
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// This is only used for JPEG images sent to the IDE not normal compression.
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#define JPEG_QUALITY_THRESH (320*240*2)
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// Low and high JPEG QS.
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 16
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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// USB IRQn.
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#define OMV_USB_IRQN (OTG_HS_IRQn)
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#define OMV_USB_ULPI (1)
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#define OMV_USB_ULPI_STP_PIN (&omv_pin_C0_OTG_HS)
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#define OMV_USB_ULPI_DIR_PIN (&omv_pin_C2_OTG_HS)
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// Defined for cpu frequency scaling to override the revid.
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#define OMV_MAX_CPU_FREQ (400)
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// PLL1 400MHz/40MHz for SDMMC and FDCAN
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// USB and RNG are clocked from the HSI48
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#define OMV_OSC_PLL1M (5)
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#define OMV_OSC_PLL1N (160)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (16)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (80)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (5)
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#define OMV_OSC_PLL3N (160)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (5)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_PLL_CLKSOURCE RCC_PLLSOURCE_HSE
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI45_CLKSOURCE RCC_SPI45CLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
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#define OMV_OSC_DFSDM1_CLKSOURCE RCC_DFSDM1CLKSOURCE_D2PCLK1
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_LDO_SUPPLY)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
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#define OMV_STACK_MEMORY DTCM // stack memory
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#define OMV_DMA_MEMORY SRAM2 // DMA buffers memory.
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#define OMV_FB_MEMORY AXI_SRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY SRAM3 // JPEG buffer memory buffer.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI frame buffer memory.
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#define OMV_VOSPI_MEMORY_OFFSET (20K) // SRAM4 reserves 16K for CM4 + 4K D3 DMA buffers.
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#define OMV_FB_SIZE (400K) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (100K) // minimum fb alloc size
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#define OMV_STACK_SIZE (64K)
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#define OMV_HEAP_SIZE (182K)
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#define OMV_LINE_BUF_SIZE (3 * 1024) // Image line buffer round(640 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (2K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
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#define OMV_FIR_LEPTON_BUF_SIZE (1K) // FIR Lepton Packet Double Buffer (328 bytes)
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#define OMV_JPEG_BUF_SIZE (32 * 1024) // IDE JPEG buffer (header + data).
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// Memory map.
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#define OMV_FLASH_ORIGIN 0x08000000
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#define OMV_FLASH_LENGTH 2048K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_ITCM_ORIGIN 0x00000000
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#define OMV_ITCM_LENGTH 64K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 240K
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#define OMV_SRAM2_ORIGIN 0x3003C000 // 16KB of SRAM1
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#define OMV_SRAM2_LENGTH 16K
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#define OMV_SRAM3_ORIGIN 0x30040000
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#define OMV_SRAM3_LENGTH 32K
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#define OMV_SRAM4_ORIGIN 0x38000000
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#define OMV_SRAM4_LENGTH 64K
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#define OMV_AXI_SRAM_ORIGIN 0x24000000
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#define OMV_AXI_SRAM_LENGTH 512K
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#define OMV_CM4_RAM_ORIGIN 0x38000000 // Cortex-M4 memory @SRAM4.
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#define OMV_CM4_RAM_LENGTH 16K
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// Flash configuration.
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#define OMV_FLASH_FFS_ORIGIN 0x08020000
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#define OMV_FLASH_FFS_LENGTH 128K
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#define OMV_FLASH_TXT_ORIGIN 0x08040000
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#define OMV_FLASH_TXT_LENGTH 1792K
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#define OMV_FLASH_EXT_ORIGIN 0x90000000
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#define OMV_FLASH_EXT_LENGTH 16M
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#define OMV_CM4_FLASH_ORIGIN 0x08020000
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#define OMV_CM4_FLASH_LENGTH 128K
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// Domain 1 DMA buffers region.
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#define OMV_DMA_MEMORY_D1 AXI_SRAM
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#define OMV_DMA_MEMORY_D1_SIZE (8*1024) // Reserved memory for DMA buffers
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#define OMV_DMA_REGION_D1_BASE (OMV_AXI_SRAM_ORIGIN+(500*1024))
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#define OMV_DMA_REGION_D1_SIZE MPU_REGION_SIZE_8KB
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// Domain 2 DMA buffers region.
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#define OMV_DMA_MEMORY_D2 SRAM2
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#define OMV_DMA_MEMORY_D2_SIZE (4*1024) // Reserved memory for DMA buffers
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#define OMV_DMA_REGION_D2_BASE (OMV_SRAM2_ORIGIN+(0*1024))
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#define OMV_DMA_REGION_D2_SIZE MPU_REGION_SIZE_16KB
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// Domain 3 DMA buffers region.
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#define OMV_DMA_MEMORY_D3 SRAM4
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#define OMV_DMA_MEMORY_D3_SIZE (4*1024) // Reserved memory for DMA buffers
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#define OMV_DMA_REGION_D3_BASE (OMV_SRAM4_ORIGIN+(16*1024))
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#define OMV_DMA_REGION_D3_SIZE MPU_REGION_SIZE_4KB
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// AXI QoS - Low-High (0:15) - default 0
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#define OMV_AXI_QOS_MDMA_R_PRI 15 // Max pri to move data.
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#define OMV_AXI_QOS_MDMA_W_PRI 15 // Max pri to move data.
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// Image sensor I2C
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#define ISC_I2C (I2C3)
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#define ISC_I2C_ID (3)
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#define ISC_I2C_SPEED (CAMBUS_SPEED_STANDARD)
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#define ISC_I2C_SCL_PIN (&omv_pin_A8_I2C3)
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#define ISC_I2C_SDA_PIN (&omv_pin_C9_I2C3)
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#define ISC_I2C_CLK_ENABLE() __I2C3_CLK_ENABLE()
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#define ISC_I2C_CLK_DISABLE() __I2C3_CLK_DISABLE()
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#define ISC_I2C_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define ISC_I2C_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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// FIR I2C
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#define FIR_I2C (I2C1)
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#define FIR_I2C_ID (1)
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#define FIR_I2C_SPEED (CAMBUS_SPEED_FULL)
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#define FIR_I2C_SCL_PIN (&omv_pin_B8_I2C1)
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#define FIR_I2C_SDA_PIN (&omv_pin_B9_I2C1)
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#define FIR_I2C_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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#define SOFT_I2C_SIOC_PIN (&omv_pin_C10_GPIO)
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#define SOFT_I2C_SIOD_PIN (&omv_pin_C11_GPIO)
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#define SOFT_I2C_SPIN_DELAY 64
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/* DCMI */
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#define DCMI_TIM (TIM3)
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#define DCMI_TIM_PIN (&omv_pin_A7_TIM3)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_2)
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#define DCMI_TIM_CLK_ENABLE() __TIM3_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM3_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
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//#define DCMI_RESET_PIN (&omv_pin_A10_GPIO)
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//#define DCMI_POWER_PIN (&omv_pin_G3_GPIO)
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//#define DCMI_FSYNC_PIN (&omv_pin_B4_GPIO)
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#define DCMI_D0_PIN (&omv_pin_C6_DCMI)
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#define DCMI_D1_PIN (&omv_pin_C7_DCMI)
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#define DCMI_D2_PIN (&omv_pin_E0_DCMI)
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#define DCMI_D3_PIN (&omv_pin_E1_DCMI)
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#define DCMI_D4_PIN (&omv_pin_E4_DCMI)
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#define DCMI_D5_PIN (&omv_pin_D3_DCMI)
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#define DCMI_D6_PIN (&omv_pin_E5_DCMI)
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#define DCMI_D7_PIN (&omv_pin_E6_DCMI)
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#define DCMI_HSYNC_PIN (&omv_pin_A4_DCMI)
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#define DCMI_VSYNC_PIN (&omv_pin_G9_DCMI)
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#define DCMI_PXCLK_PIN (&omv_pin_A6_DCMI)
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// DFSDM1
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#define AUDIO_DFSDM (DFSDM1_Channel2)
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#define AUDIO_DFSDM_CHANNEL (DFSDM_CHANNEL_2)
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// DFSDM output clock is derived from the Aclk (set in SAI1SEL[2:0])
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// for SAI1 and DFSDM1, which is clocked from PLL1Q by default (50MHz).
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#define AUDIO_DFSDM_FREQMHZ (50)
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#define AUDIO_MAX_CHANNELS (1) // Maximum number of channels.
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#define AUDIO_DFSDM_CK_PIN (&omv_pin_D10_DFSDM1)
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#define AUDIO_DFSDM_D1_PIN (&omv_pin_E7_DFSDM1)
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#define AUDIO_DFSDM_FLT0 DFSDM1_Filter0
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#define AUDIO_DFSDM_FLT0_IRQ DFSDM1_FLT0_IRQn
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#define AUDIO_DFSDM_FLT0_IRQHandler DFSDM1_FLT0_IRQHandler
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#define AUDIO_DFSDM_FLT0_DMA_STREAM DMA1_Stream1
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#define AUDIO_DFSDM_FLT0_DMA_REQUEST DMA_REQUEST_DFSDM1_FLT0
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#define AUDIO_DFSDM_FLT0_DMA_IRQ DMA1_Stream1_IRQn
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#define AUDIO_DFSDM_FLT0_DMA_IRQHandler DMA1_Stream1_IRQHandler
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#define AUDIO_DFSDM_CLK_ENABLE() __HAL_RCC_DFSDM1_CLK_ENABLE()
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#define AUDIO_DFSDM_CLK_DISABLE() __HAL_RCC_DFSDM1_CLK_DISABLE()
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#define AUDIO_DFSDM_DMA_CLK_ENABLE() __HAL_RCC_DMA1_CLK_ENABLE()
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#define IMU_SPI (SPI5)
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// SPI4/5 clock source is PLL3 (160MHz/16 == 10MHz).
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#define IMU_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16)
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#define IMU_SPI_RESET() __HAL_RCC_SPI5_FORCE_RESET()
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#define IMU_SPI_RELEASE() __HAL_RCC_SPI5_RELEASE_RESET()
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#define IMU_SPI_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE()
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#define IMU_SPI_CLK_DISABLE() __HAL_RCC_SPI5_CLK_DISABLE()
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#define IMU_SPI_SCLK_PIN (&omv_pin_F7_SPI5)
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#define IMU_SPI_MISO_PIN (&omv_pin_F8_SPI5)
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#define IMU_SPI_MOSI_PIN (&omv_pin_F11_SPI5)
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#define IMU_SPI_SSEL_PIN (&omv_pin_F6_SPI5)
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// IMU configuration
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#define OMV_IMU_X_Y_ROTATION_DEGREES 90
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#define OMV_IMU_MOUNTING_Z_DIRECTION -1
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#define IMU_CHIP_LSM6DSOX (1)
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[3])
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#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI4)
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#define OMV_SPI_LCD_MOSI_PIN (&omv_pin_E14_SPI4)
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#define OMV_SPI_LCD_MISO_PIN (&omv_pin_E13_SPI4)
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#define OMV_SPI_LCD_SCLK_PIN (&omv_pin_E12_SPI4)
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#define OMV_SPI_LCD_SSEL_PIN (&omv_pin_E11_GPIO)
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#define OMV_SPI_LCD_RS_PIN (&omv_pin_C11_GPIO)
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//#define OMV_SPI_LCD_BL_PIN (&omv_pin_A4_GPIO)
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#define OMV_SPI_LCD_RST_PIN (&omv_pin_C10_GPIO)
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#ifdef OMV_SPI_LCD_BL_PIN
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#define OMV_SPI_LCD_BL_DAC (DAC1)
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#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_1)
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#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
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#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
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#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
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#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
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#endif
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// FIR Lepton
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#define OMV_FIR_LEPTON_I2C_BUS (FIR_I2C_ID)
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#define OMV_FIR_LEPTON_I2C_BUS_SPEED (FIR_I2C_SPEED)
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#define OMV_FIR_LEPTON_CONTROLLER (&spi_obj[3])
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#define OMV_FIR_LEPTON_CONTROLLER_INSTANCE (SPI4)
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#define OMV_FIR_LEPTON_MOSI_PIN (&omv_pin_E14_SPI4)
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#define OMV_FIR_LEPTON_MISO_PIN (&omv_pin_E13_SPI4)
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#define OMV_FIR_LEPTON_SCLK_PIN (&omv_pin_E12_SPI4)
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#define OMV_FIR_LEPTON_SSEL_PIN (&omv_pin_E11_GPIO)
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#endif //__OMV_BOARDCONFIG_H__
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