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157 lines
6.3 KiB
C
157 lines
6.3 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2023 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* OpenMV MIMXRT port abstraction layer.
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*/
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#ifndef __OMV_PORTCONFIG_H__
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#define __OMV_PORTCONFIG_H__
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#include "fsl_gpio.h"
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#include "fsl_lpi2c.h"
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#include "fsl_lpspi.h"
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#include "fsl_iomuxc.h"
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#include "fsl_edma.h"
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#include "fsl_lpspi_edma.h"
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#define IOMUXC_PAD_CTL(opt, val) (IOMUXC_SW_PAD_CTL_PAD_##opt(val))
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#define IOMUXC_MUX_CTL(opt, val) (IOMUXC_SW_MUX_CTL_PAD_##opt(val))
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// *INDENT-OFF*
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// omv_gpio_t definitions
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// GPIO speeds.
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#define OMV_GPIO_SPEED_LOW ((1 << 17) | IOMUXC_PAD_CTL(SPEED, 0U) | IOMUXC_PAD_CTL(SRE, 0U)) // 50MHz
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#define OMV_GPIO_SPEED_MED ((2 << 17) | IOMUXC_PAD_CTL(SPEED, 1U) | IOMUXC_PAD_CTL(SRE, 0U)) // 100MHz
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#define OMV_GPIO_SPEED_HIGH ((3 << 17) | IOMUXC_PAD_CTL(SPEED, 2U) | IOMUXC_PAD_CTL(SRE, 1U)) // 150MHz
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#define OMV_GPIO_SPEED_MAX ((4 << 17) | IOMUXC_PAD_CTL(SPEED, 3U) | IOMUXC_PAD_CTL(SRE, 1U)) // 200MHz
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// GPIO pull.
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#define OMV_GPIO_PULL_NONE ((1 << 17) | IOMUXC_PAD_CTL(PKE, 0U) | IOMUXC_PAD_CTL(PUE, 0) | IOMUXC_PAD_CTL(PUS, 0))
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#define OMV_GPIO_PULL_UP ((2 << 17) | IOMUXC_PAD_CTL(PKE, 1U) | IOMUXC_PAD_CTL(PUE, 1) | IOMUXC_PAD_CTL(PUS, 2))
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#define OMV_GPIO_PULL_DOWN ((3 << 17) | IOMUXC_PAD_CTL(PKE, 1U) | IOMUXC_PAD_CTL(PUE, 1) | IOMUXC_PAD_CTL(PUS, 0))
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// GPIO modes.
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#define OMV_GPIO_MODE_INPUT ((1 << 17) | IOMUXC_PAD_CTL(DSE, 0U) | IOMUXC_PAD_CTL(HYS, 1U) | IOMUXC_PAD_CTL(ODE, 0U))
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#define OMV_GPIO_MODE_OUTPUT ((2 << 17) | IOMUXC_PAD_CTL(DSE, 6U) | IOMUXC_PAD_CTL(HYS, 0U) | IOMUXC_PAD_CTL(ODE, 0U))
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#define OMV_GPIO_MODE_OUTPUT_OD ((3 << 17) | IOMUXC_PAD_CTL(DSE, 6U) | IOMUXC_PAD_CTL(HYS, 0U) | IOMUXC_PAD_CTL(ODE, 1U))
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#define OMV_GPIO_MODE_ALT ((4 << 17) | IOMUXC_PAD_CTL(DSE, 6U) | IOMUXC_PAD_CTL(HYS, 0U) | IOMUXC_PAD_CTL(ODE, 0U))
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#define OMV_GPIO_MODE_ALT_OD ((5 << 17) | IOMUXC_PAD_CTL(DSE, 6U) | IOMUXC_PAD_CTL(HYS, 0U) | IOMUXC_PAD_CTL(ODE, 1U))
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// GPIO IT modes.
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#define OMV_GPIO_MODE_IT_FALL ((6 << 17) | IOMUXC_PAD_CTL(DSE, 0U) | IOMUXC_PAD_CTL(HYS, 1U))
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#define OMV_GPIO_MODE_IT_RISE ((7 << 17) | IOMUXC_PAD_CTL(DSE, 0U) | IOMUXC_PAD_CTL(HYS, 1U))
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#define OMV_GPIO_MODE_IT_BOTH ((8 << 17) | IOMUXC_PAD_CTL(DSE, 0U) | IOMUXC_PAD_CTL(HYS, 1U))
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// *INDENT-OFF*
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typedef struct {
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uint8_t idx;
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uint16_t input_register;
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uint8_t input_daisy;
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} imxrt_pad_af_t;
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typedef struct {
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GPIO_Type *port;
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uint8_t pin;
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uint16_t iomux_base;
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uint16_t mux_register;
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uint16_t cfg_register;
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uint8_t af_count;
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const imxrt_pad_af_t *af_list;
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} imxrt_pad_t;
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#include "mimxrt_pads.h"
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typedef struct _omv_gpio {
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const imxrt_pad_t *pad; // IMXRT pad.
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uint8_t af; // Default AF.
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uint8_t sion; // Software input on.
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} imxrt_gpio_t;
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typedef const imxrt_gpio_t *omv_gpio_t;
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// For board config files.
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#if OMV_GPIO_DEFINE_PINS
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#define OMV_GPIO_DEFINE(pin, pad, af, sion) \
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const imxrt_gpio_t omv_pin_##pin = {&imxrt_pad_##pad, pad##_AF_##af, sion};
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#else
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#define OMV_GPIO_DEFINE(pin, pad, af, sion) \
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extern const imxrt_gpio_t omv_pin_##pin;
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#endif
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#include "omv_pins.h"
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// omv_i2c_t definitions
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typedef LPI2C_Type *omv_i2c_dev_t;
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#define OMV_I2C_MAX_8BIT_XFER (1024U)
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#define OMV_I2C_MAX_16BIT_XFER (512U)
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// omv_spi_t definitions
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#define OMV_SPI_MODE_SLAVE (0)
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#define OMV_SPI_MODE_MASTER (1)
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#define OMV_SPI_LSB_FIRST (kLPSPI_LsbFirst)
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#define OMV_SPI_MSB_FIRST (kLPSPI_MsbFirst)
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#define OMV_SPI_BUS_TX (1 << 0)
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#define OMV_SPI_BUS_RX (1 << 1)
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#define OMV_SPI_BUS_TX_RX (OMV_SPI_BUS_TX | OMV_SPI_BUS_RX)
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#define OMV_SPI_CPOL_LOW (kLPSPI_ClockPolarityActiveHigh)
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#define OMV_SPI_CPOL_HIGH (kLPSPI_ClockPolarityActiveLow)
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#define OMV_SPI_CPHA_1EDGE (kLPSPI_ClockPhaseFirstEdge)
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#define OMV_SPI_CPHA_2EDGE (kLPSPI_ClockPhaseSecondEdge)
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#define OMV_SPI_NSS_LOW (kLPSPI_PcsActiveLow)
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#define OMV_SPI_NSS_HIGH (kLPSPI_PcsActiveHigh)
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#define OMV_SPI_MAX_8BIT_XFER (32768U - 32U)
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#define OMV_SPI_MAX_16BIT_XFER (32768U - 16U)
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#define OMV_SPI_MAX_TIMEOUT (0xFFFFFFFF)
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#define OMV_SPI_PORT_BITS \
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struct { \
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LPSPI_Type *inst; \
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lpspi_master_config_t config_backup; \
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edma_handle_t dma_descr_tx; \
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edma_handle_t dma_descr_rx; \
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union { \
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lpspi_slave_handle_t descr_slave; \
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lpspi_master_handle_t descr_master; \
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}; \
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union { \
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lpspi_slave_edma_handle_t descr_slave_edma; \
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lpspi_master_edma_handle_t descr_master_edma; \
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}; \
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lpspi_transfer_t xfer_descr; \
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uint32_t bus_mode; \
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};
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// omv_csi_t port-specific fields.
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#define OMV_CSI_PORT_BITS \
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struct { \
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int src_inc; \
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int src_size; \
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int dest_inc; \
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edma_handle_t dma_channels[OMV_CSI_DMA_CHANNEL_COUNT]; \
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};
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#endif // __OMV_PORTCONFIG_H__
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