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https://github.com/openmv/openmv.git
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218 lines
8.7 KiB
Python
Executable File
218 lines
8.7 KiB
Python
Executable File
#!/usr/bin/python3
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"""
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@brief Clock Info decode and display
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__author__ onyettr
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"""
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# pylint: disable=unused-argument, invalid-name, consider-using-f-string
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import struct
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import ctypes
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from isp_print import isp_print_color
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c_uint32 = ctypes.c_uint32
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PLL_CLK_STATUS_XTAL_STARTED = (1 << 0)
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PLL_CLK_STATUS_PLL_LOCKED = (1 << 1)
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PLL_CLK_STATUS_SE_CLOCK_PLL = (1 << 2)
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CLOCK_FREQUENCY_800MHZ = 0
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CLOCK_FREQUENCY_400MHZ = 1
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CLOCK_FREQUENCY_300MHZ = 2
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CLOCK_FREQUENCY_200MHZ = 3
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CLOCK_FREQUENCY_160MHZ = 4
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CLOCK_FREQUENCY_120MHZ = 5
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CLOCK_FREQUENCY_80MHZ = 6
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CLOCK_FREQUENCY_60MHZ = 7
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CLOCK_FREQUENCY_100MHZ = 8
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CLOCK_FREQUENCY_50MHZ = 9
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CLOCK_FREQUENCY_20MHZ = 10
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CLOCK_FREQUENCY_10MHZ = 11
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CLOCK_FREQUENCY_76_8_RC_MHZ = 12
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CLOCK_FREQUENCY_38_4_RC_MHZ = 13
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CLOCK_FREQUENCY_76_8_XO_MHZ = 14
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CLOCK_FREQUENCY_38_4_XO_MHZ = 15
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CLOCK_FREQUENCY_DISABLED = 16
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clk_frequency_lut = {
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CLOCK_FREQUENCY_800MHZ : "800Mhz",
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CLOCK_FREQUENCY_400MHZ : "400Mhz",
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CLOCK_FREQUENCY_300MHZ : "300Mhz",
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CLOCK_FREQUENCY_200MHZ : "200Mhz",
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CLOCK_FREQUENCY_160MHZ : "160Mhz",
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CLOCK_FREQUENCY_120MHZ : "120Mhz",
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CLOCK_FREQUENCY_80MHZ : "80Mhz",
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CLOCK_FREQUENCY_60MHZ : "60Mhz",
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CLOCK_FREQUENCY_100MHZ : "100Mhz",
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CLOCK_FREQUENCY_50MHZ : "50Mhz",
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CLOCK_FREQUENCY_20MHZ : "20Mhz" ,
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CLOCK_FREQUENCY_10MHZ : "10Mhz",
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CLOCK_FREQUENCY_76_8_RC_MHZ : "76.8Mhz RC",
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CLOCK_FREQUENCY_38_4_RC_MHZ : "38.4Mhz RC",
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CLOCK_FREQUENCY_76_8_XO_MHZ : "76.8Mhz XO",
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CLOCK_FREQUENCY_38_4_XO_MHZ : "38.4Mhz XO",
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CLOCK_FREQUENCY_DISABLED : "Disabled"
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}
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register_names = [
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"HOSTCPUCLK_CTRL", "HOSTCPUCLK_DIV0", "HOSTCPUCLK_DIV1", "ACLK_CTRL", "ACLK_DIV0",
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"OSC_CTRL", "PLL_LOCK_CTRL", "PLL_CLK_SEL", "ESCLK_SEL", "CLK_ENA",
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"SYSTOP_CLK_DIV", "MISC_REG1", "XO_REG1", "PD4_CLK_SEL", "PD4_CLK_PLL",
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"MISC_CTRL", "DCDC_REG1", "DCDC_REG2", "VBAT_ANA_REG1", "VBAT_ANA_REG2"
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]
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class xo_reg1_bits(ctypes.LittleEndianStructure):
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_fields_ = [
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("en_xtal" , c_uint32, 1),
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("faststart" , c_uint32, 1),
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("__reserved__0" , c_uint32, 1),
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("en_bfr_clkpll" , c_uint32, 1),
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("en_bfr_dig_2x" , c_uint32, 1),
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("en_bfr_dig" , c_uint32, 1),
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("boost" , c_uint32, 1),
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("xtal_cap" , c_uint32, 4),
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("gm_pfet" , c_uint32, 5),
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("gm_nfet" , c_uint32, 5),
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("sel_doubler_output_duty_cycle" , c_uint32, 2),
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("sel_doubler_input_duty_cycle" , c_uint32, 5),
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("sel_ibg" , c_uint32, 1),
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("ibres_cont" , c_uint32, 2),
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("__reserved__1" , c_uint32, 1)
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]
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class XO_REG1(ctypes.Union):
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_fields_ = [("b", xo_reg1_bits), ("w", c_uint32)]
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class vbat_ana_reg1_bits(ctypes.LittleEndianStructure):
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_fields_ = [
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("osc_rc_32k_freq_cont" , c_uint32, 4),
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("ret_ldo_cont_3_0" , c_uint32, 4),
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("ret_ldo_vbat_en" , c_uint32, 1),
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("ret_ldo_vbat_shunt_en" , c_uint32, 1),
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("ret_ldo_vddmain_en" , c_uint32, 1),
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("ret_ldo_vdd_main_shunt_en", c_uint32, 1),
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("xtal32k_en" , c_uint32, 1),
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("xtal32k_kick" , c_uint32, 1),
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("lpcomp_clk32k_en" , c_uint32, 1),
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("xtal32k_gm_cont" , c_uint32, 4),
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("xtal32k_cap_cont" , c_uint32, 6),
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("bor_en" , c_uint32, 1),
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("bor_hyst" , c_uint32, 3),
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("bor_thresh" , c_uint32, 3)
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]
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class VBAT_ANA_REG1(ctypes.Union):
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_fields_ = [("b", vbat_ana_reg1_bits), ("w", c_uint32)]
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class vbat_ana_reg2_bits(ctypes.LittleEndianStructure):
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_fields_ = [
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("__reserved__" , c_uint32, 1),
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("pmubg_vref_cont" , c_uint32, 4),
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("dig_ldo_18_en" , c_uint32, 1),
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("dig_ldo_cont" , c_uint32, 4),
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("osc_76Mrc_cont_bit0" , c_uint32, 1),
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("osc_76M_div_cont_fast" , c_uint32, 3),
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("osc_76Mrc_cont" , c_uint32, 5),
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("osc_76M_div_cont_slow" , c_uint32, 3),
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("ana_periph_bg_ena" , c_uint32, 1),
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("ana_periph_LDO_en" , c_uint32, 1),
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("comp_lp_en" , c_uint32, 1),
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("comp_lp0_in_p_sel" , c_uint32, 2),
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("comp_lp0_in_m_sel" , c_uint32, 2),
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("comp_lp0_hyst" , c_uint32, 3)
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]
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class VBAT_ANA_REG2(ctypes.Union):
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_fields_ = [("b", vbat_ana_reg2_bits), ("w", c_uint32)]
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def clk_frequency_to_string(clk_frequency):
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"""
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Convert input to string
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@param clk_frequency:
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@return: string based on input
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"""
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return clk_frequency_lut.get(clk_frequency)
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def clk_status_to_string(clk_status):
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"""
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parse the bit fields and return a printable string
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@param clk_status: bit encoded values
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@return: string based on input
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"""
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status_string = ''
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if clk_status & PLL_CLK_STATUS_XTAL_STARTED:
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status_string += " HFXTAL STARTED\n"
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else:
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status_string += " HFXTAL OFF\n"
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if clk_status & PLL_CLK_STATUS_PLL_LOCKED:
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status_string += " PLL LOCKED\n"
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else:
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status_string += " PLL OFF\n"
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if clk_status & PLL_CLK_STATUS_SE_CLOCK_PLL:
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status_string += " SE CLOCK: PLL\n"
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else:
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status_string += " SE CLOCK: HFRC\n"
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return status_string
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def display_clock_info(message):
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"""
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display clock, pll, xtal entries sent back from Target
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message -- ISP data to parse
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"""
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# word 0 is the status word
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(status,) = struct.unpack("<I",bytes(message[0:4]))
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isp_print_color("blue","Clock Status\n")
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isp_print_color("blue" ,"%s" % clk_status_to_string(status))
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# A32 frequency
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frequency = (status & 0x0000FF00) >> 8
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isp_print_color("blue" ,"CLK freq A32 %s\n" % (clk_frequency_to_string(frequency)))
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# M55-HP frequency
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frequency = (status & 0x00FF0000) >> 16
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isp_print_color("blue" ,"CLK freq ES0 %s\n" % (clk_frequency_to_string(frequency)))
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# M55-HE frequency
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frequency = (status & 0xFF000000) >> 24
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isp_print_color("blue" ,"CLK freq ES1 %s\n" % (clk_frequency_to_string(frequency)))
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# word 1 is the CM0+ frequency
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(cm0_freq,) = struct.unpack("<f",bytes(message[4:8]))
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isp_print_color("blue" ,"SE frequency %0.2fMHz\n" % cm0_freq)
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isp_print_color("blue" ,"\nRegisters:\n")
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for counter in range(len(register_names)):
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index = (counter + 2) * 4 # skip the first two words
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(value,) = struct.unpack("<I",bytes(message[index:index+4]))
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value_str = "{:<16}: 0x{:08X}".format(register_names[counter], value)
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isp_print_color("blue" , value_str)
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print()
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if register_names[counter] == 'XO_REG1':
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xo_reg1 = XO_REG1()
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xo_reg1.w = value
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value_str = " xtal_cap:{:d}".format(xo_reg1.b.xtal_cap)
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value_str = value_str + " gm_pfet:{:d}".format(xo_reg1.b.gm_pfet)
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value_str = value_str + " gm_nfet:{:d}".format(xo_reg1.b.gm_nfet)
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print(value_str)
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elif register_names[counter] == 'VBAT_ANA_REG1':
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ana_reg1 = VBAT_ANA_REG1()
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ana_reg1.w = value
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value_str = " osc_rc_32k_freq_cont:{:d}".format(ana_reg1.b.osc_rc_32k_freq_cont)
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value_str = value_str + " xtal32k_en:{:d}".format(ana_reg1.b.xtal32k_en)
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value_str = value_str + " xtal32k_gm_cont:{:d}".format(ana_reg1.b.xtal32k_gm_cont)
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value_str = value_str + " xtal32k_cap_cont:{:d}".format(ana_reg1.b.xtal32k_cap_cont)
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value_str = value_str + " bor_en:{:d}".format(ana_reg1.b.bor_en)
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value_str = value_str + " bor_hyst:{:d}".format(ana_reg1.b.bor_hyst)
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value_str = value_str + " bor_thresh:{:d}".format(ana_reg1.b.bor_thresh)
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print(value_str)
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elif register_names[counter] == 'VBAT_ANA_REG2':
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ana_reg2 = VBAT_ANA_REG2()
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ana_reg2.w = value
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value_str = " pmubg_vref_cont:{:d}".format(ana_reg2.b.pmubg_vref_cont)
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value_str = value_str + " osc_76Mrc_cont_bit0:{:d}".format(ana_reg2.b.osc_76Mrc_cont_bit0)
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value_str = value_str + " osc_76M_div_cont_fast:{:d}".format(ana_reg2.b.osc_76M_div_cont_fast)
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value_str = value_str + " osc_76Mrc_cont:{:d}".format(ana_reg2.b.osc_76Mrc_cont)
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value_str = value_str + " osc_76M_div_cont_slow:{:d}".format(ana_reg2.b.osc_76M_div_cont_slow)
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print(value_str)
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