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79 lines
3.1 KiB
C
79 lines
3.1 KiB
C
/*
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* Copyright (C) 2023-2024 OpenMV, LLC.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Any redistribution, use, or modification in source or binary form
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* is done solely for personal benefit and not for any commercial
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* purpose or for monetary gain. For commercial licensing options,
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* please contact openmv@openmv.io
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*
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* THIS SOFTWARE IS PROVIDED BY THE LICENSOR AND COPYRIGHT OWNER "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE LICENSOR OR COPYRIGHT
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* OWNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* I2C to UART bridge register definitions.
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*/
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#define SC16IS741A_SUB_ADDR(reg, channel) (((reg) << 3) | ((channel) << 1))
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#define SC16IS741A_REG_RHR 0x00
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#define SC16IS741A_REG_THR 0x00
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#define SC16IS741A_REG_IER 0x01
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#define SC16IS741A_REG_FCR 0x02
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#define SC16IS741A_REG_IIR 0x02
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#define SC16IS741A_REG_LCR 0x03
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#define SC16IS741A_REG_MCR 0x04
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#define SC16IS741A_REG_LSR 0x05
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#define SC16IS741A_REG_MSR 0x06
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#define SC16IS741A_REG_SPR 0x07
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#define SC16IS741A_REG_TCR 0x06
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#define SC16IS741A_REG_TLR 0x07
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#define SC16IS741A_REG_TXLVL 0x08
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#define SC16IS741A_REG_RXLVL 0x09
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#define SC16IS741A_REG_UARTRST 0x0e
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#define SC16IS741A_REG_EFCR 0x0f
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#define SC16IS741A_REG_DLL 0x00
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#define SC16IS741A_REG_DLH 0x01
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#define SC16IS741A_REG_EFR 0x02
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#define SC16IS741A_REG_XON1 0x04
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#define SC16IS741A_REG_XON2 0x05
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#define SC16IS741A_REG_XOFF1 0x06
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#define SC16IS741A_REG_XOFF2 0x07
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#define SC16IS741A_FCR_ENABLE_FIFO 0x01
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#define SC16IS741A_FCR_RX_FIFO_RESET 0x02
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#define SC16IS741A_FCR_TX_FIFO_RESET 0x04
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#define SC16IS741A_LCR_WORD_SZ_5 0x00
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#define SC16IS741A_LCR_WORD_SZ_6 0x01
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#define SC16IS741A_LCR_WORD_SZ_7 0x02
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#define SC16IS741A_LCR_WORD_SZ_8 0x03
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#define SC16IS741A_LCR_STOP_BIT 0x04
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#define SC16IS741A_LCR_PARITY_EN 0x08
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#define SC16IS741A_LCR_PARITY_EVEN 0x10
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#define SC16IS741A_LCR_PARITY_ODD 0x00
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#define SC16IS741A_LCR_PARITY_FORCE 0x20
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#define SC16IS741A_LCR_PARTIY_FORCE_1 0x00
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#define SC16IS741A_LCR_PARTIY_FORCE_0 0x10
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#define SC16IS741A_LCR_BREAK_EN 0x40
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#define SC16IS741A_LCR_ENABLE_LATCH 0x80
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#define SC16IS741A_UARTRST 0x08
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