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https://github.com/openmv/openmv.git
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245 lines
8.2 KiB
C
245 lines
8.2 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright (C) 2021-2024 OpenMV, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* Sensor driver for rp2 port.
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*/
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#if MICROPY_PY_CSI
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#include <string.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "py/mphal.h"
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#include "omv_i2c.h"
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#include "omv_csi.h"
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#include "pico/time.h"
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#include "pico/stdlib.h"
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#include "hardware/pwm.h"
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#include "hardware/pio.h"
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#include "hardware/dma.h"
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#include "hardware/irq.h"
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#include "omv_boardconfig.h"
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#include "unaligned_memcpy.h"
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#include "dcmi.pio.h"
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extern void __fatal_error(const char *msg);
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static void dma_irq_handler() {
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omv_csi_t *csi = omv_csi_get(-1);
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framebuffer_t *fb = csi->fb;
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if (dma_irqn_get_channel_status(OMV_CSI_DMA, OMV_CSI_DMA_CHANNEL)) {
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// Clear the interrupt request.
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dma_irqn_acknowledge_channel(OMV_CSI_DMA, OMV_CSI_DMA_CHANNEL);
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// Release the current buffer and acquire a new one.
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framebuffer_release(fb, FB_FLAG_FREE | FB_FLAG_CHECK_LAST);
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vbuffer_t *buffer = framebuffer_acquire(fb, FB_FLAG_FREE | FB_FLAG_PEEK);
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if (buffer != NULL) {
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// Set next buffer and retrigger the DMA channel.
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dma_channel_set_write_addr(OMV_CSI_DMA_CHANNEL, buffer->data, true);
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// Unblock the state machine
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pio_sm_restart(OMV_CSI_PIO, OMV_CSI_SM);
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pio_sm_clear_fifos(OMV_CSI_PIO, OMV_CSI_SM);
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pio_sm_put_blocking(OMV_CSI_PIO, OMV_CSI_SM, (fb->v - 1));
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pio_sm_put_blocking(OMV_CSI_PIO, OMV_CSI_SM, (fb->u * fb->bpp) - 1);
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}
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}
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}
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static bool rp2_csi_is_active(omv_csi_t *csi) {
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return dma_channel_is_busy(OMV_CSI_DMA_CHANNEL);
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}
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static int rp2_csi_config(omv_csi_t *csi, omv_csi_config_t config) {
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if (config == OMV_CSI_CONFIG_INIT) {
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// PIXCLK
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gpio_init(OMV_CSI_PXCLK_PIN);
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gpio_set_dir(OMV_CSI_PXCLK_PIN, GPIO_IN);
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// HSYNC
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gpio_init(OMV_CSI_HSYNC_PIN);
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gpio_set_dir(OMV_CSI_HSYNC_PIN, GPIO_IN);
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// VSYNC
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gpio_init(OMV_CSI_VSYNC_PIN);
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gpio_set_dir(OMV_CSI_VSYNC_PIN, GPIO_IN);
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// Install new DMA IRQ handler.
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irq_set_enabled(OMV_CSI_DMA_IRQ, false);
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// Clear DMA interrupts.
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dma_irqn_acknowledge_channel(OMV_CSI_DMA, OMV_CSI_DMA_CHANNEL);
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// Remove current handler if any
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irq_handler_t irq_handler = irq_get_exclusive_handler(OMV_CSI_DMA_IRQ);
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if (irq_handler != NULL) {
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irq_remove_handler(OMV_CSI_DMA_IRQ, irq_handler);
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}
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// Set new exclusive IRQ handler.
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irq_set_exclusive_handler(OMV_CSI_DMA_IRQ, dma_irq_handler);
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// Or set shared IRQ handler, but this needs to be called once.
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// irq_add_shared_handler(OMV_CSI_DMA_IRQ, dma_irq_handler, PICO_DEFAULT_IRQ_PRIORITY);
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irq_set_enabled(OMV_CSI_DMA_IRQ, true);
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}
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return 0;
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}
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static int rp2_csi_abort(omv_csi_t *csi, bool fifo_flush, bool in_irq) {
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// Disable DMA channel
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dma_channel_abort(OMV_CSI_DMA_CHANNEL);
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dma_irqn_set_channel_enabled(OMV_CSI_DMA, OMV_CSI_DMA_CHANNEL, false);
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// Disable state machine.
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pio_sm_set_enabled(OMV_CSI_PIO, OMV_CSI_SM, false);
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pio_sm_clear_fifos(OMV_CSI_PIO, OMV_CSI_SM);
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if (csi->fb) {
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// Clear bpp flag.
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csi->fb->pixfmt = PIXFORMAT_INVALID;
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}
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return 0;
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}
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static uint32_t rp2_clk_get_frequency(omv_clk_t *clk) {
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return OMV_CSI_CLK_FREQUENCY;
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}
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static int rp2_clk_set_frequency(omv_clk_t *clk, uint32_t frequency) {
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uint32_t p = 4;
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// Allocate pin to the PWM
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gpio_set_function(OMV_CSI_MXCLK_PIN, GPIO_FUNC_PWM);
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// Find out which PWM slice is connected to the GPIO
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uint slice_num = pwm_gpio_to_slice_num(OMV_CSI_MXCLK_PIN);
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// Set period to p cycles
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pwm_set_wrap(slice_num, p - 1);
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// Set channel A 50% duty cycle.
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pwm_set_chan_level(slice_num, PWM_CHAN_A, p / 2);
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// Set sysclk divider
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// f = 125000000 / (p * (1 + (p/16)))
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pwm_set_clkdiv_int_frac(slice_num, 1, p);
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// Set the PWM running
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pwm_set_enabled(slice_num, true);
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return 0;
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}
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int omv_csi_set_windowing(omv_csi_t *csi, int x, int y, int w, int h) {
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return OMV_CSI_ERROR_CTL_UNSUPPORTED;
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}
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static int rp2_csi_snapshot(omv_csi_t *csi, image_t *image, uint32_t flags) {
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vbuffer_t *buffer = NULL;
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framebuffer_t *fb = csi->fb;
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// If there's no ready buffer in the fifo, and the DMA is Not currently
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// transferring a new buffer, reconfigure and restart the DMA transfer.
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if (!rp2_csi_is_active(csi) && !framebuffer_readable(fb)) {
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// Acquire a buffer from the free queue.
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if (!(buffer = framebuffer_acquire(fb, FB_FLAG_FREE | FB_FLAG_PEEK))) {
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return OMV_CSI_ERROR_FRAMEBUFFER_ERROR;
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}
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// Configure the DMA on the first frame.
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dma_channel_abort(OMV_CSI_DMA_CHANNEL);
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dma_irqn_set_channel_enabled(OMV_CSI_DMA, OMV_CSI_DMA_CHANNEL, false);
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dma_channel_config c = dma_channel_get_default_config(OMV_CSI_DMA_CHANNEL);
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channel_config_set_read_increment(&c, false);
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channel_config_set_write_increment(&c, true);
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channel_config_set_dreq(&c, pio_get_dreq(OMV_CSI_PIO, OMV_CSI_SM, false));
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channel_config_set_bswap(&c, csi->rgb_swap && (fb->bpp == 2));
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dma_channel_configure(OMV_CSI_DMA_CHANNEL, &c,
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(uint32_t *) buffer->data, // Destinatinon pointer.
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&OMV_CSI_PIO->rxf[OMV_CSI_SM], // Source pointer.
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(fb->u * fb->v * fb->bpp) >> 2, // Number of transfers in words.
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true // Start immediately, will block on SM.
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);
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// Re-enable DMA IRQs.
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dma_irqn_set_channel_enabled(OMV_CSI_DMA, OMV_CSI_DMA_CHANNEL, true);
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// Re-enable the state machine.
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pio_sm_clear_fifos(OMV_CSI_PIO, OMV_CSI_SM);
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pio_sm_set_enabled(OMV_CSI_PIO, OMV_CSI_SM, true);
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// Unblock the state machine
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pio_sm_put_blocking(OMV_CSI_PIO, OMV_CSI_SM, (fb->v - 1));
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pio_sm_put_blocking(OMV_CSI_PIO, OMV_CSI_SM, (fb->u * fb->bpp) - 1);
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}
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// One shot DMA transfers must be invalidated.
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framebuffer_flags_t fb_flags = FB_FLAG_USED | FB_FLAG_PEEK | FB_FLAG_INVALIDATE;
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// Wait for a frame to be ready.
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for (mp_uint_t start = mp_hal_ticks_ms(); ; mp_event_handle_nowait()) {
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if ((buffer = framebuffer_acquire(fb, fb_flags))) {
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break;
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}
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if (flags & OMV_CSI_FLAG_NON_BLOCK) {
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return OMV_CSI_ERROR_WOULD_BLOCK;
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}
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if ((mp_hal_ticks_ms() - start) > OMV_CSI_TIMEOUT_MS) {
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omv_csi_abort(csi, true, false);
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return OMV_CSI_ERROR_CAPTURE_TIMEOUT;
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}
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}
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// Set the framebuffer width/height.
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fb->w = fb->u;
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fb->h = fb->v;
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// Set the framebuffer pixel format.
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fb->pixfmt = csi->pixformat;
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// Set the user image.
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framebuffer_to_image(fb, image);
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return 0;
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}
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int omv_csi_ops_init(omv_csi_t *csi) {
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// Set CSI ops.
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csi->abort = rp2_csi_abort;
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csi->config = rp2_csi_config;
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csi->snapshot = rp2_csi_snapshot;
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// Set CSI clock ops.
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csi->clk->freq = OMV_CSI_CLK_FREQUENCY;
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csi->clk->set_freq = rp2_clk_set_frequency;
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csi->clk->get_freq = rp2_clk_get_frequency;
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return 0;
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}
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#endif // MICROPY_PY_CSI
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