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89 lines
3.9 KiB
C
89 lines
3.9 KiB
C
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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#ifndef DRIVER_I2C_PRIVATE_H_
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#define DRIVER_I2C_PRIVATE_H_
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#include "Driver_I2C.h"
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#include "i2c.h"
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/**** system includes ****/
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#include "RTE_Device.h"
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#include "RTE_Components.h"
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#include CMSIS_device_header
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#if (RTE_I2C0_DMA_ENABLE || RTE_I2C1_DMA_ENABLE || \
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RTE_I2C2_DMA_ENABLE || RTE_I2C3_DMA_ENABLE)
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#define I2C_DMA_ENABLE 1
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#else
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#define I2C_DMA_ENABLE 0
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#endif
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#if I2C_DMA_ENABLE
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#include <DMA_Common.h>
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#endif
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typedef volatile struct _I2C_DRIVER_STATE
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{
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uint32_t initialized : 1; /**< Driver Initialized */
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uint32_t powered : 1; /**< Driver powered */
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uint32_t master_setup: 1; /**< i2c master setup */
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uint32_t slave_setup : 1; /**< i2c master setup */
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uint32_t reserved : 28; /**< Reserved */
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} I2C_DRIVER_STATE;
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#if I2C_DMA_ENABLE
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typedef struct _I2C_DMA_HW_CONFIG
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{
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DMA_PERIPHERAL_CONFIG dma_tx; /* Tx interface */
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DMA_PERIPHERAL_CONFIG dma_rx; /* Rx interface */
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}I2C_DMA_HW_CONFIG;
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#endif
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/* @brief Structure to save contexts for a i2c channel */
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typedef struct _I2C_RESOURCES
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{
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ARM_I2C_SignalEvent_t cb_event; /* Event callback */
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I2C_Type *regs; /* i2c register base address */
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ARM_I2C_STATUS status; /* I2C status */
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I2C_DRIVER_STATE state; /* i2c driver state */
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i2c_transfer_info_t transfer; /* Transfer structure for I2C */
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uint32_t clk; /* system clock */
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uint32_t addr_mode; /* I2C_ADDRESS_MODE */
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uint32_t slv_addr; /* slave address */
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uint32_t tar_addr; /* target slave device address */
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uint32_t irq_priority; /* i2c interrupt priority */
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IRQn_Type irq_num; /* i2c interrupt vector number */
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i2c_speed_mode_t speed_mode; /* I2C speed mode */
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uint8_t mode; /* current working mode as master or slave */
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#if I2C_DMA_ENABLE
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const bool dma_enable; /* I2C dma enable */
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const uint32_t dma_irq_priority; /* DMA IRQ priority number */
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ARM_DMA_SignalEvent_t dma_cb; /* I2S DMA Callback */
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I2C_DMA_HW_CONFIG *dma_cfg; /* DMA Controller configuration */
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#endif
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uint8_t tx_fifo_threshold; /* Tx Fifo Buffer threshold */
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uint8_t rx_fifo_threshold; /* Rx Fifo Buffer threshold */
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} I2C_RESOURCES;
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#define I2C_SLAVE_MODE (0) /* Indicate that the device working as slave */
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#define I2C_MASTER_MODE (1) /* Indicate that the device working as master */
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#define I2C_DIR_TRANSMITTER (0) /* direction transmitter */
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#define I2C_DIR_RECEIVER (1) /* direction receiver */
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#define I2C_0_TARADDR (0x50) /* I2C target address */
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#define I2C_7BIT_ADDRESS_MASK (0x7F) /* 7bit I2C address mask */
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#define I2C_10BIT_ADDRESS_MASK (0x3FF) /* 10bit I2C address mask */
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#endif /* DRIVER_I2C_PRIVATE_H_ */
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