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751 lines
31 KiB
C
751 lines
31 KiB
C
/**
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******************************************************************************
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* @file stm32n6xx_ll_system.h
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* @author MCD Application Team
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* @brief Header file of SYSTEM LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL SYSTEM driver contains a set of generic APIs that can be
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used by user:
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(+) Some of the FLASH features need to be handled in the SYSTEM file.
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(+) Access to DBGCMU registers
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(+) Access to SYSCFG registers
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@endverbatim
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32N6xx_LL_SYSTEM_H
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#define STM32N6xx_LL_SYSTEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32n6xx.h"
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/** @addtogroup STM32N6xx_LL_Driver
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* @{
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*/
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#if defined (SYSCFG) || defined (DBGMCU)
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/** @defgroup SYSTEM_LL SYSTEM
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
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* @{
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*/
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/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection
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* @{
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*/
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#define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell (available in the SYSCFG_CCVR)*/
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#define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation cell code register (SYSCFG_CCCR)*/
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
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* @{
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*/
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/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
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* @{
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*/
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#define LL_SYSCFG_I2C_FASTMODEPLUS_PA6 SYSCFG_CFGR1_PA6_FMP /*!< Enable Fast Mode Plus on PA6 */
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#define LL_SYSCFG_I2C_FASTMODEPLUS_PA7 SYSCFG_CFGR1_PA7_FMP /*!< Enable Fast Mode Plus on PA7 */
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#define LL_SYSCFG_I2C_FASTMODEPLUS_PA15 SYSCFG_CFGR1_PA15_FMP /*!< Enable Fast Mode Plus on PA15 */
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#define LL_SYSCFG_I2C_FASTMODEPLUS_PB3 SYSCFG_CFGR1_PB3_FMP /*!< Enable Fast Mode Plus on PB3 */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
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* @{
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*/
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#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
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with Break Input of TIM1/16/17 */
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#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
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with TIM1/16/17 Break Input and also
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the PVDE and PLS bits of the Power Control Interface */
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#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal
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with Break Input of TIM1/16/17 */
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#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33
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with Break Input of TIM1/16/17 */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes
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* @note Only available when system implements security (TZEN=1)
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* @{
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*/
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#define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */
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#define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */
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#define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */
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#define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */
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#define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */
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#define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
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* @{
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*/
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#define LL_DBGMCU_DBTRGIN 0U /*!< DBTRGIO connected to DBTRGIN */
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#define LL_DBGMCU_DBTRGOUT DBGMCU_CR_DBTRGOEN /*!< DBTRGIO connected to DBTRGOUT */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1LFZ1_DBG_TIM2_STOP
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#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1LFZ1_DBG_TIM3_STOP /*!< TIM3 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1LFZ1_DBG_TIM4_STOP /*!< TIM4 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1LFZ1_DBG_TIM5_STOP /*!< TIM5 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1LFZ1_DBG_TIM6_STOP /*!< TIM6 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1LFZ1_DBG_TIM7_STOP /*!< TIM7 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1LFZ1_DBG_TIM12_STOP /*!< TIM12 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1LFZ1_DBG_TIM13_STOP /*!< TIM13 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1LFZ1_DBG_TIM14_STOP /*!< TIM14 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1LFZ1_DBG_LPTIM1_STOP /*!< LPTIM1 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1LFZ1_DBG_WWDG1_STOP /*!< WWDG1 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM10_STOP DBGMCU_APB1LFZ1_DBG_TIM10_STOP /*!< TIM10 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_TIM11_STOP DBGMCU_APB1LFZ1_DBG_TIM11_STOP /*!< TIM11 stop in debug */
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#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1LFZ1_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout stop in debug */
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#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1LFZ1_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout stop in debug */
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#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1LFZ1_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout stop in debug */
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#define LL_DBGMCU_APB1_GRP1_I3C1_STOP DBGMCU_APB1LFZ1_DBG_I3C1_STOP /*!< I3C1 SMBUS timeout stop in debug */
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#define LL_DBGMCU_APB1_GRP1_I3C2_STOP DBGMCU_APB1LFZ1_DBG_I3C2_STOP /*!< I3C2 SMBUS timeout stop in debug */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
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* @{
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*/
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#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP DBGMCU_APB1HFZ1_DBG_FDCAN_STOP /*!< FDCAN stop in debug */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ1_DBG_TIM1_STOP /*!< TIM1 stop in debug */
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#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ1_DBG_TIM8_STOP /*!< TIM8 stop in debug */
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#define LL_DBGMCU_APB2_GRP1_TIM18_STOP DBGMCU_APB2FZ1_DBG_TIM18_STOP /*!< TIM18 stop in debug */
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#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ1_DBG_TIM15_STOP /*!< TIM15 stop in debug */
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#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ1_DBG_TIM16_STOP /*!< TIM16 stop in debug */
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#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ1_DBG_TIM17_STOP /*!< TIM17 stop in debug */
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#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2FZ1_DBG_TIM9_STOP /*!< TIM9 stop in debug */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_APB4_GRP1_I2C4_STOP DBGMCU_APB4FZ1_DBG_I2C4_STOP /*!< I2C4 stop in debug */
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#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP DBGMCU_APB4FZ1_DBG_LPTIM2_STOP /*!< LPTIM2 stop in debug */
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#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP DBGMCU_APB4FZ1_DBG_LPTIM3_STOP /*!< LPTIM3 stop in debug */
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#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP DBGMCU_APB4FZ1_DBG_LPTIM4_STOP /*!< LPTIM4 stop in debug */
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#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP DBGMCU_APB4FZ1_DBG_LPTIM5_STOP /*!< LPTIM5 stop in debug */
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#define LL_DBGMCU_APB4_GRP1_RTC_STOP DBGMCU_APB4FZ1_DBG_RTC_STOP /*!< RTC stop in debug */
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#define LL_DBGMCU_APB4_GRP1_IWDG_STOP DBGMCU_APB4FZ1_DBG_IWDG_STOP /*!< IWDG stop in debug */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_APB5_GRP1_STOP_IP DBGMCU APB5 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_APB5_GRP1_GFXTIM_STOP DBGMCU_APB5FZ1_DBG_GFXTIM_STOP /*!< GFXTIM stop in debug */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH0_STOP /*!< GPDMA1_CH0 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH1_STOP /*!< GPDMA1_CH1 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH2_STOP /*!< GPDMA1_CH2 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH3_STOP /*!< GPDMA1_CH3 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH4_STOP /*!< GPDMA1_CH4 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH5_STOP /*!< GPDMA1_CH5 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH6_STOP /*!< GPDMA1_CH6 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH7_STOP /*!< GPDMA1_CH7 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH8_STOP /*!< GPDMA1_CH8 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH9_STOP /*!< GPDMA1_CH9 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH10_STOP /*!< GPDMA1_CH10 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH11_STOP /*!< GPDMA1_CH11 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH12_STOP /*!< GPDMA1_CH12 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH13_STOP /*!< GPDMA1_CH13 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH14_STOP /*!< GPDMA1_CH14 suspend in debug */
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#define LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP DBGMCU_AHB1FZ1_DBG_GPDMA1_CH15_STOP /*!< GPDMA1_CH15 suspend in debug */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_AHB5_GRP1_STOP_IP DBGMCU AHB5 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH0_STOP /*!< HPDMA1_CH0 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH1_STOP /*!< HPDMA1_CH1 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH2_STOP /*!< HPDMA1_CH2 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH3_STOP /*!< HPDMA1_CH3 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH4_STOP /*!< HPDMA1_CH4 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH5_STOP /*!< HPDMA1_CH5 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH6_STOP /*!< HPDMA1_CH6 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH7_STOP /*!< HPDMA1_CH7 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH8_STOP /*!< HPDMA1_CH8 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH9_STOP /*!< HPDMA1_CH9 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH10_STOP /*!< HPDMA1_CH10 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH11_STOP /*!< HPDMA1_CH11 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH12_STOP /*!< HPDMA1_CH12 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH13_STOP /*!< HPDMA1_CH13 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH14_STOP /*!< HPDMA1_CH14 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP DBGMCU_AHB5FZ1_DBG_HPDMA1_CH15_STOP /*!< HPDMA1_CH15 suspend in debug */
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#define LL_DBGMCU_AHB5_GRP1_NPU_STOP DBGMCU_AHB5FZ1_NPU_DBG_FREEZE /*!< NPU stop in debug mode */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
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* @{
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*/
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#if defined (CPU_IN_SECURE_STATE)
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/**
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* @brief Returns the device identifier
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* @note The BSEC clock must be enabled before calling this function
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* Returned Device ID can be
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* 0x00006200 for STM32N645xx
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* 0x00006000 for STM32N655xx
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* 0x00002200 for STM32N647xx
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* 0x00002000 for STM32N657xx
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* 0xffffffff if an error occurs
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* @retval Device identifier
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*/
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__STATIC_INLINE uint32_t LL_GetDeviceID(void)
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{
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return (uint32_t)(READ_REG(BSEC->FVRw[9]));
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}
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/**
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* @brief Returns the device revision identifier
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* @note Returned Revision ID can be
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* 0x00000100 for Cut1.0
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* 0x00000101 for Cut1.1
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* 0x00000200 for Cut2.0
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* @retval Device revision identifier
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*/
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__STATIC_INLINE uint32_t LL_GetRevisionID(void)
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{
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return *(uint32_t *)(REVID_BASE);
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}
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#endif /* CPU_IN_SECURE_STATE */
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/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
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* @{
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*/
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/**
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* @brief Enable the Debug Module during SLEEP mode
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* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
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{
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SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
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}
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/**
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* @brief Disable the Debug Module during SLEEP mode
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* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
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{
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CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
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}
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/**
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* @brief Enable the Debug Module during STOP mode
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* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
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{
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SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
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}
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/**
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* @brief Disable the Debug Module during STOP mode
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* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
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* @retval None
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|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
|
|
{
|
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the Debug Module during STANDBY mode
|
|
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
|
|
{
|
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the Debug Module during STANDBY mode
|
|
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
|
|
{
|
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the Debug clock through software
|
|
* @rmtoll DBGMCU_CR DBGCLKEN LL_DBGMCU_EnableDBGClock
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_EnableDBGClock(void)
|
|
{
|
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the Debug clock through software
|
|
* @rmtoll DBGMCU_CR DBGCLKEN LL_DBGMCU_DisableDBGClock
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_DisableDBGClock(void)
|
|
{
|
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBGCLKEN);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable the TPIU export clock enable through software
|
|
* @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_EnableTPIUExportClock
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_EnableTPIUExportClock(void)
|
|
{
|
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable the TPIU export clock enable through software
|
|
* @rmtoll DBGMCU_CR TRACECLKEN LL_DBGMCU_DisableTPIUExportClock
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_DisableTPIUExportClock(void)
|
|
{
|
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACECLKEN);
|
|
}
|
|
|
|
/**
|
|
* @brief Set DBTRGIO connection control
|
|
* @rmtoll DBGMCU_CR DBTRGOEN LL_DBGMCU_SetDBTRGIOConnectionControl
|
|
* @param ConfigDBTRGIO This parameter can be one of the following values:
|
|
* @arg @ref LL_DBGMCU_DBTRGIN
|
|
* @arg @ref LL_DBGMCU_DBTRGOUT
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_SetDBTRGIOConnectionControl(uint32_t ConfigDBTRGIO)
|
|
{
|
|
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBTRGOEN, ConfigDBTRGIO);
|
|
}
|
|
|
|
/**
|
|
* @brief Get DBTRGIO connection control
|
|
* @rmtoll DBGMCU_CR DBTRGOEN LL_DBGMCU_GetDBTRGIOConnectionControl
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_DBGMCU_DBTRGIN
|
|
* @arg @ref LL_DBGMCU_DBTRGOUT
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_DBGMCU_GetDBTRGIOConnectionControl(void)
|
|
{
|
|
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBTRGOEN));
|
|
}
|
|
|
|
/**
|
|
* @brief Enable TSGEN halt
|
|
* @rmtoll DBGMCU_CR HLT_TSGEN_EN LL_DBGMCU_EnableTSGENHalt
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_EnableTSGENHalt(void)
|
|
{
|
|
SET_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable TSGEN halt
|
|
* @rmtoll DBGMCU_CR HLT_TSGEN_EN LL_DBGMCU_DisableTSGENHalt
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_DisableTSGENHalt(void)
|
|
{
|
|
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_HLT_TSGEN_EN);
|
|
}
|
|
|
|
/**
|
|
* @brief Freeze APB1 peripherals (group1 peripherals)
|
|
* @rmtoll DBGMCU_APB1LFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->APB1LFZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Unfreeze APB1 peripherals (group1 peripherals)
|
|
* @rmtoll DBGMCU_APB1LFZ DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM10_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM11_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I3C1_STOP
|
|
* @arg @ref LL_DBGMCU_APB1_GRP1_I3C2_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Freeze APB1 peripherals (group2 peripherals)
|
|
* @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Unfreeze APB1 peripherals (group2 peripherals)
|
|
* @rmtoll DBGMCU_APB1HFZ1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Freeze APB2 peripherals
|
|
* @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP LL_DBGMCU_APB2_FreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB2_FreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->APB2FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Unfreeze APB2 peripherals
|
|
* @rmtoll DBGMCU_APB2FZ1 DBG_TIMx_STOP LL_DBGMCU_APB2_UnFreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM18_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
|
|
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB2_UnFreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->APB2FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Freeze APB4 peripherals
|
|
* @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP LL_DBGMCU_APB4_FreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB4_FreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->APB4FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Unreeze APB4 peripherals
|
|
* @rmtoll DBGMCU_APB4FZ1 DBG_TIMx_STOP LL_DBGMCU_APB4_UnFreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP
|
|
* @arg @ref LL_DBGMCU_APB4_GRP1_IWDG_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB4_UnFreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->APB4FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Freeze APB5 peripherals
|
|
* @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP LL_DBGMCU_APB5_FreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB5_FreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->APB5FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Unreeze APB5 peripherals
|
|
* @rmtoll DBGMCU_APB5FZ1 DBG_TIMx_STOP LL_DBGMCU_APB5_UnFreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_APB5_GRP1_GFXTIM_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_APB5_UnFreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->APB5FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Freeze AHB1 peripherals
|
|
* @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB1_FreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_AHB1_FreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->AHB1FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Unreeze AHB1 peripherals
|
|
* @rmtoll DBGMCU_AHB1FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB1_UnFreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH0_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH1_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH2_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH3_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH4_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH5_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH6_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH7_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH8_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH9_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH10_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH11_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH12_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH13_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH14_STOP
|
|
* @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_CH15_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_AHB1_UnFreezePeriph(uint32_t Periphs)
|
|
{
|
|
SET_BIT(DBGMCU->AHB1FZ1, Periphs);
|
|
}
|
|
|
|
/**
|
|
* @brief Freeze AHB5 peripherals
|
|
* @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB5_FreezePeriph
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP
|
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_AHB5_FreezePeriph(uint32_t Periphs)
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{
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SET_BIT(DBGMCU->AHB5FZ1, Periphs);
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}
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/**
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* @brief Unreeze AHB5 peripherals
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* @rmtoll DBGMCU_AHB5FZ1 DBG_TIMx_STOP LL_DBGMCU_AHB5_UnFreezePeriph
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH0_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH1_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH2_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH3_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH4_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH5_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH6_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH7_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH8_STOP
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* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH9_STOP
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|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH10_STOP
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|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH11_STOP
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|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH12_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH13_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH14_STOP
|
|
* @arg @ref LL_DBGMCU_AHB5_GRP1_HPDMA1_CH15_STOP
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|
* @arg @ref LL_DBGMCU_AHB5_GRP1_NPU_STOP
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_DBGMCU_AHB5_UnFreezePeriph(uint32_t Periphs)
|
|
{
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|
SET_BIT(DBGMCU->AHB5FZ1, Periphs);
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}
|
|
|
|
|
|
/**
|
|
* @}
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|
*/
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|
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#endif /* defined (SYSCFG) || defined (DBGMCU) */
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|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32N6xx_LL_SYSTEM_H */
|