mirror of
https://github.com/openmv/openmv.git
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597 lines
27 KiB
C
597 lines
27 KiB
C
/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2019 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2019 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_ARCH_STR "OPENMVPURETHERMAL 65536 SDRAM" // 33 chars max
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#define OMV_BOARD_TYPE "H7"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800
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// Flash sectors for the bootloader.
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// Flash FS sector, main FW sector, max sector.
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#define OMV_FLASH_LAYOUT {1, 2, 15}
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// QSPI Flash layout for the bootloader.
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// First block, maximum block, block size in bytes.
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#define OMV_QSPIF_LAYOUT {0, 511, 64*1024}
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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// Sensor external clock source.
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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// Sensor external clock timer frequency.
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#define OMV_XCLK_FREQUENCY (12000000)
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// Sensor PLL register value.
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#define OMV_OV7725_PLL_CONFIG (0x41) // x4
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// Sensor Banding Filter Value
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#define OMV_OV7725_BANDING (0x7F)
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// Bootloader LED GPIO port/pin
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#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_1)
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#define OMV_BOOTLDR_LED_PORT (GPIOC)
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// RAW buffer size
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#define OMV_RAW_BUF_SIZE (33554432)
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// Enable hardware JPEG
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#define OMV_HARDWARE_JPEG (1)
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// Enable sensor drivers
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#define OMV_ENABLE_OV2640 (0)
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#define OMV_ENABLE_OV5640 (1)
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#define OMV_ENABLE_OV7690 (0)
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#define OMV_ENABLE_OV7725 (0)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9V034 (0)
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#define OMV_ENABLE_LEPTON (1)
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#define OMV_ENABLE_HM01B0 (0)
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// Enable WiFi debug
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#define OMV_ENABLE_WIFIDBG (1)
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// Enable self-tests on first boot
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#define OMV_ENABLE_SELFTEST (0)
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// If buffer size is bigger than this threshold, the quality is reduced.
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// This is only used for JPEG images sent to the IDE not normal compression.
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#define JPEG_QUALITY_THRESH (1920*1080*2)
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// Low and high JPEG QS.
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 256
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.3"
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// Clock Sources
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_PLL
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#define OMV_OSC_RNG_CLKSOURCE RCC_RNGCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL2
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL2
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//PLL1 48MHz for USB, SDMMC and FDCAN
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#define OMV_OSC_PLL1M (3)
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#define OMV_OSC_PLL1N (240)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (20)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 200MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (3)
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#define OMV_OSC_PLL2N (100)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (3)
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#define OMV_OSC_PLL3N (80)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (2)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_ON)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Power supply configuration
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#define OMV_PWR_SUPPLY (PWR_LDO_SUPPLY)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_FFS_MEMORY DTCM // Flash filesystem cache memory
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
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#define OMV_STACK_MEMORY ITCM // stack memory
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#define OMV_DMA_MEMORY AXI_SRAM // DMA buffers memory.
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#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
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#define OMV_JPEG_MEMORY_OFFSET (63M) // JPEG buffer is placed after FB/fballoc memory.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
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#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // _fballoc_overlay memory.
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#define OMV_FB_OVERLAY_MEMORY_OFFSET (480*1024) // _fballoc_overlay
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#define OMV_FB_SIZE (32M) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (31M) // minimum fb alloc size
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#define OMV_STACK_SIZE (64K)
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#define OMV_HEAP_SIZE (244K)
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#define OMV_SDRAM_SIZE (64 * 1024 * 1024) // This needs to be here for UVC firmware.
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#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (12K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
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#define OMV_JPEG_BUF_SIZE (1024*1024) // IDE JPEG buffer (header + data).
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#define OMV_BOOT_ORIGIN 0x08000000
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#define OMV_BOOT_LENGTH 128K
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#define OMV_TEXT_ORIGIN 0x08040000
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#define OMV_TEXT_LENGTH 1792K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_ITCM_ORIGIN 0x00000000
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#define OMV_ITCM_LENGTH 64K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 256K
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#define OMV_SRAM3_ORIGIN 0x30040000
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#define OMV_SRAM3_LENGTH 32K
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#define OMV_SRAM4_ORIGIN 0x38000000
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#define OMV_SRAM4_LENGTH 64K
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#define OMV_AXI_SRAM_ORIGIN 0x24000000
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#define OMV_AXI_SRAM_LENGTH 512K
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#define OMV_DRAM_ORIGIN 0xC0000000
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#define OMV_DRAM_LENGTH 64M
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#define OMV_FB_OVERLAY_MEMORY_ORIGIN OMV_AXI_SRAM_ORIGIN
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// Use the MPU to set an uncacheable memory region.
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#define OMV_DMA_REGION_BASE (OMV_AXI_SRAM_ORIGIN+OMV_FB_OVERLAY_MEMORY_OFFSET)
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#define OMV_DMA_REGION_SIZE MPU_REGION_SIZE_32KB
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/* SCCB/I2C */
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#define SCCB_I2C (I2C1)
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#define SCCB_AF (GPIO_AF4_I2C1)
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#define SCCB_CLK_ENABLE() __I2C1_CLK_ENABLE()
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#define SCCB_CLK_DISABLE() __I2C1_CLK_DISABLE()
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#define SCCB_PORT (GPIOB)
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#define SCCB_SCL_PIN (GPIO_PIN_8)
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#define SCCB_SDA_PIN (GPIO_PIN_9)
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#define SCCB_TIMING (I2C_TIMING_STANDARD)
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#define SCCB_FORCE_RESET() __HAL_RCC_I2C1_FORCE_RESET()
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#define SCCB_RELEASE_RESET() __HAL_RCC_I2C1_RELEASE_RESET()
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/* FIR I2C */
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#define FIR_I2C (I2C2)
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#define FIR_I2C_AF (GPIO_AF4_I2C2)
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#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define FIR_I2C_PORT (GPIOB)
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#define FIR_I2C_SCL_PIN (GPIO_PIN_10)
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#define FIR_I2C_SDA_PIN (GPIO_PIN_11)
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#define FIR_I2C_TIMING (I2C_TIMING_FULL)
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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/* DCMI */
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#define DCMI_TIM (TIM1)
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#define DCMI_TIM_PIN (GPIO_PIN_8)
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#define DCMI_TIM_PORT (GPIOA)
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#define DCMI_TIM_AF (GPIO_AF1_TIM1)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define DCMI_RESET_PIN (GPIO_PIN_10)
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#define DCMI_RESET_PORT (GPIOA)
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#define DCMI_PWDN_PIN (GPIO_PIN_7)
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#define DCMI_PWDN_PORT (GPIOD)
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#define DCMI_D0_PIN (GPIO_PIN_6)
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#define DCMI_D1_PIN (GPIO_PIN_7)
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#define DCMI_D2_PIN (GPIO_PIN_10)
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#define DCMI_D3_PIN (GPIO_PIN_11)
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#define DCMI_D4_PIN (GPIO_PIN_4)
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#define DCMI_D5_PIN (GPIO_PIN_6)
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#define DCMI_D6_PIN (GPIO_PIN_5)
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#define DCMI_D7_PIN (GPIO_PIN_6)
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#define DCMI_D0_PORT (GPIOC)
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#define DCMI_D1_PORT (GPIOC)
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#define DCMI_D2_PORT (GPIOG)
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#define DCMI_D3_PORT (GPIOG)
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#define DCMI_D4_PORT (GPIOE)
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#define DCMI_D5_PORT (GPIOB)
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#define DCMI_D6_PORT (GPIOE)
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#define DCMI_D7_PORT (GPIOE)
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#define DCMI_HSYNC_PIN (GPIO_PIN_4)
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#define DCMI_VSYNC_PIN (GPIO_PIN_7)
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#define DCMI_PXCLK_PIN (GPIO_PIN_6)
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#define DCMI_HSYNC_PORT (GPIOA)
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#define DCMI_VSYNC_PORT (GPIOB)
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#define DCMI_PXCLK_PORT (GPIOA)
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#define DCMI_RESET_LOW() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_RESET)
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#define DCMI_RESET_HIGH() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_SET)
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#define DCMI_PWDN_LOW() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_RESET)
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#define DCMI_PWDN_HIGH() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_SET)
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#define DCMI_VSYNC_IRQN EXTI9_5_IRQn
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#define DCMI_VSYNC_IRQ_LINE (7)
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#define WINC_SPI (SPI5)
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#define WINC_SPI_AF (GPIO_AF5_SPI5)
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#define WINC_SPI_TIMEOUT (1000)
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// SPI5 clock source is PLL2 (200MHz/4 == 50MHz) - Slightly over the maximum of 48 MHz.
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#define WINC_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_4)
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#define WINC_SPI_CLK_ENABLE() __HAL_RCC_SPI5_CLK_ENABLE()
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#define WINC_SPI_SCLK_PIN (GPIO_PIN_6)
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#define WINC_SPI_MISO_PIN (GPIO_PIN_7)
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#define WINC_SPI_MOSI_PIN (GPIO_PIN_10)
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#define WINC_SPI_SCLK_PORT (GPIOH)
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#define WINC_SPI_MISO_PORT (GPIOH)
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#define WINC_SPI_MOSI_PORT (GPIOJ)
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#define WINC_EN_PIN (GPIO_PIN_0)
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#define WINC_CS_PIN (GPIO_PIN_1)
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#define WINC_RST_PIN (GPIO_PIN_3)
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#define WINC_IRQ_PIN (pin_H5)
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#define WINC_WAKE_PIN (GPIO_PIN_1)
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#define WINC_CFG_PIN (GPIO_PIN_15)
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#define WINC_EN_PORT (GPIOA)
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#define WINC_CS_PORT (GPIOK)
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#define WINC_RST_PORT (GPIOC)
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#define WINC_WAKE_PORT (GPIOA)
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#define WINC_CFG_PORT (GPIOI)
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#define WINC_CS_LOW() HAL_GPIO_WritePin(WINC_CS_PORT, WINC_CS_PIN, GPIO_PIN_RESET)
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#define WINC_CS_HIGH() HAL_GPIO_WritePin(WINC_CS_PORT, WINC_CS_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_PORT GPIOB
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#define SOFT_I2C_SIOC_PIN GPIO_PIN_10
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#define SOFT_I2C_SIOD_PIN GPIO_PIN_11
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#define SOFT_I2C_SIOC_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_SIOC_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_RESET)
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#define SOFT_I2C_SIOD_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_SIOD_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_RESET)
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#define SOFT_I2C_SIOD_READ() HAL_GPIO_ReadPin (SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN)
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#define SOFT_I2C_SIOD_WRITE(bit) HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, bit)
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#define SOFT_I2C_SPIN_DELAY 64
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#define LEPTON_SPI (SPI3)
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// SPI1/2/3 clock source is PLL2 (200MHz/8 == 12.5MHz) - Minimum (164*240*8*27 = 8,501,760Hz)
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#define LEPTON_SPI_PRESCALER (SPI_BAUDRATEPRESCALER_16)
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#define LEPTON_SPI_IRQn (SPI3_IRQn)
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#define LEPTON_SPI_IRQHandler (SPI3_IRQHandler)
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#define LEPTON_SPI_DMA_IRQn (DMA1_Stream0_IRQn)
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#define LEPTON_SPI_DMA_STREAM (DMA1_Stream0)
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#define LEPTON_SPI_DMA_REQUEST (DMA_REQUEST_SPI3_RX)
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#define LEPTON_SPI_DMA_IRQHandler (DMA1_Stream0_IRQHandler)
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#define LEPTON_SPI_RESET() __HAL_RCC_SPI3_FORCE_RESET()
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#define LEPTON_SPI_RELEASE() __HAL_RCC_SPI3_RELEASE_RESET()
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#define LEPTON_SPI_CLK_ENABLE() __HAL_RCC_SPI3_CLK_ENABLE()
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#define LEPTON_SPI_CLK_DISABLE() __HAL_RCC_SPI3_CLK_DISABLE()
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#define LEPTON_SPI_SCLK_AF (GPIO_AF6_SPI3)
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#define LEPTON_SPI_MISO_AF (GPIO_AF6_SPI3)
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#define LEPTON_SPI_MOSI_AF (GPIO_AF7_SPI3)
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#define LEPTON_SPI_SSEL_AF (GPIO_AF6_SPI3)
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#define LEPTON_SPI_SCLK_PIN (GPIO_PIN_3)
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#define LEPTON_SPI_MISO_PIN (GPIO_PIN_4)
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#define LEPTON_SPI_MOSI_PIN (GPIO_PIN_5)
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#define LEPTON_SPI_SSEL_PIN (GPIO_PIN_15)
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#define LEPTON_SPI_SCLK_PORT (GPIOB)
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#define LEPTON_SPI_MISO_PORT (GPIOB)
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#define LEPTON_SPI_MOSI_PORT (GPIOB)
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#define LEPTON_SPI_SSEL_PORT (GPIOA)
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#define LEPTON_RST_PIN (GPIO_PIN_5)
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#define LEPTON_RST_PORT (GPIOD)
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#define LEPTON_PWND_PIN (GPIO_PIN_4)
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#define LEPTON_PWDN_PORT (GPIOD)
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#define LEPTON_RST_LOW() HAL_GPIO_WritePin(LEPTON_RST_PORT, LEPTON_RST_PIN, GPIO_PIN_RESET)
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#define LEPTON_RST_HIGH() HAL_GPIO_WritePin(LEPTON_RST_PORT, LEPTON_RST_PIN, GPIO_PIN_SET)
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#define LEPTON_PWDN_LOW() HAL_GPIO_WritePin(LEPTON_PWDN_PORT, LEPTON_PWND_PIN, GPIO_PIN_RESET)
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#define LEPTON_PWDN_HIGH() HAL_GPIO_WritePin(LEPTON_PWDN_PORT, LEPTON_PWND_PIN, GPIO_PIN_SET)
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#define LEPTON_CLK_PIN (GPIO_PIN_3)
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#define LEPTON_CLK_PORT (GPIOA)
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#define LEPTON_CLK_ALT (GPIO_AF4_TIM15)
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#define LEPTON_CLK_FREQ (25000000)
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// QSPI flash configuration for the bootloader.
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#define QSPIF_SIZE_BITS (25) // 2**25 == 32MBytes.
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#define QSPIF_SR_WIP_MASK (1 << 0)
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#define QSPIF_SR_WEL_MASK (1 << 1)
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#define QSPIF_READ_QUADIO_DCYC (6)
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#define QSPIF_PAGE_SIZE (0x100) // 256 bytes pages.
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#define QSPIF_NUM_PAGES (0x20000) // 131072 pages of 256 bytes
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#define QSPIF_SECTOR_SIZE (0x1000) // 4K bytes sectors.
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#define QSPIF_NUM_SECTORS (0x2000) // 8192 sectors of 4K bytes
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#define QSPIF_BLOCK_SIZE (0x10000) // 64K bytes blocks.
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#define QSPIF_NUM_BLOCKS (0x200) // 512 blocks of 64K bytes
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#define QSPIF_CLK_PIN (GPIO_PIN_10)
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#define QSPIF_CLK_PORT (GPIOF)
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#define QSPIF_CLK_ALT (GPIO_AF9_QUADSPI)
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#define QSPIF_CS_PIN (GPIO_PIN_6)
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#define QSPIF_CS_PORT (GPIOG)
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#define QSPIF_CS_ALT (GPIO_AF10_QUADSPI)
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#define QSPIF_D0_PIN (GPIO_PIN_8)
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#define QSPIF_D0_PORT (GPIOF)
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#define QSPIF_D0_ALT (GPIO_AF10_QUADSPI)
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#define QSPIF_D1_PIN (GPIO_PIN_9)
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#define QSPIF_D1_PORT (GPIOF)
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#define QSPIF_D1_ALT (GPIO_AF10_QUADSPI)
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#define QSPIF_D2_PIN (GPIO_PIN_7)
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#define QSPIF_D2_PORT (GPIOF)
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#define QSPIF_D2_ALT (GPIO_AF9_QUADSPI)
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#define QSPIF_D3_PIN (GPIO_PIN_6)
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#define QSPIF_D3_PORT (GPIOF)
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#define QSPIF_D3_ALT (GPIO_AF9_QUADSPI)
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#define QSPIF_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
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#define QSPIF_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
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#define QSPIF_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
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#define QSPIF_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
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#define QSPIF_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPIF_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOG_CLK_ENABLE()
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#define QSPIF_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPIF_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPIF_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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#define QSPIF_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOF_CLK_ENABLE()
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// LCD Interface
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#define OMV_LCD_CONTROLLER (LTDC)
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#define OMV_LCD_CLK_ENABLE() __HAL_RCC_LTDC_CLK_ENABLE()
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#define OMV_LCD_CLK_DISABLE() __HAL_RCC_LTDC_CLK_DISABLE()
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#define OMV_LCD_FORCE_RESET() __HAL_RCC_LTDC_FORCE_RESET()
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#define OMV_LCD_RELEASE_RESET() __HAL_RCC_LTDC_RELEASE_RESET()
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#define OMV_LCD_R0_PIN (GPIO_PIN_13)
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#define OMV_LCD_R1_PIN (GPIO_PIN_2)
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#define OMV_LCD_R2_PIN (GPIO_PIN_1)
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#define OMV_LCD_R3_PIN (GPIO_PIN_2)
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#define OMV_LCD_R4_PIN (GPIO_PIN_3)
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#define OMV_LCD_R5_PIN (GPIO_PIN_4)
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#define OMV_LCD_R6_PIN (GPIO_PIN_5)
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#define OMV_LCD_R7_PIN (GPIO_PIN_0)
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#define OMV_LCD_R0_PORT (GPIOG)
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#define OMV_LCD_R1_PORT (GPIOA)
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#define OMV_LCD_R2_PORT (GPIOJ)
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#define OMV_LCD_R3_PORT (GPIOJ)
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#define OMV_LCD_R4_PORT (GPIOJ)
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#define OMV_LCD_R5_PORT (GPIOJ)
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#define OMV_LCD_R6_PORT (GPIOJ)
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#define OMV_LCD_R7_PORT (GPIOJ)
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#define OMV_LCD_R0_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_R1_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_R2_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_R3_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_R4_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_R5_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_R6_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_R7_ALT (GPIO_AF9_LTDC)
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#define OMV_LCD_G0_PIN (GPIO_PIN_7)
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#define OMV_LCD_G1_PIN (GPIO_PIN_8)
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#define OMV_LCD_G2_PIN (GPIO_PIN_9)
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#define OMV_LCD_G3_PIN (GPIO_PIN_12)
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#define OMV_LCD_G4_PIN (GPIO_PIN_11)
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#define OMV_LCD_G5_PIN (GPIO_PIN_0)
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#define OMV_LCD_G6_PIN (GPIO_PIN_11)
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#define OMV_LCD_G7_PIN (GPIO_PIN_3)
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#define OMV_LCD_G0_PORT (GPIOJ)
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#define OMV_LCD_G1_PORT (GPIOJ)
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#define OMV_LCD_G2_PORT (GPIOJ)
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#define OMV_LCD_G3_PORT (GPIOJ)
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#define OMV_LCD_G4_PORT (GPIOJ)
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#define OMV_LCD_G5_PORT (GPIOK)
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#define OMV_LCD_G6_PORT (GPIOI)
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#define OMV_LCD_G7_PORT (GPIOD)
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#define OMV_LCD_G0_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_G1_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_G2_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_G3_ALT (GPIO_AF9_LTDC)
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#define OMV_LCD_G4_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_G5_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_G6_ALT (GPIO_AF9_LTDC)
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#define OMV_LCD_G7_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B0_PIN (GPIO_PIN_14)
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#define OMV_LCD_B1_PIN (GPIO_PIN_12)
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#define OMV_LCD_B2_PIN (GPIO_PIN_6)
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#define OMV_LCD_B3_PIN (GPIO_PIN_15)
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#define OMV_LCD_B4_PIN (GPIO_PIN_3)
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#define OMV_LCD_B5_PIN (GPIO_PIN_4)
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#define OMV_LCD_B6_PIN (GPIO_PIN_5)
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#define OMV_LCD_B7_PIN (GPIO_PIN_6)
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#define OMV_LCD_B0_PORT (GPIOG)
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#define OMV_LCD_B1_PORT (GPIOG)
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#define OMV_LCD_B2_PORT (GPIOD)
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#define OMV_LCD_B3_PORT (GPIOJ)
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#define OMV_LCD_B4_PORT (GPIOK)
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#define OMV_LCD_B5_PORT (GPIOK)
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#define OMV_LCD_B6_PORT (GPIOK)
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#define OMV_LCD_B7_PORT (GPIOK)
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#define OMV_LCD_B0_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B1_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B2_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B3_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B4_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B5_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B6_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_B7_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_CLK_PIN (GPIO_PIN_14)
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#define OMV_LCD_CLK_PORT (GPIOI)
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#define OMV_LCD_CLK_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_DE_PIN (GPIO_PIN_7)
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#define OMV_LCD_DE_PORT (GPIOK)
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#define OMV_LCD_DE_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_HSYNC_PIN (GPIO_PIN_12)
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#define OMV_LCD_HSYNC_PORT (GPIOI)
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#define OMV_LCD_HSYNC_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_VSYNC_PIN (GPIO_PIN_13)
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#define OMV_LCD_VSYNC_PORT (GPIOI)
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#define OMV_LCD_VSYNC_ALT (GPIO_AF14_LTDC)
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#define OMV_LCD_DISP_PIN (GPIO_PIN_9)
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#define OMV_LCD_DISP_PORT (GPIOG)
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#define OMV_LCD_DISP_ON() HAL_GPIO_WritePin(OMV_LCD_DISP_PORT, OMV_LCD_DISP_PIN, GPIO_PIN_SET)
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#define OMV_LCD_DISP_OFF() HAL_GPIO_WritePin(OMV_LCD_DISP_PORT, OMV_LCD_DISP_PIN, GPIO_PIN_RESET)
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#define OMV_LCD_BL_PIN (GPIO_PIN_0)
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#define OMV_LCD_BL_PORT (GPIOB)
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#define OMV_LCD_BL_ALT (GPIO_AF2_TIM3)
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#define OMV_LCD_BL_FREQ (100000)
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#define OMV_LCD_BL_ON() HAL_GPIO_WritePin(OMV_LCD_BL_PORT, OMV_LCD_BL_PIN, GPIO_PIN_SET)
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#define OMV_LCD_BL_OFF() HAL_GPIO_WritePin(OMV_LCD_BL_PORT, OMV_LCD_BL_PIN, GPIO_PIN_RESET)
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#define OMV_LCD_BL_TIM (TIM3)
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#define OMV_LCD_BL_TIM_CHANNEL (TIM_CHANNEL_3)
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#define OMV_LCD_BL_TIM_CLK_ENABLE() __HAL_RCC_TIM3_CLK_ENABLE()
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#define OMV_LCD_BL_TIM_CLK_DISABLE() __HAL_RCC_TIM3_CLK_DISABLE()
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#define OMV_LCD_BL_TIM_FORCE_RESET() __HAL_RCC_TIM3_FORCE_RESET()
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#define OMV_LCD_BL_TIM_RELEASE_RESET() __HAL_RCC_TIM3_RELEASE_RESET()
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#define OMV_LCD_BL_TIM_PCLK_FREQ() HAL_RCC_GetPCLK1Freq()
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// SPI LCD Interface
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#define OMV_SPI_LCD_CONTROLLER (&spi_obj[1])
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#define OMV_SPI_LCD_CONTROLLER_INSTANCE (SPI2)
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#define OMV_SPI_LCD_MOSI_PIN (GPIO_PIN_15)
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#define OMV_SPI_LCD_MOSI_PORT (GPIOB)
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#define OMV_SPI_LCD_MOSI_ALT (GPIO_AF5_SPI2)
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#define OMV_SPI_LCD_SCLK_PIN (GPIO_PIN_13)
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#define OMV_SPI_LCD_SCLK_PORT (GPIOB)
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#define OMV_SPI_LCD_SCLK_ALT (GPIO_AF5_SPI2)
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#define OMV_SPI_LCD_RST_PIN (GPIO_PIN_12)
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#define OMV_SPI_LCD_RST_PORT (GPIOD)
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#define OMV_SPI_LCD_RST_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_RST_PORT, OMV_SPI_LCD_RST_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_RST_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_RST_PORT, OMV_SPI_LCD_RST_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_RS_PIN (GPIO_PIN_13)
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#define OMV_SPI_LCD_RS_PORT (GPIOD)
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#define OMV_SPI_LCD_RS_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_RS_PORT, OMV_SPI_LCD_RS_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_RS_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_RS_PORT, OMV_SPI_LCD_RS_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_CS_PIN (GPIO_PIN_12)
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#define OMV_SPI_LCD_CS_PORT (GPIOB)
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#define OMV_SPI_LCD_CS_HIGH() HAL_GPIO_WritePin(OMV_SPI_LCD_CS_PORT, OMV_SPI_LCD_CS_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_CS_LOW() HAL_GPIO_WritePin(OMV_SPI_LCD_CS_PORT, OMV_SPI_LCD_CS_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_BL_PIN (GPIO_PIN_5)
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#define OMV_SPI_LCD_BL_PORT (GPIOA)
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#define OMV_SPI_LCD_BL_ON() HAL_GPIO_WritePin(OMV_SPI_LCD_BL_PORT, OMV_SPI_LCD_BL_PIN, GPIO_PIN_SET)
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#define OMV_SPI_LCD_BL_OFF() HAL_GPIO_WritePin(OMV_SPI_LCD_BL_PORT, OMV_SPI_LCD_BL_PIN, GPIO_PIN_RESET)
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#define OMV_SPI_LCD_BL_DAC (DAC1)
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#define OMV_SPI_LCD_BL_DAC_CHANNEL (DAC_CHANNEL_2)
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#define OMV_SPI_LCD_BL_DAC_CLK_ENABLE() __HAL_RCC_DAC12_CLK_ENABLE()
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#define OMV_SPI_LCD_BL_DAC_CLK_DISABLE() __HAL_RCC_DAC12_CLK_DISABLE()
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#define OMV_SPI_LCD_BL_DAC_FORCE_RESET() __HAL_RCC_DAC12_FORCE_RESET()
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#define OMV_SPI_LCD_BL_DAC_RELEASE_RESET() __HAL_RCC_DAC12_RELEASE_RESET()
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// DVI TFP410PAP I/O
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#define OMV_DVI_PRESENT
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#define OMV_DVI_RESET_PIN (pin_D11)
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#define OMV_DVI_SCL_PIN (pin_B1)
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#define OMV_DVI_SDA_PIN (pin_B2)
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#define OMV_DVI_INT_PIN (pin_I8)
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// DDC I/O
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#define OMV_DDC_PRESENT
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#define OMV_DDC_SCL_PIN (pin_H3)
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#define OMV_DDC_SDA_PIN (pin_H4)
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// Touch Screen I/O
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#define OMV_TOUCH_PRESENT
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#define OMV_TOUCH_RESET_PIN (pin_K2)
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#define OMV_TOUCH_SCL_PIN (pin_J13)
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#define OMV_TOUCH_SDA_PIN (pin_J14)
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#define OMV_TOUCH_INT_PIN (pin_J6)
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// HDMI CEC I/O
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#define OMV_CEC_PRESENT
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#define OMV_CEC_PIN (pin_H2)
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// Enable additional GPIO banks for DRAM...
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#define OMV_ENABLE_GPIO_BANK_F
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#define OMV_ENABLE_GPIO_BANK_G
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#define OMV_ENABLE_GPIO_BANK_H
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#define OMV_ENABLE_GPIO_BANK_I
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// Enable additional GPIO banks for LCD...
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#define OMV_ENABLE_GPIO_BANK_J
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#define OMV_ENABLE_GPIO_BANK_K
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#endif //__OMV_BOARDCONFIG_H__
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