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433 lines
14 KiB
C
433 lines
14 KiB
C
/*
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* Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <nrfx.h>
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#if NRFX_CHECK(NRFX_SPI_ENABLED)
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#if !(NRFX_CHECK(NRFX_SPI0_ENABLED) || NRFX_CHECK(NRFX_SPI1_ENABLED) || \
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NRFX_CHECK(NRFX_SPI2_ENABLED))
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#error "No enabled SPI instances. Check <nrfx_config.h>."
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#endif
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#include <nrfx_spi.h>
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#include "prs/nrfx_prs.h"
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#include <hal/nrf_gpio.h>
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#define NRFX_LOG_MODULE SPI
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#include <nrfx_log.h>
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// Control block - driver instance local data.
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typedef struct
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{
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nrfx_spi_evt_handler_t handler;
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void * p_context;
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nrfx_spi_evt_t evt; // Keep the struct that is ready for event handler. Less memcpy.
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nrfx_drv_state_t state;
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volatile bool transfer_in_progress;
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// [no need for 'volatile' attribute for the following members, as they
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// are not concurrently used in IRQ handlers and main line code]
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uint8_t ss_pin;
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uint8_t miso_pin;
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uint8_t orc;
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size_t bytes_transferred;
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bool abort;
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} spi_control_block_t;
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static spi_control_block_t m_cb[NRFX_SPI_ENABLED_COUNT];
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nrfx_err_t nrfx_spi_init(nrfx_spi_t const * p_instance,
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nrfx_spi_config_t const * p_config,
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nrfx_spi_evt_handler_t handler,
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void * p_context)
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{
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NRFX_ASSERT(p_config);
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spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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nrfx_err_t err_code;
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if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
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{
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err_code = NRFX_ERROR_INVALID_STATE;
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NRFX_LOG_WARNING("Function: %s, error code: %s.",
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__func__,
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NRFX_LOG_ERROR_STRING_GET(err_code));
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return err_code;
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}
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#if NRFX_CHECK(NRFX_PRS_ENABLED)
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static nrfx_irq_handler_t const irq_handlers[NRFX_SPI_ENABLED_COUNT] = {
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#if NRFX_CHECK(NRFX_SPI0_ENABLED)
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nrfx_spi_0_irq_handler,
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#endif
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#if NRFX_CHECK(NRFX_SPI1_ENABLED)
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nrfx_spi_1_irq_handler,
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#endif
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#if NRFX_CHECK(NRFX_SPI2_ENABLED)
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nrfx_spi_2_irq_handler,
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#endif
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};
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if (nrfx_prs_acquire(p_instance->p_reg,
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irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS)
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{
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err_code = NRFX_ERROR_BUSY;
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NRFX_LOG_WARNING("Function: %s, error code: %s.",
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__func__,
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NRFX_LOG_ERROR_STRING_GET(err_code));
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return err_code;
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}
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#endif // NRFX_CHECK(NRFX_PRS_ENABLED)
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p_cb->handler = handler;
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p_cb->p_context = p_context;
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uint32_t mosi_pin;
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uint32_t miso_pin;
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// Configure pins used by the peripheral:
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// - SCK - output with initial value corresponding with the SPI mode used:
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// 0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1);
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// according to the reference manual guidelines this pin and its input
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// buffer must always be connected for the SPI to work.
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if (p_config->mode <= NRF_SPI_MODE_1)
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{
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nrf_gpio_pin_clear(p_config->sck_pin);
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}
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else
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{
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nrf_gpio_pin_set(p_config->sck_pin);
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}
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nrf_gpio_cfg(p_config->sck_pin,
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NRF_GPIO_PIN_DIR_OUTPUT,
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NRF_GPIO_PIN_INPUT_CONNECT,
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NRF_GPIO_PIN_NOPULL,
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NRF_GPIO_PIN_S0S1,
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NRF_GPIO_PIN_NOSENSE);
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// - MOSI (optional) - output with initial value 0,
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if (p_config->mosi_pin != NRFX_SPI_PIN_NOT_USED)
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{
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mosi_pin = p_config->mosi_pin;
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nrf_gpio_pin_clear(mosi_pin);
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nrf_gpio_cfg_output(mosi_pin);
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}
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else
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{
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mosi_pin = NRF_SPI_PIN_NOT_CONNECTED;
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}
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// - MISO (optional) - input,
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if (p_config->miso_pin != NRFX_SPI_PIN_NOT_USED)
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{
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miso_pin = p_config->miso_pin;
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nrf_gpio_cfg_input(miso_pin, p_config->miso_pull);
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}
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else
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{
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miso_pin = NRF_SPI_PIN_NOT_CONNECTED;
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}
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m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin;
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// - Slave Select (optional) - output with initial value 1 (inactive).
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if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED)
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{
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nrf_gpio_pin_set(p_config->ss_pin);
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nrf_gpio_cfg_output(p_config->ss_pin);
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}
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m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
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NRF_SPI_Type * p_spi = p_instance->p_reg;
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nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin);
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nrf_spi_frequency_set(p_spi, p_config->frequency);
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nrf_spi_configure(p_spi, p_config->mode, p_config->bit_order);
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m_cb[p_instance->drv_inst_idx].orc = p_config->orc;
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if (p_cb->handler)
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{
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nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
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}
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nrf_spi_enable(p_spi);
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if (p_cb->handler)
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{
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NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(p_instance->p_reg),
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p_config->irq_priority);
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NRFX_IRQ_ENABLE(nrfx_get_irq_number(p_instance->p_reg));
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}
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p_cb->transfer_in_progress = false;
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p_cb->state = NRFX_DRV_STATE_INITIALIZED;
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err_code = NRFX_SUCCESS;
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NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
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return err_code;
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}
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void nrfx_spi_uninit(nrfx_spi_t const * p_instance)
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{
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spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
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if (p_cb->handler)
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{
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NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
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}
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NRF_SPI_Type * p_spi = p_instance->p_reg;
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if (p_cb->handler)
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{
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nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK);
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}
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if (p_cb->miso_pin != NRFX_SPI_PIN_NOT_USED)
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{
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nrf_gpio_cfg_default(p_cb->miso_pin);
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}
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nrf_spi_disable(p_spi);
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#if NRFX_CHECK(NRFX_PRS_ENABLED)
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nrfx_prs_release(p_instance->p_reg);
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#endif
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p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
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}
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static void finish_transfer(spi_control_block_t * p_cb)
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{
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// If Slave Select signal is used, this is the time to deactivate it.
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if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
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{
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nrf_gpio_pin_set(p_cb->ss_pin);
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}
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// By clearing this flag before calling the handler we allow subsequent
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// transfers to be started directly from the handler function.
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p_cb->transfer_in_progress = false;
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p_cb->evt.type = NRFX_SPI_EVENT_DONE;
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p_cb->handler(&p_cb->evt, p_cb->p_context);
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}
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// This function is called from the IRQ handler or, in blocking mode, directly
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// from the 'spi_xfer' function.
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// It returns true as long as the transfer should be continued, otherwise (when
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// there is nothing more to send/receive) it returns false.
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static bool transfer_byte(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
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{
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// Read the data byte received in this transfer (always, because no further
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// READY event can be generated until the current byte is read out from the
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// RXD register), and store it in the RX buffer (only when needed).
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volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi);
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if (p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length)
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{
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p_cb->evt.xfer_desc.p_rx_buffer[p_cb->bytes_transferred] = rx_data;
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}
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++p_cb->bytes_transferred;
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// Check if there are more bytes to send or receive and write proper data
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// byte (next one from TX buffer or over-run character) to the TXD register
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// when needed.
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// NOTE - we've already used 'p_cb->bytes_transferred + 1' bytes from our
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// buffers, because we take advantage of double buffering of TXD
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// register (so in effect one byte is still being transmitted now);
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// see how the transfer is started in the 'spi_xfer' function.
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size_t bytes_used = p_cb->bytes_transferred + 1;
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if (p_cb->abort)
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{
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if (bytes_used < p_cb->evt.xfer_desc.tx_length)
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{
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p_cb->evt.xfer_desc.tx_length = bytes_used;
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}
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if (bytes_used < p_cb->evt.xfer_desc.rx_length)
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{
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p_cb->evt.xfer_desc.rx_length = bytes_used;
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}
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}
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if (bytes_used < p_cb->evt.xfer_desc.tx_length)
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{
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nrf_spi_txd_set(p_spi, p_cb->evt.xfer_desc.p_tx_buffer[bytes_used]);
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return true;
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}
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else if (bytes_used < p_cb->evt.xfer_desc.rx_length)
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{
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nrf_spi_txd_set(p_spi, p_cb->orc);
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return true;
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}
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return (p_cb->bytes_transferred < p_cb->evt.xfer_desc.tx_length ||
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p_cb->bytes_transferred < p_cb->evt.xfer_desc.rx_length);
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}
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static void spi_xfer(NRF_SPI_Type * p_spi,
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spi_control_block_t * p_cb,
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nrfx_spi_xfer_desc_t const * p_xfer_desc)
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{
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p_cb->bytes_transferred = 0;
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nrf_spi_int_disable(p_spi, NRF_SPI_INT_READY_MASK);
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nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
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// Start the transfer by writing some byte to the TXD register;
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// if TX buffer is not empty, take the first byte from this buffer,
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// otherwise - use over-run character.
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nrf_spi_txd_set(p_spi,
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(p_xfer_desc->tx_length > 0 ? p_xfer_desc->p_tx_buffer[0] : p_cb->orc));
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// TXD register is double buffered, so next byte to be transmitted can
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// be written immediately, if needed, i.e. if TX or RX transfer is to
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// be more that 1 byte long. Again - if there is something more in TX
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// buffer send it, otherwise use over-run character.
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if (p_xfer_desc->tx_length > 1)
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{
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nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]);
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}
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else if (p_xfer_desc->rx_length > 1)
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{
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nrf_spi_txd_set(p_spi, p_cb->orc);
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}
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// For blocking mode (user handler not provided) wait here for READY
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// events (indicating that the byte from TXD register was transmitted
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// and a new incoming byte was moved to the RXD register) and continue
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// transaction until all requested bytes are transferred.
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// In non-blocking mode - IRQ service routine will do this stuff.
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if (p_cb->handler)
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{
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nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
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}
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else
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{
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do {
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while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {}
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nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
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NRFX_LOG_DEBUG("SPI: Event: NRF_SPI_EVENT_READY.");
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} while (transfer_byte(p_spi, p_cb));
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if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
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{
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nrf_gpio_pin_set(p_cb->ss_pin);
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}
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}
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}
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nrfx_err_t nrfx_spi_xfer(nrfx_spi_t const * p_instance,
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nrfx_spi_xfer_desc_t const * p_xfer_desc,
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uint32_t flags)
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{
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spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
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NRFX_ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
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NRFX_ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);
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nrfx_err_t err_code = NRFX_SUCCESS;
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if (p_cb->transfer_in_progress)
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{
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err_code = NRFX_ERROR_BUSY;
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NRFX_LOG_WARNING("Function: %s, error code: %s.",
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__func__,
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NRFX_LOG_ERROR_STRING_GET(err_code));
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return err_code;
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}
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else
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{
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if (p_cb->handler)
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{
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p_cb->transfer_in_progress = true;
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}
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}
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p_cb->evt.xfer_desc = *p_xfer_desc;
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p_cb->abort = false;
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if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
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{
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nrf_gpio_pin_clear(p_cb->ss_pin);
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}
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if (flags)
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{
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p_cb->transfer_in_progress = false;
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err_code = NRFX_ERROR_NOT_SUPPORTED;
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}
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else
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{
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spi_xfer(p_instance->p_reg, p_cb, p_xfer_desc);
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}
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NRFX_LOG_INFO("Function: %s, error code: %s.",
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__func__,
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NRFX_LOG_ERROR_STRING_GET(err_code));
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return err_code;
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}
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void nrfx_spi_abort(nrfx_spi_t const * p_instance)
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{
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spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
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NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
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p_cb->abort = true;
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}
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static void irq_handler(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
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{
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NRFX_ASSERT(p_cb->handler);
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nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
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NRFX_LOG_DEBUG("Event: NRF_SPI_EVENT_READY.");
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if (!transfer_byte(p_spi, p_cb))
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{
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finish_transfer(p_cb);
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}
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}
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#if NRFX_CHECK(NRFX_SPI0_ENABLED)
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void nrfx_spi_0_irq_handler(void)
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{
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irq_handler(NRF_SPI0, &m_cb[NRFX_SPI0_INST_IDX]);
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}
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#endif
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#if NRFX_CHECK(NRFX_SPI1_ENABLED)
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void nrfx_spi_1_irq_handler(void)
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{
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irq_handler(NRF_SPI1, &m_cb[NRFX_SPI1_INST_IDX]);
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}
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#endif
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#if NRFX_CHECK(NRFX_SPI2_ENABLED)
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void nrfx_spi_2_irq_handler(void)
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{
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irq_handler(NRF_SPI2, &m_cb[NRFX_SPI2_INST_IDX]);
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}
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#endif
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#endif // NRFX_CHECK(NRFX_SPI_ENABLED)
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