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https://github.com/openmv/openmv.git
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102 lines
3.5 KiB
C
102 lines
3.5 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file Driver_GPIO_Private.h
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* @author Girish BN, Manoj A Murudi
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* @email girish.bn@alifsemi.com, manoj.murudi@alifsemi.com
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* @version V1.0.0
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* @date 29-March-2023
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* @brief Header file for GPIO.
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* @bug None.
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* @Note None
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******************************************************************************/
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#ifndef DRIVER_GPIO_PRIVATE_H_
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#define DRIVER_GPIO_PRIVATE_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "RTE_Device.h"
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#include "RTE_Components.h"
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#include CMSIS_device_header
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#include "Driver_GPIO.h"
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#include "gpio.h"
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#define GPIO_PORT_MAX_PIN_NUMBER 0x8U /* Number of pins in each port */
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#define ARM_GPIO_BIT_IRQ_POLARITY_Pos 0U ///< bits - 0
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#define ARM_GPIO_BIT_IRQ_POLARITY_Msk (1U << ARM_GPIO_BIT_IRQ_POLARITY_Pos)
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#define ARM_GPIO_BIT_IRQ_POLARITY(x) (((x)& ARM_GPIO_BIT_IRQ_POLARITY_Msk) >> ARM_GPIO_BIT_IRQ_POLARITY_Pos)
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#define ARM_GPIO_BIT_IRQ_BOTH_EDGE_Pos 1U ///< bits - 1
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#define ARM_GPIO_BIT_IRQ_BOTH_EDGE_Msk (1U << ARM_GPIO_BIT_IRQ_BOTH_EDGE_Pos)
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#define ARM_GPIO_BIT_IRQ_BOTH_EDGE(x) (((x)& ARM_GPIO_BIT_IRQ_BOTH_EDGE_Msk) >> ARM_GPIO_BIT_IRQ_BOTH_EDGE_Pos)
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#define ARM_GPIO_BIT_IRQ_SENSITIVE_Pos 2U ///< bits - 2
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#define ARM_GPIO_BIT_IRQ_SENSITIVE_Msk (1U << ARM_GPIO_BIT_IRQ_SENSITIVE_Pos)
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#define ARM_GPIO_BIT_IRQ_SENSITIVE(x) (((x)& ARM_GPIO_BIT_IRQ_SENSITIVE_Msk) >> ARM_GPIO_BIT_IRQ_SENSITIVE_Pos)
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/**
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* enum GPIO_INSTANCE.
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* GPIO instances.
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*/
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typedef enum _GPIO_INSTANCE
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{
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GPIO0_INSTANCE,
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GPIO1_INSTANCE,
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GPIO2_INSTANCE,
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GPIO3_INSTANCE,
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GPIO4_INSTANCE,
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GPIO5_INSTANCE,
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GPIO6_INSTANCE,
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GPIO7_INSTANCE,
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GPIO8_INSTANCE,
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GPIO9_INSTANCE,
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GPIO10_INSTANCE,
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GPIO11_INSTANCE,
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GPIO12_INSTANCE,
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GPIO13_INSTANCE,
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GPIO14_INSTANCE,
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LPGPIO_INSTANCE
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} GPIO_INSTANCE;
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typedef struct _GPIO_DRV_STATE {
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uint32_t initialized : 1; /* Driver Initialized*/
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uint32_t powered : 1; /* Driver powered */
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uint32_t reserved : 30;/* Reserved */
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} GPIO_DRV_STATE;
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/**
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* @brief GPIO Resources
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*/
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typedef struct _GPIO_RESOURCES {
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GPIO_Type *reg_base; /**< GPIO PORT Base Address>**/
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IRQn_Type IRQ_base_num; /**< GPIO PORT IRQ base Num>**/
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uint16_t db_clkdiv; /**< GPIO PORT debounce clk divisor: only for GPIO 0-14 >**/
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GPIO_DRV_STATE state; /**< GPIO PORT status flag >**/
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uint8_t IRQ_priority[GPIO_PORT_MAX_PIN_NUMBER]; /**< GPIO PIN IRQ priority >**/
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GPIO_INSTANCE gpio_id; /**< GPIO instance >*/
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ARM_GPIO_SignalEvent_t cb_event[GPIO_PORT_MAX_PIN_NUMBER]; /**< GPIO Call back function >*/
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} GPIO_RESOURCES;
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#ifdef __cplusplus
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}
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#endif
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#endif /* DRIVER_GPIO_PRIVATE_H_ */
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/************************ (C) COPYRIGHT ALIF SEMICONDUCTOR *****END OF FILE****/
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