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107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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#ifndef DRIVER_I3C_PRIVATE_H
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#define DRIVER_I3C_PRIVATE_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "RTE_Device.h"
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#include "RTE_Components.h"
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#include CMSIS_device_header
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#include "Driver_I3C.h"
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#include "i3c.h"
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/* Check if DMA Support is enable? */
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#if RTE_I3C_DMA_ENABLE
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#define I3C_DMA_ENABLE 1
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#else
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#define I3C_DMA_ENABLE 0
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#endif
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#if I3C_DMA_ENABLE
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#include <DMA_Common.h>
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#endif
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#define I3C_TARGET_SLAVE_TYPE_I2C (1U << 7U) /* Represents slave type */
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/**
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\brief I3C Driver states.
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*/
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typedef volatile struct _I3C_DRIVER_STATE
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{
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uint32_t initialized : 1; /* Driver initialized */
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uint32_t powered : 1; /* Driver powered */
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uint32_t is_master : 1; /* Driver master mode */
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uint32_t enabled : 1; /* Driver enabled */
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uint32_t reserved : 28;/* Reserved */
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} I3C_DRIVER_STATE;
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/**
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\brief I3C Slave Device Address info
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*/
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typedef struct _I3C_SLAVE_DAT_TYPE
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{
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uint32_t datp; /* DAT (Device Address Table) offset */
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uint32_t maxdevs; /* maximum number of slaves supported */
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uint8_t addrs[I3C_MAX_DEVS]; /* Assigned dynamic(i3c) or static address(i2c slave) */
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uint32_t freepos; /* bitmask of used addresses */
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uint32_t last_asgd_addr_pos; /* Last assigned slave address positions */
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}I3C_SLAVE_DAT_TYPE;
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#if I3C_DMA_ENABLE
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typedef struct _I3C_DMA_HW_CONFIG
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{
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DMA_PERIPHERAL_CONFIG dma_tx; /* DMA Tx interface */
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DMA_PERIPHERAL_CONFIG dma_rx; /* DMA Rx interface */
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} I3C_DMA_HW_CONFIG;
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#endif
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/**
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\brief I3C Device Resources
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*/
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typedef struct _I3C_RESOURCES
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{
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I3C_Type *regs; /* Pointer to i3c regs */
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ARM_I3C_SignalEvent_t cb_event; /* Pointer to call back function */
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#if I3C_DMA_ENABLE
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ARM_DMA_SignalEvent_t dma_cb; /* Pointer to DMA Callback */
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#endif
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uint32_t core_clk; /* i3c core clock frequency */
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I3C_SLAVE_DAT_TYPE slave_dat; /* i3c slave devices address local information */
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i3c_xfer_t xfer; /* i3c transfer structure */
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ARM_I3C_STATUS status; /* i3c driver status */
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I3C_DRIVER_STATE state; /* I3C driver state */
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#if RTE_I3C_BLOCKING_MODE_ENABLE
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bool blocking_mode; /* I3C blocking mode transfer enable */
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#endif
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bool adaptive_mode; /* I3C slave I2C/I3C adaptive mode */
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IRQn_Type irq; /* i3c interrupt number */
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uint32_t irq_priority; /* i3c interrupt priority */
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#if I3C_DMA_ENABLE
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I3C_DMA_HW_CONFIG *dma_cfg; /* DMA Controller configuration */
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const uint32_t dma_irq_priority; /* DMA IRQ priority number */
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#endif
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}I3C_RESOURCES;
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#ifdef __cplusplus
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}
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#endif
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#endif /* DRIVER_I3C_PRIVATE_H */
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