mirror of
https://github.com/openmv/openmv.git
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277 lines
10 KiB
C
277 lines
10 KiB
C
/*
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* This file is part of the OpenMV project.
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*
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* Copyright (c) 2013-2019 Ibrahim Abdelkader <iabdalkader@openmv.io>
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* Copyright (c) 2013-2019 Kwabena W. Agyeman <kwagyeman@openmv.io>
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*
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* This work is licensed under the MIT license, see the file LICENSE for details.
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*
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* Board configuration and pin definitions.
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*/
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#ifndef __OMV_BOARDCONFIG_H__
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#define __OMV_BOARDCONFIG_H__
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// Architecture info
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#define OMV_ARCH_STR "PORTENTA H7 8192 SDRAM" // 33 chars max
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#define OMV_BOARD_TYPE "H7"
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#define OMV_UNIQUE_ID_ADDR 0x1FF1E800
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// Flash sectors for the bootloader.
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// Flash FS sector, main FW sector, max sector.
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#define OMV_FLASH_LAYOUT {1, 2, 15}
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#define OMV_XCLK_MCO (0U)
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#define OMV_XCLK_TIM (1U)
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#define OMV_XCLK_OSC (2U)
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// Sensor external clock source.
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#define OMV_XCLK_SOURCE (OMV_XCLK_TIM)
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// Sensor external clock timer frequency.
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#define OMV_XCLK_FREQUENCY (6000000)
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// Sensor PLL register value.
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#define OMV_OV7725_PLL_CONFIG (0x41) // x4
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// Sensor Banding Filter Value
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#define OMV_OV7725_BANDING (0x7F)
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// Bootloader LED GPIO port/pin
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#define OMV_BOOTLDR_LED_PIN (GPIO_PIN_1)
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#define OMV_BOOTLDR_LED_PORT (GPIOC)
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// RAW buffer size
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#define OMV_RAW_BUF_SIZE (4*1024*1024)
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// Enable hardware JPEG
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#define OMV_HARDWARE_JPEG (1)
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// Enable sensor drivers
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#define OMV_ENABLE_OV2640 (0)
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#define OMV_ENABLE_OV5640 (0)
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#define OMV_ENABLE_OV7690 (0)
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#define OMV_ENABLE_OV7725 (0)
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#define OMV_ENABLE_OV9650 (0)
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#define OMV_ENABLE_MT9V034 (0)
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#define OMV_ENABLE_LEPTON (0)
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#define OMV_ENABLE_HM01B0 (1)
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// Enable WiFi debug
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#define OMV_ENABLE_WIFIDBG (0)
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// Enable self-tests on first boot
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#define OMV_ENABLE_SELFTEST (0)
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// If buffer size is bigger than this threshold, the quality is reduced.
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// This is only used for JPEG images sent to the IDE not normal compression.
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#define JPEG_QUALITY_THRESH (320*240*2)
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// Low and high JPEG QS.
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#define JPEG_QUALITY_LOW 50
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#define JPEG_QUALITY_HIGH 90
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// FB Heap Block Size
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#define OMV_UMM_BLOCK_SIZE 256
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// Core VBAT for selftests
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#define OMV_CORE_VBAT "3.0"
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// PLL1 400MHz/40MHz for SDMMC and FDCAN
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// USB and RNG are clocked from the HSI48
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#define OMV_OSC_PLL1M (5)
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#define OMV_OSC_PLL1N (160)
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#define OMV_OSC_PLL1P (2)
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#define OMV_OSC_PLL1Q (16)
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#define OMV_OSC_PLL1R (2)
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#define OMV_OSC_PLL1VCI (RCC_PLL1VCIRANGE_2)
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#define OMV_OSC_PLL1VCO (RCC_PLL1VCOWIDE)
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#define OMV_OSC_PLL1FRAC (0)
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// PLL2 180MHz for FMC and QSPI.
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#define OMV_OSC_PLL2M (5)
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#define OMV_OSC_PLL2N (72)
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#define OMV_OSC_PLL2P (2)
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#define OMV_OSC_PLL2Q (2)
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#define OMV_OSC_PLL2R (2)
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#define OMV_OSC_PLL2VCI (RCC_PLL2VCIRANGE_2)
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#define OMV_OSC_PLL2VCO (RCC_PLL2VCOWIDE)
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#define OMV_OSC_PLL2FRAC (0)
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// PLL3 160MHz for ADC and SPI123
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#define OMV_OSC_PLL3M (5)
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#define OMV_OSC_PLL3N (160)
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#define OMV_OSC_PLL3P (2)
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#define OMV_OSC_PLL3Q (5)
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#define OMV_OSC_PLL3R (2)
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#define OMV_OSC_PLL3VCI (RCC_PLL3VCIRANGE_2)
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#define OMV_OSC_PLL3VCO (RCC_PLL3VCOWIDE)
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#define OMV_OSC_PLL3FRAC (0)
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// Clock Sources
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#define OMV_OSC_USB_CLKSOURCE RCC_USBCLKSOURCE_HSI48
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#define OMV_OSC_ADC_CLKSOURCE RCC_ADCCLKSOURCE_PLL3
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#define OMV_OSC_SPI123_CLKSOURCE RCC_SPI123CLKSOURCE_PLL3
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// HSE/HSI/CSI State
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#define OMV_OSC_HSE_STATE (RCC_HSE_BYPASS)
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#define OMV_OSC_HSI48_STATE (RCC_HSI48_ON)
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// Flash Latency
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#define OMV_FLASH_LATENCY (FLASH_LATENCY_2)
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// Linker script constants (see the linker script template stm32fxxx.ld.S).
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// Note: fb_alloc is a stack-based, dynamically allocated memory on FB.
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// The maximum available fb_alloc memory = FB_ALLOC_SIZE + FB_SIZE - (w*h*bpp).
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#define OMV_FFS_MEMORY DTCM // Flash filesystem cache memory
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#define OMV_MAIN_MEMORY SRAM1 // data, bss and heap
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#define OMV_STACK_MEMORY SRAM1 // stack memory
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#define OMV_DMA_MEMORY AXI_SRAM // DMA buffers memory.
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#define OMV_FB_MEMORY DRAM // Framebuffer, fb_alloc
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#define OMV_JPEG_MEMORY DRAM // JPEG buffer memory buffer.
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#define OMV_JPEG_MEMORY_OFFSET (7M) // JPEG buffer is placed after FB/fballoc memory.
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#define OMV_VOSPI_MEMORY SRAM4 // VoSPI buffer memory.
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#define OMV_FB_OVERLAY_MEMORY AXI_SRAM // _fballoc_overlay memory.
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#define OMV_FB_OVERLAY_MEMORY_OFFSET (480*1024) // _fballoc_overlay
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#define OMV_CYW43_MEMORY FLASH_EXT // CYW43 firmware in external flash mmap'd flash.
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#define OMV_CYW43_MEMORY_OFFSET (0x90F00000)// Last Mbyte.
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#define OMV_FB_SIZE (4M) // FB memory: header + VGA/GS image
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#define OMV_FB_ALLOC_SIZE (3M) // minimum fb alloc size
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#define OMV_STACK_SIZE (32K)
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#define OMV_HEAP_SIZE (212K)
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#define OMV_SDRAM_SIZE (8 * 1024 * 1024) // This needs to be here for UVC firmware.
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#define OMV_SDRAM_TEST (0)
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#define OMV_LINE_BUF_SIZE (11 * 1024) // Image line buffer round(2592 * 2BPP * 2 buffers).
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#define OMV_MSC_BUF_SIZE (12K) // USB MSC bot data
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#define OMV_VFS_BUF_SIZE (1K) // VFS sturct + FATFS file buffer (624 bytes)
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#define OMV_JPEG_BUF_SIZE (1024*1024) // IDE JPEG buffer (header + data).
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#define OMV_BOOT_ORIGIN 0x08000000
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#define OMV_BOOT_LENGTH 128K
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#define OMV_TEXT_ORIGIN 0x08040000
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#define OMV_TEXT_LENGTH 1792K
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#define OMV_DTCM_ORIGIN 0x20000000 // Note accessible by CPU and MDMA only.
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#define OMV_DTCM_LENGTH 128K
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#define OMV_SRAM1_ORIGIN 0x30000000
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#define OMV_SRAM1_LENGTH 288K
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#define OMV_SRAM4_ORIGIN 0x38000000
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#define OMV_SRAM4_LENGTH 64K
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#define OMV_AXI_SRAM_ORIGIN 0x24000000
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#define OMV_AXI_SRAM_LENGTH 512K
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#define OMV_DRAM_ORIGIN 0xC0000000
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#define OMV_DRAM_LENGTH 8M
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#define OMV_FLASH_EXT_ORIGIN 0x90000000
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#define OMV_FLASH_EXT_LENGTH 16M
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#define OMV_FB_OVERLAY_MEMORY_ORIGIN OMV_AXI_SRAM_ORIGIN
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// Use the MPU to set an uncacheable memory region.
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#define OMV_DMA_REGION_BASE (OMV_AXI_SRAM_ORIGIN+OMV_FB_OVERLAY_MEMORY_OFFSET)
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#define OMV_DMA_REGION_SIZE MPU_REGION_SIZE_32KB
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/* SCCB/I2C */
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#define SCCB_I2C (I2C3)
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#define SCCB_AF (GPIO_AF4_I2C3)
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#define SCCB_CLK_ENABLE() __I2C3_CLK_ENABLE()
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#define SCCB_CLK_DISABLE() __I2C3_CLK_DISABLE()
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#define SCCB_PORT (GPIOH)
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#define SCCB_SCL_PIN (GPIO_PIN_7)
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#define SCCB_SDA_PIN (GPIO_PIN_8)
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#define SCCB_TIMING (I2C_TIMING_STANDARD)
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#define SCCB_FORCE_RESET() __HAL_RCC_I2C3_FORCE_RESET()
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#define SCCB_RELEASE_RESET() __HAL_RCC_I2C3_RELEASE_RESET()
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/* FIR I2C */
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// TODO which I2C can be used for external sensors ?
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#define FIR_I2C (I2C2)
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#define FIR_I2C_AF (GPIO_AF4_I2C2)
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#define FIR_I2C_CLK_ENABLE() __I2C2_CLK_ENABLE()
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#define FIR_I2C_CLK_DISABLE() __I2C2_CLK_DISABLE()
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#define FIR_I2C_PORT (GPIOB)
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#define FIR_I2C_SCL_PIN (GPIO_PIN_10)
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#define FIR_I2C_SDA_PIN (GPIO_PIN_11)
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#define FIR_I2C_TIMING (I2C_TIMING_FULL)
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#define FIR_I2C_FORCE_RESET() __HAL_RCC_I2C2_FORCE_RESET()
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#define FIR_I2C_RELEASE_RESET() __HAL_RCC_I2C2_RELEASE_RESET()
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#define DCMI_PWDN_PIN (GPIO_PIN_13)
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#define DCMI_PWDN_PORT (GPIOC)
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/* DCMI */
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#define DCMI_TIM (TIM1)
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#define DCMI_TIM_PIN (GPIO_PIN_1)
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#define DCMI_TIM_PORT (GPIOK)
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#define DCMI_TIM_AF (GPIO_AF1_TIM1)
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#define DCMI_TIM_CHANNEL (TIM_CHANNEL_1)
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#define DCMI_TIM_CLK_ENABLE() __TIM1_CLK_ENABLE()
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#define DCMI_TIM_CLK_DISABLE() __TIM1_CLK_DISABLE()
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#define DCMI_TIM_PCLK_FREQ() HAL_RCC_GetPCLK2Freq()
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#define DCMI_D0_PIN (GPIO_PIN_9)
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#define DCMI_D1_PIN (GPIO_PIN_10)
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#define DCMI_D2_PIN (GPIO_PIN_11)
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#define DCMI_D3_PIN (GPIO_PIN_12)
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#define DCMI_D4_PIN (GPIO_PIN_14)
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#define DCMI_D5_PIN (GPIO_PIN_4)
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#define DCMI_D6_PIN (GPIO_PIN_6)
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#define DCMI_D7_PIN (GPIO_PIN_7)
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#define DCMI_D0_PORT (GPIOH)
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#define DCMI_D1_PORT (GPIOH)
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#define DCMI_D2_PORT (GPIOH)
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#define DCMI_D3_PORT (GPIOH)
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#define DCMI_D4_PORT (GPIOH)
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#define DCMI_D5_PORT (GPIOI)
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#define DCMI_D6_PORT (GPIOI)
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#define DCMI_D7_PORT (GPIOI)
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#define DCMI_HSYNC_PIN (GPIO_PIN_4)
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#define DCMI_VSYNC_PIN (GPIO_PIN_5)
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#define DCMI_PXCLK_PIN (GPIO_PIN_6)
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#define DCMI_HSYNC_PORT (GPIOA)
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#define DCMI_VSYNC_PORT (GPIOI)
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#define DCMI_PXCLK_PORT (GPIOA)
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#if defined(DCMI_RESET_PIN)
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#define DCMI_RESET_LOW() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_RESET)
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#define DCMI_RESET_HIGH() HAL_GPIO_WritePin(DCMI_RESET_PORT, DCMI_RESET_PIN, GPIO_PIN_SET)
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#else
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#define DCMI_RESET_LOW()
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#define DCMI_RESET_HIGH()
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#endif
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#if defined(DCMI_PWDN_PIN)
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#define DCMI_PWDN_LOW() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_SET)
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#define DCMI_PWDN_HIGH() HAL_GPIO_WritePin(DCMI_PWDN_PORT, DCMI_PWDN_PIN, GPIO_PIN_RESET)
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#else
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#define DCMI_PWDN_LOW()
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#define DCMI_PWDN_HIGH()
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#endif
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#define DCMI_VSYNC_IRQN EXTI9_5_IRQn
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#define DCMI_VSYNC_IRQ_LINE (7)
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#define SOFT_I2C_PORT GPIOB
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#define SOFT_I2C_SIOC_PIN GPIO_PIN_10
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#define SOFT_I2C_SIOD_PIN GPIO_PIN_11
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#define SOFT_I2C_SIOC_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_SIOC_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOC_PIN, GPIO_PIN_RESET)
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#define SOFT_I2C_SIOD_H() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_SET)
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#define SOFT_I2C_SIOD_L() HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, GPIO_PIN_RESET)
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#define SOFT_I2C_SIOD_READ() HAL_GPIO_ReadPin (SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN)
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#define SOFT_I2C_SIOD_WRITE(bit) HAL_GPIO_WritePin(SOFT_I2C_PORT, SOFT_I2C_SIOD_PIN, bit);
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#define SOFT_I2C_SPIN_DELAY 64
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// Enable additional GPIO banks for DRAM...
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#define OMV_ENABLE_GPIO_BANK_F
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#define OMV_ENABLE_GPIO_BANK_G
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#define OMV_ENABLE_GPIO_BANK_H
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#define OMV_ENABLE_GPIO_BANK_I
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#define OMV_ENABLE_GPIO_BANK_J
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#endif //__OMV_BOARDCONFIG_H__
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