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139 lines
3.8 KiB
C
139 lines
3.8 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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#ifndef ANALOG_CONFIG_H_
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#define ANALOG_CONFIG_H_
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#include "peripheral_types.h"
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#define VBAT_ANA_REG2_VAL 0x00C00000 /* Enable analog peripheral LDO and precision bandgap */
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/* Used to scale the input reference to the DAC6 with a step size of 1/16.
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* Ex: DAC6_VREF_SCALE has a value of 0x5, then
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* Scaling factor = Register value/16 => 0x5/16 => 0.3125
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* which means input reference to the DAC6 is scaled by a factor of 5/16 */
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#define DAC6_VREF_SCALE (0x1U << 27)
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/* Output of DAC6 programmable reference voltage.
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* DAC6 Output = (DAC6_VREF_SCALE × DAC6_CONT) / 64 */
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#define DAC6_CONT (0x20U << 21)
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#define DAC6_EN (0x1U << 20) /* Enable the DAC6 */
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/* Used select different voltage reference values for a DAC12
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* 000: 0.500 (or 500 mv)
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001: 0.667 (or 667 mV)
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010: 0.667 (or 667 mV)
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011: 0.750 (or 750 mV)
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100: 0.750 (or 750 mV)
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101: 0.800 (or 800 mV)
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110: 0.800 (or 800 mV)
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111: 0.833 (or 833 mV)
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*/
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#define DAC12_VREF_CONT (0x4U << 17)
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/* 0x0: Vref = 1.8 V
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0x1: Vref = 1.5 V
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*/
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#define ADC_VREF_BUF_RDIV_EN (0x0U << 16)
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/* 0x0: ADC Vref is off
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0x1: ADC Vref is on
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*/
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#define ADC_VREF_BUF_EN (0x1U << 15)
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/* Control the ADC Vref: 1.8 V ± 100 mV, where:
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00000: -100 mV
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00001: -93 mV
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00010: -86 mV
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...
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11110: 93 mV
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11111: 100 mV
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10000: 1.8 V = Default (0x10)
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Step size = 7 mV
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*/
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#define ADC_VREF_CONT (0x10U << 10)
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/* Analog peripheral LDO (LDO-5) output voltage (VDD_ANA):
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0000: 1.6 V
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0001: 1.62 V
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...
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1010: 1.8 V
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1111: 1.9 V
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Step: 20 mV Default (0xA)
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*/
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#define ANA_PERIPH_LDO_CONT (0xAU << 6)
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/* Calibration for analog peripherals precision bandgap:
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0000: 1.140 V
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...
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1010: 1.2 V
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1111: 1.233 V
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Step: 6 mV Default (0xA)
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*/
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#define ANA_PERIPH_BG_CONT (0xAU << 1)
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#define CMP_REG2_VAL (DAC6_VREF_SCALE | DAC6_CONT | DAC6_EN | \
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DAC12_VREF_CONT | ADC_VREF_BUF_RDIV_EN | \
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ADC_VREF_BUF_EN | ADC_VREF_CONT | \
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ANA_PERIPH_LDO_CONT | ANA_PERIPH_BG_CONT)
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#define CMP_REG2_BASE (CMP0_BASE + 0x00000004) /* CMP register2 base address */
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/**
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@fn void analog_config_vbat_reg2(void)
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@brief Assigning Vbat registers values to the Vbat register2 base address
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@param[in] none
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@return none
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*/
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static inline void analog_config_vbat_reg2(void)
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{
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/* Analog configuration Vbat register2 */
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ANA_REG->VBAT_ANA_REG2 |= VBAT_ANA_REG2_VAL;
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}
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/**
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@fn void analog_config_cmp_reg2(void)
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@brief Assigning comparator register2 values to the comparator
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register2 base address
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@param[in] none
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@return none
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*/
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static inline void analog_config_cmp_reg2(void)
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{
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/* Analog configuration comparator register2 */
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*((volatile uint32_t *)CMP_REG2_BASE) = CMP_REG2_VAL;
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}
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/**
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\fn static inline void enable_cmp_periph_clk(void)
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\brief Enable CMP Control register.
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\param none.
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\return none.
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*/
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static inline void enable_cmp_periph_clk(void)
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{
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CLKCTL_PER_SLV->CMP_CTRL |= CMP_CTRL_CMP0_CLKEN;
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}
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/**
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\fn static inline void disable_cmp_periph_clk(void)
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\brief Disable CMP Control register.
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\param none.
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\return none.
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*/
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static inline void disable_cmp_periph_clk(void)
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{
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CLKCTL_PER_SLV->CMP_CTRL &= ~CMP_CTRL_CMP0_CLKEN;
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}
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#endif /* ANALOG_CONFIG_H_ */
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