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166 lines
8.1 KiB
C
166 lines
8.1 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/******************************************************************************
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* @file pm_internal.h
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* @author Raj Ranjan
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* @email raj.ranjan@alifsemi.com
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* @version V1.0.0
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* @date 19-Apr-2023
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* @brief Power Management Services API
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* @bug None.
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* @Note None
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******************************************************************************/
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#ifndef PM_INTERNAL_H_
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#define PM_INTERNAL_H_
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/* Includes ------------------------------------------------------------------*/
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Coprocessor Power Control Register Definitions */
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#define ICB_CPPWR_SU11_Pos 22U /*!< CPPWR: State Unknown 11 Position */
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#define ICB_CPPWR_SU11_Msk (0x1UL << ICB_CPPWR_SU11_Pos) /*!< CPPWR: State Unknown 11 Mask */
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#define ICB_CPPWR_SU10_Pos 20U /*!< CPPWR: State Unknown 10 Position */
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#define ICB_CPPWR_SU10_Msk (0x1UL << ICB_CPPWR_SU10_Pos) /*!< CPPWR: State Unknown 10 Mask */
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/**
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\ingroup CMSIS_core_register
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\defgroup EWIC_Type External Wakeup Interrupt Controller Registers
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\brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC)
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@{
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*/
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/**
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@brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC).
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*/
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typedef struct
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{
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__IOM uint32_t EWIC_CR; /*!< Offset: 0x000 (R/W) EWIC Control Register */
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__IOM uint32_t EWIC_ASCR; /*!< Offset: 0x004 (R/W) EWIC Automatic Sequence Control Register */
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__OM uint32_t EWIC_CLRMASK; /*!< Offset: 0x008 ( /W) EWIC Clear Mask Register */
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__IM uint32_t EWIC_NUMID; /*!< Offset: 0x00C (R/ ) EWIC Event Number ID Register */
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uint32_t RESERVED0[124U];
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__IOM uint32_t EWIC_MASKA; /*!< Offset: 0x200 (R/W) EWIC MaskA Register */
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__IOM uint32_t EWIC_MASKn[15]; /*!< Offset: 0x204 (R/W) EWIC Maskn Registers */
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uint32_t RESERVED1[112U];
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__IM uint32_t EWIC_PENDA; /*!< Offset: 0x400 (R/ ) EWIC PendA Event Register */
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__IOM uint32_t EWIC_PENDn[15]; /*!< Offset: 0x404 (R/W) EWIC Pendn Event Registers */
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uint32_t RESERVED2[112U];
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__IM uint32_t EWIC_PSR; /*!< Offset: 0x600 (R/ ) EWIC Pend Summary Register */
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} _EWIC_Type;
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/* EWIC Control (EWIC_CR) Register Definitions */
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#define EWIC_EWIC_CR_EN_Pos 0U /*!< EWIC EWIC_CR: EN Position */
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#define EWIC_EWIC_CR_EN_Msk (0x1UL /*<< EWIC_EWIC_CR_EN_Pos*/) /*!< EWIC EWIC_CR: EN Mask */
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/* EWIC Automatic Sequence Control (EWIC_ASCR) Register Definitions */
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#define EWIC_EWIC_ASCR_ASPU_Pos 1U /*!< EWIC EWIC_ASCR: ASPU Position */
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#define EWIC_EWIC_ASCR_ASPU_Msk (0x1UL << EWIC_EWIC_ASCR_ASPU_Pos) /*!< EWIC EWIC_ASCR: ASPU Mask */
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#define EWIC_EWIC_ASCR_ASPD_Pos 0U /*!< EWIC EWIC_ASCR: ASPD Position */
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#define EWIC_EWIC_ASCR_ASPD_Msk (0x1UL /*<< EWIC_EWIC_ASCR_ASPD_Pos*/) /*!< EWIC EWIC_ASCR: ASPD Mask */
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/* EWIC Event Number ID (EWIC_NUMID) Register Definitions */
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#define EWIC_EWIC_NUMID_NUMEVENT_Pos 0U /*!< EWIC_NUMID: NUMEVENT Position */
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#define EWIC_EWIC_NUMID_NUMEVENT_Msk (0xFFFFUL /*<< EWIC_EWIC_NUMID_NUMEVENT_Pos*/) /*!< EWIC_NUMID: NUMEVENT Mask */
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/* EWIC Mask A (EWIC_MASKA) Register Definitions */
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#define EWIC_EWIC_MASKA_EDBGREQ_Pos 2U /*!< EWIC EWIC_MASKA: EDBGREQ Position */
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#define EWIC_EWIC_MASKA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_MASKA_EDBGREQ_Pos) /*!< EWIC EWIC_MASKA: EDBGREQ Mask */
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#define EWIC_EWIC_MASKA_NMI_Pos 1U /*!< EWIC EWIC_MASKA: NMI Position */
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#define EWIC_EWIC_MASKA_NMI_Msk (0x1UL << EWIC_EWIC_MASKA_NMI_Pos) /*!< EWIC EWIC_MASKA: NMI Mask */
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#define EWIC_EWIC_MASKA_EVENT_Pos 0U /*!< EWIC EWIC_MASKA: EVENT Position */
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#define EWIC_EWIC_MASKA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_MASKA_EVENT_Pos*/) /*!< EWIC EWIC_MASKA: EVENT Mask */
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/* EWIC Mask n (EWIC_MASKn) Register Definitions */
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#define EWIC_EWIC_MASKn_IRQ_Pos 0U /*!< EWIC EWIC_MASKn: IRQ Position */
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#define EWIC_EWIC_MASKn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_MASKn_IRQ_Pos*/) /*!< EWIC EWIC_MASKn: IRQ Mask */
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/* EWIC Pend A (EWIC_PENDA) Register Definitions */
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#define EWIC_EWIC_PENDA_EDBGREQ_Pos 2U /*!< EWIC EWIC_PENDA: EDBGREQ Position */
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#define EWIC_EWIC_PENDA_EDBGREQ_Msk (0x1UL << EWIC_EWIC_PENDA_EDBGREQ_Pos) /*!< EWIC EWIC_PENDA: EDBGREQ Mask */
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#define EWIC_EWIC_PENDA_NMI_Pos 1U /*!< EWIC EWIC_PENDA: NMI Position */
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#define EWIC_EWIC_PENDA_NMI_Msk (0x1UL << EWIC_EWIC_PENDA_NMI_Pos) /*!< EWIC EWIC_PENDA: NMI Mask */
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#define EWIC_EWIC_PENDA_EVENT_Pos 0U /*!< EWIC EWIC_PENDA: EVENT Position */
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#define EWIC_EWIC_PENDA_EVENT_Msk (0x1UL /*<< EWIC_EWIC_PENDA_EVENT_Pos*/) /*!< EWIC EWIC_PENDA: EVENT Mask */
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/* EWIC Pend n (EWIC_PENDn) Register Definitions */
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#define EWIC_EWIC_PENDn_IRQ_Pos 0U /*!< EWIC EWIC_PENDn: IRQ Position */
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#define EWIC_EWIC_PENDn_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EWIC_PENDn_IRQ_Pos*/) /*!< EWIC EWIC_PENDn: IRQ Mask */
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/* EWIC Pend Summary (EWIC_PSR) Register Definitions */
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#define EWIC_EWIC_PSR_NZ_Pos 1U /*!< EWIC EWIC_PSR: NZ Position */
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#define EWIC_EWIC_PSR_NZ_Msk (0x7FFFUL << EWIC_EWIC_PSR_NZ_Pos) /*!< EWIC EWIC_PSR: NZ Mask */
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#define EWIC_EWIC_PSR_NZA_Pos 0U /*!< EWIC EWIC_PSR: NZA Position */
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#define EWIC_EWIC_PSR_NZA_Msk (0x1UL /*<< EWIC_EWIC_PSR_NZA_Pos*/) /*!< EWIC EWIC_PSR: NZA Mask */
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/*@}*/ /* end of group EWIC_Type */
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/**
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@brief WakeUp Interrupt Controller(WIC) Type:-
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*/
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typedef enum _PM_WIC
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{
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PM_WIC_IS_EWIC, /*!< WIC used is EWIC */
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PM_WIC_IS_IWIC , /*!< WIC used is IWIC */
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} PM_WIC;
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/**
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@brief enum Low power state:-
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*/
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typedef enum _PM_LPSTATE
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{
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PM_LPSTATE_ON, /*!< ON */
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PM_LPSTATE_ON_CLK_OFF , /*!< ON, clock is off */
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PM_LPSTATE_RET, /*!< Not supported */
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PM_LPSTATE_OFF /*!< OFF */
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} PM_LPSTATE;
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/* Same address for both RTSS */
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/* Cold_Wakeup bit in external system 0/1 */
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/*!< EXTSYS0/1 : bit 0 (architecture dependent) */
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#define COLD_WAKEUP_Pos (0U)
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#define COLD_WAKEUP_Msk (1U << COLD_WAKEUP_Pos)
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/* WIC bit positions in WICCONTROL */
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/*!< WICCONTROL: bit 8 (architecture dependent) */
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#define WICCONTROL_WIC_Pos (8U)
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#define WICCONTROL_WIC_Msk (1U << WICCONTROL_WIC_Pos)
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/* IWIC bit positions in WICCONTROL */
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/*!< WICCONTROL: bit 9 (architecture dependent)*/
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#define WICCONTROL_IWIC_Pos (9U)
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#define WICCONTROL_IWIC_Msk (1U << WICCONTROL_IWIC_Pos)
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/*!< External Wakeup Interrupt Controller Base Address */
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#define _EWIC_BASE (0xE0047000UL)
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/*!< EWIC configuration struct */
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#define _EWIC ((_EWIC_Type *) _EWIC_BASE )
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#ifdef __cplusplus
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}
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#endif
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#endif /* POWER_MANAGEMENT_INTERNAL_H_ */
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