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252 lines
7.9 KiB
C
252 lines
7.9 KiB
C
/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/*
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* Copyright (c) 2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file system_M55.c
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* @author Rupesh Kumar
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* @email rupesh@alifsemi.com
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* @brief CMSIS Device System Source File for
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* Alif Semiconductor M55_HP / M55_HE Device
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* @version V1.0.0
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* @date 23. Feb 2021
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* @bug None
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* @Note None
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******************************************************************************/
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#if defined (M55_HP)
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#include "M55_HP.h"
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#include "M55_HP_Config.h"
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#elif defined (M55_HE)
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#include "M55_HE.h"
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#include "M55_HE_Config.h"
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#else
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#error device not specified!
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#endif
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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#if defined (M55_HP)
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#include "partition_M55_HP.h"
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#elif defined (M55_HE)
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#include "partition_M55_HE.h"
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#endif
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#endif
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#include "tcm_partition.h"
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#include "tgu_M55.h"
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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#include <mpu_M55.h>
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#endif
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#include "app_map.h"
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define MHZ ( 1000000UL)
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#if defined (M55_HP)
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#define SYSTEM_CLOCK (400U * MHZ)
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#elif defined (M55_HE)
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#define SYSTEM_CLOCK (160U * MHZ)
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#endif
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/*----------------------------------------------------------------------------
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WICCONTROL register
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*----------------------------------------------------------------------------*/
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/* WIC bit positions in WICCONTROL */
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#define WICCONTROL_WIC_Pos (8U)
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#define WICCONTROL_WIC_Msk (1U << WICCONTROL_WIC_Pos)
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#if defined(M55_HP)
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#define WICCONTROL (AON->RTSS_HP_CTRL)
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#elif defined(M55_HE)
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#define WICCONTROL (AON->RTSS_HE_CTRL)
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#endif
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/*----------------------------------------------------------------------------
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Exception / Interrupt Vector table
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*----------------------------------------------------------------------------*/
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extern const VECTOR_TABLE_Type __VECTOR_TABLE[496];
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/*----------------------------------------------------------------------------
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System Core Clock Variable
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = SYSTEM_CLOCK;
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/*----------------------------------------------------------------------------
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System Core Clock update function
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void)
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{
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SystemCoreClock = SYSTEM_CLOCK;
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}
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/*----------------------------------------------------------------------------
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Get System Core Clock function
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*----------------------------------------------------------------------------*/
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uint32_t GetSystemCoreClock (void)
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{
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return SystemCoreClock;
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}
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/*----------------------------------------------------------------------------
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Default Handler for Spurious wakeup
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*----------------------------------------------------------------------------*/
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__attribute__ ((weak))
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void System_HandleSpuriousWakeup (void)
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{
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/*
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* pm.c has the implementation to handle the spurious wakeup.
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* User may override and can have their own implementation.
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*/
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}
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/* This hook is called automatically by the ARM C library after scatter loading */
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/* We add it to the preinit table for GCC */
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void _platform_pre_stackheap_init(void)
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{
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/* Synchronise the caches for any copied code */
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if (!(MEMSYSCTL->MSCR & MEMSYSCTL_MSCR_DCCLEAN_Msk))
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{
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SCB_CleanDCache();
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}
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SCB_InvalidateICache();
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/* Enable the Counter module for busy loops */
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sys_busy_loop_init();
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}
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#if !defined(__ARMCC_VERSION)
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void (*_do_platform_pre_stackheap_init)() __attribute__((section(".preinit_array"))) = _platform_pre_stackheap_init;
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#endif
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/*----------------------------------------------------------------------------
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System initialization function
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*----------------------------------------------------------------------------*/
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void SystemInit (void)
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{
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// Avoid DSB as long as possible, as it will block until cache
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// auto-invalidation has completed. First DSB is currently at the
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// end of MPU_Setup.
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#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
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SCB->VTOR = (uint32_t) __VECTOR_TABLE;
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#endif
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/* Enable UsageFault, BusFault, MemFault and SecurityFault exceptions */
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/* Otherwise all you see is HardFault, even in the debugger */
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SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk |
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SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_SECUREFAULTENA_Msk;
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/*
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* Handle Spurious Wakeup
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*/
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System_HandleSpuriousWakeup();
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/* Clear the WIC Sleep */
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WICCONTROL &= ~WICCONTROL_WIC_Msk;
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#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \
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(defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U))
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SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
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(3U << 11U*2U) ); /* enable CP11 Full Access */
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#endif
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#ifdef UNALIGNED_SUPPORT_DISABLE
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SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
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#endif
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/*
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* Prefetch Control
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*
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* By Reset, the Prefetch is enabled with the below values,
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* MAX_LA = 6
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* MIN_LA = 2
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* MAX_OS = 2
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*
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* Here we modify only the MAX_OS based on the performance achieved in our
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* trials.
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*
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*/
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MEMSYSCTL->PFCR = (MEMSYSCTL_PFCR_MAX_OS_DEFAULT_VALUE << MEMSYSCTL_PFCR_MAX_OS_Pos) |
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(MEMSYSCTL_PFCR_MAX_LA_DEFAULT_VALUE << MEMSYSCTL_PFCR_MAX_LA_Pos) |
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(MEMSYSCTL_PFCR_MIN_LA_DEFAULT_VALUE << MEMSYSCTL_PFCR_MIN_LA_Pos) |
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MEMSYSCTL_PFCR_ENABLE_Msk;
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#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
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/*
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* Do not do MPU_Setup() if running from the OSPI XIP regions as MPU_Setup() temporarily
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* disables the MPU which causes the default Device/XN attributes to take effect for the
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* OSPI XIP regions.
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*/
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#if !BOOT_FROM_OSPI_FLASH
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MPU_Setup();
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#endif
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#endif
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// Enable caches now, for speed, but we will have to clean
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// after scatter-loading, in _platform_pre_stackheap_init
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// We do not use the CMSIS functions, as these manually invalidate the
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// cache - this is not required on the M55, as it is auto-invalidated
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// (and we implicitly rely on this already before activating, if booting
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// from MRAM).
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// Enable Loop and branch info cache
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SCB->CCR |= SCB_CCR_IC_Msk | SCB_CCR_DC_Msk | SCB_CCR_LOB_Msk;
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// Enable limited static branch prediction using low overhead loops
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ICB->ACTLR &= ~ICB_ACTLR_DISLOBR_Msk;
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__DSB();
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__ISB();
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#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
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TZ_SAU_Setup();
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TGU_Setup();
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#else
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setup_tcm_ns_partition();
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#endif
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SystemCoreClock = SYSTEM_CLOCK;
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/* Add a feature to bypass the clock gating in the EXPMST0.
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*
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* Note: This will be removed in the future release
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*/
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#define FORCE_ENABLE_SYSTEM_CLOCKS 1
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#if FORCE_ENABLE_SYSTEM_CLOCKS
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/* Bypass clock gating */
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enable_force_peripheral_functional_clk();
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/* Bypass clock gating */
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enable_force_apb_interface_clk();
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#endif
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}
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