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89 lines
3.9 KiB
C
89 lines
3.9 KiB
C
/* Copyright (C) 2024 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file tcm_partition.c
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* @author Sudhir Sreedharan
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* @email sudhir@alifsemi.com
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* @version V1.0.0
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* @date 06-August-2024
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* @brief TCM paritioning to non-secure by configuring the SAU and TGU
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*
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* This routine will be used only for partitioning the TCM for the
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* non-secure only when the CMSE feature is not enabled.
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* If complete trustzone is going to be used, please do the
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* modifications in the respective partition_* header file.
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* @bug None.
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******************************************************************************/
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/* Includes ------------------------------------------------------------------*/
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#if defined (M55_HP)
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#include "M55_HP.h"
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#elif defined (M55_HE)
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#include "M55_HE.h"
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#else
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#error device not specified!
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#endif
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#include "tcm_partition.h"
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#include "tgu_M55.h"
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#if !(defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U))
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typedef struct
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{
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__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
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__IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
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__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
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__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
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__IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
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__IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
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__IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
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} SAU_Type;
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#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
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#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
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/* SAU Region Base Address Register Definitions */
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#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
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#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
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/* SAU Region Limit Address Register Definitions */
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#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
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#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
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#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
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#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
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#define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
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#define SAU ((SAU_Type *) SAU_BASE) /*!< Security Attribution Unit */
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__STATIC_INLINE void SAU_TCM_NS_Setup (void)
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{
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SAU->RNR = 0;
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SAU->RBAR = (uint32_t)&ns_region_0_start & SAU_RBAR_BADDR_Msk;
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SAU->RLAR = (((uint32_t)&ns_region_0_end - 1) & SAU_RLAR_LADDR_Msk) | \
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SAU_RLAR_ENABLE_Msk;
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SAU->CTRL = ((1U << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk);
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}
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void setup_tcm_ns_partition (void)
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{
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/* Do nothing if partitions are not defined in the linker script */
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if (&ns_region_0_end == &ns_region_0_start)
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return;
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SAU_TCM_NS_Setup();
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TGU_Setup();
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}
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#endif /* __ARM_FEATURE_CMSE */ |