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482 lines
22 KiB
C
482 lines
22 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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#ifndef ADC_H_
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#define ADC_H_
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#include <stdint.h>
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#include <stdbool.h>
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typedef struct {
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volatile uint32_t ADC_START_SRC; /*!< (@ 0x00000000) ADC Start-of-Conversion Source Register */
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volatile uint32_t ADC_COMP_THRESH_A; /*!< (@ 0x00000004) ADC Comparator Threshold A Register */
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volatile uint32_t ADC_COMP_THRESH_B; /*!< (@ 0x00000008) ADC Comparator Threshold B Register */
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volatile uint32_t ADC_CLK_DIVISOR; /*!< (@ 0x0000000C) ADC Clock Divider Value Register */
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volatile uint32_t ADC_INTERRUPT; /*!< (@ 0x00000010) ADC Interrupt Status and Clear Register */
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volatile uint32_t ADC_INTERRUPT_MASK; /*!< (@ 0x00000014) ADC Interrupt Mask Register */
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volatile uint32_t ADC_SAMPLE_WIDTH; /*!< (@ 0x00000018) ADC Sampling Signal Duration Register */
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volatile const uint32_t RESERVED;
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volatile uint32_t ADC_AVG_NUM; /*!< (@ 0x00000020) ADC Number of Samples for Averaging Register */
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volatile uint32_t ADC_SHIFT_CONTROL; /*!< (@ 0x00000024) ADC Data Shift Select Register */
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volatile const uint32_t RESERVED1[2];
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volatile uint32_t ADC_CONTROL; /*!< (@ 0x00000030) ADC Single-shot Conversion Start and Comparator
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Threshold Mode Register */
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volatile uint32_t ADC_SEQUENCER_CTRL; /*!< (@ 0x00000034) ADC Sequencer Control Register */
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volatile uint32_t ADC_REG1; /*!< (@ 0x00000038) ADC Analog Control Register for ADC12 Modules */
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volatile const uint32_t ADC_SEL; /*!< (@ 0x0000003C) ADC Sample Register Selected (read-only value of n) */
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volatile const uint32_t RESERVED2[4];
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volatile uint32_t ADC_SAMPLE_REG_[9]; /*!< (@ 0x00000050) ADC Sampled Value From Input n Register */
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} ADC_Type; /*!< Size = 116 (0x74) */
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/****ADC Register macros****/
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#define ADC_START_CONTINUOUS_CONV (1U << 6) /* start continuous conversion */
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#define ADC_START_ENABLE (1U << 7) /* Enable ENA for single shot conversion */
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#define ADC_START_SINGLE_SHOT_CONV (1U << 0) /* start single shot conversion */
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#define ADC_SHIFT_CTRL_RIGHT_OR_LEFT (1U << 16) /* Enable the right or left shift */
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#define ADC_SEQUENCER_CTRL_FIXED_OR_ROTATE (1U << 16) /* Enable to select particular scan mode */
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/****ADC Differential macros****/
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#define ADC_DIFFERENTIAL_ENABLE (0X01) /* Enable differential mode */
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#define ADC_MAX_DIFFERENTIAL_CHANNEL (0X03) /* Max differential input channel */
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/****ADC24 Differential macros****/
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#define ADC24_MAX_DIFFERENTIAL_CHANNEL (0x04) /* ADC24 Max differential input channel */
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/****ADC24 sample width macros****/
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#define ADC24_SAMPLE_HOLD_ENABLE_Pos (16) /* ADC24 enable sample hold bit */
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#define ADC12_SAMPLE_WIDTH_Msk (0XFFFF) /* ADC sample width mask */
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/****ADC Differential mask macros****/
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#define ADC120_DIFFERENTIAL_ENABLE (1UL << 1) /* ADC instance 0 differential enable position */
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#define ADC121_DIFFERENTIAL_ENABLE (1UL << 7) /* ADC instance 1 differential enable position */
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#define ADC122_DIFFERENTIAL_ENABLE (1UL << 13) /* ADC instance 2 differential enable position */
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#define ADC_DIFFERENTIAL_ENABLE_MSK (ADC120_DIFFERENTIAL_ENABLE |\
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ADC121_DIFFERENTIAL_ENABLE |\
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ADC122_DIFFERENTIAL_ENABLE)
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/* ADC external trigger mask macro */
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#define ADC_EXTERNAL_TRIGGER_MAX_VAL (0x3F) /* ADC External trigger max value */
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/********Interrupt mask macro*******/
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#define ADC_INTR_CMPA_POS (2) /* Interrupt comparator A mask position */
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#define ADC_INTR_CMPA_MSK (1 << ADC_INTR_CMPA_POS) /* Interrupt comparator A mask */
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#define ADC_INTR_CMPB_POS (3) /* Interrupt comparator B mask position */
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#define ADC_INTR_CMPB_MSK (1 << ADC_INTR_CMPB_POS) /* Interrupt comparator B mask */
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#define ADC_THRSHLD_CMP_MASK_BIT_POS (16) /* Comparator threshold mask bit position */
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#define ADC_THRSHLD_CMP_MASK_BIT (0x03 << ADC_THRSHLD_CMP_MASK_BIT_POS) /* Comparator threshold mask bit */
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/****Interrupt clear macros****/
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#define ADC_INTR_DONE0_CLEAR (0x01) /* Interrupt done0 clear bit */
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#define ADC_INTR_DONE1_CLEAR (0x02) /* Interrupt done1 clear bit */
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#define ADC_INTR_COMPA_CLEAR (0x04) /* Interrupt compA clear bit */
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#define ADC_INTR_COMPB_CLEAR (0x08) /* Interrupt compB clear bit */
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/****Comparator Macros****/
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#define ADC_CMP_THRHLD_ABOVE_A 0 /* ADC comparator threshold above A */
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#define ADC_CMP_THRHLD_BELOW_A 1 /* ADC comparator threshold below A */
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#define ADC_CMP_THRHLD_BETWEEN_A_B 2 /* ADC comparator threshold between a_b */
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#define ADC_CMP_THRHLD_ABOVE_B 0 /* ADC comparator threshold above B */
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#define ADC_CMP_THRHLD_BELOW_B 1 /* ADC comparator threshold above B */
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#define ADC_CMP_THRHLD_OUTSIDE_A_B 2 /* ADC comparator threshold outside A_B */
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/****channels Macros****/
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#define ADC_LAST_AVAILABLE_CHANNEL 8 /* ADC last available channels */
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/****limit Macros****/
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#define ADC_CLOCK_DIV_MIN_VALUE 2 /* ADC Clock divisor minimum value */
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#define ADC_CLOCK_DIV_MAX_VALUE 16 /* ADC Clock divisor maximum value */
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#define ADC_AVG_SAMPLES_FOR_AVG_MIN 2 /* ADC Average sample for Avergae minimum */
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#define ADC_AVG_SAMPLES_FOR_AVG_MAX 256 /* ADC Average sample for Avergae maximum */
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#define ADC_24_BIAS_MAX_VALUE 4 /* ADC24 bias max input value */
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#define ADC_24_OUPUT_RATE_MAX_VALUE 4 /* ADC24 output rate max input value */
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#define ADC_SAMPLE_WIDTH_MIN_VALUE 2 /* ADC sample width minimum value */
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#define ADC_SAMPLE_WIDTH_MAX_VALUE 32 /* ADC sample width maximum value */
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#define ADC_24_SAMPLE_WIDTH_MAX_VALUE 65536 /* ADC24 sample hold 16th bit */
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#define ADC_PGA_GAIN_MAX_VALUE 7 /* ADC pga gain max input value */
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/****Shift bit macro****/
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#define ADC_SHIFT_BIT 16 /* Shift bit */
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#define ADC_SEQUENCER_INIT_Pos 12 /* Initial shift bit position */
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/****Sequencer Macros****/
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#define ADC_SEQUENCER_MSK_BIT (0x01) /* Sequencer mask bit */
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#define ADC_MAX_INIT_CHANNEL (0X100) /* Initial max channel */
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#define ADC_MSK_INIT_CHANNEL (0X0F) /* Initial mask channel */
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#define ADC_MSK_ALL_CHANNELS (0X1FF) /* Masking all channel */
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/****Interrupt****/
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#define ADC_INT_AVG_SAMPLE_RDY (1U) /* Interrupt for average sample ready */
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#define ADC_INT_AVG_SAMPLE_TAKEN (2U) /* Interrupt for all sample taken */
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/**
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* enum _ADC_SCAN_MODE.
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* Set the scan mode for ADC conversion.
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*/
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typedef enum _ADC_SCAN_MODE{
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ADC_SCAN_MODE_MULTI_CH, /* ADC SCAN MODE MULTIPLE CHANNEL */
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ADC_SCAN_MODE_SINGLE_CH /* ADC SCAN MODE SINGLE CHANNEL */
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} ADC_SCAN_MODE;
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/**
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* enum ADC_CONV_MODE.
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* Set the conversion mode for ADC.
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*/
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typedef enum _ADC_CONV_MODE{
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ADC_CONV_MODE_CONTINUOUS, /* ADC CONVERSRION MODE CONTINUOUS */
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ADC_CONV_MODE_SINGLE_SHOT /* ADC CONVERSRION MODE SINGLE SHOT */
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}ADC_CONV_MODE;
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/**
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* enum ADC_CONV_STAT.
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* Status of an ongoing ADC conversion.
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*/
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typedef enum _ADC_CONV_STAT{
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ADC_CONV_STAT_NONE, /* ADC Conversion status none */
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ADC_CONV_STAT_COMPLETE = (1U << 0), /* ADC Conversion status complete */
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ADC_CONV_STAT_CMP_THLD_ABOVE_A = (1U << 1), /* ADC Conversion status comparator threshold above A */
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ADC_CONV_STAT_CMP_THLD_ABOVE_B = (1U << 2), /* ADC Conversion status comparator threshold above B */
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ADC_CONV_STAT_CMP_THLD_BELOW_A = (1U << 3), /* ADC Conversion status comparator threshold below A */
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ADC_CONV_STAT_CMP_THLD_BELOW_B = (1U << 4), /* ADC Conversion status comparator threshold below B */
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ADC_CONV_STAT_CMP_THLD_BETWEEN_A_B = (1U << 5), /* ADC Conversion status comparator threshold between A & B */
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ADC_CONV_STAT_CMP_THLD_OUTSIDE_A_B = (1U << 6), /* ADC Conversion status comparator threshold outside A & B */
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} ADC_CONV_STAT;
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/* Structure to store the conversion info */
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typedef struct conv_info{
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const uint32_t user_input; /* user channel input */
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volatile uint32_t sampled_value; /* Conversion value stored */
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volatile uint32_t curr_channel; /* conversion current channel */
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ADC_SCAN_MODE sequencer_ctrl_status; /* sequencer control status */
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volatile ADC_CONV_STAT status; /* Conversion status */
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volatile ADC_CONV_MODE mode; /* Conversion status control */
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volatile uint8_t read_channel; /* Store channel */
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}conv_info_t;
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/**
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* @fn : void adc_enable_single_shot_conv(ADC_Type *adc)
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* @brief : Enable the single shot conversion
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* @param[in] : adc : Pointer to the ADC register map
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* @return : none
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*/
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static inline void adc_enable_single_shot_conv(ADC_Type *adc)
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{
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adc->ADC_START_SRC |= ADC_START_ENABLE;
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adc->ADC_CONTROL |= ADC_START_SINGLE_SHOT_CONV;
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}
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/**
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* @fn : void adc_disable_single_shot_conv(ADC_Type *adc)
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* @brief : disable the single shot conversion
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* @param[in] : adc : Pointer to the ADC register map
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* @return : none
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*/
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static inline void adc_disable_single_shot_conv(ADC_Type *adc)
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{
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adc->ADC_START_SRC &= ~(ADC_START_ENABLE);
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adc->ADC_CONTROL &= ~ADC_START_SINGLE_SHOT_CONV;
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}
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/**
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* @fn : void adc_enable_continuous_conv(ADC_Type *adc)
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* @brief : Enable the continuous conversion
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* @param[in] : adc : Pointer to the ADC register map
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* @return : none
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*/
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static inline void adc_enable_continuous_conv(ADC_Type *adc)
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{
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adc->ADC_START_SRC |= ADC_START_CONTINUOUS_CONV;
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}
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/**
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* @fn : void adc_disable_continuous_conv(ADC_Type *adc)
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* @brief : Disable the continuous conversion
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* @param[in] : adc : Pointer to the ADC register map
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* @return : none
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*/
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static inline void adc_disable_continuous_conv(ADC_Type *adc)
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{
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adc->ADC_START_SRC &= ~ADC_START_CONTINUOUS_CONV;
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}
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/**
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* @fn : void adc_enable_external_trigger(ADC_Type *adc, uint8_t arg)
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* @brief : Enable external trigger from UTIMER and QEC
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* @param[in] : adc : Pointer to the ADC register map
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* @param[in] : arg : Enable trigger bit fields
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* @return : none
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*/
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static inline void adc_enable_external_trigger(ADC_Type *adc, uint8_t arg)
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{
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adc->ADC_START_SRC |= arg;
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}
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/**
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* @fn : void adc_disable_external_trigger(ADC_Type *adc)
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* @brief : Disable conversion from external trigger from UTIMER and QEC
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* @param[in] : adc : Pointer to the ADC register map
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* @param[in] : arg : Disable trigger bit fields
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* @return : none
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*/
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static inline void adc_disable_external_trigger(ADC_Type *adc, uint8_t arg)
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{
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adc->ADC_START_SRC &= ~arg;
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}
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/*
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* @func : void adc_init_channel_select(ADC_Type *adc, uint32_t arg)
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* @brief : control to select initial channel for storing sample value
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : arg : selecting initial channel
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* @return : ARM_DRIVER_OK : if driver initialized successfully
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* : ARM_DRIVER_ERROR_PARAMETER : if parameter is invalid or not
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*/
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static inline void adc_init_channel_select(ADC_Type *adc, uint32_t channel)
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{
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/* clearing the channels */
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adc->ADC_SEQUENCER_CTRL &= ~(ADC_MSK_INIT_CHANNEL << ADC_SEQUENCER_INIT_Pos);
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/* masking the channels */
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adc->ADC_SEQUENCER_CTRL |= (channel << ADC_SEQUENCER_INIT_Pos);
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}
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/*
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* @func : void adc_set_clock_divisor(ADC_Type *adc, uint32_t divisor)
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* @brief : Setting the value for the clock divisor and
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* clock value should be between 2 to 64
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : clock_value : value to set clock divisor
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* @return : NONE
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*/
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static inline void adc_set_clk_div(ADC_Type *adc, uint32_t divisor)
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{
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adc->ADC_CLK_DIVISOR = divisor;
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}
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/*
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* @func : void adc_set_avg_sample(ADC_Type *adc, uint32_t average)
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* @brief : Setting the average value, the value must be
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* up to 256 and value should be power of 2
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : average : value to set average number
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* @return : NONE
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*/
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static inline void adc_set_avg_sample(ADC_Type *adc, uint32_t average)
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{
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adc->ADC_AVG_NUM = average;
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}
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/*
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* @func : void adc_set_sample_width(ADC_Type *adc, uint32_t width)
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* @brief : Setting the sample width and value must be between
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* 2 to 32
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : width : value to set sample width
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* @return : NONE
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*/
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static inline void adc_set_sample_width(ADC_Type *adc, uint32_t width)
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{
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adc->ADC_SAMPLE_WIDTH = (adc->ADC_SAMPLE_WIDTH & ~ADC12_SAMPLE_WIDTH_Msk) | width;
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}
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/*
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* @func : void adc24_enable_continous_sample(ADC_Type *adc)
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* @brief : Set sample hold bit for adc24
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* @parameter[1] : adc : Pointer to the ADC register map
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* @return : NONE
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*/
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static inline void adc24_enable_continous_sample(ADC_Type *adc)
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{
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adc->ADC_SAMPLE_WIDTH = (1 << ADC24_SAMPLE_HOLD_ENABLE_Pos);
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}
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/*
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* @func : void adc_set_n_shift_bit(ADC_Type *adc,
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uint32_t shift_number,
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uint32_t shift_left_right_control)
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* @brief : Setting the number of shift to bit (as per user input)
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : shift number : number of bytes to shift
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* @parameter[3] : shift_left_right_control : enable shift control 0 for left
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* 1 for right
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* @return : NONE
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*/
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static inline void adc_set_n_shift_bit(ADC_Type *adc,
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uint32_t shift_number,
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uint32_t shift_left_right_control)
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{
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adc->ADC_SHIFT_CONTROL = (shift_number | shift_left_right_control << 16);
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}
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/*
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* @func : void adc_unmask_interrupt(ADC_Type *adc)
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* @brief : Enable the interrupts
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* @parameter[1] : adc : Pointer to the ADC register map
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* @return : NONE
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*/
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static inline void adc_unmask_interrupt(ADC_Type *adc)
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{
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adc->ADC_INTERRUPT_MASK = 0x0;
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}
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/*
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* @func : void adc_mask_interrupt(ADC_Type *adc)
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* @brief : Disable the interrupts
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* @parameter[1] : adc : Pointer to the ADC register map
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* @return : NONE
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*/
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static inline void adc_mask_interrupt(ADC_Type *adc)
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{
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adc->ADC_INTERRUPT_MASK = 0xF;
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}
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/*
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* @func : void adc_sequencer_msk_ch_control(ADC_Type *adc, uint32_t mask_channel)
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* @brief : Masking the channel which are not required
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : arg : value for masking the un-required channel
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* @return : NONE
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*/
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static inline void adc_sequencer_msk_ch_control(ADC_Type *adc, uint32_t mask_channel)
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{
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/* clearing the previous mask bits */
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adc->ADC_SEQUENCER_CTRL &= ~(ADC_MSK_ALL_CHANNELS);
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/* masking the channels */
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adc->ADC_SEQUENCER_CTRL |= mask_channel;
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}
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/*
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* @func : void adc_set_comparator_A(ADC_Type *adc, uint32_t threshold)
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* @brief : setting comparator A threshold value
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : arg : value for threshold
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* @return : NONE
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*/
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static inline void adc_set_comparator_A(ADC_Type *adc, uint32_t threshold)
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{
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adc->ADC_COMP_THRESH_A = threshold;
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}
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/*
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* @func : void adc_set_comparator_B(ADC_Type *adc, uint32_t threshold)
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* @brief : setting comparator A threshold value
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : arg : value for threshold
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* @return : NONE
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*/
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static inline void adc_set_comparator_B(ADC_Type *adc, uint32_t threshold)
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{
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adc->ADC_COMP_THRESH_B = threshold;
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}
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/*
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* @func : void adc_set_comparator_ctrl_bit(ADC_Type *adc, uint32_t arg)
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* @brief : setting comparator control bit
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : arg : value for threshold
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* @return : NONE
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*/
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static inline void adc_set_comparator_ctrl_bit(ADC_Type *adc, uint32_t arg)
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{
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adc->ADC_CONTROL = (arg << 16);
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}
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/*
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* @func : void adc_output_right_shift(ADC_Type *adc)
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* @brief : control for right shift of bit
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* @parameter[1] : adc : Pointer to the ADC register map
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* @return : NONE
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*/
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static inline void adc_output_right_shift(ADC_Type *adc)
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{
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adc->ADC_SHIFT_CONTROL |= (ADC_SHIFT_CTRL_RIGHT_OR_LEFT);
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}
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/*
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* @func : void adc_output_left_shift(ADC_Type *adc)
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* @brief : control for left shift of bit
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* @parameter : adc : Pointer to the ADC register map
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* @return : NONE
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*/
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static inline void adc_output_left_shift(ADC_Type *adc)
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{
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adc->ADC_SHIFT_CONTROL &= ~(ADC_SHIFT_CTRL_RIGHT_OR_LEFT);
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}
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/*
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* @func : void adc_set_single_ch_scan_mode(ADC_Type *adc, conv_info_t *conv_info)
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* @brief : control to single channel scan
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : conv_info : Pointer to the conv_info_t structure
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* @return : NONE
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*/
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static inline void adc_set_single_ch_scan_mode(ADC_Type *adc, conv_info_t *conv_info)
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{
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/* set to single input scan */
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adc->ADC_SEQUENCER_CTRL |= (ADC_SEQUENCER_CTRL_FIXED_OR_ROTATE);
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conv_info->sequencer_ctrl_status = ADC_SCAN_MODE_SINGLE_CH;
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}
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/*
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* @func : void adc_set_multi_ch_scan_mode(ADC_Type *adc, conv_info_t *conv_info)
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* @brief : control to rotate through all channels
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* @parameter[1] : adc : Pointer to the ADC register map
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* @parameter[2] : conv_info : Pointer to the conv_info_t structure
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* @return : NONE
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*/
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static inline void adc_set_multi_ch_scan_mode(ADC_Type *adc, conv_info_t *conv_info)
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{
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/* Set to continuous input scan */
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adc->ADC_SEQUENCER_CTRL &= ~(ADC_SEQUENCER_CTRL_FIXED_OR_ROTATE);
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conv_info->sequencer_ctrl_status = ADC_SCAN_MODE_MULTI_CH;
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}
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/**
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* @fn : void adc_irq_handler(ADC_Type *adc, conv_info_t *conversion)
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* @brief : Handle DONE0 (avg sample ready)interrupts for the ADC instance.
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* @param[1] : adc : Pointer to the ADC register map
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* @param[2] : conversion : The conversion structure for the ADC instance
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* @return : none
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*/
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void adc_done0_irq_handler(ADC_Type *adc, conv_info_t *conversion);
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/**
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* @fn : void adc_done1_irq_handler(ADC_Type *adc, conv_info_t *conversion)
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* @brief : Handle DONE1 (all sample taken)interrupts for the ADC instance.
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* @param[1] : adc : Pointer to the ADC register map
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* @param[2] : conversion : The conversion structure for the ADC instance
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* @return : none
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*/
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void adc_done1_irq_handler(ADC_Type *adc, conv_info_t *conversion);
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/**
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* @fn : void adc_cmpa_irq_handler(ADC_Type *adc, conv_info_t *conversion)
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* @brief : Handle CMPA interrupts for the ADC instance.
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* @param[1] : adc : Pointer to the ADC register map
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* @param[2] : conversion : The conversion structure for the ADC instance
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* @return : none
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*/
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void adc_cmpa_irq_handler(ADC_Type *adc, conv_info_t *conversion);
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/**
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* @fn : void adc_cmpb_irq_handler(ADC_Type *adc, conv_info_t *conversion)
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* @brief : Handle CMPB interrupts for the ADC instance.
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* @param[1] : adc : Pointer to the ADC register map
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|
* @param[2] : conversion : The conversion structure for the ADC instance
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* @return : none
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|
*/
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void adc_cmpb_irq_handler(ADC_Type *adc, conv_info_t *conversion);
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#endif /* ADC_H_ */
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