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476 lines
21 KiB
C
476 lines
21 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file cpi.h
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* @author Chandra Bhushan Singh
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* @email chandrabhushan.singh@alifsemi.com
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* @version V1.0.0
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* @date 27-March-2023
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* @brief Low level driver Specific header file.
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******************************************************************************/
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#ifndef CPI_H_
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#define CPI_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <stdint.h>
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typedef struct { /*!< LPCPI/CPI Structure */
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volatile uint32_t CAM_CTRL; /*!< (@ 0x00000000) Camera Control Register */
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volatile uint32_t CAM_INTR; /*!< (@ 0x00000004) Camera Interrupt Status Register */
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volatile uint32_t CAM_INTR_ENA; /*!< (@ 0x00000008) Camera Interrupt Enable Register */
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volatile const uint32_t RESERVED; /*!< (@ 0x0000000C) Camera reserved Register */
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volatile uint32_t CAM_CFG; /*!< (@ 0x00000010) Camera Configuration Register */
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volatile uint32_t CAM_FIFO_CTRL; /*!< (@ 0x00000014) Camera FIFO Control Register */
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volatile const uint32_t CAM_AXI_ERR_STAT; /*!< (@ 0x00000018) Camera AXI Error Status Register */
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volatile const uint32_t RESERVED1[3]; /*!< (@ 0x0000001C) Camera Reserved Register */
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volatile uint32_t CAM_VIDEO_FCFG; /*!< (@ 0x00000028) Camera Video Frame Configuration Register */
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volatile uint32_t CAM_CSI_CMCFG; /*!< (@ 0x0000002C) Camera MIPI CSI Color Mode Configuration Register */
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volatile uint32_t CAM_FRAME_ADDR; /*!< (@ 0x00000030) Camera Video Frame A Start Address Register */
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} CPI_Type; /*!< Size = 52 (0x34) */
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/* Camera Control Register (CAM_CTRL) bit Definition, Macros, Offsets and Masks
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* these include CPI capture mode, capture status, software reset, start/stop capture and FIFO clock select.
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*/
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/* CAM_CTRL Start Capture bit[0] */
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#define CAM_CTRL_START (1U << 0)
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/* CAM_CTRL Capture Status bit[2] */
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#define CAM_CTRL_BUSY (1U << 2)
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/* CAM_CTRL Capture Mode bit[4] */
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#define CAM_CTRL_SNAPSHOT (1U << 4)
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/* CAM_CTRL Software Reset bit[8] */
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#define CAM_CTRL_SW_RESET (1U << 8)
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/* CAM_CTRL CAM_CTRL FIFO clock select bit[12] */
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#define CAM_CTRL_FIFO_CLK_SEL (1U << 12)
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/* CAM_INTR control bit parameters */
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/* Frame Capture Stop IRQ bit[0] */
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#define CAM_INTR_STOP (1U << 0)
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/* Input FIFO overrun Warning IRQ bit[4] */
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#define CAM_INTR_INFIFO_OVERRUN (1U << 4)
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/* Output FIFO Overrun Warning IRQ bit[5] */
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#define CAM_INTR_OUTFIFO_OVERRUN (1U << 5)
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/* Bus error IRQ bit[6] */
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#define CAM_INTR_BRESP_ERR (1U << 6)
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/* VSYNC Detected IRQ bit[16] */
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#define CAM_INTR_VSYNC (1U << 16)
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/* HSYNC Detected IRQ bit[20] */
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#define CAM_INTR_HSYNC (1U << 20)
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/* Camera Configuration Register (CAM_CFG) bit Definition, Macros, Offsets and Masks
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* these include data mode, data mask etc
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*/
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/* CAM_CFG vsync wait bit[4] */
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#define CAM_CFG_VSYNC_WAIT_Pos 4U
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/* CAM_CFG vsync mode bit[5] */
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#define CAM_CFG_VSYNC_MODE_Pos 5U
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/* CAM_CFG row roundup bit[8] */
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#define CAM_CFG_ROW_ROUNDUP_Pos 8U
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/* CAM_CFG pixel clock polarity bit[12] */
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#define CAM_CFG_PIXELCLK_POL_Pos 12U
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/* CAM_CFG hsync polarity bit[13] */
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#define CAM_CFG_HSYNC_POL_Pos 13U
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/* CAM_CFG vsync polarity bit[14] */
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#define CAM_CFG_VSYNC_POL_Pos 14U
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/* CAM_CFG Data Mode bit[18-16] */
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#define CAM_CFG_DATA_MODE_Pos 16U
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#define CAM_CFG_DATA_MODE_Msk (0x7U << CAM_CFG_DATA_MODE_Pos)
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/* CAM_CFG Data endianness bit[20] */
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#define CAM_CFG_DATA_ENDIANNESS_Pos 20U
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/* CAM_CFG code10on8 bit[24] */
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#define CAM_CFG_CODE10ON8_Pos 24U
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/* CAM_CFG Data Mask bit[29-28] */
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#define CAM_CFG_DATA_MASK_Pos 28U
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#define CAM_CFG_DATA_MASK_Msk (0x3U << CAM_CFG_DATA_MASK_Pos)
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/* Camera FIFO Control Register (CAM_FIFO_CTRL) bit Definition, Macros, Offsets and Masks
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* these include FIFO read and write watermark.
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*/
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/* CAM_FIFO_CTRL FIFO read watermark bit[4:0] */
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#define CAM_FIFO_CTRL_RD_WMARK_Pos 0U
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#define CAM_FIFO_CTRL_RD_WMARK_Msk (0X1FU << CAM_FIFO_CTRL_RD_WMARK_Pos)
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/* CAM_FIFO_CTRL FIFO write watermark bit[12:8] */
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#define CAM_FIFO_CTRL_WR_WMARK_Pos 8U
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#define CAM_FIFO_CTRL_WR_WMARK_Msk (0X1FU << CAM_FIFO_CTRL_WR_WMARK_Pos)
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/* Camera AXI Error Status Register (CAM_AXI_ERR_STAT) bit Definition, Macros, Offsets and Masks
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* these include CPI BRESP error counter and code.
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*/
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/* CAM_AXI_ERR_STAT frame width bit[1:0] */
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#define CAM_AXI_ERR_STAT_BRESP_Pos 0U
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#define CAM_AXI_ERR_STAT_BRESP_Msk (0x3U << CAM_AXI_ERR_STAT_BRESP_Pos)
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/* CAM_AXI_ERR_STAT frame height bit[15:8] */
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#define CAM_AXI_ERR_STAT_CNT_Pos 8U
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#define CAM_AXI_ERR_STAT_CNT_Msk (0xFF00U << CAM_AXI_ERR_STAT_CNT_Pos)
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/* Camera Video Frame Configuration Register (CAM_VIDEO_FCFG) bit Definition, Macros, Offsets and Masks
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* these include CPI frame width and frame height.
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*/
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/* CAM_VIDEO_FCFG frame width bit[13:0] */
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#define CAM_VIDEO_FCFG_DATA_Pos 0U
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#define CAM_VIDEO_FCFG_DATA_Msk (0x3FFFU << CAM_VIDEO_FCFG_DATA_Pos)
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/* CAM_VIDEO_FCFG frame height bit[27:16] */
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#define CAM_VIDEO_FCFG_ROW_Pos 16U
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#define CAM_VIDEO_FCFG_ROW_Msk (0xFFFU << CAM_VIDEO_FCFG_ROW_Pos)
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/* Camera MIPI CSI Color Mode Configuration Register (CAM_CSI_CMCFG) bit Definition, Macros, Offsets and Masks
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* these include color encode mode.
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*/
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/* Camera MIPI CSI color mode 16-bit encode bit[3:0] */
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#define CAM_CSI_CMCFG_MODE_Pos 0U
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#define CAM_CSI_CMCFG_MODE_Msk (0XFU << CAM_CSI_CMCFG_MODE_Pos)
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/* Camera Video Frame Start Address Register (CAM_FRAME_ADDR) bit Definition, Macros, Offsets and Masks
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* these include CPI framebuffer start address.
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*/
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/* CAM_FRAME_ADDR framebuffer start address bit[31:3] */
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#define CAM_FRAME_ADDR_ADDR_Pos 0U
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#define CAM_FRAME_ADDR_ADDR_Msk (0xFFFFFFF8U << CAM_FRAME_ADDR_ADDR_Pos)
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/**
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* enum CPI_VIDEO_CAPTURE_STATUS
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* CPI Video Capture Status.
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*/
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typedef enum _CPI_VIDEO_CAPTURE_STATUS
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{
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CPI_VIDEO_CAPTURE_STATUS_NOT_CAPTURING, /**< not capturing video */
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CPI_VIDEO_CAPTURE_STATUS_CAPTURING /**< capturing video */
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} CPI_VIDEO_CAPTURE_STATUS;
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/**
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* enum CPI_MODE_SELECT.
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* CPI capture mode.
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*/
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typedef enum _CPI_MODE_SELECT
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{
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CPI_MODE_SELECT_VIDEO, /**< Capture video data frames continuously */
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CPI_MODE_SELECT_SNAPSHOT /**< Capture one frame then stop (snapshot mode) */
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} CPI_MODE_SELECT;
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/**
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* enum CPI_INTERFACE
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* CPI interface.
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*/
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typedef enum _CPI_INTERFACE
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{
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CPI_INTERFACE_PARALLEL, /**< select video data from parallel camera interface */
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CPI_INTERFACE_MIPI_CSI /**< select video data from MIPI_CSI interface (Not valid for LPCPI) */
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} CPI_INTERFACE;
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/**
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* enum CPI_WAIT_VSYNC
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* CPI wait for vsync to start capture frame.
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*/
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typedef enum _CPI_WAIT_VSYNC
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{
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CPI_WAIT_VSYNC_DISABLE, /**< CPI Start video capture without waiting for VSYNC */
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CPI_WAIT_VSYNC_ENABLE /**< CPI Start video capture on rising edge of VSYNC */
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} CPI_WAIT_VSYNC;
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/**
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* enum CPI_CAPTURE_DATA_ENABLE
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* CPI vsync signal mode for capturing data.
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*/
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typedef enum _CPI_CAPTURE_DATA_ENABLE
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{
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CPI_CAPTURE_DATA_ENABLE_IF_HSYNC_HIGH, /**< Capture data when HSYNC is high */
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CPI_CAPTURE_DATA_ENABLE_IF_VSYNC_AND_HSYNC_HIGH /**< Capture data when both VSYNC and HSYNC are high */
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} CPI_CAPTURE_DATA_ENABLE;
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/**
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* enum CPI_ROW_ROUNDUP.
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* CPI round up pixel data to 64 bit at end of each row.
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*/
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typedef enum _CPI_ROW_ROUNDUP
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{
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CPI_ROW_ROUNDUP_DISABLE, /**< CPI round up pixel data to 64 bit at end of each row disable */
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CPI_ROW_ROUNDUP_ENABLE /**< CPI round up pixel data to 64 bit at end of each row */
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} CPI_ROW_ROUNDUP;
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/**
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* enum CPI_SIG_POLARITY
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* CPI signal polarity.
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*/
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typedef enum _CPI_SIG_POLARITY
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{
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CPI_SIG_POLARITY_INVERT_DISABLE, /**< Disable invert signal polarity */
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CPI_SIG_POLARITY_INVERT_ENABLE /**< Enable invert signal polarity */
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} CPI_SIG_POLARITY;
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/**
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* enum CPI_DATA_MODE
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* CPI data mode selection.
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*/
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typedef enum _CPI_DATA_MODE
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{
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CPI_DATA_MODE_BIT_1, /**< Select 1 bit data mode */
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CPI_DATA_MODE_BIT_2, /**< Select 2 bit data mode */
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CPI_DATA_MODE_BIT_4, /**< Select 4 bit data mode */
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CPI_DATA_MODE_BIT_8, /**< Select 8 bit data mode */
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CPI_DATA_MODE_BIT_16, /**< Select 16 bit data mode (Not valid for LPCPI) */
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CPI_DATA_MODE_BIT_32, /**< Select 32 bit data mode (Valid for MIPI CSI interface) */
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CPI_DATA_MODE_BIT_64 /**< Select 64 bit data mode (Valid for MIPI CSI interface) */
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} CPI_DATA_MODE;
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/**
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* enum CPI_DATA_FIELD
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* CPI MSB/LSB to be stored first in memory.
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*/
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typedef enum _CPI_DATA_ENDIANNESS {
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CPI_DATA_ENDIANNESS_LSB_FIRST, /**< Select LSB first to be stored in memory */
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CPI_DATA_ENDIANNESS_MSB_FIRST /**< Select MSB first to be stored in memory */
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} CPI_DATA_ENDIANNESS;
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/**
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* enum CPI_CODE10ON8_CODING
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* CPI transfer 10 bit code on 8 bit data bus.
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*/
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typedef enum _CPI_CODE10ON8_CODING {
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CPI_CODE10ON8_CODING_DISABLE, /**< Disable special 10-bit coding */
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CPI_CODE10ON8_CODING_ENABLE /**< Enable special 10-bit coding */
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} CPI_CODE10ON8_CODING;
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/**
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* enum CPI_DATA_MASK
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* CPI data mask.
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* Valid for 16 bit data mode only and not valid for LPCPI.
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*/
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typedef enum _CPI_DATA_MASK
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{
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CPI_DATA_MASK_BIT_16, /**< Select 16 bit data mask */
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CPI_DATA_MASK_BIT_10, /**< Select 10 bit data mask */
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CPI_DATA_MASK_BIT_12, /**< Select 12 bit data mask */
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CPI_DATA_MASK_BIT_14 /**< Select 14 bit data mask */
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} CPI_DATA_MASK;
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/**
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* @struct _cpi_sensor_info_t
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* @brief CPI camera sensor information.
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*/
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typedef struct _cpi_sensor_info_t
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{
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CPI_INTERFACE interface; /**< CPI Interface */
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CPI_WAIT_VSYNC vsync_wait; /**< CPI VSYNC Wait */
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CPI_CAPTURE_DATA_ENABLE vsync_mode; /**< CPI VSYNC Mode */
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CPI_SIG_POLARITY pixelclk_pol; /**< CPI Pixel Clock Polarity */
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CPI_SIG_POLARITY hsync_pol; /**< CPI HSYNC Polarity */
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CPI_SIG_POLARITY vsync_pol; /**< CPI VSYNC Polarity */
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CPI_DATA_MODE data_mode; /**< CPI Data Mode */
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CPI_DATA_ENDIANNESS data_endianness; /**< Select MSB/LSB */
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CPI_CODE10ON8_CODING code10on8; /**< code10on8 enable/disable */
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CPI_DATA_MASK data_mask; /**< CPI Data Mask */
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} cpi_sensor_info_t;
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/**
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* @struct cpi_fifo_ctrl_cfg_t
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* @brief CPI fifo control configuration.
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*/
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typedef struct _cpi_fifo_ctrl_cfg_t
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{
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uint8_t rd_wmark; /**< FIFO read watermark */
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uint8_t wr_wmark; /**< FIFO write watermark */
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} cpi_fifo_ctrl_cfg_t;
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/**
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* @struct _cpi_frame_cfg_t
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* @brief CPI frame configuration.
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*/
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typedef struct _cpi_frame_cfg_t
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{
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uint16_t data; /**< Valid data in a row */
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uint16_t row; /**< Valid data rows in a frame */
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} cpi_frame_cfg_t;
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/**
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* enum CPI_COLOR_MODE_CONFIG
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* CPI CSI IPI color mode configuration.
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* Not valid for LPCPI.
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*/
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typedef enum _CPI_COLOR_MODE_CONFIG {
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CPI_COLOR_MODE_CONFIG_IPI16_RAW6, /**< Select color encode mode IPI-16 RAW 6 */
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CPI_COLOR_MODE_CONFIG_IPI16_RAW7, /**< Select color encode mode IPI-16 RAW 7 */
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CPI_COLOR_MODE_CONFIG_IPI16_RAW8, /**< Select color encode mode IPI-16 RAW 8 */
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CPI_COLOR_MODE_CONFIG_IPI16_RAW10, /**< Select color encode mode IPI-16 RAW 10 */
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CPI_COLOR_MODE_CONFIG_IPI16_RAW12, /**< Select color encode mode IPI-16 RAW 12 */
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CPI_COLOR_MODE_CONFIG_IPI16_RAW14, /**< Select color encode mode IPI-16 RAW 14 */
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CPI_COLOR_MODE_CONFIG_IPI16_RAW16, /**< Select color encode mode IPI-16 RAW 16 */
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CPI_COLOR_MODE_CONFIG_IPI48_RGB444, /**< Select color encode mode IPI-48 RGB444 */
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CPI_COLOR_MODE_CONFIG_IPI48_RGB555, /**< Select color encode mode IPI-48 RGB555 */
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CPI_COLOR_MODE_CONFIG_IPI48_RGB565, /**< Select color encode mode IPI-48 RGB565 */
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CPI_COLOR_MODE_CONFIG_IPI48_RGB666, /**< Select color encode mode IPI-48 RGB666 */
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CPI_COLOR_MODE_CONFIG_IPI48_XRGB888, /**< Select color encode mode IPI-48 XRGB888 */
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CPI_COLOR_MODE_CONFIG_IPI48_RGBX888, /**< Select color encode mode IPI-48 RGBX888 */
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CPI_COLOR_MODE_CONFIG_IPI48_RAW32, /**< Select color encode mode IPI-48 RAW 32 */
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CPI_COLOR_MODE_CONFIG_IPI48_RAW48, /**< Select color encode mode IPI-48 RAW 48 */
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} CPI_COLOR_MODE_CONFIG;
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/**
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* @struct _cpi_cfg_info_t
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* @brief CPI configuration information.
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*/
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typedef struct _cpi_cfg_info_t
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{
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cpi_sensor_info_t sensor_info; /**< CPI sensor configuration */
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CPI_ROW_ROUNDUP rw_roundup; /**< CPI row roundup */
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cpi_fifo_ctrl_cfg_t fifo_ctrl; /**< CPI FIFO control */
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cpi_frame_cfg_t frame_cfg; /**< CPI Frame */
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CPI_COLOR_MODE_CONFIG csi_ipi_color_mode; /**< CPI CSI IPI color mode */
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} cpi_cfg_info_t;
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/**
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\fn CPI_VIDEO_CAPTURE_STATUS cpi_get_capture_status(CPI_Type *cpi)
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\brief Get the capture status of the CPI.
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\param[in] cpi Pointer to the CPI register map.
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\return Capture status of the CPI.
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*/
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static inline CPI_VIDEO_CAPTURE_STATUS cpi_get_capture_status(CPI_Type *cpi)
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{
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return (cpi->CAM_CTRL & CAM_CTRL_BUSY) ? \
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CPI_VIDEO_CAPTURE_STATUS_CAPTURING : CPI_VIDEO_CAPTURE_STATUS_NOT_CAPTURING;
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}
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/**
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\fn uint32_t cpi_get_interrupt_status(CPI_Type *cpi)
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\brief Get the interrupt status from the CPI.
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\param[in] cpi Pointer to the CPI register map.
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\return interrupt status from the CPI.
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*/
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static inline uint32_t cpi_get_interrupt_status(CPI_Type *cpi)
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{
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return (cpi->CAM_INTR & cpi->CAM_INTR_ENA);
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}
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/**
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\fn void cpi_enable_interrupt(CPI_Type *cpi, uint32_t irq_bitmask)
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\brief Enable CPI interrupt.
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\param[in] cpi Pointer to CPI register map.
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\param[in] irq_bitmask Possible camera events (refer CPI_INTR_* macros Bitmask).
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\return none
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*/
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static inline void cpi_enable_interrupt(CPI_Type *cpi, uint32_t irq_bitmask)
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{
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cpi->CAM_INTR_ENA |= irq_bitmask;
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}
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/**
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\fn void cpi_disable_interrupt(CPI_Type *cpi, uint32_t irq_bitmask)
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\brief Disable CPI interrupt.
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\param[in] cpi Pointer to CPI register map.
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\param[in] irq_bitmask Possible camera events (refer CPI_INTR_* macros Bitmask).
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\return none
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*/
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static inline void cpi_disable_interrupt(CPI_Type *cpi, uint32_t irq_bitmask)
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{
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cpi->CAM_INTR_ENA &= ~irq_bitmask;
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}
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/**
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\fn void cpi_irq_handler_clear_intr_status(CPI_Type *cpi, uint32_t irq_bitmask)
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\brief Clear CPI interrupt.
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\param[in] cpi Pointer to CPI register map
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\param[in] irq_bitmask CPI interrupt status (refer CPI_INTR_* macros Bitmask)
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\return none.
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*/
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static inline void cpi_irq_handler_clear_intr_status(CPI_Type *cpi, uint32_t irq_bitmask)
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{
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cpi->CAM_INTR |= irq_bitmask;
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(void)cpi->CAM_INTR;
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}
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/**
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\fn void cpi_set_framebuff_start_addr(CPI_Type *cpi, uint32_t addr)
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\brief Set the Video frame start address.
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\param[in] cpi Pointer to the CPI register map.
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\param[in] addr Video frame start address.
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\return none.
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*/
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static inline void cpi_set_framebuff_start_addr(CPI_Type *cpi, uint32_t addr)
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{
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cpi->CAM_FRAME_ADDR = addr;
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}
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/**
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\fn void cpi_stop_capture(CPI_Type *cpi)
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\brief CPI Stop capturing frame.
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\param[in] cpi Pointer to the CPI register map.
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\return none.
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*/
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static inline void cpi_stop_capture(CPI_Type *cpi)
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{
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cpi->CAM_CTRL = 0;
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}
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/**
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\fn void cpi_software_reset(CPI_Type *cpi)
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\brief CPI software reset
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\param[in] cpi Pointer to the CPI register map.
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\param[in] mode Soft reset the CPI
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\return none.
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*/
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void cpi_software_reset(CPI_Type *cpi);
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/**
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\fn void cpi_start_capture(CPI_Type *cpi, CPI_MODE_SELECT mode)
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\brief Capture frame in snapshot/ continuous capture mode.
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-Set CAM_CTRL = 0—prepare for soft reset
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-Set CAM_CTRL = 0x100—activate soft reset
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-Set CAM_CTRL = 0—stop soft reset
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-Set CAM_CTRL = 0x1001 or 0x1011—start the CPI controller,
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with bit [SNAPSHOT] defining the operation mode:
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-[SNAPSHOT] = 0—Capture video frames continuously
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-[SNAPSHOT] = 1—Capture one frame then stop
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\param[in] cpi Pointer to the CPI register map.
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\param[in] mode Select to capture one frame and stop/ or to capture video frames continuously
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\return none.
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*/
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void cpi_start_capture(CPI_Type *cpi, CPI_MODE_SELECT mode);
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/**
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\fn void cpi_set_config(CPI_Type *cpi, cpi_cfg_info_t *info)
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\brief Configure the cpi with given information.
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\param[in] cpi Pointer to CPI register map
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\param[in] info Pointer to cpi configuration structure.
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\return none
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*/
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void cpi_set_config(CPI_Type *cpi, cpi_cfg_info_t *info);
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPI_H_ */
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