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367 lines
15 KiB
C
367 lines
15 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file dma_info.h
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* @author Sudhir Sreedharan
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* @email sudhir@alifsemi.com
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* @version V1.0.0
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* @date 11-08-2023
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* @brief DMA Header file for channel and thread info
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* @bug None.
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* @Note None
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******************************************************************************/
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#ifndef DMA_CTRL_H_
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#define DMA_CTRL_H_
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#include <dma_config.h>
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#include <dma_opcode.h>
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#include <dma.h>
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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}
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#endif
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/**
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\brief DMA Transfer Direction
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*/
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typedef enum _DMA_TRANSFER {
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DMA_TRANSFER_MEM_TO_MEM,
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DMA_TRANSFER_MEM_TO_DEV,
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DMA_TRANSFER_DEV_TO_MEM,
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DMA_TRANSFER_NONE,
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} DMA_TRANSFER;
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typedef struct _dma_desc_info_t {
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DMA_TRANSFER direction; /*!< Direction of data transfer */
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DMA_SECURE_STATE sec_state; /*!< Secure state of channel */
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uint32_t total_len; /*!< Number of bytes */
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uint32_t src_addr; /*!< Source address */
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uint32_t dst_addr0; /*!< Destination address */
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uint32_t dst_addr1; /*!< Destination address */
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uint8_t src_bsize; /*!< Src Burst Size */
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uint8_t dst_bsize; /*!< Dest Burst Size */
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uint8_t src_blen; /*!< Src Burst length */
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uint8_t dst_blen; /*!< Dest Burst length */
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uint8_t periph_num; /*!< Peripheral request number */
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uint8_t dst_cache_ctrl; /*!< Dest Cache Control */
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uint8_t src_cache_ctrl; /*!< Src Cache Control */
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uint8_t dst_prot_ctrl; /*!< Dest Protection Control */
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uint8_t src_prot_ctrl; /*!< Src Protection Control */
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uint8_t endian_swap_size; /*!< Endian Swap Size */
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} dma_desc_info_t;
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typedef struct _dma_channel_info_t {
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uint32_t flags; /*!< Channel flags */
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bool last_req; /*!< If this is last request */
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uint8_t event_index; /*!< Event/IRQ index */
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dma_desc_info_t desc_info; /*!< DMA descriptor */
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} dma_channel_info_t;
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typedef struct _dma_thread_info_t {
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dma_channel_info_t channel_info; /*!< Channel information */
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uint8_t dma_mcode[DMA_MICROCODE_SIZE];/*!< DMA microcode buffer */
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void *user_mcode; /*!< User provided mcode address */
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bool in_use; /*!< Status of DMA thread being used */
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} dma_thread_info_t;
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typedef struct _dma_config_info_t {
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dma_thread_info_t channel_thread[DMA_MAX_CHANNELS];/*!< Channel thread info */
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uint8_t event_map[DMA_MAX_EVENTS]; /*!< Events utilization mapping */
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} dma_config_info_t;
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/**
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\fn uint8_t dma_get_event_index(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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\brief Get the event index of the channel
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel Number
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\return uint8_t Event index
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*/
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static inline uint8_t dma_get_event_index(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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return channel_info->event_index;
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}
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/**
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\fn uint8_t dma_get_channel_flags(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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\brief Get the flags set for the channel
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel Number
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\return uint8_t Return the current flags
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*/
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static inline uint32_t dma_get_channel_flags(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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return channel_info->flags;
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}
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/**
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\fn dma_desc_info_t* dma_get_desc_info(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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\brief Get the descriptor info of the channel
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel Number
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\return dma_desc_info_t* Pointer to the descriptor
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*/
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static inline dma_desc_info_t* dma_get_desc_info(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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return &channel_info->desc_info;
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}
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/**
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\fn void dma_reset_all_channels(dma_config_info_t *dma_cfg)
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\brief Reset all the channels
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\return void
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*/
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static inline void dma_reset_all_channels(dma_config_info_t *dma_cfg)
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{
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uint8_t channel_num = 0;
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for (channel_num = 0; channel_num < DMA_MAX_CHANNELS; channel_num++)
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{
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dma_cfg->channel_thread[channel_num].in_use = false;
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}
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}
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/**
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\fn int8_t dma_allocate_channel(dma_config_info_t *dma_cfg)
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\brief Allocate a channel if available
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\return int8_t channel number or -1 if not available
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*/
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int8_t dma_allocate_channel(dma_config_info_t *dma_cfg);
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/**
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\fn void dma_release_channel(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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\brief Release the channel
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel Number
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\return void
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*/
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static inline void dma_release_channel(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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thread_info->in_use = false;
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thread_info->user_mcode = (void *)0;
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channel_info->flags = 0;
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}
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/**
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\fn void dma_reset_all_events(dma_config_info_t *dma_cfg)
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\brief Reset all the events
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\return void
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*/
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static inline void dma_reset_all_events(dma_config_info_t *dma_cfg)
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{
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uint8_t event_index = 0;
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for (event_index = 0; event_index < DMA_MAX_EVENTS; event_index++)
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{
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dma_cfg->event_map[event_index] = 0xFF;
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}
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}
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/**
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\fn int8_t dma_allocate_event(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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\brief Allocate a event if available
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel Number
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\return int8_t Event index number or -1 if not available
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*/
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int8_t dma_allocate_event(dma_config_info_t *dma_cfg, uint8_t channel_num);
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/**
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\fn int8_t dma_release_event(dma_config_info_t *dma_cfg,
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int8_t event_index)
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\brief Release the event
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] event_index Event Index
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\return void
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*/
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static inline void dma_release_event(dma_config_info_t *dma_cfg,
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uint8_t event_index)
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{
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dma_cfg->event_map[event_index] = 0xFF;
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}
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/**
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\fn void dma_copy_desc_info(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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dma_desc_info_t *desc_info)
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\brief Update the channel descriptor Structure
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel Number
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\param[in] desc_info Descriptor Information
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\return None
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*/
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void dma_copy_desc_info(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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dma_desc_info_t *desc_info);
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/**
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\fn void dma_set_secure_state(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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DMA_SECURE_STATE sec_state)
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\brief Set the Secure state of the channel desc
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel number
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\param[in] sec_state Secure State
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\return void
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*/
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static inline void dma_set_secure_state(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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DMA_SECURE_STATE sec_state)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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dma_desc_info_t *channel_desc_info = &channel_info->desc_info;
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channel_desc_info->sec_state = sec_state;
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}
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/**
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\fn DMA_SECURE_STATE dma_get_secure_state(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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DMA_SECURE_STATE sec_state)
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\brief Get the Secure state of the channel desc
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel number
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\return DMA_SECURE_STATE Secure State
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*/
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static inline DMA_SECURE_STATE dma_get_secure_state(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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dma_desc_info_t *channel_desc_info = &channel_info->desc_info;
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return channel_desc_info->sec_state;
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}
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/**
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\fn void dma_set_cache_ctrl(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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uint8_t src_cache_ctrl,
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uint8_t dst_cache_ctrl)
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\brief Set the Cache control state of the channel desc
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel number
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\param[in] src_cache_ctrl Source Cache Control bits
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\param[in] dst_cache_ctrl Destination Cache Control bits
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\return void
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*/
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static inline void dma_set_cache_ctrl(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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uint8_t src_cache_ctrl,
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uint8_t dst_cache_ctrl)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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dma_desc_info_t *channel_desc_info = &channel_info->desc_info;
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channel_desc_info->dst_cache_ctrl = dst_cache_ctrl;
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channel_desc_info->src_cache_ctrl = src_cache_ctrl;
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}
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/**
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\fn void dma_set_prot_ctrl(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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uint8_t src_prot_ctrl,
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uint8_t dst_prot_ctrl)
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\brief Set the protection(secure) control state of the channel desc
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel number
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\param[in] src_prot_ctrl Source protection Control bits
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\param[in] dst_prot_ctrl Destination protection Control bits
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\return void
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*/
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static inline void dma_set_prot_ctrl(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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uint8_t src_prot_ctrl,
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uint8_t dst_prot_ctrl)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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dma_desc_info_t *channel_desc_info = &channel_info->desc_info;
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channel_desc_info->dst_prot_ctrl = dst_prot_ctrl;
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channel_desc_info->src_prot_ctrl = src_prot_ctrl;
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}
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/**
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\fn void dma_set_endian_swap_size(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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DMA_SWAP endian_swap)
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\brief Set the Endian Swap Size of the channel desc
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel number
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\param[in] endian_swap Endian Swap Size
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\return void
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*/
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static inline void dma_set_endian_swap_size(dma_config_info_t *dma_cfg,
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uint8_t channel_num,
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DMA_SWAP endian_swap)
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{
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dma_thread_info_t *thread_info = &dma_cfg->channel_thread[channel_num];
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dma_channel_info_t *channel_info = &thread_info->channel_info;
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dma_desc_info_t *channel_desc_info = &channel_info->desc_info;
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channel_desc_info->endian_swap_size = endian_swap;
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}
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/**
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\fn dma_ccr_t dma_get_channel_ctrl_info(dma_config_info_t *dma_cfg,
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uint8_t channel_num)
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\brief Return the Channel Control Info from Descriptor info
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\param[in] dma_cfg Pointer to DMA Configuration resources
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\param[in] channel_num Channel Number
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\return dma_ccr_t channel Control Info (CCR)
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*/
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dma_ccr_t dma_get_channel_ctrl_info(dma_config_info_t *dma_cfg,
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uint8_t channel_num);
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#ifdef __cplusplus
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}
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#endif
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#endif /* DMA_CTRL_H_ */
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