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102 lines
2.8 KiB
C
102 lines
2.8 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file sys_ctrl_cdc.h
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* @author Prasanna Ravi
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* @email prasanna.ravi@alifsemi.com
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* @version V1.0.0
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* @date 10-April-2023
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* @brief CDC system control Specific Header file.
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******************************************************************************/
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#ifndef SYS_CTRL_CDC_H_
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#define SYS_CTRL_CDC_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "peripheral_types.h"
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/**
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* enum CDC_PIX_CLKSEL
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* CDC pixel clock source selection
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*/
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typedef enum _CDC_PIX_CLKSEL
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{
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CDC_PIX_CLKSEL_400MZ, /**< Select 400 MHz clock source (PLL_CLK1/2) */
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CDC_PIX_CLKSEL_480MZ /**< Select 480 MHz clock source (PLL_CLK3) */
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}CDC_PIX_CLKSEL;
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/**
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\fn static inline void enable_dpi_periph_clk(void)
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\brief Enable clock supply for DPI controller (CDC).
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\return none.
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*/
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static inline void enable_dpi_periph_clk(void)
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{
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CLKCTL_PER_MST->PERIPH_CLK_ENA |= PERIPH_CLK_ENA_DPI_CKEN;
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}
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/**
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\fn static inline void disable_dpi_periph_clk(void)
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\brief Disable clock supply for DPI controller (CDC).
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\return none.
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*/
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static inline void disable_dpi_periph_clk(void)
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{
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CLKCTL_PER_MST->PERIPH_CLK_ENA &= ~PERIPH_CLK_ENA_DPI_CKEN;
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}
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/**
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\fn static inline void set_cdc_pixel_clk(CDC_PIX_CLKSEL clksel, uint32_t div)
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\brief Set cdc pixel clock.
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param[in] clksel pixel clock source to select.
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param[in] div pixel clock divisor.
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\return none.
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*/
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static inline void set_cdc_pixel_clk(CDC_PIX_CLKSEL clksel, uint32_t div)
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{
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CLKCTL_PER_MST->CDC200_PIXCLK_CTRL &= ~CDC200_PIXCLK_CTRL_DIVISOR_Msk;
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CLKCTL_PER_MST->CDC200_PIXCLK_CTRL |= (div << CDC200_PIXCLK_CTRL_DIVISOR_Pos);
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switch(clksel)
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{
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case CDC_PIX_CLKSEL_400MZ:
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CLKCTL_PER_MST->CDC200_PIXCLK_CTRL &= ~CDC200_PIXCLK_CTRL_CLK_SEL;
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break;
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case CDC_PIX_CLKSEL_480MZ:
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CLKCTL_PER_MST->CDC200_PIXCLK_CTRL |= CDC200_PIXCLK_CTRL_CLK_SEL;
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break;
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default:
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break;
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}
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CLKCTL_PER_MST->CDC200_PIXCLK_CTRL |= CDC200_PIXCLK_CTRL_CKEN;
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}
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/**
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\fn static inline void disable_cdc_pixel_clk(void)
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\brief Disable cdc pixel clock.
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\return none.
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*/
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static inline void disable_cdc_pixel_clk(void)
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{
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CLKCTL_PER_MST->CDC200_PIXCLK_CTRL = 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* SYS_CTRL_CDC_H_ */
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