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569 lines
17 KiB
C
569 lines
17 KiB
C
/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved.
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* Use, distribution and modification of this code is permitted under the
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* terms stated in the Alif Semiconductor Software License Agreement
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*
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* You should have received a copy of the Alif Semiconductor Software
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* License Agreement with this file. If not, please write to:
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* contact@alifsemi.com, or visit: https://alifsemi.com/license
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*
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*/
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/**************************************************************************//**
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* @file sys_ctrl_dphy.h
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* @author Prasanna Ravi
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* @email prasanna.ravi@alifsemi.com
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* @version V1.0.0
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* @date 19-April-2023
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* @brief DPHY system control Specific Header file.
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******************************************************************************/
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#ifndef SYS_CTRL_DPHY_H_
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#define SYS_CTRL_DPHY_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "peripheral_types.h"
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/**
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* enum DPHY_PLL_CLKSEL
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* DPHY pll clock selection
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*/
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typedef enum _DPHY_PLL_CLKSEL
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{
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DPHY_PLL_CLKSEL_CLOCK_STOP, /**< DPHY Clocks stopped */
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DPHY_PLL_CLKSEL_CLOCK_GENERAT, /**< DPHY CLOCK generation */
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DPHY_PLL_CLKSEL_CLOCK_BYPASS, /**< Buffered CLKEXT (PLL bypass clock) */
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}DPHY_PLL_CLKSEL;
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/**
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* enum DPHY_TESTPORT_SELECT
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* DPHY dphy testport selection
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*/
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typedef enum _DPHY_TESTPORT_SELECT
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{
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DPHY_TESTPORT_SELECT_TX, /**< DPHY Select TX_TESTPORT */
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DPHY_TESTPORT_SELECT_RX, /**< DPHY Select RX_TESTPORT */
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}DPHY_TESTPORT_SELECT;
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/**
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* enum DPHY_MODE
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* DPHY mode Master/Slave.
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*/
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typedef enum _DPHY_MODE
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{
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DPHY_MODE_MASTER, /**< DPHY mode master */
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DPHY_MODE_SLAVE /**< DPHY mode slave */
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}DPHY_MODE;
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/**
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* enum DPHY_BIST_OK
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* DPHY BISt OK SET/NOT_SET.
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*/
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typedef enum _DPHY_BIST_OK_STATUS
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{
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DPHY_BIST_OK_STATUS_NOT_SET = (0U << 2), /**< DPHY BIST OK set */
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DPHY_BIST_OK_STATUS_SET = (1U << 2) /**< DPHY BIST OK not set */
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}DPHY_BIST_OK_STATUS;
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/**
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* enum DPHY_DATA_LANE
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* DPHY data lanes.
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*/
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typedef enum _DPHY_DATA_LANE
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{
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DPHY_DATA_LANE_0 = (1U << 0), /**< DPHY data lane 0 */
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DPHY_DATA_LANE_1 = (1U << 1) /**< DPHY data lane 1 */
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}DPHY_DATA_LANE;
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/**
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* @struct _pll_config_t
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* @brief pll configuration parameters description.
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*/
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typedef struct _pll_config_t
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{
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uint8_t pll_gmp_ctrl; /* Controls the effective loop-filter resistance */
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uint16_t pll_m; /* Control of the input frequency division ratio */
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uint8_t pll_n; /* Control of the feedback multiplication ratio */
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uint8_t pll_cpbias_ctrl; /* Charge pump bias control */
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uint8_t pll_int_ctrl; /* Integral charge pump control */
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uint8_t pll_prop_ctrl; /* Proportional charge pump control */
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uint8_t pll_vco_ctrl; /* VCO operating range */
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} pll_config_t;
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/**
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\fn static inline void enable_dphy_pll_force_lock (void)
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\brief Enable Force lock to device.
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\return none.
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*/
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static inline void enable_dphy_pll_force_lock (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 |= DPHY_PLL_CTRL0_FORCE_LOCK;
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}
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/**
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\fn static inline void disable_dphy_pll_force_lock (void)
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\brief Disable Force lock to device.
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\return none.
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*/
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static inline void disable_dphy_pll_force_lock (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 &= ~DPHY_PLL_CTRL0_FORCE_LOCK;
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}
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/**
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\fn static inline void enable_dphy_pll_shadow_control (void)
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\brief Enable dphy pll shadow control.
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\return none.
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*/
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static inline void enable_dphy_pll_shadow_control (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 |= DPHY_PLL_CTRL0_SHADOW_CONTROL;
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}
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/**
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\fn static inline void disable_dphy_pll_shadow_control (void)
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\brief Disable dphy pll shadow control.
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\return none.
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*/
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static inline void disable_dphy_pll_shadow_control (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 &= ~DPHY_PLL_CTRL0_SHADOW_CONTROL;
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}
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/**
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\fn static inline void enable_dphy_updatepll (void)
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\brief Enable dphy updatepll.
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\return none.
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*/
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static inline void enable_dphy_updatepll (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 |= DPHY_PLL_CTRL0_UPDATEPLL;
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}
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/**
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\fn static inline void disable_dphy_updatepll (void)
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\brief Disable dphy updatepll.
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\return none.
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*/
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static inline void disable_dphy_updatepll (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 &= ~DPHY_PLL_CTRL0_UPDATEPLL;
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}
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/**
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\fn static inline void enable_dphy_pll_shadow_clear (void)
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\brief Enable dphy pll shadow clear.
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\return none.
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*/
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static inline void enable_dphy_pll_shadow_clear (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 |= DPHY_PLL_CTRL0_SHADOW_CLEAR;
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}
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/**
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\fn static inline void disable_dphy_pll_shadow_clear (void)
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\brief Disable dphy pll shadow clear.
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\return none.
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*/
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static inline void disable_dphy_pll_shadow_clear (void)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 &= ~DPHY_PLL_CTRL0_SHADOW_CLEAR;
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}
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/**
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\fn static inline void set_dphy_pll_configuration (pll_config_t *info)
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\brief Set dphy pll configuration.
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\param[in] info Pointer to pll configuration structure.
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\return none.
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*/
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static inline void set_dphy_pll_configuration (pll_config_t *info)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 &= ~DPHY_PLL_CTRL0_GMP_CTRL_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 |= (info->pll_gmp_ctrl << DPHY_PLL_CTRL0_GMP_CTRL_Pos);
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CLKCTL_PER_MST->DPHY_PLL_CTRL1 &= ~DPHY_PLL_CTRL1_FEEDBACK_MULT_RATIO_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL1 |= (info->pll_m << DPHY_PLL_CTRL1_FEEDBACK_MULT_RATIO_Pos);
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CLKCTL_PER_MST->DPHY_PLL_CTRL1 &= ~DPHY_PLL_CTRL1_INPUT_DIV_FACTOR_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL1 |= (info->pll_n << DPHY_PLL_CTRL1_INPUT_DIV_FACTOR_Pos);
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 &= ~DPHY_PLL_CTRL2_CPBIAS_CTRL_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 |= (info->pll_cpbias_ctrl << DPHY_PLL_CTRL2_CPBIAS_CTRL_Pos);
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 &= ~DPHY_PLL_CTRL2_INT_CTRL_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 |= (info->pll_int_ctrl << DPHY_PLL_CTRL2_INT_CTRL_Pos);
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 &= ~DPHY_PLL_CTRL2_PROP_CTRL_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 |= (info->pll_prop_ctrl << DPHY_PLL_CTRL2_PROP_CTRL_Pos);
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 &= ~DPHY_PLL_CTRL2_VCO_CTRL_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL2 |= (info->pll_vco_ctrl << DPHY_PLL_CTRL2_VCO_CTRL_Pos);
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}
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/**
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\fn static inline void set_dphy_pll_clksel (void)
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\brief Set dphy CLKEXT divider selection.
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\param[in] clksel dphy CLKEXT divider selection to set.
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\return none.
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*/
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static inline void set_dphy_pll_clksel (DPHY_PLL_CLKSEL clksel)
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{
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 &= ~DPHY_PLL_CTRL0_CLKSEL_Msk;
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CLKCTL_PER_MST->DPHY_PLL_CTRL0 |= (clksel << DPHY_PLL_CTRL0_CLKSEL_Pos);
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}
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/**
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\fn static inline void set_tx_dphy_txrx (DPHY_MODE mode)
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\brief Selects master or slave configuration for the dphy.
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\param[in] mode select Mater/Slave.
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\return none.
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*/
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static inline void set_tx_dphy_txrx (DPHY_MODE mode)
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{
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if(mode == DPHY_MODE_MASTER)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 |= DPHY_CTRL0_TXRXZ;
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}
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else
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 &= ~DPHY_CTRL0_TXRXZ;
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}
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}
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/**
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\fn static inline void set_rx_dphy_txrx (DPHY_MODE mode)
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\brief Selects master or slave configuration for the dphy.
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\param[in] mode select Mater/Slave.
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\return none.
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*/
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static inline void set_rx_dphy_txrx (DPHY_MODE mode)
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{
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if(mode == DPHY_MODE_MASTER)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 |= DPHY_CTRL0_TXRXZ;
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}
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else
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 &= ~DPHY_CTRL0_TXRXZ;
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}
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}
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/**
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\fn static inline void set_tx_dphy_testport_select (DPHY_TESTPORT_SELECT testport)
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\brief Test port select for dphy.
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\param[in] testport dphy CLKEXT divider selection to set.
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\return none.
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*/
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static inline void set_tx_dphy_testport_select (DPHY_TESTPORT_SELECT testport)
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{
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if(testport == DPHY_TESTPORT_SELECT_RX)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 |= DPHY_CTRL0_TESTPORT_SEL;
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}
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else
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 &= ~DPHY_CTRL0_TESTPORT_SEL;
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}
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}
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/**
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\fn static inline void set_rx_dphy_testport_select (DPHY_TESTPORT_SELECT testport)
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\brief Test port select for dphy.
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\param[in] testport dphy CLKEXT divider selection to set.
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\return none.
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*/
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static inline void set_rx_dphy_testport_select (DPHY_TESTPORT_SELECT testport)
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{
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if(testport == DPHY_TESTPORT_SELECT_RX)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 |= DPHY_CTRL0_TESTPORT_SEL;
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}
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else
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 &= ~DPHY_CTRL0_TESTPORT_SEL;
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}
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}
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/**
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\fn static inline void set_tx_dphy_hsfreqrange (uint32_t range)
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\brief Set dphy Module operating frequency.
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\param[in] range dphy hsfreqrange to set.
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\return none.
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*/
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static inline void set_tx_dphy_hsfreqrange (uint32_t range)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 &= ~DPHY_CTRL0_HSFREQRANGE_Msk;
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CLKCTL_PER_MST->TX_DPHY_CTRL0 |= (range << DPHY_CTRL0_HSFREQRANGE_Pos);
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}
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/**
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\fn static inline void set_rx_dphy_hsfreqrange (uint32_t range)
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\brief Set dphy Module operating frequency.
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\param[in] range dphy hsfreqrange to set.
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\return none.
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*/
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static inline void set_rx_dphy_hsfreqrange (uint32_t range)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 &= ~DPHY_CTRL0_HSFREQRANGE_Msk;
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CLKCTL_PER_MST->RX_DPHY_CTRL0 |= (range << DPHY_CTRL0_HSFREQRANGE_Pos);
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}
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/**
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\fn static inline void set_tx_dphy_cfgclkfreqrange (uint32_t range)
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\brief Set dphy Input configure clock frequency
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\param[in] range dphy cfgclkfreqrange to set.
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\return none.
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*/
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static inline void set_tx_dphy_cfgclkfreqrange (uint32_t range)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 &= ~DPHY_CTRL0_CFGCLKFREQRANGE_Msk;
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CLKCTL_PER_MST->TX_DPHY_CTRL0 |= (range << DPHY_CTRL0_CFGCLKFREQRANGE_Pos);
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}
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/**
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\fn static inline void set_rx_dphy_cfgclkfreqrange (uint32_t range)
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\brief Set dphy Input configure clock frequency
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\param[in] range dphy cfgclkfreqrange to set.
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\return none.
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*/
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static inline void set_rx_dphy_cfgclkfreqrange (uint32_t range)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 &= ~DPHY_CTRL0_CFGCLKFREQRANGE_Msk;
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CLKCTL_PER_MST->RX_DPHY_CTRL0 |= (range << DPHY_CTRL0_CFGCLKFREQRANGE_Pos);
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}
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/**
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\fn static inline void set_tx_dphy_basedir (DPHY_DATA_LANE lane)
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\brief Configures the base direction for dphy data lane
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\param[in] lane dphy base direction for data lane.
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\return none.
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*/
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static inline void set_tx_dphy_basedir (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 |= (lane << DPHY_CTRL0_BASEDIR_Pos);
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}
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/**
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\fn static inline void unset_tx_dphy_basedir (DPHY_DATA_LANE lane)
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\brief Configures the base direction for dphy data lane
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\param[in] lane dphy base direction for data lane.
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\return none.
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*/
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static inline void unset_tx_dphy_basedir (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 &= ~(lane << DPHY_CTRL0_BASEDIR_Pos);
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}
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/**
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\fn static inline void set_rx_dphy_basedir (DPHY_DATA_LANE lane)
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\brief Configures the base direction for dphy data lane
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\param[in] lane dphy base direction for data lane.
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\return none.
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*/
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static inline void set_rx_dphy_basedir (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 |= (lane << DPHY_CTRL0_BASEDIR_Pos);
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}
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/**
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\fn static inline void unset_rx_dphy_basedir (DPHY_DATA_LANE lane)
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\brief Configures the base direction for dphy data lane
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\param[in] lane dphy base direction for data lane.
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\return none.
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*/
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static inline void unset_rx_dphy_basedir (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 &= ~(lane << DPHY_CTRL0_BASEDIR_Pos);
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}
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/**
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\fn static inline void set_tx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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\brief Controls forcerxmode pin of dphy.
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\param[in] lane controls forcerxmode pin for data lane.
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\return none.
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*/
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static inline void set_tx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL1 |= (lane << DPHY_CTRL1_FORCERXMODE_Pos);
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}
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/**
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\fn static inline void unset_tx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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\brief Controls forcerxmode pin of dphy.
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\param[in] lane controls forcerxmode pin for data lane.
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\return none.
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*/
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static inline void unset_tx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL1 &= ~(lane << DPHY_CTRL1_FORCERXMODE_Pos);
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}
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/**
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\fn static inline void set_rx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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\brief Controls forcerxmode pin of dphy.
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\param[in] lane controls forcerxmode pin for data lane.
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\return none.
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*/
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static inline void set_rx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL1 |= (lane << DPHY_CTRL1_FORCERXMODE_Pos);
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}
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/**
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\fn static inline void unset_rx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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\brief Controls forcerxmode pin of dphy.
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\param[in] lane controls forcerxmode pin for data lane.
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\return none.
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*/
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static inline void unset_rx_dphy_forcerxmode (DPHY_DATA_LANE lane)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL1 &= ~(lane << DPHY_CTRL1_FORCERXMODE_Pos);
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}
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/**
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\fn static inline void enable_tx_dphy_bist_on (void)
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\brief Enable configure clock for TX D-PHY
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\return none.
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*/
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static inline void enable_tx_dphy_bist_on (void)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 |= DPHY_CTRL0_BIST_ON;
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}
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/**
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\fn static inline void disable_tx_dphy_bist_on (void)
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\brief Disable configure clock for TX D-PHY
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\return none.
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*/
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static inline void disable_tx_dphy_bist_on (void)
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{
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CLKCTL_PER_MST->TX_DPHY_CTRL0 &= ~DPHY_CTRL0_BIST_ON;
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}
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/**
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\fn static inline void enable_rx_dphy_bist_on (void)
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\brief Enable configure clock for RX D-PHY
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\return none.
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*/
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static inline void enable_rx_dphy_bist_on (void)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 |= DPHY_CTRL0_BIST_ON;
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}
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/**
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\fn static inline void disable_rx_dphy_bist_on (void)
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\brief Disable configure clock for TX D-PHY
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\return none.
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*/
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static inline void disable_rx_dphy_bist_on (void)
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{
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CLKCTL_PER_MST->RX_DPHY_CTRL0 &= ~DPHY_CTRL0_BIST_ON;
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}
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/**
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\fn static inline void disable_tx_dphy_bist_on (void)
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\brief Disable configure clock for TX D-PHY
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\return none.
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*/
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static inline DPHY_BIST_OK_STATUS get_tx_dphy_bist_ok (void)
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|
{
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return (CLKCTL_PER_MST->TX_DPHY_CTRL0 & DPHY_CTRL0_BIST_OK);
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}
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|
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/**
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\fn static inline void disable_rx_dphy_bist_on (void)
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\brief Disable configure clock for TX D-PHY
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|
\return none.
|
|
*/
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static inline DPHY_BIST_OK_STATUS get_rx_dphy_bist_ok (void)
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|
{
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return (CLKCTL_PER_MST->RX_DPHY_CTRL0 & DPHY_CTRL0_BIST_OK);
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|
}
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|
|
|
/**
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|
\fn static inline void enable_txdphy_configure_clock (void)
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\brief Enable configure clock for TX D-PHY
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|
\return none.
|
|
*/
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|
static inline void enable_txdphy_configure_clock (void)
|
|
{
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|
CLKCTL_PER_MST->MIPI_CKEN |= MIPI_CLKEN_TXDPHY_CKEN;
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|
}
|
|
|
|
/**
|
|
\fn static inline void disable_txdphy_configure_clock (void)
|
|
\brief Disable configure clock for TX D-PHY.
|
|
\return none.
|
|
*/
|
|
static inline void disable_txdphy_configure_clock (void)
|
|
{
|
|
CLKCTL_PER_MST->MIPI_CKEN &= ~MIPI_CLKEN_TXDPHY_CKEN;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void enable_rxdphy_configure_clock (void)
|
|
\brief Enable configure clock for RX D-PHY.
|
|
\return none.
|
|
*/
|
|
static inline void enable_rxdphy_configure_clock (void)
|
|
{
|
|
CLKCTL_PER_MST->MIPI_CKEN |= MIPI_CLKEN_RXDPHY_CKEN;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void disable_rxdphy_configure_clock (void)
|
|
\brief Disable configure clock for RX D-PHY.
|
|
\return none.
|
|
*/
|
|
static inline void disable_rxdphy_configure_clock (void)
|
|
{
|
|
CLKCTL_PER_MST->MIPI_CKEN &= ~MIPI_CLKEN_RXDPHY_CKEN;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void enable_dphy_pll_reference_clock (void)
|
|
\brief Enable reference clock for MIPI D-PHY PLL.
|
|
\return none.
|
|
*/
|
|
static inline void enable_dphy_pll_reference_clock (void)
|
|
{
|
|
CLKCTL_PER_MST->MIPI_CKEN |= MIPI_CLKEN_PLLREF_CKEN;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void disable_dphy_pll_reference_clock (void)
|
|
\brief Disable reference clock for MIPI D-PHY PLL.
|
|
\return none.
|
|
*/
|
|
static inline void disable_dphy_pll_reference_clock (void)
|
|
{
|
|
CLKCTL_PER_MST->MIPI_CKEN &= ~MIPI_CLKEN_PLLREF_CKEN;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void enable_dphy_pll_bypass_clock (void)
|
|
\brief Enable bypass clock for MIPI D-PHY PLL.
|
|
\return none.
|
|
*/
|
|
static inline void enable_dphy_pll_bypass_clock (void)
|
|
{
|
|
CLKCTL_PER_MST->MIPI_CKEN |= MIPI_CLKEN_BYPASS_CKEN;
|
|
}
|
|
|
|
/**
|
|
\fn static inline void disable_dphy_pll_bypass_clock (void)
|
|
\brief Disable bypass clock for MIPI D-PHY PLL.
|
|
\return none.
|
|
*/
|
|
static inline void disable_dphy_pll_bypass_clock (void)
|
|
{
|
|
CLKCTL_PER_MST->MIPI_CKEN &= ~MIPI_CLKEN_BYPASS_CKEN;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif /* SYS_CTRL_DPHY_H_ */
|