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593 lines
32 KiB
C
593 lines
32 KiB
C
/**
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******************************************************************************
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* @file ll_aton_rcompat.h
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* @author SRA Artificial Intelligence & Embedded Architectures
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* @brief Backward compatibility layer for raSTa flow.
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* Enables using ATON.h files generated by old regparser.
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* Tested with N6 RTL.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2024 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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#ifndef __LL_ATON_COMPAT_H
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#define __LL_ATON_COMPAT_H
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/* Macros not yet defined in ATON.h
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* TODO: add them to raSTa generation
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*/
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#ifndef ATON_DECUN_MEM_LOW_DT
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#define ATON_DECUN_MEM_LOW_IDX_MIN (0)
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#define ATON_DECUN_MEM_LOW_IDX_MAX (256 - 1)
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#define ATON_DECUN_MEM_LOW_ADDR(UNIT, IDX) (ATON_DECUN_BASE(UNIT) + 0x800 + 8 * (IDX))
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#define ATON_DECUN_MEM_LOW_DT (0)
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#define ATON_DECUN_MEM_LOW_SET_MOD8_0(REG, DATA) ATON_SET_FIELD(REG, 0UL, 8UL, DATA)
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#define ATON_DECUN_MEM_LOW_SET_MOD8_1(REG, DATA) ATON_SET_FIELD(REG, 8UL, 8UL, DATA)
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#define ATON_DECUN_MEM_LOW_SET_MOD8_2(REG, DATA) ATON_SET_FIELD(REG, 16UL, 8UL, DATA)
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#define ATON_DECUN_MEM_LOW_SET_MOD8_3(REG, DATA) ATON_SET_FIELD(REG, 24UL, 8UL, DATA)
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#define ATON_DECUN_MEM_LOW_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_DECUN_MEM_LOW_ADDR(UNIT, IDX), (DATA))
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#endif
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#ifndef ATON_DECUN_MEM_HIGH_DT
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#define ATON_DECUN_MEM_HIGH_IDX_MIN (0)
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#define ATON_DECUN_MEM_HIGH_IDX_MAX (256 - 1)
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#define ATON_DECUN_MEM_HIGH_ADDR(UNIT, IDX) (ATON_DECUN_BASE(UNIT) + 0x800 + 8 * (IDX) + 4)
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#define ATON_DECUN_MEM_HIGH_DT (0)
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#define ATON_DECUN_MEM_HIGH_SET_MOD8_0(REG, DATA) ATON_SET_FIELD(REG, 0UL, 8UL, DATA)
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#define ATON_DECUN_MEM_HIGH_SET_MOD8_1(REG, DATA) ATON_SET_FIELD(REG, 8UL, 8UL, DATA)
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#define ATON_DECUN_MEM_HIGH_SET_MOD8_2(REG, DATA) ATON_SET_FIELD(REG, 16UL, 8UL, DATA)
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#define ATON_DECUN_MEM_HIGH_SET_MOD8_3(REG, DATA) ATON_SET_FIELD(REG, 24UL, 8UL, DATA)
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#define ATON_DECUN_MEM_HIGH_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_DECUN_MEM_HIGH_ADDR(UNIT, IDX), (DATA))
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#endif
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#ifndef RASTA_SVN_REV
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/** Generic macros
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*/
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#define ATON_ADDR_SPACE_SIZE ATON_SIZE
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/** Interrupt controller macros
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*/
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#define ATON_INTCTRL_INTS(UNIT) ATON_INT_NR
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#define ATON_STRENG_INT(IDX) ATON_STRENG##IDX##_INT
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#define ATON_INTCTRL_INTORMSK_OFFSET(UNIT, IOM) (((IOM) >= 0) && ((IOM) <= 3) ? (0x4 * (IOM) + UINT32_C(0x14)) : 0)
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#define ATON_INTCTRL_INTORMSK_ADDR(UNIT, IOM) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTORMSK_OFFSET(UNIT, IOM))
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#define ATON_INTCTRL_INTORMSK_GET(UNIT, IOM) ATON_GET_REG32(ATON_INTCTRL_INTORMSK_ADDR(UNIT, IOM))
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#define ATON_INTCTRL_INTORMSK_SET(UNIT, IOM, DATA) \
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do \
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{ \
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ATON_SET_REG32(ATON_INTCTRL_INTORMSK_ADDR(UNIT, IOM), DATA); \
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} while (0)
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#define ATON_INTCTRL_INTANDMSK_OFFSET(UNIT, IAM) (((IAM) >= 0) && ((IAM) <= 3) ? (0x4 * (IAM) + UINT32_C(0x24)) : 0)
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#define ATON_INTCTRL_INTANDMSK_ADDR(UNIT, IAM) (ATON_INTCTRL_BASE(UNIT) + ATON_INTCTRL_INTANDMSK_OFFSET(UNIT, IAM))
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#define ATON_INTCTRL_INTANDMSK_GET(UNIT, IAM) ATON_GET_REG32(ATON_INTCTRL_INTANDMSK_ADDR(UNIT, IAM))
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#define ATON_INTCTRL_INTANDMSK_SET(UNIT, IAM, DATA) \
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do \
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{ \
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ATON_SET_REG32(ATON_INTCTRL_INTANDMSK_ADDR(UNIT, IAM), DATA); \
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} while (0)
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#define ATON_STRENG_INT_MASK(UNIT, INDEX, DATA) ATON_STRENG_INT_GET_MASK(UNIT, DATA)
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#define ATON_STRENG_ERR_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_STRENG_ERR_INT_GET_MASK(UNIT, REG_IDX)
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#define ATON_STRSWITCH_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_STRSWITCH_INT_GET_MASK(UNIT, REG_IDX)
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#define ATON_BUSIF_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_BUSIF_INT_GET_MASK(UNIT, REG_IDX)
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#if (ATON_INT_NR > 32)
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#define ATON_INT_GET_MASK(_macro_, _unit_) (_macro_(_unit_, 0, 0) | (((uint64_t)_macro_(_unit_, 1, 0)) << 32))
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#define __ATON_INTCTRL_INTORMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTORMSK_H_SET(IDX, DATA)
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#define __ATON_INTCTRL_INTANDMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTANDMSK_H_SET(IDX, DATA)
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#else //(ATON_INT_NR <= 32)
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#define ATON_INT_GET_MASK(_macro_, _unit_) _macro_(_unit_, 0, 0)
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#endif //(ATON_INT_NR <= 32)
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#define ATON_INTCTRL_0_INTSET_STRENG_0_0_IDX ATON_STRENG0_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_1_0_IDX ATON_STRENG1_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_2_0_IDX ATON_STRENG2_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_3_0_IDX ATON_STRENG3_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_4_0_IDX ATON_STRENG4_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_5_0_IDX ATON_STRENG5_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_6_0_IDX ATON_STRENG6_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_7_0_IDX ATON_STRENG7_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_8_0_IDX ATON_STRENG8_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_9_0_IDX ATON_STRENG9_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_0_1_IDX ATON_STRENG0_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_1_1_IDX ATON_STRENG1_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_2_1_IDX ATON_STRENG2_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_3_1_IDX ATON_STRENG3_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_4_1_IDX ATON_STRENG4_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_5_1_IDX ATON_STRENG5_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_6_1_IDX ATON_STRENG6_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_7_1_IDX ATON_STRENG7_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_8_1_IDX ATON_STRENG8_ERR_INT
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#define ATON_INTCTRL_0_INTSET_STRENG_9_1_IDX ATON_STRENG9_ERR_INT
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#define ATON_INTCTRL_0_INTSET_CONVACC_0_IDX ATON_CONVACC0_INT
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#define ATON_INTCTRL_0_INTSET_CONVACC_1_IDX ATON_CONVACC1_INT
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#define ATON_INTCTRL_0_INTSET_CONVACC_2_IDX ATON_CONVACC2_INT
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#define ATON_INTCTRL_0_INTSET_CONVACC_3_IDX ATON_CONVACC3_INT
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#define ATON_INTCTRL_0_INTSET_BUSIF_0_IDX ATON_BUSIF0_INT
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#define ATON_INTCTRL_0_INTSET_BUSIF_1_IDX ATON_BUSIF1_INT
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#define ATON_INTCTRL_0_INTSET_STRSWITCH_0_IDX ATON_STRSWITCH_INT
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#define ATON_INTCTRL_0_INTSET_EPOCHCTRL_0_0_IDX ATON_EPOCHCTRL0_INT
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#define ATON_INTCTRL_0_INTSET_EPOCHCTRL_0_1_IDX ATON_EPOCHCTRL0_NOACK_INT
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#define ATON_INTCTRL_0_INTSET_EPOCHCTRL_0_2_IDX ATON_EPOCHCTRL0_ERR_INT
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#define ATON_INTCTRL_0_INTSET_DEBUG_TRACE_0_IDX ATON_DEBUG_TRACE0_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_0_0_IDX ATON_STRENG0_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_1_0_IDX ATON_STRENG1_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_2_0_IDX ATON_STRENG2_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_3_0_IDX ATON_STRENG3_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_4_0_IDX ATON_STRENG4_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_5_0_IDX ATON_STRENG5_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_6_0_IDX ATON_STRENG6_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_7_0_IDX ATON_STRENG7_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_8_0_IDX ATON_STRENG8_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_9_0_IDX ATON_STRENG9_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_0_1_IDX ATON_STRENG0_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_1_1_IDX ATON_STRENG1_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_2_1_IDX ATON_STRENG2_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_3_1_IDX ATON_STRENG3_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_4_1_IDX ATON_STRENG4_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_5_1_IDX ATON_STRENG5_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_6_1_IDX ATON_STRENG6_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_7_1_IDX ATON_STRENG7_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_8_1_IDX ATON_STRENG8_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_STRENG_9_1_IDX ATON_STRENG9_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_CONVACC_0_IDX ATON_CONVACC0_INT
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#define ATON_INTCTRL_0_INTCLR_CONVACC_1_IDX ATON_CONVACC1_INT
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#define ATON_INTCTRL_0_INTCLR_CONVACC_2_IDX ATON_CONVACC2_INT
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#define ATON_INTCTRL_0_INTCLR_CONVACC_3_IDX ATON_CONVACC3_INT
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#define ATON_INTCTRL_0_INTCLR_BUSIF_0_IDX ATON_BUSIF0_INT
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#define ATON_INTCTRL_0_INTCLR_BUSIF_1_IDX ATON_BUSIF1_INT
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#define ATON_INTCTRL_0_INTCLR_STRSWITCH_0_IDX ATON_STRSWITCH_INT
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#define ATON_INTCTRL_0_INTCLR_EPOCHCTRL_0_0_IDX ATON_EPOCHCTRL0_INT
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#define ATON_INTCTRL_0_INTCLR_EPOCHCTRL_0_1_IDX ATON_EPOCHCTRL0_NOACK_INT
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#define ATON_INTCTRL_0_INTCLR_EPOCHCTRL_0_2_IDX ATON_EPOCHCTRL0_ERR_INT
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#define ATON_INTCTRL_0_INTCLR_DEBUG_TRACE_0_IDX ATON_DEBUG_TRACE0_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_0_0_IDX ATON_STRENG0_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_1_0_IDX ATON_STRENG1_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_2_0_IDX ATON_STRENG2_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_3_0_IDX ATON_STRENG3_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_4_0_IDX ATON_STRENG4_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_5_0_IDX ATON_STRENG5_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_6_0_IDX ATON_STRENG6_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_7_0_IDX ATON_STRENG7_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_8_0_IDX ATON_STRENG8_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_9_0_IDX ATON_STRENG9_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_0_1_IDX ATON_STRENG0_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_1_1_IDX ATON_STRENG1_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_2_1_IDX ATON_STRENG2_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_3_1_IDX ATON_STRENG3_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_4_1_IDX ATON_STRENG4_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_5_1_IDX ATON_STRENG5_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_6_1_IDX ATON_STRENG6_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_7_1_IDX ATON_STRENG7_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_8_1_IDX ATON_STRENG8_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_STRENG_9_1_IDX ATON_STRENG9_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_CONVACC_0_IDX ATON_CONVACC0_INT
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#define ATON_INTCTRL_0_INTORMSK_CONVACC_1_IDX ATON_CONVACC1_INT
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#define ATON_INTCTRL_0_INTORMSK_CONVACC_2_IDX ATON_CONVACC2_INT
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#define ATON_INTCTRL_0_INTORMSK_CONVACC_3_IDX ATON_CONVACC3_INT
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#define ATON_INTCTRL_0_INTORMSK_BUSIF_0_IDX ATON_BUSIF0_INT
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#define ATON_INTCTRL_0_INTORMSK_BUSIF_1_IDX ATON_BUSIF1_INT
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#define ATON_INTCTRL_0_INTORMSK_STRSWITCH_0_IDX ATON_STRSWITCH_INT
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#define ATON_INTCTRL_0_INTORMSK_EPOCHCTRL_0_0_IDX ATON_EPOCHCTRL0_INT
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#define ATON_INTCTRL_0_INTORMSK_EPOCHCTRL_0_1_IDX ATON_EPOCHCTRL0_NOACK_INT
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#define ATON_INTCTRL_0_INTORMSK_EPOCHCTRL_0_2_IDX ATON_EPOCHCTRL0_ERR_INT
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#define ATON_INTCTRL_0_INTORMSK_DEBUG_TRACE_0_IDX ATON_DEBUG_TRACE0_INT
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/**
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* Stream Switch macros
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*/
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#define ATON_STRSWITCH_0_LINK_STRENG_0_0 ATON_LINK_STRENG0
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#define ATON_STRSWITCH_0_LINK_STRENG_1_0 ATON_LINK_STRENG1
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#define ATON_STRSWITCH_0_LINK_STRENG_2_0 ATON_LINK_STRENG2
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#define ATON_STRSWITCH_0_LINK_STRENG_3_0 ATON_LINK_STRENG3
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#if defined(ATON_LINK_STRENG4)
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#define ATON_STRSWITCH_0_LINK_STRENG_4_0 ATON_LINK_STRENG4
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#define ATON_STRSWITCH_0_LINK_STRENG_5_0 ATON_LINK_STRENG5
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#endif
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#if defined(ATON_LINK_STRENG6)
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#define ATON_STRSWITCH_0_LINK_STRENG_6_0 ATON_LINK_STRENG6
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#define ATON_STRSWITCH_0_LINK_STRENG_7_0 ATON_LINK_STRENG7
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#define ATON_STRSWITCH_0_LINK_STRENG_8_0 ATON_LINK_STRENG8
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#define ATON_STRSWITCH_0_LINK_STRENG_9_0 ATON_LINK_STRENG9
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#endif
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#ifdef ATON_CONVACC_NUM
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#define ATON_CONVACC_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_CONVACC_INT_GET_MASK(UNIT, REG_IDX)
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#define ATON_STRSWITCH_0_LINK_CONVACC_0_0 ATON_LINK_CONVACC0
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#define ATON_STRSWITCH_0_LINK_CONVACC_1_0 ATON_LINK_CONVACC1
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#if defined(ATON_LINK_CONVACC2)
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#define ATON_STRSWITCH_0_LINK_CONVACC_2_0 ATON_LINK_CONVACC2
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#define ATON_STRSWITCH_0_LINK_CONVACC_3_0 ATON_LINK_CONVACC3
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#endif // ATON_LINK_CONVACC2
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#endif // ATON_CONVACC_NUM
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#ifdef ATON_ARITH_NUM
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#if defined(ATON_LINK_ARITH0)
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#define ATON_STRSWITCH_0_LINK_ARITH_0_0 ATON_LINK_ARITH0
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#endif
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#if defined(ATON_LINK_ARITH1)
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#define ATON_STRSWITCH_0_LINK_ARITH_1_0 ATON_LINK_ARITH1
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#endif
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#if defined(ATON_LINK_ARITH2)
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#define ATON_STRSWITCH_0_LINK_ARITH_2_0 ATON_LINK_ARITH2
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#endif
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#if defined(ATON_LINK_ARITH3)
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#define ATON_STRSWITCH_0_LINK_ARITH_3_0 ATON_LINK_ARITH3
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#endif
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#endif // ATON_ARITH_NUM
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#ifdef ATON_POOL_NUM
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#if defined(ATON_LINK_POOL0)
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#define ATON_STRSWITCH_0_LINK_POOL_0_0 ATON_LINK_POOL0
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#endif
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#if defined(ATON_LINK_POOL1)
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#define ATON_STRSWITCH_0_LINK_POOL_1_0 ATON_LINK_POOL1
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#endif
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#if defined(ATON_LINK_POOL2)
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#define ATON_STRSWITCH_0_LINK_POOL_2_0 ATON_LINK_POOL2
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#endif
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#endif // ATON_POOL_NUM
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#ifdef ATON_ACTIV_NUM
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#if defined(ATON_LINK_ACTIV0)
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#define ATON_STRSWITCH_0_LINK_ACTIV_0_0 ATON_LINK_ACTIV0
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#endif
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#if defined(ATON_LINK_ACTIV1)
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#define ATON_STRSWITCH_0_LINK_ACTIV_1_0 ATON_LINK_ACTIV1
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#endif
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#if defined(ATON_LINK_ACTIV2)
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#define ATON_STRSWITCH_0_LINK_ACTIV_2_0 ATON_LINK_ACTIV2
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#endif
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#endif // ATON_ACTIV_NUM
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#ifdef ATON_DECUN_NUM
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#define ATON_STRSWITCH_0_LINK_DECUN_0_0 ATON_LINK_DECUN0
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#if defined(ATON_LINK_DECUN1)
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#define ATON_STRSWITCH_0_LINK_DECUN_1_0 ATON_LINK_DECUN1
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#endif
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#if defined(ATON_LINK_DECUN2)
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#define ATON_STRSWITCH_0_LINK_DECUN_2_0 ATON_LINK_DECUN2
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#endif
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#endif // ATON_DECUN_NUM
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#ifdef ATON_IMC_NUM
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#define ATON_STRSWITCH64_0_LINK_IMC_0_0 ATON_LINK_IMC00
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#define ATON_STRSWITCH64_0_LINK_IMC_0_1 ATON_LINK_IMC01
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#define ATON_STRSWITCH64_0_LINK_IMC_0_2 ATON_LINK_IMC02
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#define ATON_STRSWITCH64_0_LINK_IMC_0_3 ATON_LINK_IMC03
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#define ATON_STRSWITCH64_0_LINK_IMC_0_4 ATON_LINK_IMC04
|
|
#define ATON_STRSWITCH64_0_LINK_IMC_0_5 ATON_LINK_IMC05
|
|
#define ATON_STRSWITCH64_0_LINK_IMC_0_6 ATON_LINK_IMC06
|
|
#define ATON_STRSWITCH64_0_LINK_IMC_0_7 ATON_LINK_IMC07
|
|
#define ATON_STRSWITCH64_0_LINK_IMC_0_8 ATON_LINK_IMC08
|
|
#define ATON_STRSWITCH64_0_LINK_IMC_0_9 ATON_LINK_IMC09
|
|
#endif
|
|
|
|
#if defined(ATON_DEBUG_TRACE_NUM)
|
|
#define ATON_DEBUG_TRACE_CLKB_CLK(UNIT) ATON_DEBUG_TRACE0_CLK_CLKB
|
|
#undef ATON_DEBUG_TRACE_CTRL_DT
|
|
#define ATON_DEBUG_TRACE_CTRL_DT(UNIT) 0
|
|
#endif
|
|
|
|
#ifdef ATON_RECBUF_NUM
|
|
#define ATON_RECBUF_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_RECBUF_INT_GET_MASK(UNIT, REG_IDX)
|
|
#endif
|
|
|
|
#ifdef ATON_EPOCHCTRL_NUM
|
|
#define ATON_EPOCHCTRL_ERR_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_EPOCHCTRL_ERR_INT_GET_MASK(UNIT, REG_IDX)
|
|
#define ATON_EPOCHCTRL_NOACK_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_EPOCHCTRL_NOACK_INT_GET_MASK(UNIT, REG_IDX)
|
|
#define ATON_EPOCHCTRL_INT_MASK(UNIT, INTCTRL, REG_IDX) ATON_EPOCHCTRL_INT_GET_MASK(UNIT, REG_IDX)
|
|
#endif
|
|
|
|
#if defined(ATON_LINK_CONVACC2)
|
|
// compiling for N6 4CA // FIXME this is a very shallow check
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_0_0_IDX 0
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_1_0_IDX 1
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_2_0_IDX 2
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_3_0_IDX 3
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_4_0_IDX 4
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_5_0_IDX 5
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_6_0_IDX 6
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_7_0_IDX 7
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_8_0_IDX 8
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_9_0_IDX 9
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_0_0_IDX 10
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_0_1_IDX 11
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_0_2_IDX 12
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_1_0_IDX 13
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_1_1_IDX 14
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_1_2_IDX 15
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_2_0_IDX 16
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_2_1_IDX 17
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_2_2_IDX 18
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_3_0_IDX 19
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_3_1_IDX 20
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_3_2_IDX 21
|
|
#define ATON_STRSWITCH_0_DSTDECUN_0_0_IDX 22
|
|
#define ATON_STRSWITCH_0_DSTDECUN_0_1_IDX 23
|
|
#define ATON_STRSWITCH_0_DSTDECUN_1_0_IDX 24
|
|
#define ATON_STRSWITCH_0_DSTDECUN_1_1_IDX 25
|
|
#define ATON_STRSWITCH_0_DSTACTIV_0_0_IDX 26
|
|
#define ATON_STRSWITCH_0_DSTACTIV_1_0_IDX 27
|
|
#define ATON_STRSWITCH_0_DSTARITH_0_0_IDX 28
|
|
#define ATON_STRSWITCH_0_DSTARITH_0_1_IDX 29
|
|
#define ATON_STRSWITCH_0_DSTARITH_1_0_IDX 30
|
|
#define ATON_STRSWITCH_0_DSTARITH_1_1_IDX 31
|
|
#define ATON_STRSWITCH_0_DSTARITH_2_0_IDX 32
|
|
#define ATON_STRSWITCH_0_DSTARITH_2_1_IDX 33
|
|
#define ATON_STRSWITCH_0_DSTARITH_3_0_IDX 34
|
|
#define ATON_STRSWITCH_0_DSTARITH_3_1_IDX 35
|
|
#define ATON_STRSWITCH_0_DSTPOOL_0_0_IDX 36
|
|
#define ATON_STRSWITCH_0_DSTPOOL_1_0_IDX 37
|
|
#define ATON_STRSWITCH_0_DSTRECBUF_0_0_IDX 38
|
|
#define ATON_STRSWITCH_0_DSTRECBUF_0_1_IDX 39
|
|
#define ATON_STRSWITCH_0_DSTRECBUF_0_2_IDX 40
|
|
// additional destination indices for old ATON.h of hybrid RTL
|
|
#ifdef ATON_IMC_NUM
|
|
#define ATON_STRSWITCH_0_DSTSSCONN_0_0_IDX 41
|
|
#define ATON_STRSWITCH_0_DSTSSCONN_1_0_IDX 42
|
|
#define ATON_STRSWITCH_0_DSTSSCONN_2_0_IDX 43
|
|
#define ATON_STRSWITCH_0_DSTSSCONN_3_0_IDX 44
|
|
#endif // ATON_IMC_NUM
|
|
|
|
#else
|
|
// compiling for tiny N6 (2CA)
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_0_0_IDX 0
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_1_0_IDX 1
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_2_0_IDX 2
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_3_0_IDX 3
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_4_0_IDX 4
|
|
#define ATON_STRSWITCH_0_DSTSTRENG_5_0_IDX 5
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_0_0_IDX 6
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_0_1_IDX 7
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_0_2_IDX 8
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_1_0_IDX 9
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_1_1_IDX 10
|
|
#define ATON_STRSWITCH_0_DSTCONVACC_1_2_IDX 11
|
|
#define ATON_STRSWITCH_0_DSTDECUN_0_0_IDX 12
|
|
#define ATON_STRSWITCH_0_DSTDECUN_0_1_IDX 13
|
|
#define ATON_STRSWITCH_0_DSTACTIV_0_0_IDX 14
|
|
#define ATON_STRSWITCH_0_DSTARITH_0_0_IDX 15
|
|
#define ATON_STRSWITCH_0_DSTARITH_0_1_IDX 16
|
|
#define ATON_STRSWITCH_0_DSTPOOL_0_0_IDX 17
|
|
#define ATON_STRSWITCH_0_DSTRECBUF_0_0_IDX 18
|
|
#define ATON_STRSWITCH_0_DSTRECBUF_0_1_IDX 19
|
|
#define ATON_STRSWITCH_0_DSTRECBUF_0_2_IDX 20
|
|
#endif
|
|
|
|
/* Compute offset instead of doing 40 ifs */
|
|
#define ATON_STRSWITCH_DST_OFFSET(UNIT, IDX) (ATON_STRSWITCH_DSTSTRENG0_OFFSET + ((IDX) << 2))
|
|
|
|
#define ATON_STRSWITCH_DST_EN0_LSB ATON_STRSWITCH_DSTSTRENG1_EN0_LSB
|
|
#define ATON_STRSWITCH_DST_EN1_LSB ATON_STRSWITCH_DSTSTRENG1_EN1_LSB
|
|
#define ATON_STRSWITCH_DST_LINK0_LSB ATON_STRSWITCH_DSTSTRENG0_LINK0_LSB
|
|
#define ATON_STRSWITCH_DST_LINK1_LSB ATON_STRSWITCH_DSTSTRENG0_LINK1_LSB
|
|
#define ATON_STRSWITCH_DST_FNR0_LSB ATON_STRSWITCH_DSTSTRENG0_FNR0_LSB
|
|
#define ATON_STRSWITCH_DST_FNR1_LSB ATON_STRSWITCH_DSTSTRENG0_FNR1_LSB
|
|
#define ATON_STRSWITCH_DST_FNR0_MASK ATON_STRSWITCH_DSTSTRENG0_FNR0_MASK
|
|
#define ATON_STRSWITCH_DST_FNR1_MASK ATON_STRSWITCH_DSTSTRENG0_FNR1_MASK
|
|
|
|
/** Debug and Trace Unit macros
|
|
*/
|
|
#define ATON_DEBUG_TRACE_TRIG_ADDR(UNIT, IDX) (ATON_DEBUG_TRACE_TRIG_0_ADDR(UNIT) + ((IDX) << 2))
|
|
#define ATON_DEBUG_TRACE_EVENT_ADDR(UNIT, IDX) (ATON_DEBUG_TRACE_EVENT_0_ADDR(UNIT) + ((IDX) << 2))
|
|
#define ATON_DEBUG_TRACE_EVENT_CNT_ADDR(UNIT, IDX) (ATON_DEBUG_TRACE_EVENT_0_CNT_ADDR(UNIT) + ((IDX) << 2))
|
|
|
|
#define ATON_DEBUG_TRACE_TRIG_DT ATON_DEBUG_TRACE_TRIG_0_DT
|
|
#define ATON_DEBUG_TRACE_EVENT_DT ATON_DEBUG_TRACE_EVENT_0_DT
|
|
#define ATON_DEBUG_TRACE_TRIG_SET_SEL(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_SEL(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_TRIG_SET_EVENT_TYPE(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_EVENT_TYPE(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_TRIG_SET_FILTER(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_FILTER(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_TRIG_SET_EN(REG, DATA) ATON_DEBUG_TRACE_TRIG_0_SET_EN(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_SEL(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_SEL(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_EVENT_TYPE(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_EVENT_TYPE(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_WRAP(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_WRAP(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_CNT_DOWN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_CNT_DOWN(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_EN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_EN(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_INT_DISABLE(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_INT_DISABLE(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_START_EVENT_EN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_START_EVENT_SEL(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_STOP_EVENT_EN(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_EN(REG, DATA)
|
|
#define ATON_DEBUG_TRACE_EVENT_SET_STOP_EVENT_SEL(REG, DATA) ATON_DEBUG_TRACE_EVENT_0_SET_START_EVENT_SEL(REG, DATA)
|
|
|
|
#define ATON_DEBUG_TRACE_TRIG_OVR_MASK ATON_DEBUG_TRACE_TRIG_0_OVR_MASK
|
|
#define ATON_DEBUG_TRACE_TRIG_SWTRIG_LSB ATON_DEBUG_TRACE_TRIG_0_SWTRIG_LSB
|
|
|
|
#define ATON_DEBUG_TRACE_ILINK_STATES_GET(unit, idx) \
|
|
(idx == 0 ? ATON_DEBUG_TRACE_LOW_ILINK_STATES_GET(unit) : ATON_DEBUG_TRACE_HIGH_ILINK_STATES_GET(unit))
|
|
#define ATON_DEBUG_TRACE_OLINK_STATES_GET(unit, idx) \
|
|
(idx == 0 ? ATON_DEBUG_TRACE_LOW_OLINK_STATES_GET(unit) : ATON_DEBUG_TRACE_HIGH_OLINK_STATES_GET(unit))
|
|
#define ATON_DEBUG_TRACE_ILINK_STATES_IDX_MAX(id) 1
|
|
#define ATON_DEBUG_TRACE_OLINK_STATES_IDX_MAX(id) 1
|
|
|
|
/**
|
|
* Bus Interface crypto engine macros: straight from raSTa header
|
|
*/
|
|
#define ATON_BUSIF_0_KEY0_31_0_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_31_0_S 0
|
|
#define ATON_BUSIF_0_KEY0_63_32_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_63_32_S 1
|
|
#define ATON_BUSIF_0_KEY0_95_64_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_95_64_S 2
|
|
#define ATON_BUSIF_0_KEY0_127_96_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_127_96_S 3
|
|
#define ATON_BUSIF_0_KEY1_31_0_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_31_0_S 0
|
|
#define ATON_BUSIF_0_KEY1_63_32_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_63_32_S 1
|
|
#define ATON_BUSIF_0_KEY1_95_64_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_95_64_S 2
|
|
#define ATON_BUSIF_0_KEY1_127_96_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_127_96_S 3
|
|
#define ATON_BUSIF_0_KEY0_31_0_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_31_0_S 0
|
|
#define ATON_BUSIF_0_KEY0_63_32_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_63_32_S 1
|
|
#define ATON_BUSIF_0_KEY0_95_64_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_95_64_S 2
|
|
#define ATON_BUSIF_0_KEY0_127_96_IDX 0
|
|
#define ATON_BUSIF_0_KEY0_127_96_S 3
|
|
#define ATON_BUSIF_0_KEY1_31_0_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_31_0_S 0
|
|
#define ATON_BUSIF_0_KEY1_63_32_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_63_32_S 1
|
|
#define ATON_BUSIF_0_KEY1_95_64_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_95_64_S 2
|
|
#define ATON_BUSIF_0_KEY1_127_96_IDX 1
|
|
#define ATON_BUSIF_0_KEY1_127_96_S 3
|
|
|
|
#ifndef ATON_HIDE_REG_MACROS
|
|
#define ATON_GET_REG32(ADDR) (*((volatile uint32_t *)(uintptr_t)(ADDR)))
|
|
|
|
#define ATON_SET_REG32(ADDR, DATA) \
|
|
do \
|
|
{ \
|
|
*((volatile uint32_t *)(uintptr_t)(ADDR)) = (DATA); \
|
|
} while (0);
|
|
#endif // #ifndef ATON_HIDE_REG_MACROS
|
|
|
|
#define ATON_BUSIF_KEY_OFFSET(UNIT, IDX, S) \
|
|
(((IDX) == 0) && ((S) == 0) ? 0x14UL \
|
|
: ((IDX) == 0) && ((S) == 1) ? 0x18UL \
|
|
: ((IDX) == 0) && ((S) == 2) ? 0x1cUL \
|
|
: ((IDX) == 0) && ((S) == 3) ? 0x20UL \
|
|
: ((IDX) == 1) && ((S) == 0) ? 0x24UL \
|
|
: ((IDX) == 1) && ((S) == 1) ? 0x28UL \
|
|
: ((IDX) == 1) && ((S) == 2) ? 0x2cUL \
|
|
: ((IDX) == 1) && ((S) == 3) ? 0x30UL \
|
|
: 0)
|
|
|
|
#define ATON_BUSIF_KEY_ADDR(UNIT, IDX, S) (ATON_BUSIF_BASE(UNIT) + ATON_BUSIF_KEY_OFFSET(UNIT, IDX, S))
|
|
#define ATON_BUSIF_KEY_SET(UNIT, IDX, S, DATA) ATON_SET_REG32(ATON_BUSIF_KEY_ADDR(UNIT, IDX, S), DATA)
|
|
|
|
/*
|
|
* STRENG ENCR registers, macros copied from RaSTa-produced ATON.h
|
|
*/
|
|
#ifndef ATON_STRENG_ENCR_LSB_SET
|
|
|
|
#define ATON_STRENG_ENCR_LSB_SET(UNIT, DATA) ATON_SET_REG32(ATON_STRENG_ENCR_LSB_ADDR(UNIT), DATA)
|
|
#define ATON_STRENG_ENCR_MSB_SET_ID_MSB(REG, DATA) \
|
|
ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ID_MSB_LSB, ATON_STRENG_ENCR_MSB_ID_MSB_W, DATA)
|
|
#define ATON_STRENG_ENCR_MSB_SET_EN(REG, DATA) \
|
|
ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_EN_LSB, ATON_STRENG_ENCR_MSB_EN_W, DATA)
|
|
#define ATON_STRENG_ENCR_MSB_SET_ROUNDS(REG, DATA) \
|
|
ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_ROUNDS_LSB, ATON_STRENG_ENCR_MSB_ROUNDS_W, DATA)
|
|
#define ATON_STRENG_ENCR_MSB_SET_KEY_SEL(REG, DATA) \
|
|
ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_KEY_SEL_LSB, ATON_STRENG_ENCR_MSB_KEY_SEL_W, DATA)
|
|
#define ATON_STRENG_ENCR_MSB_SET_INC(REG, DATA) \
|
|
ATON_SET_FIELD(REG, ATON_STRENG_ENCR_MSB_INC_LSB, ATON_STRENG_ENCR_MSB_INC_W, DATA)
|
|
#define ATON_STRENG_ENCR_MSB_SET(UNIT, DATA) ATON_SET_REG32(ATON_STRENG_ENCR_MSB_ADDR(UNIT), DATA)
|
|
|
|
#endif
|
|
|
|
/** Clock gating macros
|
|
*/
|
|
#define ATON_STRENG_CLKB_CLK(X) (ATON_STRENG0_CLK_CLKB + X)
|
|
#define ATON_CONVACC_CLKB_CLK(X) (ATON_CONVACC0_CLK_CLKB + X)
|
|
#define ATON_DECUN_CLKB_CLK(X) (ATON_DECUN0_CLK_CLKB + X)
|
|
#define ATON_ACTIV_CLKB_CLK(X) (ATON_ACTIV0_CLK_CLKB + X)
|
|
#define ATON_ARITH_CLKB_CLK(X) (ATON_ARITH0_CLK_CLKB + X)
|
|
#define ATON_POOL_CLKB_CLK(X) (ATON_POOL0_CLK_CLKB + X)
|
|
#define ATON_RECBUF_CLKB_CLK(X) (ATON_RECBUF0_CLK_CLKB + X)
|
|
#define ATON_EPOCHCTRL_CLKB_CLK(X) (ATON_EPOCHCTRL0_CLK_CLKB + X)
|
|
|
|
/** Coefficients tables offset macros
|
|
*/
|
|
#define ATON_ACTIV_ROM0_IDX_MIN (0)
|
|
#define ATON_ACTIV_ROM0_IDX_MAX (32 - 1)
|
|
#define ATON_ACTIV_ROM0_OFFSET(UNIT, IDX) (ATON_ACTIV_ROM_OFFSET_0 + 4 * (IDX))
|
|
#define ATON_ACTIV_ROM0_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM0_OFFSET(UNIT, IDX))
|
|
#define ATON_ACTIV_ROM0_DT (0x0)
|
|
#define ATON_ACTIV_ROM0_SET_ENTRY(REG, DATA) ATON_SET_FIELD(REG, 0UL, 8UL, DATA)
|
|
#define ATON_ACTIV_ROM0_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ACTIV_ROM0_ADDR(UNIT, IDX), (DATA))
|
|
#define ATON_ACTIV_ROM0_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM0_OFFSET(UNIT, IDX))
|
|
|
|
#define ATON_ACTIV_ROM1_AB_IDX_MIN (0)
|
|
#define ATON_ACTIV_ROM1_AB_IDX_MAX (64 - 1)
|
|
#define ATON_ACTIV_ROM1_AB_OFFSET(UNIT, IDX) (ATON_ACTIV_ROM_OFFSET_1 + 8 * (IDX))
|
|
#define ATON_ACTIV_ROM1_AB_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM1_AB_OFFSET(UNIT, IDX))
|
|
#define ATON_ACTIV_ROM1_AB_DT (0x0)
|
|
#define ATON_ACTIV_ROM1_AB_SET_A(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA)
|
|
#define ATON_ACTIV_ROM1_AB_SET_B(REG, DATA) ATON_SET_FIELD(REG, 16UL, 16UL, DATA)
|
|
#define ATON_ACTIV_ROM1_AB_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ACTIV_ROM1_AB_ADDR(UNIT, IDX), (DATA))
|
|
|
|
#define ATON_ACTIV_ROM1_C_IDX_MIN (0)
|
|
#define ATON_ACTIV_ROM1_C_IDX_MAX (64 - 1)
|
|
#define ATON_ACTIV_ROM1_C_OFFSET(UNIT, IDX) (ATON_ACTIV_ROM_OFFSET_1 + 8 * (IDX) + 4)
|
|
#define ATON_ACTIV_ROM1_C_ADDR(UNIT, IDX) (ATON_ACTIV_BASE(UNIT) + ATON_ACTIV_ROM1_C_OFFSET(UNIT, IDX))
|
|
#define ATON_ACTIV_ROM1_C_DT (0x0)
|
|
#define ATON_ACTIV_ROM1_C_SET_C(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA)
|
|
#define ATON_ACTIV_ROM1_C_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ACTIV_ROM1_C_ADDR(UNIT, IDX), (DATA))
|
|
|
|
#define ATON_ARITH_COEFF_AB_IDX_MIN (0)
|
|
#define ATON_ARITH_COEFF_AB_IDX_MAX ((3 * 128) - 1)
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#define ATON_ARITH_COEFF_AB_OFFSET(UNIT, IDX) (ATON_ARITH_MEM_OFFSET + 8 * (IDX))
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#define ATON_ARITH_COEFF_AB_ADDR(UNIT, IDX) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFF_AB_OFFSET(UNIT, IDX))
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#define ATON_ARITH_COEFF_AB_DT (0x0)
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#define ATON_ARITH_COEFF_AB_SET_A(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA)
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#define ATON_ARITH_COEFF_AB_SET_B(REG, DATA) ATON_SET_FIELD(REG, 16UL, 16UL, DATA)
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#define ATON_ARITH_COEFF_AB_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ARITH_COEFF_AB_ADDR(UNIT, IDX), (DATA))
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#define ATON_ARITH_COEFF_C_IDX_MIN (0)
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#define ATON_ARITH_COEFF_C_IDX_MAX ((3 * 128) - 1)
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#define ATON_ARITH_COEFF_C_OFFSET(UNIT, IDX) (ATON_ARITH_MEM_OFFSET + 8 * (IDX) + 4)
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#define ATON_ARITH_COEFF_C_ADDR(UNIT, IDX) (ATON_ARITH_BASE(UNIT) + ATON_ARITH_COEFF_C_OFFSET(UNIT, IDX))
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#define ATON_ARITH_COEFF_C_DT (0x0)
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#define ATON_ARITH_COEFF_C_SET_C(REG, DATA) ATON_SET_FIELD(REG, 0UL, 16UL, DATA)
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#define ATON_ARITH_COEFF_C_SET(UNIT, IDX, DATA) ATON_REG_WRITE(ATON_ARITH_COEFF_C_ADDR(UNIT, IDX), (DATA))
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#else // defined RASTA_SVN_REV
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#if (ATON_INTCTRL_INTS(0) > 32)
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#define ATON_INT_GET_MASK(_macro_, _unit_) (_macro_(_unit_, 0, 0) | (((uint64_t)_macro_(_unit_, 1, 0)) << 32))
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#define __ATON_INTCTRL_INTORMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTORMSK_H_SET(0, IDX, DATA)
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#define __ATON_INTCTRL_INTANDMSK_H_SET(IDX, DATA) ATON_INTCTRL_INTANDMSK_H_SET(0, IDX, DATA)
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#else //(ATON_INT_NR <= 32)
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#define ATON_INT_GET_MASK(_macro_, _unit_) _macro_(_unit_, 0, 0)
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#endif //(ATON_INT_NR <= 32)
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#endif // RASTA_SVN_REV
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/* These macros are NOT defined in some older versions of ATON.h
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(namely Neuromem & Centauri), so define them here */
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/* TODO: should not be here as ll_aton_rcompat.h is meant for raSTa compatibility only */
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#ifndef ATON_DECUN_BFORMAT_DT
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#define ATON_DECUN_BFORMAT_DT \
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((ATON_DECUN_BFORMAT_CVS_DT << ATON_DECUN_BFORMAT_CVS_LSB) | \
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(ATON_DECUN_BFORMAT_CWS_DT << ATON_DECUN_BFORMAT_CWS_LSB) | \
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(ATON_DECUN_BFORMAT_OSAM_DT << ATON_DECUN_BFORMAT_OSAM_LSB))
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#endif
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#ifndef ATON_DECUN_DFORMAT_DT
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#define ATON_DECUN_DFORMAT_DT \
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((ATON_DECUN_DFORMAT_CV8_DT << ATON_DECUN_DFORMAT_CV8_LSB) | \
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(ATON_DECUN_DFORMAT_RAWLINE_DT << ATON_DECUN_DFORMAT_RAWLINE_LSB))
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#endif
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#ifndef ATON_DECUN_FFORMAT_DT
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#define ATON_DECUN_FFORMAT_DT (ATON_DECUN_FFORMAT_BN_DT << ATON_DECUN_FFORMAT_BN_LSB)
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#endif
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#ifndef ATON_DECUN_CTRL_SET_PAGEADDR
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#define ATON_DECUN_CTRL_SET_PAGEADDR(REG, DATA) ATON_SET_FIELD(REG, 4UL, 3UL, DATA)
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#endif
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#ifndef ATON_SET_FIELD
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#define ATON_SET_FIELD ATON_SET_FIELD32
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#endif
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#endif //__LL_ATON_COMPAT_H
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