mirror of
https://github.com/openmv/openmv.git
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577 lines
21 KiB
XML
577 lines
21 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<Root xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="SCHVerif.xsd">
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<Device>
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<DeviceID>0x417</DeviceID>
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<Vendor>STMicroelectronics</Vendor>
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<Type>MCU</Type>
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<CPU>Cortex-M0+</CPU>
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<Name>STM32L05x/L06x/L010</Name>
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<Series>STM32L0</Series>
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<Description>ARM 32-bit Cortex-M0+ based device</Description>
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<Configurations>
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<!-- JTAG_SWD Interface -->
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<Interface name="JTAG_SWD">
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<Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
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<WPRMOD reference="0x1">
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<ReadRegister address="0x4002201C" mask="0x000000100" value="0x0"/>
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</WPRMOD>
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</Configuration>
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<Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
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<WPRMOD reference="0x0">
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<ReadRegister address="0x4002201C" mask="0x000000100" value="0x100"/>
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</WPRMOD>
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</Configuration>
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</Interface>
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<!-- Bootloader Interface -->
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<Interface name="Bootloader">
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<Configuration number="0x0"> <!-- WRPx control the write protection of user sector-->
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<WPRMOD reference="0x1">
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<ReadRegister address="0x1FF80000" mask="0x00000100" value="0x0"/>
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</WPRMOD>
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</Configuration>
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<Configuration number="0x1"> <!-- WRPx control the read/write protection PcROP-->
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<WPRMOD reference="0x0">
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<ReadRegister address="0x1FF80000" mask="0x00000100" value="0x100"/>
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</WPRMOD>
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</Configuration>
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</Interface>
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</Configurations>
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<!-- Peripherals -->
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<Peripherals>
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<!-- Embedded SRAM -->
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<Peripheral>
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<Name>Embedded SRAM</Name>
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<Type>Storage</Type>
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<Description/>
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<ErasedValue>0x00</ErasedValue>
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<Access>RWE</Access>
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<!-- 16 KB -->
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<Configuration>
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<Parameters address="0x20000000" name="SRAM" size="0x2000"/>
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<Description/>
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<Organization>Single</Organization>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x20000000" name="SRAM" occurrence="0x1" size="0x2000"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Embedded Flash -->
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<Peripheral>
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<Name>Embedded Flash</Name>
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<Type>Storage</Type>
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<Description>The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms</Description>
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<ErasedValue>0x00</ErasedValue>
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<Access>RWE</Access>
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<FlashSize address="0x1FF8007C" default="0x10000"/>
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<BootloaderVersion address="0x1FF00FFE"/>
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<!-- 128KB single Bank -->
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<Configuration>
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<Parameters address="0x08000000" name="64 Kbytes Embedded Flash" size="0x10000"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08000000" name="sector0" occurrence="0x200" size="0x80"/>
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</Field>
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</Bank>
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<Bank name="EEPROM1">
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<Field>
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<Parameters address="0x08080000" name="sector65281" occurrence="0x1" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Data EEPROM -->
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<Peripheral>
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<Name>Data EEPROM</Name>
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<Type>Storage</Type>
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<Description>The Data EEPROM memory block. It contains user data.</Description>
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<ErasedValue>0x00</ErasedValue>
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<Access>RWE</Access>
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<!-- 1KB single Bank -->
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<Configuration>
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<Parameters address="0x08080000" name=" 2 Kbytes Data EEPROM" size="0x800"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="Bank 1">
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<Field>
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<Parameters address="0x08080000" name="EEPROM1" occurrence="0x1" size="0x800"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Mirror Option Bytes -->
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<Peripheral>
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<Name>MirrorOptionBytes</Name>
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<Type>Storage</Type>
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<Description>Mirror Option Bytes contains the extra area.</Description>
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<ErasedValue>0xFF</ErasedValue>
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<Access>RW</Access>
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<!-- 20 Bytes single bank -->
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<Configuration>
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<Parameters address="0x1FF80000" name=" 20 Bytes Data MirrorOptionBytes" size="0x14"/>
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<Description/>
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<Organization>Single</Organization>
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<Alignment>0x4</Alignment>
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<Bank name="MirrorOptionBytes">
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<Field>
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<Parameters address="0x1FF80000" name="MirrorOptionBytes" occurrence="0x1" size="0x14"/>
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</Field>
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</Bank>
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</Configuration>
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</Peripheral>
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<!-- Option Bytes -->
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<Peripheral>
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<Name>Option Bytes</Name>
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<Type>Configuration</Type>
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<Description/>
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<Access>RW</Access>
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<Bank interface="JTAG_SWD">
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<Parameters address="0x4002201C" name="Bank 1" size="0x68"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>PCROP Protection</Name>
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<Field>
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<Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
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<AssignedBits>
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<Bit reference="SPRMode">
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<Name>WPRMOD</Name>
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<Description>Sector protection mode selection option byte.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0x0">WRPx bit defines sector write protection</Val>
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<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x10</BitOffset>
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<BitWidth>0x4</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
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<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
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<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
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<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
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<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
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<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
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<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x4002201C" name="FLASH_OBR" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_SW</Name>
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<Description/>
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<BitOffset>0x14</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0x0">Hardware independent watchdog</Val>
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<Val value="0x1">Software independent watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STOP</Name>
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<Description/>
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<BitOffset>0x15</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Stop mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STDBY</Name>
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<Description/>
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<BitOffset>0x16</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Standby mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nBOOT1</Name>
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<Description/>
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<BitOffset>0x1F</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>R</Access>
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<Values>
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<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
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<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>Write Protection</Name>
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<Field>
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<Parameters address="0x40022020" name="FLASH_WRPR1" size="0x4"/>
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<AssignedBits>
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<Bit config="0">
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<Name>WRPOT1</Name>
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<Description/>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x10</BitWidth>
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<Access>R</Access>
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<Values ByBit="true">
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<Val value="0x0">Write protection not active</Val>
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<Val value="0x1">Write protection active</Val>
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</Values>
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</Bit>
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<Bit config="1">
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<Name>WRPOT1</Name>
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<Description/>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x10</BitWidth>
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<Access>R</Access>
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<Values ByBit="true">
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<Val value="0x0">read/Write protection active</Val>
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<Val value="0x1">read/Write protection not active</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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</Bank>
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<Bank interface="JTAG_SWD">
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<Parameters address="0x1FF80000" name="Bank 1" size="0x14"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x1FF80000" name="RDP" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>PCROP Protection</Name>
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<Field>
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<Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
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<AssignedBits>
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<Bit reference="SPRMode">
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<Name>WPRMOD</Name>
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<Description>Sector protection mode selection option byte.</Description>
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<BitOffset>0x8</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0x0">WRPx bit defines sector write protection</Val>
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<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>BOR Level</Name>
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<Field>
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<Parameters address="0x1FF80004" name="USER" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>BOR_LEV</Name>
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<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x4</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
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<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
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<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
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<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
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<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
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<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
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<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
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<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>User Configuration</Name>
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<Field>
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<Parameters address="0x1FF80004" name="USER" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>IWDG_SW</Name>
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<Description/>
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<BitOffset>0x4</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0x0">Hardware independent watchdog</Val>
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<Val value="0x1">Software independent watchdog</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STOP</Name>
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<Description/>
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<BitOffset>0x5</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Stop mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nRST_STDBY</Name>
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<Description/>
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<BitOffset>0x6</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0x0">Reset generated when entering Standby mode</Val>
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<Val value="0x1">No reset generated</Val>
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</Values>
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</Bit>
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<Bit>
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<Name>nBOOT1</Name>
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<Description/>
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<BitOffset>0x0F</BitOffset>
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<BitWidth>0x1</BitWidth>
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<Access>W</Access>
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<Values>
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<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
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<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>Write Protection</Name>
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<Field>
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<Parameters address="0x1FF80008" name="WRP1" size="0x8"/>
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<AssignedBits>
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<Bit>
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<Name>WRPOT1</Name>
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<Description/>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x10</BitWidth>
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<Access>W</Access>
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<Values ByBit="true">
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<Val value="0x0">Write protection not active</Val>
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<Val value="0x1">Write protection active</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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</Bank>
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<Bank interface="Bootloader">
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<Parameters address="0x1FF80000" name="Bank 2" size="0x14"/>
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<Category>
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<Name>Read Out Protection</Name>
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<Field>
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<Parameters address="0x1FF80000" name="RDP" size="0x4"/>
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<AssignedBits>
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<Bit>
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<Name>RDP</Name>
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<Description>Read protection option byte. The read protection is used to protect the software code stored in Flash memory.</Description>
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<BitOffset>0x0</BitOffset>
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<BitWidth>0x8</BitWidth>
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<Access>RW</Access>
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<Values>
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<Val value="0xAA">Level 0, no protection</Val>
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<Val value="0xBB">or any value other than 0xAA and 0xCC: Level 1, read protection</Val>
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<Val value="0xCC">Level 2, chip protection</Val>
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</Values>
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</Bit>
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</AssignedBits>
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</Field>
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</Category>
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<Category>
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<Name>PCROP Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FF80000" name="FLASH_OBR" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit reference="SPRMode">
|
|
<Name>WPRMOD</Name>
|
|
<Description>Sector protection mode selection option byte.</Description>
|
|
<BitOffset>0x8</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">WRPx bit defines sector write protection</Val>
|
|
<Val value="0x1">WRPx bit defines sector read/write (PCROP) protection</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>BOR Level</Name>
|
|
<Field>
|
|
<Parameters address="0x1FF80004" name="USER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>BOR_LEV</Name>
|
|
<Description>These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level value into Flash memory</Description>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x4</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
|
|
<Val value="0x1">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
|
|
<Val value="0x2">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
|
|
<Val value="0x3">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
|
|
<Val value="0x4">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
|
|
<Val value="0x5">BOR Level OFF, reset level threshold the 1.45 V-1.55 V</Val>
|
|
<Val value="0x6">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
|
|
<Val value="0x7">BOR Level OFF, reset level threshold for 1.45 V-1.55 V</Val>
|
|
<Val value="0x8">BOR Level 1, reset level threshold for 1.69 V-1.8 V</Val>
|
|
<Val value="0x9">BOR Level 2, reset level threshold for 1.94 V-2.1 V</Val>
|
|
<Val value="0xA">BOR Level 3, reset level threshold for 2.3 V-2.49 V</Val>
|
|
<Val value="0xB">BOR Level 4, reset level threshold for 2.54 V-2.74 V</Val>
|
|
<Val value="0xC">BOR Level 5, reset level threshold for 2.77 V-3.0 V</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>User Configuration</Name>
|
|
<Field>
|
|
<Parameters address="0x1FF80004" name="USER" size="0x4"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>IWDG_SW</Name>
|
|
<Description/>
|
|
<BitOffset>0x4</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Hardware independent watchdog</Val>
|
|
<Val value="0x1">Software independent watchdog</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_STOP</Name>
|
|
<Description/>
|
|
<BitOffset>0x5</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Stop mode</Val>
|
|
<Val value="0x1">No reset generated</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nRST_STDBY</Name>
|
|
<Description/>
|
|
<BitOffset>0x6</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Reset generated when entering Standby mode</Val>
|
|
<Val value="0x1">No reset generated</Val>
|
|
</Values>
|
|
</Bit>
|
|
<Bit>
|
|
<Name>nBOOT1</Name>
|
|
<Description/>
|
|
<BitOffset>0x0F</BitOffset>
|
|
<BitWidth>0x1</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values>
|
|
<Val value="0x0">Boot from Flash if BOOT0 = 0, otherwise Embedded SRAM1</Val>
|
|
<Val value="0x1">Boot from Flash if BOOT0 = 0, otherwise system memory</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
<Category>
|
|
<Name>Write Protection</Name>
|
|
<Field>
|
|
<Parameters address="0x1FF80008" name="WRP1" size="0x8"/>
|
|
<AssignedBits>
|
|
<Bit>
|
|
<Name>WRPOT1</Name>
|
|
<Description/>
|
|
<BitOffset>0x0</BitOffset>
|
|
<BitWidth>0x10</BitWidth>
|
|
<Access>RW</Access>
|
|
<Values ByBit="true">
|
|
<Val value="0x0">Write protection not active</Val>
|
|
<Val value="0x1">Write protection active</Val>
|
|
</Values>
|
|
</Bit>
|
|
</AssignedBits>
|
|
</Field>
|
|
</Category>
|
|
</Bank>
|
|
</Peripheral>
|
|
</Peripherals>
|
|
</Device>
|
|
</Root> |